Network interface instruction processing method and apparatus for multi-path remote memory access
By employing a multi-way instruction queue state maintenance and dynamic shared buffer scheduling method in a multi-node system, the problems of unfair scheduling of multi-way remote memory access instructions and uneven allocation of cache resources are solved, achieving efficient instruction processing and low-latency network interface services.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NAT UNIV OF DEFENSE TECH
- Filing Date
- 2026-04-24
- Publication Date
- 2026-07-17
AI Technical Summary
In multi-node systems, issues such as unfair scheduling of multiple remote memory access commands, uneven allocation of cache resources, low throughput, high latency, and insufficient quality of service lead to inefficiencies in network interfaces when processing massive numbers of multiple remote memory access commands.
A state maintenance method using a multi-way instruction queue is adopted. This method allocates an independent address space in local memory, manages the instruction queue using write pointers and read pointers, combines a dynamic shared buffer and a round-robin arbitrator for instruction scheduling, and implements network transmission through CrossBar switching. It prioritizes the use of private credits and then shared credits, and designs a fast FIFO structure to hide memory access latency.
It achieves efficient instruction scheduling and caching among multiple nodes, improves the efficiency of software and hardware interaction, reduces interaction latency, scientifically utilizes cache resources, reduces buffer access latency, and improves the service quality of network interfaces.
Smart Images
Figure CN122420262A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a hardware and software interaction technology in the field of high-performance computing, and more particularly to a network interface instruction processing method and apparatus for multi-channel remote memory access. Background Technology
[0002] With the rapid development of AI and HPC technologies, the industry has put forward higher requirements for high-speed interconnection and scalability between nodes. A high-bandwidth, low-latency, and high-performance interconnection technology is crucial for improving the overall AI computing performance.
[0003] When data is transferred between multiple nodes, it is typically necessary to access the memory space of other nodes through an interconnect network. For each node, the processor generates a large number of remote memory access instructions during job execution. These multiple remote memory access instructions need to be scheduled reasonably to ensure fairness. These instructions need to be sent to the interconnect network through network interface hardware and eventually reach the destination node to perform memory access operations. The network interface hardware needs to perform efficient caching and scheduling of these instructions. Efficient caching can hide the interaction latency between the processor node and the network interface hardware, and a reasonable scheduling mechanism can guarantee the fairness and quality of service when instructions are sent to the interconnect network.
[0004] The scheduling of multiple remote memory access instructions and the caching of these instructions on the network interface hardware are key factors in ensuring efficient remote memory access between nodes. They are crucial for solving technical problems such as low throughput, high latency, uneven allocation of cache resources, poor scheduling fairness, and insufficient quality of service in large-scale node interconnection scenarios when the network interface is processing massive numbers of multiple remote memory access instructions. Summary of the Invention
[0005] To address the aforementioned technical problems, this invention provides a network interface instruction processing method for multi-channel remote memory access, comprising the following steps:
[0006] S1, State maintenance of the multiplexed instruction queue:
[0007] S1.1: Store all remote memory access instructions in the local memory address space;
[0008] S1.2: Configure N-way Remote Memory Access Command Queues (IQ) for the network interface. i (i = 0, 1, ..., N-1), each path is allocated an independent address space in local memory, which is written by software and read out by hardware, and the queue is reused in a circular manner;
[0009] S1.3: Maintain the base address (Base_Address) for each path. i Upper Addressi Write pointer (Write_Pointer) i Read pointer (Read_Pointer) i The write pointer is incremented by software, and the read pointer is incremented by hardware. Both pointers roll back to the base address after reaching the top address.
[0010] S1.4: Based on Write_Pointer i With Read_Pointer i The size relationship is calculated by the number of unread instructions and the number of free addresses in the queue. Before writing an instruction, it is first determined whether the queue has enough free space.
[0011] S2, scheduling of read requests from a multi-way instruction queue:
[0012] S2.1: via Base_Address i Upper_Address i Write_Pointer i Read_Pointer i Calculate whether there is an instruction to be processed in the instruction queue; if so, and the corresponding network interface hardware buffer has free space to buffer the instruction, then generate the corresponding IQ. i Request Req i ;
[0013] S2.2: For all requests in the instruction queue, a round-robin arbitrator is used to arbitrate the requests, and one request is scheduled for execution. The request that receives the arbitration response is sent to local memory and the instruction read operation is performed.
[0014] S2.3: When there are multiple instructions in the instruction queue that receive the arbitration response, execute them by reading multiple instructions in one request;
[0015] S3, on-chip cache for multiplexed instructions:
[0016] A dynamic shared buffer memory is constructed in groups of P paths. When N is greater than P, a total of [number] paths are configured. Groups; each group has a total capacity of M bytes and a bit width of W. A private credit limit MAX_Private_C is configured for each input instruction stream i (i = 0, 1, 2, ..., P-1) of this dynamic buffer. i Simultaneously, configure a shared credit value limit MAX_Shared_C for all input commands, with each credit value corresponding to W bits of data, satisfying:
[0017] (MAX_Private_C i (×P+MAX_Shared_C)×W=8M
[0018] When writing commands, private credits are used first. Once private credits are exhausted, shared credits are used to continue writing data. A shared credit usage threshold MAX_Shared_Thres_C is set for each port. i 0; When reading data, release shared credits first, then release the corresponding private credits;
[0019] S4, Network Sending Request Scheduling for Multiplexed Instruction Queues:
[0020] S4.1: The instructions from the N-way instruction queue are sent to the Q network ports through an N×Q CrossBar switching method;
[0021] S4.2: Read instructions from the dynamic shared buffer through CrossBar, identify the buffer with active instructions based on the queue status indicator, and select one of the buffers for instruction reading operation through the arbitrator;
[0022] S4.3: After the instruction is read, based on the instruction type and the load of the Q output queues, the instruction is sent to one of the output queues and finally sent to the destination node through the network port;
[0023] S4.4: Set up multiple output queues for each instruction type, parse the type of the current instruction, check the priority and load of the multiple output queues for that instruction type, and output the instruction to the less busy queue of the corresponding priority.
[0024] Further, in step S1, Base_Address i and Upper_Address i Keeps fixed after being configured by the software; Write_Pointer i The software updates the Read_Pointer synchronously when a new instruction enters the queue. i The network interface hardware updates synchronously when reading instructions.
[0025] Further, in step S1, Write_Pointer i >Read_Pointer i At that time, the number of instructions that have not yet been read in the queue = (Write_Pointer) i -Read_Pointer i ); when Write_Pointer i <Read_Pointer i At that time, the number of instructions that have not yet been read in the queue = (Write_Pointer) i +1+Upper_Address i-Base_Address i -Read_Pointer i ).
[0026] Furthermore, in step S3, the buffer uses a fast FIFO method and device to hide memory access latency. The fast FIFO includes a main buffer FIFO_MAIN, a top buffer FIFO_TOP, read / write address management of FIFO_MAIN, read / write management of FIFO_TOP, and input data bypass control, etc.
[0027] When data is input, the bypass control determines whether the data is written to the main buffer or the top buffer;
[0028] When reading data, data is read from address 0 of FIFO_TOP, and the data in FIFO_TOP is shifted forward sequentially. It is also determined whether to load data from the current address of FIFO_MAIN to FIFO_TOP. After reading and writing, the state of FIFO_MAIN or FIFO_TOP is updated.
[0029] Further, in step S4, the method for selecting the buffer is as follows: for each of the P instruction queues in a dynamic shared buffer, a P-to-1 arbitrator is used respectively, and all... The arbitration result from the P-select-1 arbitrator is then processed by the second level. Select arbitrator 1, and finally select one instruction queue for instruction reading.
[0030] The present invention also provides a network interface instruction processing device for multi-channel remote memory access, comprising:
[0031] The state maintenance device for the multiplexed instruction queue includes a memory and a read / write controller for that memory; the memory data width is Base_Address. i Upper_Address i Write_Pointer i Read_Pointer i The total bit width is equal to the depth of the instruction queues, and each address stores the status information of one instruction queue. The read / write controller is used to control the read and write operations of the memory according to the state maintenance method of the multi-way instruction queues.
[0032] A read request scheduling device for a multi-channel instruction queue includes a read request generation device for each instruction queue, a device for calculating the available space of a dynamic shared buffer, and a round-robin arbitrator device.
[0033] On-chip cache for multiplexed instructions: containing Each dynamic shared buffer mainly includes a data buffer, an address buffer, a port-private buffer, port head and tail pointer management, and free address queue head and tail pointer management; the data buffer and the port-private buffer constitute a fast FIFO structure.
[0034] Network transmission request scheduling device with multiple instruction queues: A CrossBar switch consisting of N×Q components, by... One P-selection level 1 arbitrator, one It consists of a second-level arbitrator and Q output queues.
[0035] The present invention also provides a computer-readable storage medium storing a computer program for being programmed or configured by a microprocessor to execute a network interface instruction processing method for multiplexed remote memory access.
[0036] In summary, the present invention has the following advantages over the prior art:
[0037] (1) Supports efficient scheduling and caching of a large number of instruction queues across multiple nodes;
[0038] (2) The method and apparatus for maintaining the status of multiple instruction queues can save a large amount of instruction queue status information in the network interface hardware in real time, which can greatly improve the efficiency of software and hardware interaction between the host and the network interface hardware and reduce the interaction latency.
[0039] (3) Support a buffer resource allocation mechanism based on a combination of private credit and shared credit to ensure that multiple instruction queues can make more scientific and effective use of limited hardware cache resources;
[0040] (4) Supports data prefetching, which reads the header data from the buffer in advance and stores it. The corresponding data can be used as soon as the data read request is valid, which reduces the memory access latency of the buffer. Attached Figure Description
[0041] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0042] Figure 1 A schematic diagram of a state maintenance device for a multi-way instruction queue;
[0043] Figure 2 A schematic diagram of a read request scheduling device for a multi-channel instruction queue;
[0044] Figure 3 A schematic diagram of an on-chip cache device for multiplexed instructions;
[0045] Figure 4 A schematic diagram of a network request scheduling device for multiple instruction queues;
[0046] Figure 5 This is a flowchart of a network interface instruction processing method for multi-channel remote memory access. Detailed Implementation
[0047] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0048] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments of the invention. As used herein, the singular form may also include the plural form unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0049] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.
[0050] See Figures 1 to 5 As shown, the present invention provides a network interface instruction processing method for multi-channel remote memory access, comprising the following steps:
[0051] S1, State maintenance of the multi-way instruction queue:
[0052] S1.1: Store all remote memory access instructions in the local memory address space;
[0053] S1.2: Suppose the network interface has N remote memory access instruction queues. Allocate address space for each instruction queue IQi in local memory; the software allocates address space to each instruction queue IQi. i From base address Base_Addressi Instructions are written starting from (i = 0, 1, 2, ..., N-1). The network interface hardware reads instructions from this queue, and the instruction queue is used cyclically.
[0054] S1.3: Write_Pointer i This pointer is used to indicate the write position of instructions in the queue, and it increments gradually as instructions are written; when an instruction is written to the top address (Upper_Address), the pointer is incremented. i At that time, the next instruction rolls back to Base_Address. i To perform the write, the network interface hardware retrieves data from the base address of the queue. i Read the instruction;
[0055] S1.4: Read Pointer i This pointer is used to indicate the read position of an instruction in the queue. As instructions are read, the read pointer gradually increments; when the top address of the queue (Upper_Address) is reached... i After the instruction is read, the next instruction will roll back to Base_Address. i Perform a read; an address that has already been read can be overwritten by a new instruction.
[0056] S1.5: Based on Write_Pointer i With Read_Pointer i The size relationship is calculated by comparing the number of unread instructions and the number of free addresses in the instruction queue; software adds instructions to the instruction queue IQ. i Before writing the command, first check if the queue has enough free space. If the condition is met, then execute the write operation.
[0057] S2, Multiplexed instruction queue read request scheduling: The network interface hardware first determines which instruction queues have instructions to be read and can generate instruction read requests based on the status information of each instruction queue and the corresponding instruction buffer status in the network interface hardware. Then, the scheduler selects one from this group of requests and sends a read request to local memory.
[0058] S2.1: via Base_Address i Upper_Address i Write_Pointer i Read_Pointer i Calculate whether there is an instruction to be processed in the instruction queue; if so, and the corresponding network interface hardware buffer has free space to buffer the instruction, then generate the corresponding IQ. i Request Req i ;
[0059] S2.2: For all requests in the instruction queue, one request needs to be scheduled out for execution; a round-robin arbitrator is used to arbitrate the requests, and one request is scheduled out for execution. The request that receives the arbitration response is sent to local memory and the instruction read operation is performed.
[0060] S2.3: When there are multiple instructions in the instruction queue that receive the arbitration response, the method of reading multiple instructions in one request is adopted for execution; the number of requested instructions is determined by the data packet size of the software and hardware interaction interface, so that all the instruction data returned at one time can fill a data packet exactly, in order to avoid the situation of low data packet load efficiency.
[0061] S3, on-chip cache for multiplexed instructions:
[0062] A dynamic shared buffer approach combining grouped multi-way dynamic sharing and private caching is adopted. For N-way instruction queues, buffer storage is set up in groups of P. When N is greater than P, a total of [number] buffers are set up. There are P-way buffers; each P-way buffer has a total capacity of M bytes and a data width of W. A private credit limit MAX_Private_C is set for each input instruction stream i (i = 0, 1, 2, ..., P-1) of this dynamic buffer. i Simultaneously, a shared credit value limit MAX_Shared_C is set for all input commands, with each credit value corresponding to W bits of data, and satisfying the following:
[0063] (MAX_Private_C i (×P+MAX_Shared_C)×W=8M
[0064] When writing instructions, the private credits corresponding to the instruction stream are consumed first. When the private credits are exhausted, shared credits are requested to continue writing data. A shared credit usage threshold MAX_Shared_Thres_C is set for each port. i 0. When reading data, shared credits are released first, followed by the corresponding private credits;
[0065] S4, Network Sending Request Scheduling for Multiplexed Instruction Queues:
[0066] S4.1: On the network interface hardware, an N×Q CrossBar switching method is used to send instructions from N instruction queues to Q network port queues;
[0067] S4.2: Read instructions from the dynamic shared buffer via CrossBar; when preparing to read instructions, CrossBar first determines which instruction queue buffers contain active instructions based on the queue status indicator. For all active buffers, an arbitrator selects one buffer for instruction reading. This method uses a P-to-1 arbitrator for each of the P instruction queues in each dynamic shared buffer. The arbitration result from the P-select-1 arbitrator is then processed by the second level. The arbitrator ultimately selects one instruction queue for instruction reading.
[0068] S4.3: After the instruction is read, based on the instruction type and the load of the Q output queues, the instruction is sent to one of the output queues and finally sent to the destination node through the network port;
[0069] S4.4: Set up multiple output queues for each instruction type, parse the type of the current instruction, check the priority and load of the multiple output queues for that instruction type, and output the instruction to the less busy queue of the corresponding priority.
[0070] As a preferred embodiment, in step S1, the network interface hardware saves and maintains the Base_Address for each instruction queue. i Upper_Address i Write_Pointer i Read_Pointer i ,in:
[0071] Base_Address i and Upper_Address i The queue is written by software into the network interface hardware and stored during operation;
[0072] Write_Pointer i The software synchronously writes new instructions to the network interface hardware when they enter the queue, and reads them on demand.
[0073] Read_Pointer i The network interface hardware updates synchronously when reading instructions, and reads on demand.
[0074] As a preferred embodiment, in step S1, when Write_Pointer i Read_Pointer i At that time, the number of instructions that have not yet been read in the queue = (Write_Pointer) i - Read_Pointeri ); when Write_Pointer i < Read_Pointer i At that time, the number of instructions that have not yet been read in the queue = (Write_Pointer) i + 1 + Upper_Address i -Base_Address i - Read_Pointer i The network interface hardware needs to continuously read instructions from the instruction queue in local memory. Therefore, the network interface hardware needs to save and maintain the state of each instruction queue, mainly including the Base_Address mentioned above. i Upper_Address i Write_Pointer i Read_Pointer i Among them, Base_Address i and Upper_Address i The information is written by software to the network interface hardware and stored during queue creation; these two sets of information are typically not changed during queue operation; Write_Pointer i When new instructions enter the queue, the software synchronously writes them to the network interface hardware, which then reads the Write_Pointer when needed. i Data; Read_Pointer i The network interface hardware updates synchronously when reading instructions, and the software reads the Read_Pointer from the network interface hardware when needed. i data.
[0075] As a preferred embodiment, in step S3, a fast FIFO method and apparatus are designed in the buffer to hide the memory access latency of the data buffer, realizing zero-latency writing and reading of instruction information. Similar to a regular FIFO, the fast FIFO's external interface is for data writing and data reading. Internally, the fast FIFO includes the FIFO main buffer FIFO_MAIN, the FIFO top buffer FIFO_TOP, FIFO_MAIN read / write address management, FIFO_TOP read / write management, and input data bypass control. When data is input into the fast FIFO, the bypass control determines whether the data is written to FIFO_MAIN. The read / write address management of N or FIFO_TOP, FIFO_MAIN or FIFO_TOP determines the address where data is written to FIFO_MAIN and FIFO_TOP respectively; when data is read from the FIFO, it is always read from FIFO_TOP address 0, and the data in FIFO_TOP is moved forward sequentially, that is, data at address 2 is written to address 1, data at address 1 is written to address 0, and it is determined whether data needs to be read from the position pointed to by the current read address of FIFO_MAIN and written to FIFO_TOP; after reading and writing, the state of FIFO_MAIN or FIFO_TOP is updated accordingly.
[0076] As a preferred embodiment, in step S4, the method for selecting the buffer is as follows: for each of the P instruction queues in a dynamic shared buffer, a P-to-1 arbitrator is used respectively, and all... The arbitration result from the P-select-1 arbitrator is then processed by the second level. Select arbitrator 1, and finally select one instruction queue for instruction reading.
[0077] To implement the above method, the present invention also provides a network interface instruction processing apparatus for multiple remote memory accesses, including a state maintenance device for multiple instruction queues, a read request scheduling device for multiple instruction queues, an on-chip cache device for multiple instructions, and a network transmission request scheduling device for multiple instruction queues; wherein:
[0078] The state maintenance device for the multiplexed instruction queue includes a memory and a read / write controller for that memory; the memory data width is Base_Address. i Upper_Address i Write_Pointer i Read_Pointer i The total bit width is equal to the depth of the instruction queues, and each address stores the status information of one instruction queue. The read / write controller is used to control the read and write operations of the memory according to the state maintenance method of the multi-way instruction queues.
[0079] The read request scheduling device for a multi-way instruction queue includes a read request generation device for each instruction queue, a device for calculating the available space of a dynamic shared buffer, and a round-robin arbitrator device.
[0080] The on-chip cache device for multiplexed instructions includes Each dynamic shared buffer mainly includes a data buffer, an address buffer, a port-private buffer, port head and tail pointer management, and free address queue head and tail pointer management; the data buffer and the port-private buffer constitute a fast FIFO structure.
[0081] The network transmission request scheduling device for multiple instruction queues includes an N×Q CrossBar switch, consisting of... One P-selection level 1 arbitrator, one It consists of a second-level arbitrator and Q output queues.
[0082] The present invention also provides a computer-readable storage medium storing a computer program for being programmed or configured by a microprocessor to execute a network interface instruction processing method for multiplexed remote memory access.
[0083] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A network interface instruction processing method for multi-channel remote memory access, characterized in that, Including the following steps: S1, State maintenance of the multiplexed instruction queue: S1.1: Store all remote memory access instructions in the local memory address space; S1.2: Configure N-way Remote Memory Access Command Queues (IQ) for the network interface. i (i = 0, 1, ..., N-1), each path is allocated an independent address space in local memory, which is written by software and read out by hardware, and the queue is reused in a circular manner; S1.3: Maintain the base address (Base_Address) for each path. i Upper Address i Write pointer (Write_Pointer) i Read pointer (Read_Pointer) i The write pointer is incremented by software, and the read pointer is incremented by hardware. Both pointers roll back to the base address after reaching the top address. S1.4: Based on Write_Pointer i With Read_Pointer i The size relationship is calculated by the number of unread instructions and the number of free addresses in the queue. Before writing an instruction, it is first determined whether the queue has enough free space. S2, scheduling of read requests from a multi-way instruction queue: S2.1: via Base_Address i Upper_Address i Write_Pointer i Read_Pointer i Calculate whether there is an instruction to be processed in the instruction queue; if so, and the corresponding network interface hardware buffer has free space to buffer the instruction, then generate the corresponding IQ. i Request Req i ; S2.2: For all requests in the instruction queue, a round-robin arbitrator is used to arbitrate the requests, and one request is scheduled for execution. The request that receives the arbitration response is sent to local memory and the instruction read operation is performed. S2.3: When there are multiple instructions in the instruction queue that receive the arbitration response, execute them by reading multiple instructions in one request; S3, on-chip cache for multiplexed instructions: A dynamic shared buffer memory is constructed in groups of P paths. When N is greater than P, a total of [number] paths are configured. Groups; each group has a total capacity of M bytes and a bit width of W. A private credit value limit MAX_Private_C is configured for each input instruction stream i (i = 0, 1, 2, ..., P-1) of this dynamic buffer. i Simultaneously, configure a shared credit value limit MAX_Shared_C for all input commands, with each credit value corresponding to W bits of data, satisfying: (MAX_Private_C i ×P+MAX_Shared_C)×W=8M When writing commands, private credits are used first. Once private credits are exhausted, shared credits are used to continue writing data. A shared credit usage threshold MAX_Shared_Thres_C is set for each port. i 0; When reading data, release shared credits first, then release the corresponding private credits; S4, Network Sending Request Scheduling for Multiplexed Instruction Queues: S4.1: The N-way instruction queue is sent to Q network ports using an N×Q crossbar switching method; S4.2: Read instructions from the dynamic shared buffer through CrossBar, identify the buffer with active instructions based on the queue status indicator, and select one of the buffers for instruction reading operation through the arbitrator; S4.3: After the instruction is read, based on the instruction type and the load of the Q output queues, the instruction is sent to one of the output queues and finally sent to the destination node through the network port; S4.4: Set up multiple output queues for each instruction type, parse the type of the current instruction, check the priority and load of the multiple output queues for that instruction type, and output the instruction to the less busy queue of the corresponding priority.
2. The network interface instruction processing method for multi-channel remote memory access according to claim 1, characterized in that: In step S1, Base_Address i and Upper_Address i Keeps fixed after being configured by the software; Write_Pointer i The software updates the Read_Pointer synchronously when a new instruction enters the queue. i The network interface hardware updates synchronously when reading instructions.
3. The network interface instruction processing method for multi-channel remote memory access according to claim 1, characterized in that: In step S1, Write_Pointer i >Read_Pointer i At that time, the number of instructions that have not yet been read in the queue = (Write_Pointer) i -Read_Pointer i ); when Write_Pointer i <Read_Pointer i At that time, the number of instructions that have not yet been read in the queue = (Write_Pointer) i +1+Upper_Address i -Base_Address i -Read_Pointer i ).
4. The network interface instruction processing method for multi-channel remote memory access according to claim 1, characterized in that: In step S3, the buffer uses a fast FIFO method and device to hide memory access latency. The fast FIFO includes a main buffer FIFO_MAIN, a top buffer FIFO_TOP, read / write address management of FIFO_MAIN, read / write management of FIFO_TOP, and input data bypass control, etc. When data is input, the bypass control determines whether the data is written to the main buffer or the top buffer; When reading data, data is read from address 0 of FIFO_TOP, and the data in FIFO_TOP is shifted forward sequentially. It is also determined whether to load data from the current address of FIFO_MAIN to FIFO_TOP. After reading and writing, the state of FIFO_MAIN or FIFO_TOP is updated.
5. The network interface instruction processing method for multi-channel remote memory access according to claim 1, characterized in that, In step S4, the method for selecting the buffer is as follows: for each of the P instruction queues in a dynamic shared buffer, a P-to-1 arbitrator is used respectively, and all... The arbitration result from the P-select-1 arbitrator is then processed by the second level. Select arbitrator 1, and finally select one instruction queue for instruction reading.
6. A network interface instruction processing device for multi-channel remote memory access, characterized in that, include: The state maintenance device for the multiplexed instruction queue includes a memory and a read / write controller for that memory, with a memory data width of Base_Address. i Upper_Address i Write_Pointer i Read_Pointer i The total bit width is equal to the depth of the instruction queues. Each address stores the status information of one instruction queue. The read / write controller is used to control the read and write operations of the memory according to the state maintenance method of the multi-way instruction queues. A read request scheduling device for a multi-channel instruction queue includes a read request generation device for each instruction queue, a device for calculating the available space of a dynamic shared buffer, and a round-robin arbitrator device. On-chip cache for multiplexed instructions: containing Each dynamic shared buffer memory mainly includes a data buffer, an address buffer, a port private buffer, port head and tail pointer management, and free address queue head and tail pointer management. The data buffer and the port private buffer constitute a fast FIFO structure. Network transmission request scheduling device with multiple instruction queues: A CrossBar switch consisting of N×Q components, by... One P-selection level 1 arbitrator, one It consists of a second-level arbitrator and Q output queues.
7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program for being programmed or configured by a microprocessor to execute the network interface instruction processing method for multiplexed remote memory access as described in any one of claims 1-5.