Cross-network for decentralized arbitration

Abstract

The present invention relates to a decentralized arbitration crossbar network. In the crossbar network of the present invention, arbitration units are not designed to configure data paths between circuits. In the crossbar network of the present invention, a data path can be established after a three-way handshake between two circuits.

Description

Technical Field

[0001] This invention relates to a crossbar network, and more particularly to a decentralized arbitration crossbar network. Background Technology

[0002] As is well known, an IC chip contains multiple circuits, and each circuit can exchange data and instructions with each other. Therefore, a crossbar network was developed to enable circuits to exchange data and commands.

[0003] Please refer to Figure 1A The diagram illustrates a conventional IC chip. The IC chip 100 includes a first circuit 110, a second circuit 120, a third circuit 130, and a fourth circuit 140. The first circuit 110 includes a transmitter (Tx1) and a receiver (Rx1). The second circuit 120 includes a transmitter (Tx2) and a receiver (Rx2). The third circuit 130 includes a transmitter (Tx3) and a receiver (Rx3). The fourth circuit 140 includes a transmitter (Tx4) and a receiver (Rx4). Furthermore, any one of these circuits can receive data and instructions from the other three circuits, and any one of these circuits can also transmit data and instructions to the other three circuits. For example, each of the circuits 110, 120, 130, and 140 can be one of a control unit, a storage unit, a data processing unit, a graphics processing unit, etc.

[0004] To achieve the aforementioned relationship, IC chip 100 further incorporates an arbitrating unit to allocate the data paths between all circuits 110, 120, 130, and 140 for transmitting data and instructions. The arbitrating unit includes an arbitrator 150 and multiplexers 151, 152, 153, and 154.

[0005] The four input terminals of the first multiplexer 151 are connected to the transmitters Tx1, Tx2, Tx3, and Tx4 of the four circuits 110, 120, 130, and 140, respectively. The output terminal of the first multiplexer 151 is connected to the receiver Rx1 of the first circuit 110. The selection terminal of the first multiplexer 151 receives the first selection signal S. AThe four input terminals of the second multiplexer 152 are connected to the transmitters Tx1, Tx2, Tx3, and Tx4 of the four circuits 110, 120, 130, and 140, respectively. The output terminal of the second multiplexer 152 is connected to the receiver Rx2 of the second circuit 120. The selection terminal of the second multiplexer 152 receives the second selection signal S. B The four input terminals of the third multiplexer 153 are connected to the transmitters Tx1, Tx2, Tx3, and Tx4 of the four circuits 110, 120, 130, and 140, respectively. The output terminal of the third multiplexer 153 is connected to the receiver Rx3 of the third circuit 130. The selection terminal of the third multiplexer 153 receives the third selection signal S. C The four input terminals of the fourth multiplexer 154 are connected to the transmitters Tx1, Tx2, Tx3, and Tx4 of the four circuits 110, 120, 130, and 140, respectively. The output terminal of the fourth multiplexer 154 is connected to the receiver Rx4 of the fourth circuit 140. The selection terminal of the fourth multiplexer 154 receives the fourth selection signal S. D .

[0006] Arbitrator 150 is connected to four circuits 110, 120, 130, and 140. Arbitrator 150 uses a first communication signal (C1) to exchange link information with the first circuit 110. Arbitrator 150 uses a second communication signal (C2) to exchange link information with the second circuit 120. Arbitrator 150 uses a third communication signal (C3) to exchange link information with the third circuit 130. Arbitrator 150 uses a fourth communication signal (C4) to exchange link information with the fourth circuit 140. Furthermore, arbitrator 150 configures the data paths between all circuits 110, 120, 130, and 140 based on the link information from the four communication signals (C1, C2, C3, and C4).

[0007] Please refer to Figure 1B The illustration depicts a conventional IC chip operation example. For instance, based on the information from communication signals C1, C2, C3, and C4, the arbitrator 150 determines the data and instructions that are transmitted between the first circuit 110 and the second circuit 120, and between the third circuit 130 and the fourth circuit 140.

[0008] At this time, the arbitrator 150 uses the first selection signal S A The first multiplexer 151 is controlled to establish a data path, connecting the transmitter Tx2 of the second circuit 120 to the receiver Rx1 of the first circuit 110; the second selection signal S is used. BThe second multiplexer 152 is controlled to establish a data path, connecting the transmitter Tx1 of the first circuit 110 to the receiver Rx2 of the second circuit 120; the third selection signal S is used. C The third multiplexer 153 is controlled to establish a data path, connecting the transmitter Tx4 of the fourth circuit 140 to the receiver Rx3 of the third circuit 130; the fourth selection signal S is used. D The fourth multiplexer 154 is controlled to establish a data path, connecting the transmitter Tx3 of the third circuit 130 to the receiver Rx4 of the fourth circuit 140.

[0009] Once all data paths are established, the arbitrator 150 uses communication signals C1, C2, C3, and C4 to notify the four circuits 110, 120, 130, and 140, which can then begin transmitting data and instructions. In other words, the four circuits 110, 120, 130, and 140 transmit data and instructions to the desired circuit through the established data paths.

[0010] Of course, if a change in the data path is desired, the arbitrator 150 can establish an alternative data path at an appropriate time. For example, if the first circuit 110 wants to transmit data and instructions to the third circuit 130, the first circuit 110 first notifies the arbitrator 150 using the communication signal C1. When the third circuit 130 confirms that it can receive the data and instructions from the first circuit 110, it notifies the arbitrator 150 using the communication signal C3. At this time, the arbitrator 150 uses the third selection signal S... C The third multiplexer 153 is used to establish a new data path. Once the new data path is established, the arbitrator 150 uses the communication signal C1 to notify the first circuit 110 to transmit data and instructions to the third circuit 130.

[0011] Basically, data transmission within a conventional IC chip is achieved using cross-networks. Please refer to... Figure 2 The diagram illustrates a conventional cross-network. The cross-network includes: an arbitration unit 260, multiple transmitters Tx1, Tx2, Tx3, Tx4, Tx5, Tx6, and multiple receivers Rx1, Rx2, Rx3, Rx4, Rx5, Rx6. Similar to... Figure 1A-Figure 1B Transmitter Tx1 and receiver Rx1 may be included in a first circuit (not shown), transmitter Tx2 and receiver Rx2 may be included in a second circuit (not shown), and so on. Additionally, in Figure 2The example used here is six transmitters Tx1, Tx2, Tx3, Tx4, Tx5, and Tx6, and six receivers Rx1, Rx2, Rx3, Rx4, Rx5, and Rx6. Of course, there is no limit to the number of transmitters and receivers; those skilled in the art can design any number of transmitters and receivers in a cross-network.

[0012] Arbitration unit 260 includes an arbitrator 250 and multiplexers 251, 252, 253, 254, 255, and 256. Multiplexer 251 has multiple inputs connected to transmitters Tx1, Tx2, Tx3, Tx4, Tx5, and Tx6; its output is connected to receiver Rx1; and its selection terminal receives a selection signal S. Multiplexer 252 has multiple inputs connected to transmitters Tx1, Tx2, Tx3, Tx4, Tx5, and Tx6; its output is connected to receiver Rx2; and its selection terminal receives a selection signal S. And so on. Multiplexer 256 has multiple inputs connected to transmitters Tx1, Tx2, Tx3, Tx4, Tx5, and Tx6; its output is connected to receiver Rx6; and its selection terminal receives a selection signal S.

[0013] For example, the selection signal S includes multiple sub-selection signals used to control the corresponding multiplexers 251, 252, 253, 254, 255, and 256. That is, the arbitrator 250 issues the selection signal S to control the multiplexers 251, 252, 253, 254, 255, and 256 to establish multiple data paths between transmitters Tx1, Tx2, Tx3, Tx4, Tx5, and Tx6 and receivers Rx1, Rx2, Rx3, Rx4, Rx5, and Rx6. Of course, the arbitrator 250 also uses communication signals (not shown) to exchange connection information with all transmitters Tx1, Tx2, Tx3, Tx4, Tx5, and Tx6 and receivers Rx1, Rx2, Rx3, Rx4, Rx5, and Rx6 to determine the data paths.

[0014] As explained above, a conventional cross-network requires an arbitration unit 260 to configure all data paths. Furthermore, if a new data path needs to be established, the arbitrator 250 needs to coordinate and allocate it again.

[0015] Furthermore, in a cross-connect network, the more transmitters Tx1, Tx2, Tx3, Tx4, Tx5, Tx6 and receivers Rx1, Rx2, Rx3, Rx4, Rx5, Rx6 there are, the more communication lines there are, which will make the internal wiring design of the IC chip more complex.

[0016] Of course, transmitters Tx1, Tx2, Tx3, Tx4, Tx5, Tx6 and receivers Rx1, Rx2, Rx3, Rx4, Rx5, Rx6 can also share a communication line to transmit communication signals. In this case, arbitrator 250 needs to use polling to sequentially exchange link information with transmitters Tx1, Tx2, Tx3, Tx4, Tx5, Tx6 and receivers Rx1, Rx2, Rx3, Rx4, Rx5, Rx6. Obviously, the time required for arbitrator 250 to use polling to exchange link information with transmitters Tx1, Tx2, Tx3, Tx4, Tx5, Tx6 and receivers Rx1, Rx2, Rx3, Rx4, Rx5, Rx6 will reduce the operating performance of the cross-connect network. Summary of the Invention

[0017] This invention relates to a cross-connect network, comprising: a first circuit including a first transmitter and a first receiver; a second circuit including a second transmitter and a second receiver; a first bus connected to the first transmitter of the first circuit; a second bus connected to the second transmitter of the second circuit; a first multiplexer connected to the second bus; wherein the first receiver of the first circuit is coupled to the second bus via the first multiplexer; and a second multiplexer connected to the first bus; wherein the second... The second receiver of the circuit is coupled to the first bus via the second multiplexing element; a first connection detection element is coupled to the second bus; wherein, when the second circuit issues a connection request to the first circuit, the first connection detection element detects the connection request via the second bus and notifies the first circuit; and a second connection detection element is coupled to the first bus; wherein, when the first circuit issues the connection request to the second circuit, the second connection detection element detects the connection request via the first bus and notifies the second circuit.

[0018] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] Figure 1A A schematic diagram of a familiar IC chip;

[0020] Figure 1B This serves as a familiar example of how IC chips operate;

[0021] Figure 2 This is a schematic diagram of a familiar cross-network.

[0022] Figure 3A This is a schematic diagram of the cross-network of the present invention;

[0023] Figure 3B This describes the operational flow of the initiator in the cross-network of this invention;

[0024] Figure 3C This describes the operational flow of the target in the cross-network of this invention;

[0025] Figure 4 This is a schematic diagram of the cross-network of the present invention; and

[0026] Figure 5 This is another embodiment of the cross-network of the present invention.

[0027] The reference numerals in the attached figures are explained as follows:

[0028] 100: IC chip

[0029] 110, 310: First circuit

[0030] 120, 320: Second circuit

[0031] 130, 330: Third circuit

[0032] 140, 340: Fourth Circuit

[0033] 150, 250: Arbitrator

[0034] 151, 152, 153, 154, 251, 252, 253, 254, 255, 256: Multiplexers

[0035] 260: Arbitration Unit

[0036] 312, 322, 332, 342: Multiplexer components

[0037] 314, 324, 334, 344: Connecting configuration elements

[0038] 316, 326, 336, 346: Connect to detection elements

[0039] 421, 422, 423, 424: Phase conversion elements

[0040] 454: Integrated clock gate element

[0041] 464: Phase alignment element Detailed Implementation

[0042] This invention proposes a decentralized arbitration crossbar network. In this crossbar network, instead of an arbitration unit to configure data paths, a data path is established through a three-way handshake between two circuits. In other words, a link is established between two circuits after a three-way handshake.

[0043] Please refer to Figure 3A The diagram illustrates the cross-network of this invention. The cross-network is designed within an IC chip. The cross-network includes a first circuit 310, a second circuit 320, a third circuit 330, and a fourth circuit 340. Essentially, each circuit 310, 320, 330, and 340 corresponds to a unique address. That is, the addresses of each circuit 310, 320, 330, and 340 are all different.

[0044] The first circuit 310 includes a link allocation device 314, a transmitter Tx1, and a receiver Rx1. The second circuit 320 includes a link allocation device 324, a transmitter Tx2, and a receiver Rx2. The third circuit 330 includes a link allocation device 334, a transmitter Tx3, and a receiver Rx3. The fourth circuit 340 includes a link allocation device 344, a transmitter Tx4, and a receiver Rx4.

[0045] Furthermore, the first circuit 310 further includes a multiplexing device 312 and a link detecting device 316. The second circuit 320 further includes a multiplexing device 322 and a link detecting device 326. The third circuit 330 further includes a multiplexing device 332 and a link detecting device 336. The fourth circuit 340 further includes a multiplexing device 342 and a link detecting device 346. The multiplexing devices 312, 322, 332, and 342, and the link detecting devices 316, 326, 336, and 346 can also be designed externally to circuits 310, 320, 330, and 340.

[0046] For example, each circuit 310, 320, 330, 340 can be one of a control unit, storage unit, processing unit, graphics processing unit, etc. Figure 3A The cross-connection example uses only four circuits, 310, 320, 330, and 340. Of course, those skilled in the art can use any number of circuits to construct a cross-connection. In other words, the number of circuits in the cross-connection must be greater than or equal to two.

[0047] Furthermore, each circuit's transmitter is connected to a corresponding bus, and signals from each circuit are transmitted using this corresponding bus. For example... Figure 3A As shown, transmitter Tx1 of the first circuit 310 is connected to the first bus Bus1. Transmitter Tx2 of the second circuit 320 is connected to the second bus Bus2. Transmitter Tx3 of the third circuit 330 is connected to the third bus Bus3. Transmitter Tx4 of the fourth circuit 340 is connected to the fourth bus Bus4.

[0048] In the first circuit 310, the signals of transmitter Tx1 include data signal D1, address signal A1, clock signal CK1, and command signal CMD1, which are transmitted via the first bus Bus1. In the second circuit 320, the signals of transmitter Tx2 include data signal D2, address signal A2, clock signal CK2, and command signal CMD2, which are transmitted via the second bus Bus2. In the third circuit 330, the signals of transmitter Tx3 include data signal D3, address signal A3, clock signal CK3, and command signal CMD3, which are transmitted via the third bus Bus3. In the fourth circuit 340, the signals of transmitter Tx4 include data signal D4, address signal A4, clock signal CK4, and command signal CMD4, which are transmitted via the fourth bus Bus4.

[0049] Additionally, the receiver of each circuit is coupled to all non-corresponding buses via a multiplexing element, allowing the receiver to control the multiplexing element and be coupled to one of the non-corresponding buses. The receiver Rx1 of the first circuit 310 is coupled to the second bus Bus2, the third bus Bus3, and the fourth bus Bus4 via multiplexing element 312. The receiver Rx2 of the second circuit 320 is coupled to the first bus Bus1, the third bus Bus3, and the fourth bus Bus4 via multiplexing element 322. The receiver Rx3 of the third circuit 330 is coupled to the first bus Bus1, the second bus Bus2, and the fourth bus Bus4 via multiplexing element 332. The receiver Rx4 of the fourth circuit 340 is coupled to the first bus Bus1, the second bus Bus2, and the third bus Bus3 via multiplexing element 342. Of course, multiplexing elements 312, 322, 332, and 342 can also be integrated into the corresponding receivers Rx1, Rx2, Rx3, and Rx4.

[0050] Taking the first circuit 310 as an example, the multiplexing element 312 includes four multiplexers. Each of the four multiplexers selects four signals on a specific bus to the receiver Rx1 according to the selection signal S1. That is, the receiver Rx1 uses the selection signal S1 to control the multiplexing element 312 to selectively couple to one of the second bus Bus2, the third bus Bus3, and the fourth bus Bus4. When the first circuit 310 decides to couple to the second bus Bus2 of the second circuit 320, the receiver Rx1 of the first circuit 310 uses the selection signal S1 to control the four multiplexers in the multiplexing element 312, so that the receiver Rx1 receives the data signal D2, the address signal A2, the clock signal CK2, and the instruction signal CMD2 transmitted by the second bus Bus2. These signals are output by the transmitter Tx2 of the second circuit 320. Similarly, when the first circuit 310 decides to couple to the fourth bus Bus4 of the fourth circuit 340, the receiver Rx1 of the first circuit 310 uses the selection signal S1 to control the four multiplexers in the multiplexing element 312, so that the receiver Rx1 receives the data signal D4, address signal A4, clock signal CK4, and instruction signal CMD4 transmitted by the fourth bus Bus4, and these signals are output by the transmitter Tx4 of the fourth circuit 340. Of course, the control method of the receivers Rx2, Rx3, and Rx4 in the other circuits 320, 330, and 340 is similar to that of the first circuit 310, and will not be described again here.

[0051] In addition, the connection detection element of each circuit is connected to all non-corresponding buses to detect whether other circuits initiate link requests and to notify the connection configuration element. The connection detection element 316 of the first circuit 310 is connected to the second bus (Bus2), the third bus (Bus3), and the fourth bus (Bus4). The connection detection element 326 of the second circuit 320 is connected to the first bus (Bus1), the third bus (Bus3), and the fourth bus (Bus4). The connection detection element 336 of the third circuit 330 is connected to the first bus (Bus1), the second bus (Bus2), and the fourth bus (Bus4). The connection detection element 346 of the fourth circuit 340 is connected to the first bus (Bus1), the second bus (Bus2), and the third bus (Bus3).

[0052] For example, the connection detection element 316 of the first circuit 310 is connected to the second bus (Bus2), the third bus (Bus3), and the fourth bus (Bus4) to detect whether the second circuit 320, the third circuit 330, or the fourth circuit 340 initiates a link request. For example, the link detector (Ld2) of the connection detection element 316 is connected to the second bus (Bus2), the link detector (Ld3) of the connection detection element 316 is connected to the third bus (Bus3), and the link detector (Ld4) of the connection detection element 316 is connected to the fourth bus (Bus4).

[0053] When the second circuit 320 initiates a link request to the first circuit 310, the link detector Ld2 of the first circuit 310 confirms the link request based on the address signal A2, clock signal CK2, and command signal CMD2 on the second bus Bus2. Then, the link detection element 316 notifies the link configuration element 314 of the first circuit 310. Similarly, when the fourth circuit 340 initiates a link request to the first circuit 310, the link detector Ld4 of the first circuit 310 confirms the link request based on the address signal A4, clock signal CK4, and command signal CMD4 on the fourth bus Bus4. Then, the link detection element 316 notifies the link configuration element 314 of the first circuit 310. Of course, the link detection elements 326, 336, and 346 of other circuits 320, 330, and 340 can also detect link requests, and their operation is similar to that of the first circuit 310, which will not be described further here.

[0054] According to an embodiment of the present invention, the link configuration element 314 in the first circuit 310 can be configured with a link priority to determine the order in which the first circuit 310 establishes connections with other circuits 320, 330, and 340. For example, since the link detection element 316 of the first circuit 310 is connected to the second bus Bus2, the third bus Bus3, and the fourth bus Bus4, the three link detectors Ld2, Ld3, and Ld4 in the link detection element 316 may simultaneously receive link requests from the other three circuits 320, 330, and 340. Based on the link priority setting, the link configuration element 314 can determine the order in which the first circuit 310 establishes connections with other circuits 320, 330, and 340. Basically, each link configuration element 314, 324, 334, and 344 has a set link priority. The link configuration elements 314, 324, 334, and 344 in each circuit 310, 320, 330, and 340 can be modified appropriately according to the actual operating conditions.

[0055] Furthermore, the connection detection elements 316, 326, 336, and 346 described above can be integrated into the corresponding connection configuration elements 314, 324, 334, and 344. Similarly, the connection detection elements 316, 326, 336, and 346, and the connection configuration elements 314, 324, 334, and 344 can also be integrated into the corresponding receivers Rx1, Rx2, Rx3, and Rx4. Of course, the design of the connection configuration elements 314, 324, 334, and 344 can also be omitted from the circuits 310, 320, 330, and 340 of the present invention. In this case, the connection sequence between the circuits can be performed according to a preset order.

[0056] According to an embodiment of the present invention, the connection detection element 316 of the first circuit 310 uses an address signal, a clock signal, and an instruction signal to detect whether other circuits initiate a connection request. Of course, those skilled in the art can make appropriate modifications. For example, the connection detection element 316 may also use only the address signal and the instruction signal to detect whether other circuits initiate a connection request.

[0057] Please refer to Figure 3B The diagram illustrates the operational flow of the initiator in the cross-network of this invention. Please refer to... Figure 3C The diagram illustrates the operational flow of the target in the cross-network of this invention. The initiator can be any circuit 310, 320, 330, or 340 in the cross-network. The target can be any circuit 310, 320, 330, or 340 in the cross-network. Furthermore, the initiator does not send connection requests to itself. In the following description, the second circuit 320 will be used as the initiator, and the first circuit 310 as the target, as an example.

[0058] like Figure 3B As shown, when the second circuit 320 wants to establish a connection with the first circuit 310, the second circuit 320 issues a link request (step S351), and the second circuit 320 transmits this link request via the second bus Bus2.

[0059] When a connection request is issued, the transmitter Tx2 of the second circuit 320 controls the clock signal CK2 on the second bus Bus2 to operate, the address signal A2 transmits the address of the first circuit 310, and the instruction signal CMD2 transmits synchronization information (synchronous message, SYC). Afterwards, the receiver Rx2 of the second circuit 320 can use the control signal S2 to control the multiplexer 322, causing the receiver Rx2 to be coupled to the first bus Bus1.

[0060] like Figure 3BAs shown, the second circuit 320 then determines whether it has received a link acceptance from the first circuit 310 (step S352), and the first circuit 310 transmits this link acceptance via the first bus Bus1. Before the timeout (step 353), the second circuit 320 continues to wait for the link acceptance from the first circuit 310. After a specific period of time, if no link acceptance is received, that is, after the timeout (step 353), the second circuit 320 confirms a link failure (step S354).

[0061] After a connection failure, the second circuit 320 can continue to send connection requests to the first circuit 310 again. For example, the second circuit 320 first adjusts the connection priority in the connection configuration element 324, increasing the connection priority of the first circuit 310, and then sends the connection request again. Of course, there is a limit to the number of times the second circuit 320 can send connection requests. When the second circuit 320 fails to send connection requests after reaching the limit, it reports that the connection request failed and will not send any more connection requests.

[0062] Additionally, during the connection acceptance process, the receiver Rx2 of the second circuit 320 or the connection detector Ld1 of the connection detection element 326 receives the clock signal CK1, the address signal A1, and the instruction signal CMD1 on the first bus Bus1. Based on the clock signal CK1, the connection detector Ld1 decodes the address signal A1 and the instruction signal CMD1. Upon confirming that the address signal A1 transmits the address of the second circuit 320 and the instruction signal CMD1 transmits the synchronous acceptance message (SYN ACPT), the second circuit 320 confirms that the first circuit 310 has issued a connection acceptance.

[0063] like Figure 3B As shown, after receiving the connection acceptance (step S352), the second circuit 320 sends a connection acknowledgment (step S355), and the second bus Bus2 transmits this connection acknowledgment to the first circuit 310.

[0064] When a connection confirmation is sent, the transmitter Tx2 of the second circuit 320 controls the clock signal CK2 on the second bus Bus2 to operate, the address signal A2 transmits the address of the first circuit 310, and the instruction signal CMD2 transmits the synchronous acknowledge message (SYC ACK). Therefore, the first circuit 310 can receive the connection confirmation sent by the second circuit 320.

[0065] like Figure 3BAs shown, after issuing a connection confirmation, it indicates that a connection has been established between the second circuit 320 and the first circuit 310 (step S356). At this time, the second circuit 320 can begin to transmit data and instructions to the first circuit 310 using the second bus Bus2.

[0066] During connection establishment, the receiver Rx1 of the first circuit 310 uses the selection signal S1 to control all multiplexers in the multiplexing element 312, transmitting the data signal D2, address signal A2, clock signal CK2, and instruction signal CMD2 of the second bus Bus2 to the receiver Rx1. Therefore, the data and instructions of the second circuit 320 can be output from the transmitter Tx2 and transmitted to the receiver Rx1 of the first circuit 310 via the second bus Bus2. Of course, to terminate the connection, the second circuit 320 only needs to issue a link termination signal to the first circuit 310.

[0067] like Figure 3C As shown, the first circuit 310 can receive link requests from other circuits 320, 330, and 340 at any time (step S361). For example, in the first circuit 310, the link detector Ld2 of the link detection element 316 receives the clock signal CK2, the address signal A2, and the instruction signal CMD2 on the second bus Bus2. Based on the clock signal CK2, the link detector Ld2 decodes the address signal A2 and the instruction signal CMD2. When it is confirmed that the address signal A2 transmits the address of the first circuit 310 and the instruction signal CMD2 transmits the synchronization information SYN, the first circuit 310 confirms that the second circuit 320 has issued a link request. Similarly, the link detector Ld3 of the first circuit 310 can also determine whether the third circuit 330 has issued a link request via the third bus Bus3. Likewise, the link detector Ld4 of the first circuit 310 can also determine whether the fourth circuit 340 has issued a link request via the fourth bus Bus4.

[0068] Furthermore, although the connection detection element 336 of the third circuit 330 and the connection detection element 346 of the fourth circuit 340 are also connected to the second bus Bus2, since the address signal A2 transmits the address of the first circuit 310, the connection detection element 336 of the third circuit 330 and the connection detection element 346 of the fourth circuit 340 will ignore this connection request.

[0069] like Figure 3CAs shown, when the first circuit 310 is in a busy state (step S362) for more than a certain time, that is, when the timeout occurs (step S363), the first circuit 310 cannot send a link acceptance, indicating that the connection has failed (step S364). At this time, the first circuit 310 can adjust the connection priority in the connection configuration element 314 to increase the connection priority of the second circuit 320.

[0070] Additionally, when the first circuit 310 is not in a busy state (step S362), the first circuit 310 issues a link acceptance (step S365), and the first circuit 310 transmits this link acceptance via the first bus Bus1.

[0071] When a connection is initiated / accepted, the transmitter Tx1 of the first circuit 310 controls the clock signal CK1 on the first bus Bus1 to operate, the address signal A1 transmits the address of the second circuit 320, and the instruction signal CMD1 transmits the synchronous acceptance message (SYC ACPT). Afterwards, the receiver Rx1 of the first circuit 310 can use the control signal S1 to control the multiplexing element 316, thereby connecting the receiver Rx1 to the second bus Bus2.

[0072] like Figure 3C As shown, the first circuit 310 then waits for link acknowledgement (step S366). While waiting for link acknowledgement, the receiver Rx1 of the first circuit 310 or the link detector Ld2 of the link detection element 314 receives the clock signal CK2, the address signal A2, and the instruction signal CMD2 on the second bus Bus2. According to the clock signal CK2, the link detector Ld2 decodes the address signal A2 and the instruction signal CMD2. When the address signal A2 confirms that the address of the first circuit 310 is transmitted, and the instruction signal CMD2 confirms that the second circuit 320 has issued a link acknowledgement.

[0073] like Figure 3C As shown, upon receiving the connection confirmation, it indicates that a connection has been established between the second circuit 320 and the first circuit 310 (step S367). At this time, the first circuit 310 can begin to transmit data and instructions to the second circuit 320 using the first bus Bus1.

[0074] During connection establishment, the receiver Rx2 of the second circuit 320 uses the selection signal S2 to control all multiplexers in the multiplexing element 322, transmitting the data signal D1, address signal A1, clock signal CK1, and instruction signal CMD1 of the first bus Bus1 to the receiver Rx2. Therefore, the data and instructions from the first circuit 310 can be output from the transmitter Tx1 and transmitted to the receiver Rx2 of the second circuit 320 via the first bus Bus1. Of course, to terminate the connection, the first circuit 310 only needs to issue a link termination signal to the second circuit 320.

[0075] Depend on Figure 3B and Figure 3C As explained, a three-way handshake is required for two circuits to establish a connection. Taking the second circuit 320 as the initiator and the first circuit 310 as the target, the second circuit 320 transmits a link request to the first circuit 310 via the second bus (Bus2). Next, the first circuit 310 transmits a link acceptance to the second circuit 320 via the first bus (Bus1). Finally, the second circuit 320 transmits a link acknowledgement to the first circuit 310 via the second bus (Bus2), establishing a connection between the two circuits. Therefore, the data and instructions from the second circuit 320 can be output by the transmitter Tx2 and transmitted via the second bus (Bus2) to the receiver Rx1 of the first circuit 310. Similarly, the data and instructions from the first circuit 310 can be output by the transmitter Tx1 and transmitted via the first bus (Bus1) to the receiver Rx2 of the second circuit 320.

[0076] Next, the detailed circuit diagram will be introduced. Please refer to [link / reference]. Figure 4 The diagram shown is a schematic representation of the cross-network of this invention. Essentially, Figure 4 for Figure 3A A simplified version, the two cross-network architectures are similar. In Figure 4 In the cross-connect network, phase conversion devices 421, 422, 423, and 424 are also included. Of course, phase conversion devices 421, 422, 423, and 424 can also be integrated into the corresponding receivers Rx1, Rx2, Rx3, and Rx4.

[0077] The crossover network comprises four circuits (not shown). Similarly, the first circuit includes: transmitter Tx1 and receiver Rx1. The second circuit includes: transmitter Tx2 and receiver Rx2. The third circuit includes: transmitter Tx3 and receiver Rx3. The fourth circuit includes: transmitter Tx4 and receiver Rx4. For example, Figure 4 The connection detection element and connection configuration element of each circuit are integrated into the corresponding receivers Rx1, Rx2, Rx3, and Rx4.

[0078] Each circuit's transmitter is connected to its corresponding bus. For example... Figure 4 As shown, transmitter Tx1 is connected to the first bus Bus1, transmitter Tx2 is connected to the second bus Bus2, transmitter Tx3 is connected to the third bus Bus3, and transmitter Tx4 is connected to the fourth bus Bus4.

[0079] Furthermore, the receiver of each circuit is coupled to all non-corresponding buses via multiplexing and phase-shifting elements, allowing the receiver to be selectively coupled to one of these non-corresponding buses. For example... Figure 4 As shown, multiplexer 312 is controlled by selection signal S1, and receiver Rx1 can be connected to the second bus (Bus2), the third bus (Bus3), or the fourth bus (Bus4). Multiplexer 322 is controlled by selection signal S2, and receiver Rx2 can be connected to the first bus (Bus1), the third bus (Bus3), or the fourth bus (Bus4). Multiplexer 332 is controlled by selection signal S3, and receiver Rx3 can be connected to the first bus (Bus1), the second bus (Bus2), or the fourth bus (Bus4). Multiplexer 342 is controlled by selection signal S4, and receiver Rx4 can be connected to the first bus (Bus1), the second bus (Bus2), or the third bus (Bus3).

[0080] Additionally, connection detection elements 316, 326, 336, and 346 are connected to non-corresponding buses to detect whether other circuits initiate link requests. Furthermore, connection detection elements 316, 326, 336, and 346 are coupled to corresponding connection configuration elements 314, 324, 334, and 344 via phase conversion elements 421, 422, 423, and 424.

[0081] Taking the receiver Rx4 of the fourth circuit as an example, the receiver Rx4 is coupled to all non-corresponding buses Bus1, Bus2, and Bus3 via phase conversion element 424 and multiplexing element 342. Additionally, the connection configuration element 344 is also coupled to all non-corresponding buses Bus1, Bus2, and Bus3 via phase conversion element 424 and connection detection element 346. Furthermore, the connection detection element 346 can receive the address signal A1, clock signal CK1, and command signal CMD1 on the first bus Bus1, the address signal A2, clock signal CK2, and command signal CMD2 on the second bus Bus2, and the address signal A3, clock signal CK3, and command signal CMD3 on the third bus Bus3.

[0082] According to an embodiment of the present invention, when the receiver Rx4 is coupled to the first bus Bus1, the phase conversion element 424 can ensure that the receiver Rx4 receives the correct data signal D1, address signal A1, clock signal CK1, and command signal CMD1. That is, the phase conversion element 424 needs to remove noise on the first bus Bus1 and adjust the phases of the data signal D1, address signal A1, and command signal CMD1 according to the clock signal CK4. This is then passed to the receiver Rx4 to ensure that the receiver Rx4 receives the correct data signal D1, address signal A1, and command signal CMD1.

[0083] Similarly, the link configuration element 344 can also be coupled to the first bus Bus1 via the phase conversion element 424 and the link detection element 346 to ensure that the correct address signal A1, clock signal CK1, and instruction signal CMD1 are received. In this way, the link configuration element 344 can correctly detect the link request.

[0084] Taking phase conversion element 424 as an example, phase conversion element 424 includes: an integrated clock gating device (ICG element) 454 and two phase alignment devices (PA elements) 464 and 466. The integrated clock gating device (ICG element) 454 and the phase alignment device (PA element) 464 are coupled between multiplexing element 342 and Rx4, and the phase alignment device (PA element) 466 is coupled between connection detection element 346 and connection configuration element 344. For example, before receiver Rx4 is coupled to the first bus Bus1, the integrated clock gating device (ICG element) 454 is disabled to temporarily isolate the clock signal CK1 and prevent noise from being generated during the bus switching process. Then, receiver Rx4 controls multiplexing element 342 to switch to the first bus Bus1. Next, the integrated clock gate element (ICG element) 454 is enabled, allowing the clock signal CK1 to pass through it. Then, the phase alignment element (PA element) 464 is used to align the pulse signal CK1, data signal D1, address signal A1, and command signal CMD1 of the first bus Bus1 to CK4. Therefore, the receiver Rx4 can correctly receive all signals on the first bus Bus1. Similarly, the phase alignment element (PA element) 466 operates in the same way, and will not be described further here.

[0085] Alternatively, the phase alignment elements (PA elements) 464 and 466 can also be replaced by clock domain crossing devices (CDC elements). The function of the clock domain crossing device (CDC element) is similar to that of the phase alignment element (PA element) 464, which allows all signals on the first bus Bus1 to be aligned with the clock signal CK4.

[0086] Of course, to save power consumption, a cross-connected bus can be designed, with the bus divided into multiple sections. Depending on the location of the initiator and the target, the circuit's transmitter only sends signals to a portion of the bus. Please refer to [reference needed]. Figure 5 The diagram illustrates another embodiment of the cross-network of the present invention. Compared to Figure 4 cross-network, Figure 5 The cross-network divides the four buses into two parts.

[0087] like Figure 5 As shown, transmitter Tx1 is connected to the left side of the first bus. 1_L Bus on the right side of the first bus 1_R Transmitter Tx2 is connected to the left side of the second bus.2_L With the right side of the second bus 2_R Transmitter Tx3 is connected to the left side of the third bus. 3_L Bus on the right side of the third bus 3_R Transmitter Tx4 is connected to the left side of the fourth bus section. 4_L Bus on the right side of the fourth bus 4_R Depending on the location of the initiator and the target, transmitters Tx1, Tx2, Tx3, and Tx4 use a portion of buses Bus1, Bus2, Bus3, and Bus4 to transmit signals.

[0088] For example, the first circuit initiates a connection request to the fourth circuit. At this point, a three-way handshake is required between the first and fourth circuits before a connection can be established. First, the transmitter Tx1 of the first circuit utilizes the right-hand side of the first bus... 1_R This is used to transmit a link request to the receiver Rx4 of the fourth circuit. Then, the transmitter Tx4 of the fourth circuit uses the left-hand portion of the fourth bus... 4_L This is used to transmit the link acceptance to the receiver Rx1 of the first circuit. Finally, the transmitter Tx1 of the first circuit utilizes the right-hand portion of the first bus... 1_R A link acknowledgment is transmitted to the receiver Rx4 of the fourth circuit. Therefore, a connection is established between the first and fourth circuits.

[0089] Of course, once the connection is established between the first circuit and the fourth circuit, the transmitter Tx1 of the first circuit utilizes the right-side portion of the first bus. 1_R The receiver Rx4 of the fourth circuit transmits data and instructions, and the transmitter Tx4 of the fourth circuit utilizes the left-side portion of the fourth bus. 4_L The receiver Rx1 is used to transmit data and instructions to the first circuit.

[0090] Due to the aforementioned three-way handshake process, and the data and command transmission process after the connection is established. The left side of the first bus... 1_L Bus on the right side of the fourth bus 4_R Since no signals are transmitted, power consumption in the cross-connect network can be saved.

[0091] In the above description, each bus (Bus1, Bus2, Bus3, Bus4) is illustrated by transmitting four signals. Of course, each bus (Bus1, Bus2, Bus3, Bus4) can transmit more or fewer signals depending on actual needs. Taking the first bus (Bus1) of this invention as an example, the address of the data signal D1 and the address of the instruction signal CMD1 are both transmitted using the address signal A1. In other embodiments, two address signals can be designed in the first bus (Bus1), one of which transmits the data address and the other transmits the instruction address. Alternatively, the first bus (Bus1) can be designed to combine the data signal D1, the address signal A1, and the instruction signal CMD1 into a single general signal, so that the first bus (Bus1) only has the clock signal CK1 and the general signal.

[0092] Furthermore, the weights of the connection priority in the connection configuration elements 314, 324, 334, and 344 of circuits 310, 320, 330, and 340 can be set according to actual conditions. For example, when a connection confirmation, connection acceptance, or connection request is received, different weights of connection priority are set. For instance, connection confirmation has the highest priority, connection acceptance has the next highest priority, and connection request has the lowest priority. Moreover, circuits 310, 320, 330, and 340 can also adjust the weights of the connection priority accordingly based on the number of connection failures. Additionally, when the second circuit 320 receives a connection interruption from the first circuit 310, the weight of the connection priority to the first circuit 310 can be reduced.

[0093] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A cross-network, comprising: A first circuit includes a first transmitter and a first receiver; A second circuit includes a second transmitter and a second receiver; A first bus is connected to the first transmitter of the first circuit; A second bus is connected to the second transmitter of the second circuit; A first multiplexing element is connected to the second bus; wherein the first receiver of the first circuit is coupled to the second bus via the first multiplexing element; A second multiplexing element is connected to the first bus; wherein the second receiver of the second circuit is coupled to the first bus via the second multiplexing element; A first connection detection element is coupled to the second bus; wherein, when the second circuit issues a connection request to the first circuit, the first connection detection element detects the connection request via the second bus and notifies the first circuit; and A second connection detection element is coupled to the first bus; wherein, when the first circuit sends the connection request to the second circuit, the second connection detection element detects the connection request by the first bus and notifies the second circuit.

2. The cross-network as described in claim 1, further comprising: A third circuit, comprising a third transmitter and a third receiver; A third bus, connected to the third transmitter of the third circuit; A third multiplexing element is connected to the first bus and the second bus; wherein the third receiver of the third circuit is coupled to the first bus and the second bus via the third multiplexing element; A third connection detection element is coupled to the first bus and the second bus; wherein, when the first circuit issues the connection request to the third circuit, the third connection detection element detects the connection request by the first bus and notifies the third circuit; and when the second circuit issues the connection request to the third circuit, the third connection detection element detects the connection request by the second bus and notifies the third circuit.

3. The cross-connect network of claim 2, wherein the first receiver of the first circuit is coupled to the third bus via the first multiplexing element; the second receiver of the second circuit is coupled to the third bus via the second multiplexing element; the first connection detection element is coupled to the third bus, and when the third circuit issues the connection request to the first circuit, the first connection detection element detects the connection request by the third bus and notifies the first circuit; and the second connection detection element is coupled to the third bus, and when the third circuit issues the connection request to the second circuit, the second connection detection element detects the connection request by the third bus and notifies the second circuit.

4. The cross-network of claim 1, wherein the first circuit further includes a first connection configuration element, wherein when the first connection detection element detects the connection request by the second bus, the first connection configuration element determines whether to establish a connection with the second circuit according to a first connection priority.

5. The cross-network of claim 4, wherein the second circuit further includes a second connection configuration element, wherein when the second connection detection element detects the connection request by the first bus, the second connection configuration element determines whether to establish the connection with the first circuit according to a second connection priority.

6. The cross-network of claim 1, wherein when the first connection detection element detects the connection request by the second bus, the first transmitter of the first circuit selectively sends a connection to the first bus.

7. The cross-connect network of claim 6, wherein if, after a certain period of time, the second circuit is unable to detect the connection acceptance by the first bus, the second circuit confirms a connection failure.

8. The cross-network of claim 6, wherein when the second circuit detects the connection acceptance by the first bus, the second transmitter of the second circuit sends a connection confirmation to the second bus and establishes a connection with the first circuit.

9. The cross network of claim 8, wherein the second connection detection element of the second circuit detects the connection acceptance by the first bus.

10. The cross-network of claim 8, wherein the second receiver of the second circuit controls the second multiplexing element to be coupled to the first bus, and the second receiver of the second circuit detects the connection acceptance by the first bus.

11. The cross network of claim 8, wherein the first connection detection element of the first circuit detects the connection confirmation by the second bus.

12. The cross-network of claim 8, wherein the first receiver of the first circuit controls the first multiplexing element to be coupled to the second bus, and the first receiver of the first circuit detects the connection confirmation by the second bus.

13. The cross-connect network of claim 8, wherein when the second circuit establishes the connection with the first circuit, the first receiver of the first circuit controls the first multiplexer to be coupled to the second bus, and the second receiver of the second circuit controls the second multiplexer to be coupled to the first bus; the first transmitter of the first circuit transmits a first data signal, a first address signal, a first clock signal and a first instruction signal to the second receiver of the second circuit via the first bus; and the second transmitter of the second circuit transmits a second data signal, a second address signal, a second clock signal and a second instruction signal to the first receiver of the first circuit via the second bus.

14. The cross-network of claim 13, wherein when the second circuit issues the connection request to the first circuit, the second address signal includes a first address of the first circuit, and the second instruction signal includes synchronization information.

15. The cross-network of claim 13, wherein when the first transmitter of the first circuit sends the connection to the first bus, the first address signal includes a second address of the second circuit, and the first instruction signal includes a synchronization reception information.

16. The cross-network of claim 13, wherein when the second transmitter of the second circuit sends the connection confirmation to the second bus, the second address signal includes the first address of the first circuit, and the second instruction signal includes a synchronization confirmation message.

17. The cross-connect network of claim 13, wherein when the first circuit sends a connection interruption to the second circuit via the first bus, the connection between the first circuit and the second circuit is terminated; or, when the second circuit sends the connection interruption to the first circuit via the second bus, the connection between the first circuit and the second circuit is terminated.

18. The cross-network of claim 13, wherein the first connection detection element is coupled to the second bus via a phase conversion element for receiving the connection request.

19. The crossover network of claim 13, wherein the first receiver is coupled to the second bus via the first multiplexing element and a phase conversion element, the phase conversion element adjusting the second data signal, the second address signal and the second command signal according to the first clock signal.

20. The cross-network of claim 19, wherein the phase conversion element includes an integrated clock gate element and a phase alignment element, the integrated clock gate element being connected to the first multiplexing element, and the phase alignment element being connected between the integrated clock gate element and the first receiver; or, the phase conversion element includes the integrated clock gate element and a cross-clock domain element, the integrated clock gate element being connected to the first multiplexing element, and the cross-clock domain element being connected between the integrated clock gate element and the first receiver.

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