A data management system and method applied to memory chip testing

Abstract

This invention discloses a data management system and method for memory chip testing, relating to the field of chip testing technology. The invention acquires the memory chip under test from a hard disk drive, collects raw event data during the testing process and generates standard event data, compresses it according to the testing process sequence to obtain stage status data, and connects adjacent stages into directed stage pairs. It extracts the deviation values ​​of preceding and following terms, calculates the forward sequence ratio, response enhancement value, average deviation value of the preceding term, and average deviation value of the following term to obtain the influence relationship; filters effective influence relationships and splices them into candidate influence chains according to the testing process sequence; combines the link stability value and hard disk anomaly coverage value to calculate the link attribution value, determines the main influence chain, and outputs test conclusions including chip identity, region, environmental conditions, initial anomaly type, and associated hard disk performance. This invention can achieve quantitative localization of abnormal links in the testing process, improving the efficiency of memory chip test data analysis.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, specifically a data management system and method for testing memory chips. Background Technology

[0002] With the continued application of hard disk drives (HDDs) in data storage, backup archiving, and industrial equipment, the requirements for operational stability and data access reliability of their internal control circuits are constantly increasing. The memory chips in HDDs typically handle functions such as firmware storage, parameter storage, and data caching; therefore, they need to be tested to confirm their ability to stably support the hard drive control system during power-on, operation, read / write, and long-term use.

[0003] However, in actual testing, the abnormal behavior of hard disk drives (HDDs) is often subtle and intermittent, such as occasional unrecognizable events or abnormal interruptions during operation. When judging a single component or functional part, it is easy to encounter problems such as unclear sources of abnormality and insufficient basis for localization. Especially when memory chips, controllers, power interfaces, and the overall operating status of the hard drive can all affect the device's performance, existing testing processes cannot fully reflect the inherent influence between different components, resulting in low fault analysis efficiency and hindering the accurate evaluation of the reliability of memory chips in actual HDD operating scenarios. Summary of the Invention

[0004] The purpose of this invention is to provide a data management system and method for testing memory chips, in order to solve the problems raised in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A data management method for memory chip testing, comprising the following steps: The test memory chip is obtained from the mechanical hard disk, raw event data is collected during the test, and the raw event data is preprocessed to obtain standard event data. The mechanical hard drive mainly consists of disk platters, read / write heads, spindle motor, voice coil motor, hard drive control board, controller chip, cache chip, firmware storage chip, power management circuit, etc.; the memory chip under test is a semiconductor storage device in the internal control circuit of the mechanical hard drive used to assist the operation of the hard drive. Furthermore, the chip identifier of the memory chip under test, the identifier of the mechanical hard drive to which it belongs, and the circuit location of the chip are matched to obtain the chip identity; The circuit location of the chip refers to the comprehensive identification of the physical installation location and electrical connection location of the memory chip under test in the mechanical hard disk control circuit. It can usually be determined by the circuit board number, board surface location, silkscreen reference number, package pad location, functional partition, connected controller port, accessed bus channel, power domain, and relationship with adjacent key components. In a mechanical hard drive, memory chips may be located on the hard drive control board or integrated inside the hard drive controller. Their circuit location is used to distinguish the actual ownership of different memory devices in the same mechanical hard drive. For example, a certain DRAM cache chip is located at U3 bit number on the front of the control board near the main control chip and is connected to the main control chip through the data bus. A certain Flash firmware chip is located at U5 bit number on the back of the control board and is connected to the main control chip through the SPI interface. A power-on operation is performed on the memory chip under test. The process from the start to the end of the power-on operation is taken as a test cycle of the current test process. The test time in the test cycle is sampled at a preset frequency. The test status value and the environmental conditions of the memory chip under test are obtained based on the test time. At the end of each test round, record the test type, the area of ​​the memory chip under test in the hard disk, and the performance of the hard disk; the hard disk performance includes normal hard disk performance and abnormal hard disk performance; each test round includes several test types; Power-on operation refers to the complete process of powering on the memory chip under test in the mechanical hard disk test platform, including power supply, reset, initialization, test execution, and test termination. Specifically, the mechanical hard disk containing the memory chip under test is first connected to the test fixture or test jig, and then power is supplied to the hard disk control board according to the preset power sequence, so that the main control chip, cache chip, firmware storage area, parameter storage area and other related circuits enter the working state. The current test cycle is established from the moment of power supply and is closed when all test types in the test cycle are completed, the mechanical hard disk enters the end state or the test platform issues a termination command. The testing platform starts a timer after the test round begins and generates continuous sampling points according to a preset frequency. For example, it records the test moment once every fixed time. Each test moment serves as a time index for the test status value and environmental conditions, which is used to indicate the order in which the test data occurs in the current test round. Preferably, the test types can be power-on identification test, storage access test, cache write test, cache read verification test, parameter verification test, firmware verification test, and whole-machine continuous read and write test, etc. The test status values ​​are state quantities that can be collected, compared, and calculated for each test type. For example, the test status values ​​in the power-on identification test can be identification response time, initialization completion flag, and number of identification errors; the test status values ​​in the cache write test can be write time, number of write failures, and number of write verification errors; the test status values ​​in the cache read verification test can be the number of read errors, number of CRC check failures, and number of read data inconsistencies; the test status values ​​in the parameter verification test can be the number of parameter matching failures and the number of verification differences; the test status values ​​in the firmware verification test can be the number of firmware verification errors and the checksum difference value; and the test status values ​​in the whole machine continuous read and write test can be the number of read and write errors, the number of response timeouts, and the quantized value corresponding to the disk drop event flag. The area refers to the data area or functional area of ​​the memory chip that this round of testing is applied to. For example, firmware verification test corresponds to the firmware area, parameter verification test corresponds to the parameter area, cache write test and cache read verification test correspond to the cache area, and controller running status test corresponds to the temporary state area, etc. The performance of a mechanical hard drive (HDD) is the result of its operation at the system level after a test cycle. Specifically, it includes whether the HDD performs normally or abnormally. During operation, at the end of the test cycle, the HDD performance should be determined based on whether it has been recognized, whether the connection has been maintained, whether read and write operations have been completed, whether there has been an abnormal interruption, whether there has been a verification error or response timeout. If the HDD completes the test task and no preset abnormal events occur, it is recorded as performing normally. If the HDD fails to be recognized, drops, fails to read or write, experiences an abnormal interruption, or returns an error status, it is recorded as performing abnormally. The test type, test status value, test round, environmental conditions, test time, region, hard disk performance, and chip identity of the memory chip under test are associated and stored as the original event data. The preprocessing process includes: According to the test type, the state value threshold, fluctuation range, and fluctuation threshold of the test state value are retrieved. Based on the state value threshold, the test state value is divided into normal data and abnormal data. The test time when the normal data and abnormal data are converted is taken as the fluctuation time. If the time difference between two fluctuation times is greater than the fluctuation range, and there are more than a certain number of other fluctuation times between the two fluctuation times, then the test state value between the two fluctuation times is taken as the fluctuation data. The normal data, abnormal data, and fluctuation data are stored as state value types in association with the original event data to obtain the standard event data.

[0006] Among them, the status value threshold is the judgment boundary used to determine whether the test status value is within the normal range. For example, the power-on recognition test can correspond to the recognition response time threshold, the cache write test can correspond to the write error count threshold, the cache read verification test can correspond to the bit error count threshold, and the parameter verification test can correspond to the parameter difference count threshold. The standard event data is compressed according to the order of the test process to obtain the stage status data, and the adjacent stages of the stage status data are connected into directed stage pairs. Furthermore, the standard event data is grouped according to chip identity and test round to obtain round event data, and the round event data is arranged in order from early to late according to the test time to obtain time-series event data; Grouping sequential event data of the same test type that occur consecutively into the same test phase yields phase event data. The number of test state values ​​corresponding to normal data, abnormal data and fluctuation data in the event data of each stage are counted respectively to obtain the normal quantity, abnormal quantity and fluctuation quantity of the stage in turn. The sum of the normal quantity, abnormal quantity and fluctuation quantity of the stage is taken as the stage data quantity. The ratios of normal quantity, abnormal quantity, and fluctuation quantity in a process to the total amount of data in that process are respectively used as the normal rate, abnormal rate, and fluctuation rate of the process. The deviation value of the process is calculated based on the process abnormality rate, process volatility rate, and process normality rate. ; Where D represents the deviation value of the process, P a P represents the abnormality rate of the process. f P represents the volatility of the process. n W represents the normality rate of the process. a W represents the outlier weight. f The value represents the volatility weight; the abnormal weight is greater than the volatility weight, and the sum of the abnormal weight and the volatility weight is 1; 1-p n Used to reduce the impact of minor anomalies or fluctuations on subsequent link attribution; The process status data includes time-series event data and corresponding process data volume, process normal volume, process abnormal volume, process fluctuation volume, process abnormality rate, process fluctuation rate, and process deviation value.

[0007] Furthermore, the earliest test moment is extracted from the time-series event data corresponding to the status data of each stage as the stage start moment, and the earliest test moment when abnormal or fluctuating data appears is extracted as the stage deviation moment. Arrange the stage status data of stages with the same chip identity, test round, region, and environmental conditions in order from the earliest to the latest according to the stage start time to obtain the stage status sequence; Connect two adjacent stage state data in the stage state sequence to obtain a directed stage pair; the directed stage pair includes the preceding stage state data and the following stage state data, wherein the stage start time of the preceding stage state data is earlier than the stage start time of the following stage state data.

[0008] Obtain the influence relationship between directed link pairs, splice the directed link pairs into candidate influence chains according to the influence relationship, and calculate the link attribution value of each candidate influence chain based on the hard disk. Furthermore, the deviation values ​​of the preceding and following stage state data are extracted from the directed stage pairs to obtain the preceding deviation value and the following deviation value. Directed link pairs are categorized according to chip identity, test type, region, and environmental conditions to obtain directed link pairs of the same type, and the number of directed link pairs of the same type is taken as the number of link pairs. The directed link pairs whose link deviation time of the preceding link state data is earlier than the link deviation time of their corresponding following link state data are regarded as positive directed link pairs, and the number of positive directed link pairs in the same type is counted as the number of positive link pairs. The average deviation values ​​of the preceding and following terms in the same type of directed element pairs are calculated separately to obtain the average deviation value of the preceding term and the average deviation value of the following term; The same type of directed link pairs whose deviation value of the preceding term is greater than the average deviation value of the preceding term are regarded as high deviation directed link pairs, and other same type of directed link pairs are regarded as low deviation directed link pairs; the subsequent deviation values ​​of the high deviation directed link pairs and the low deviation directed link pairs are averaged to obtain the high deviation response value and the low deviation response value, and the difference between the high deviation response value and the low deviation response value is taken as the response enhancement value. The response enhancement value represents the increase in the average deviation of the subsequent test stage when the preceding test stage changes from a low deviation state to a high deviation state. A positive response enhancement value indicates that the deviation of the subsequent test stage increases as the deviation of the preceding test stage increases. A response enhancement value close to 0 indicates that the difference between the deviation of the preceding test stage and the deviation of the subsequent test stage is relatively weak. A negative response enhancement value indicates that the average deviation level of the subsequent test stage corresponding to a high preceding test stage deviation is lower than the average deviation level of the subsequent test stage corresponding to a low preceding test stage deviation. The proportion of the number of positive link pairs to the total number of link pairs is taken as the positive order proportion; The product of the forward order ratio, response enhancement value, average deviation of the preceding term, and average deviation of the following term is taken as the link influence value; and the link influence value is associated with the corresponding directed link pair to obtain the influence relationship.

[0009] Among them, the link influence value is used to comprehensively represent the influence strength of the preceding link on the following link in a directional link of the same type; when any factor in calculating the link influence value is low, the final link influence value will be reduced, thereby reducing the interference of accidental sequence, one-sided anomaly or weak deviation data on the judgment of influence relationship; Furthermore, influence relationships with positive values ​​for the impact value of a link are considered valid influence relationships; Specifically, only when the value of the impact value of a link is greater than zero does it indicate that the deviation of the preceding link occurs before the deviation of the following link in time, and that the deviation of the following link also increases when the deviation of the preceding link increases. At the same time, both the preceding and following links have a certain basis for deviation. If the value of the impact value of a link is zero or negative, it means that the relationship lacks a basis for order, deviation, or response enhancement. Continuing to use it for candidate impact chain splicing will reduce the accuracy of subsequent link attribution. Therefore, impact relationships with positive values ​​of impact value are selected as valid impact relationships. The test type of the state data of the preceding link in the effective influence relationship is used as the head type, and the test type of the state data of the following link is used as the tail type. By concatenating different effective influence relationships with the same head and tail types in the order of the testing process, the candidate influence chain is obtained.

[0010] Furthermore, the process of calculating the link attribution value for each candidate influence chain based on the hard disk drive includes: Extract the head type of the first valid influence relationship in the candidate influence chain and the tail type of each valid influence relationship to form a candidate chain type sequence; Extract the chip identity, region, environmental conditions, and candidate chain type sequence corresponding to the candidate influence chain to obtain candidate chain matching data; multiply the influence values ​​of all links in the candidate influence chain corresponding to the same candidate chain matching data to obtain the link continuity value; The number of effective influence relationships in the candidate influence chains is counted to obtain the candidate chain length; the link continuity value is square-rooted according to the candidate chain length to obtain the link stability value; Match the candidate impact chains in each test round with the candidate chain matching data. If the candidate impact chains in the current test round have the same chip identity, region, environmental conditions and candidate chain type sequence, then the current test round is taken as the link occurrence round. In the rounds in which the hard drive exhibits abnormal behavior, the rounds in which the hard drive exhibits abnormal behavior are considered the rounds in which the hard drive exhibits abnormal behavior. The total number of abnormal test rounds is obtained by counting the number of abnormal test rounds. The total number of abnormal test rounds is obtained by counting the number of test rounds in which the chip identity, region, and environmental conditions are the same and the hard drive shows abnormal performance. The ratio of the number of abnormal link rounds to the total number of abnormal hard disk rounds is used as the hard disk abnormality coverage value; The link attribution value is obtained by multiplying the link stability value corresponding to the matching data of the same candidate link with the disk abnormal coverage value.

[0011] The main influence chain is obtained based on the link attribution value, and the test conclusion is obtained based on the main influence chain.

[0012] Furthermore, candidate impact chains whose link attribution values ​​reach a preset attribution threshold are selected as candidate impact chains; among the candidate impact chains, the candidate impact chain with the largest disk abnormal coverage value is extracted as the main impact chain. If there are multiple candidate impact chains with the same abnormal hard drive coverage value, the candidate impact chain with the largest link attribution value will be taken as the main impact chain. Extract candidate chain matching data corresponding to the main impact chain to obtain main chain matching data. Extract candidate chain type sequence from the main chain matching data. Take the first test type in the candidate chain type sequence as the first abnormal type. Extract hard disk performance in the link abnormal round corresponding to the main impact chain to obtain associated hard disk performance. The chip identity, region, and environmental conditions in the main chain matching data are correlated with the abnormal initial launch type and the performance of the associated hard drive, and used as the test conclusion.

[0013] A data management system for memory chip testing, comprising a data acquisition module, a state compression module, a link attribution module, and a conclusion generation module; The data acquisition module is used to acquire the memory chip under test in the mechanical hard disk, collect and preprocess the raw event data during the test process, and obtain standard event data. The state compression module is used to compress standard event data according to the order of the test process to obtain stage state data and form directed stage pairs. The link attribution module is used to obtain the influence relationship between directed link pairs, splice the directed link pairs into candidate influence chains, and calculate the link attribution value of each candidate influence chain. The conclusion generation module is used to determine the main influence chain based on the link attribution value and generate test conclusions based on the main influence chain.

[0014] The output of the data acquisition module is connected to the input of the state compression module; the output of the state compression module is connected to the input of the link attribution module; and the output of the link attribution module is connected to the input of the conclusion generation module.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention compresses test data into stage status data and calculates stage deviation values ​​based on stage normality rate, stage abnormality rate, and stage volatility rate, so that the state changes of each test stage can be presented as quantitative results, reducing the interference of accidental anomalies at a single sampling point on the judgment results and improving the stability of test stage anomaly evaluation.

[0016] 2. This invention constructs directed link pairs and calculates the link influence value by combining the forward sequence ratio, response enhancement value, average deviation value of the preceding term, and average deviation value of the following term. This allows the sequential deviation relationship and response change between adjacent test links to be quantitatively expressed, thereby improving the accuracy of judging the influence relationship between different test links.

[0017] 3. This invention constructs a candidate influence chain by splicing effective influence relationships together, and calculates the link attribution value by combining the link stability value and the hard disk anomaly coverage value. The main influence chain is then determined from the candidate influence chains, so that memory chip test anomalies can be matched with the initial anomaly type and associated hard disk performance, thereby improving fault location efficiency. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a data management method for memory chip testing according to the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Example: Figure 1 As shown, the present invention provides a technical solution, a data management method for memory chip testing, the method comprising the following steps: The test memory chip is obtained from the mechanical hard disk, raw event data is collected during the test, and the raw event data is preprocessed to obtain standard event data. The chip's identity is obtained by matching its chip identifier, the hard disk identifier it belongs to, and the circuit location where the chip is located. In this embodiment, the DRAM cache chip in HDD01 is selected as the memory chip to be tested. The chip is identified as M01, the mechanical hard disk to which it belongs is identified as HDD01, and the chip is located at the U3 position on the front of PCB01. The U3 position is close to the main control chip and connected to the data bus, so as to clearly distinguish the cache chip from the firmware storage chip and the parameter storage chip, and obtain the chip identity M01-HDD01-PCB01-U3. A power-on operation is performed on the memory chip under test. The process from the start to the end of the power-on operation is taken as a test cycle of the current test process. The test time in the test cycle is sampled at a preset frequency. The test status value and the environmental conditions of the memory chip under test are obtained based on the test time. In this embodiment, T1 to T6 are set as test rounds. In each test round, the power-on identification test, cache write test, cache read verification test, and whole machine continuous read and write test are executed in sequence. The test environment temperature is 55°C and the sampling frequency is 1Hz. The test state changes are usually on the order of seconds. 1Hz can record the continuous change trend and avoid forming too large a amount of raw event data. At the end of each test round, record the test type, the area of ​​the memory chip under test in the hard disk, and the performance of the hard disk; the hard disk performance includes normal hard disk performance and abnormal hard disk performance; each test round includes several test types; For example, the test status value for cache write test is the number of write verification errors, the test status value for cache read verification test is the number of CRC check failures, and the test status value for whole machine continuous read and write test is the number of response timeouts. The test area is the cache area, and the hard drive performance is determined based on whether recognition failure, disk drop, read / write failure, abnormal interruption, or return error status occurs in the current test round. T1, T2, T4, and T6 are recorded as abnormal hard drive performance, and T3 and T5 are recorded as normal hard drive performance. The test type, test status value, test round, environmental conditions, test time, region, hard disk performance, and chip identity of the memory chip under test are associated and stored as the original event data. For example, a representative record of the original event data is: chip identity M01-HDD01-PCB01-U3, test round T1, test time 8s, test type cache write test, test status value 2, environmental conditions 55℃, area cache, hard drive performance abnormal; another representative record is: chip identity M01-HDD01-PCB01-U3, test round T3, test time 28s, test type cache read verification test, test status value 0, environmental conditions 55℃, area cache, hard drive performance normal; The preprocessing process includes: According to the test type, the state value threshold, fluctuation range, and fluctuation threshold of the test state value are retrieved. Based on the state value threshold, the test state value is divided into normal data and abnormal data. The test time when the normal data and abnormal data are converted is taken as the fluctuation time. If the time difference between two fluctuation times is greater than the fluctuation range, and there are more than a certain number of other fluctuation times between the two fluctuation times, then the test state value between the two fluctuation times is taken as the fluctuation data. The normal data, abnormal data, and fluctuation data are stored as state value types in association with the original event data to obtain the standard event data.

[0021] In this embodiment, for example, the threshold values ​​for the status values ​​of cache write test, cache read verification test, and whole machine continuous read and write test are all set to 1. When the test status value is less than or equal to 1, it is recorded as normal data, and when the test status value is greater than 1, it is recorded as abnormal data. This threshold value can distinguish between occasional sporadic errors and continuous anomalies. The fluctuation range is set to 3s, and the fluctuation threshold is set to 2. The reason is that a single switch of less than 3s is easily caused by sampling jitter, while a number of switches exceeding 2 can better reflect the continuous change of the state value between normal and abnormal data. In the T1 cache write test, the normal quantity of the preprocessed stage was 6, the abnormal quantity of the stage was 3, the fluctuation quantity of the stage was 1, and the data quantity of the stage was 10. The standard event data is compressed according to the order of the test process to obtain the stage status data, and the adjacent stages of the stage status data are connected into directed stage pairs. The standard event data is grouped according to chip identity and test round to obtain round event data, and the round event data is arranged in order from early to late test time to obtain time-series event data; Grouping sequential event data of the same test type that occur consecutively into the same test phase yields phase event data. The number of test state values ​​corresponding to normal data, abnormal data and fluctuation data in the event data of each stage are counted respectively to obtain the normal quantity, abnormal quantity and fluctuation quantity of the stage in turn. The sum of the normal quantity, abnormal quantity and fluctuation quantity of the stage is taken as the stage data quantity. The ratios of normal quantity, abnormal quantity, and fluctuation quantity in a process to the total amount of data in that process are respectively used as the normal rate, abnormal rate, and fluctuation rate of the process. The deviation value of the process is calculated based on the abnormality rate, the volatility rate, and the normality rate of the process. In this embodiment, an anomaly weight W is exemplarily set. a The fluctuation weight W is 0.7. f It is 0.3; In the T1 cache write test, the normal quantity of the stage was 6, the abnormal quantity of the stage was 3, the fluctuation of the stage was 1, the data volume of the stage was 10, the normal rate of the stage was 0.60, the abnormal rate of the stage was 0.30, the fluctuation rate of the stage was 0.10, and the deviation of the stage was 0.096. In the T1 cache read verification test, the normal rate was 0.50, the abnormal rate was 0.40, the fluctuation rate was 0.10, and the deviation rate was 0.155. In the T1's continuous read / write test, the normal rate was 0.40%, the abnormal rate was 0.50%, the fluctuation rate was 0.10%, and the deviation rate was 0.228. The process status data includes time-series event data and corresponding process data volume, process normal volume, process abnormal volume, process fluctuation volume, process abnormality rate, process fluctuation rate, and process deviation value.

[0022] Extract the earliest test time from the time-series event data corresponding to the status data of each stage as the stage start time, and extract the earliest test time when abnormal or fluctuating data appears as the stage deviation time. Arrange the stage status data of stages with the same chip identity, test round, region, and environmental conditions in order from the earliest to the latest according to the stage start time to obtain the stage status sequence; Connect two adjacent stage state data in the stage state sequence to obtain a directed stage pair; the directed stage pair includes the preceding stage state data and the following stage state data, wherein the stage start time of the preceding stage state data is earlier than the stage start time of the following stage state data.

[0023] In T1 of this embodiment, the cache write test starts at 0s and deviates from the test at 3s; the cache read verification test starts at 10s and deviates from the test at 13s; the whole machine continuous read and write test starts at 20s and deviates from the test at 24s. After sorting by the start time of each stage, two directed stage pairs are formed, from cache write test to cache read verification test and from cache read verification test to continuous read and write test of the whole machine. Obtain the influence relationship between directed link pairs, splice the directed link pairs into candidate influence chains according to the influence relationship, and calculate the link attribution value of each candidate influence chain based on the hard disk. Extract the deviation values ​​of the preceding and following stage state data from the directed stage pair to obtain the preceding deviation value and the following deviation value. Directed link pairs are categorized according to chip identity, test type, region, and environmental conditions to obtain directed link pairs of the same type, and the number of directed link pairs of the same type is taken as the number of link pairs. The directed link pairs whose link deviation time of the preceding link state data is earlier than the link deviation time of their corresponding following link state data are regarded as positive directed link pairs, and the number of positive directed link pairs in the same type is counted as the number of positive link pairs. The average deviation values ​​of the preceding and following terms in the same type of directed element pairs are calculated separately to obtain the average deviation value of the preceding term and the average deviation value of the following term; In this embodiment, taking the cache write test to cache read verification test as an example, the deviation values ​​of the first term corresponding to T1 to T6 are 0.096, 0.080, 0.012, 0.088, 0.016, and 0.072, respectively, and the deviation values ​​of the second term are 0.155, 0.140, 0.025, 0.150, 0.030, and 0.130, respectively. The average deviation value of the first term is 0.0607, and the average deviation value of the second term is 0.1050. The same type of directed link pairs whose deviation value of the preceding term is greater than the average deviation value of the preceding term are regarded as high deviation directed link pairs, and other same type of directed link pairs are regarded as low deviation directed link pairs; the subsequent deviation values ​​of the high deviation directed link pairs and the low deviation directed link pairs are averaged to obtain the high deviation response value and the low deviation response value, and the difference between the high deviation response value and the low deviation response value is taken as the response enhancement value. In the same directed element pair in this embodiment, the deviation values ​​of the preceding terms of T1, T2, T4, and T6 are greater than 0.0607, and they are classified as high deviation directed element pairs with a high deviation response value of 0.1438; T3 and T5 are classified as low deviation directed element pairs with a low deviation response value of 0.0275 and a response enhancement value of 0.1163. The proportion of the number of positive link pairs to the total number of link pairs is taken as the positive order proportion; In this embodiment, the number of stages from cache write test to cache read verification test is 6, the number of forward stages is 5, and the forward order ratio is 0.8333. The product of the forward order ratio, response enhancement value, average deviation of the preceding term, and average deviation of the following term is taken as the link influence value; and the link influence value is associated with the corresponding directed link pair to obtain the influence relationship.

[0024] In this embodiment, the impact value of the process from cache write test to cache read verification test is 0.000617, the impact value of the process from cache read verification test to whole machine continuous read and write test is 0.002248, and the impact value of the process from parameter verification test to whole machine continuous read and write test is 0.001300. A positive value for the impact value of a link is considered an effective impact relationship. Since the impact values ​​of the stages from cache write test to cache read verification test, cache read verification test to whole machine continuous read and write test, and parameter verification test to whole machine continuous read and write test are all greater than 0, the above impact relationships are considered as valid impact relationships; the impact value of the stage from power-on identification test to cache write test is 0, and it did not enter the candidate impact chain concatenation. The test type of the state data of the preceding link in the effective influence relationship is used as the head type, and the test type of the state data of the following link is used as the tail type. By concatenating different effective influence relationships with the same head and tail types in the order of the testing process, the candidate influence chain is obtained.

[0025] In this embodiment, according to the connection relationship between the head type and the tail type, the cache write test to the cache read verification test and the cache read verification test to the whole machine continuous read and write test are spliced ​​together to obtain the candidate influence chain L1. The candidate chain type sequence is cache write test, cache read verification test, and whole machine continuous read and write test. Meanwhile, the parameter verification test to the whole machine continuous read and write test is used as an example as a candidate influence chain L2, and the candidate chain type sequence is parameter verification test and whole machine continuous read and write test; The process of calculating the link attribution value for each candidate influence chain based on a hard disk drive includes: Extract the head type of the first valid influence relationship in the candidate influence chain and the tail type of each valid influence relationship to form a candidate chain type sequence; Extract the chip identity, region, environmental conditions, and candidate chain type sequence corresponding to the candidate influence chain to obtain candidate chain matching data; multiply the influence values ​​of all links in the candidate influence chain corresponding to the same candidate chain matching data to obtain the link continuity value; The number of effective influence relationships in the candidate influence chains is counted to obtain the candidate chain length. The chain continuity value is then square-rooted according to the candidate chain length to obtain the chain stability value, in order to reduce the excessive suppression of long chains due to multiple multiplications. ; Where S represents the link stability value, C represents the link continuity value, and n represents the candidate link length; In this embodiment, the link continuity value of L1 is 0.00000139, the candidate link length is 2, and the link stability value is 0.001179; the link continuity value of L2 is 0.001300, the candidate link length is 1, and the link stability value is 0.001300. Match the candidate impact chains in each test round with the candidate chain matching data. If the candidate impact chains in the current test round have the same chip identity, region, environmental conditions and candidate chain type sequence, then the current test round is taken as the link occurrence round. In the rounds in which the hard drive exhibits abnormal behavior, the rounds in which the hard drive exhibits abnormal behavior are considered the rounds in which the hard drive exhibits abnormal behavior. The total number of abnormal test rounds is obtained by counting the number of abnormal test rounds. The total number of abnormal test rounds is obtained by counting the number of test rounds in which the chip identity, region, and environmental conditions are the same and the hard drive shows abnormal performance. The ratio of the number of abnormal link rounds to the total number of abnormal hard disk rounds is used as the hard disk abnormality coverage value; The link attribution value is obtained by multiplying the link stability value corresponding to the matching data of the same candidate link with the disk abnormal coverage value.

[0026] In T1 to T6 of this embodiment, the total number of rounds of hard disk anomalies is 4. L1 appears as a link in T1, T2, T4 and T6 and corresponds to hard disk anomalies. The number of link anomaly rounds is 4, the hard disk anomaly coverage value is 1.0000, and the link attribution value is 0.001179. The hard disk anomaly coverage value corresponding to L2 is 0.5000, and the link attribution value is 0.000650.

[0027] The main influence chain is obtained based on the link attribution value, and the test conclusion is obtained based on the main influence chain.

[0028] Candidate impact chains whose link attribution values ​​reach a preset attribution threshold are selected as candidate impact chains; among the candidate impact chains, the candidate impact chain with the largest disk abnormal coverage value is extracted as the main impact chain. For example, the preset attribution threshold is set to 0.000500. Both L1 and L2 reach the preset attribution threshold and are both selected as candidate influence chains. If there are multiple candidate impact chains with the same abnormal hard drive coverage value, the candidate impact chain with the largest link attribution value will be taken as the main impact chain. Extract candidate chain matching data corresponding to the main impact chain to obtain main chain matching data. Extract candidate chain type sequence from the main chain matching data. Take the first test type in the candidate chain type sequence as the first abnormal type. Extract hard disk performance in the link abnormal round corresponding to the main impact chain to obtain associated hard disk performance. The chip identity, region, and environmental conditions in the main chain matching data are correlated with the abnormal initial launch type and the performance of the associated hard drive, and used as the test conclusion.

[0029] In this embodiment, since the disk abnormality coverage value of L1 is 1.0000, which is greater than the disk abnormality coverage value of L2 is 0.5000, L1 is determined to be the main influence chain; the test conclusion is that the chip identity is M01-HDD01-PCB01-U3, the area cache area, the environmental condition is 55℃, the abnormal first type cache write test, and the associated disk shows abnormal disk performance.

[0030] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A data management method for memory chip testing, characterized in that: The method includes the following steps: The test memory chip is obtained from the mechanical hard disk, raw event data is collected during the test, and the raw event data is preprocessed to obtain standard event data. The standard event data is compressed according to the order of the test process to obtain the stage status data, and the adjacent stages of the stage status data are connected into directed stage pairs. Obtain the influence relationship between directed link pairs, splice the directed link pairs into candidate influence chains according to the influence relationship, and calculate the link attribution value of each candidate influence chain based on the hard disk. The main influence chain is obtained based on the link attribution value, and the test conclusion is obtained based on the main influence chain.

2. The data management method for memory chip testing according to claim 1, characterized in that, The process of collecting raw event data during the test and preprocessing the raw event data to obtain standard event data includes: The chip's identity is obtained by matching its chip identifier, the hard disk identifier it belongs to, and the circuit location where the chip is located. A power-on operation is performed on the memory chip under test. The process from the start to the end of the power-on operation is taken as a test cycle of the current test process. The test time in the test cycle is sampled at a preset frequency. The test status value and the environmental conditions of the memory chip under test are obtained based on the test time. At the end of each test round, record the test type, the area of ​​the memory chip under test in the hard disk, and the performance of the hard disk; the hard disk performance includes normal hard disk performance and abnormal hard disk performance; each test round includes several test types; The test type, test status value, test round, environmental conditions, test time, region, hard disk performance, and chip identity of the memory chip under test are associated and stored as the original event data. The preprocessing process includes: According to the test type, the state value threshold, fluctuation range, and fluctuation threshold of the test state value are retrieved. Based on the state value threshold, the test state value is divided into normal data and abnormal data. The test time when the normal data and abnormal data are converted is taken as the fluctuation time. If the time difference between two fluctuation times is greater than the fluctuation range, and there are more than a certain number of other fluctuation times between the two fluctuation times, then the test state value between the two fluctuation times is taken as the fluctuation data. The normal data, abnormal data, and fluctuation data are stored as state value types in association with the original event data to obtain the standard event data.

3. The data management method for memory chip testing according to claim 2, characterized in that, The process of compressing standard event data according to the order of the testing process to obtain the stage status data includes: The standard event data is grouped according to chip identity and test round to obtain round event data, and the round event data is arranged in order from early to late test time to obtain time-series event data; Grouping sequential event data of the same test type that occur consecutively into the same test phase yields phase event data. The number of test state values ​​corresponding to normal data, abnormal data and fluctuation data in the event data of each stage are counted respectively to obtain the normal quantity, abnormal quantity and fluctuation quantity of the stage in turn. The sum of the normal quantity, abnormal quantity and fluctuation quantity of the stage is taken as the stage data quantity. The ratios of normal quantity, abnormal quantity, and fluctuation quantity in a process to the total amount of data in that process are respectively used as the normal rate, abnormal rate, and fluctuation rate of the process. The deviation value of the process is calculated based on the abnormality rate, the volatility rate, and the normality rate of the process. The process status data includes time-series event data and corresponding process data volume, process normal volume, process abnormal volume, process fluctuation volume, process abnormality rate, process fluctuation rate, and process deviation value.

4. The data management method for memory chip testing according to claim 3, characterized in that, The process of connecting adjacent links in the link state data into directed link pairs includes: Extract the earliest test time from the time-series event data corresponding to the status data of each stage as the stage start time, and extract the earliest test time when abnormal or fluctuating data appears as the stage deviation time. Arrange the stage status data of stages with the same chip identity, test round, region, and environmental conditions in order from the earliest to the latest according to the stage start time to obtain the stage status sequence; Connect two adjacent stage state data in the stage state sequence to obtain a directed stage pair; the directed stage pair includes the preceding stage state data and the following stage state data, wherein the stage start time of the preceding stage state data is earlier than the stage start time of the following stage state data.

5. A data management method for memory chip testing according to claim 4, characterized in that, The process of obtaining the influence relationship between directed links includes: Extract the deviation values ​​of the preceding and following stage state data from the directed stage pair to obtain the preceding deviation value and the following deviation value. Directed link pairs are categorized according to chip identity, test type, region, and environmental conditions to obtain directed link pairs of the same type, and the number of directed link pairs of the same type is taken as the number of link pairs. The directed link pairs whose link deviation time of the preceding link state data is earlier than the link deviation time of their corresponding following link state data are regarded as positive directed link pairs, and the number of positive directed link pairs in the same type is counted as the number of positive link pairs. The average deviation values ​​of the preceding and following terms in the same type of directed element pairs are calculated separately to obtain the average deviation value of the preceding term and the average deviation value of the following term. The same type of directed link pairs whose deviation value of the preceding term is greater than the average deviation value of the preceding term are regarded as high deviation directed link pairs, and other same type of directed link pairs are regarded as low deviation directed link pairs; the subsequent deviation values ​​of the high deviation directed link pairs and the low deviation directed link pairs are averaged to obtain the high deviation response value and the low deviation response value, and the difference between the high deviation response value and the low deviation response value is taken as the response enhancement value. The proportion of the number of positive link pairs to the total number of link pairs is taken as the positive order proportion; The product of the forward order ratio, response enhancement value, average deviation of the preceding term, and average deviation of the following term is taken as the link influence value; and the link influence value is associated with the corresponding directed link pair to obtain the influence relationship.

6. The data management method for memory chip testing according to claim 5, characterized in that, The process of piecing together directed link pairs into candidate influence chains based on the aforementioned influence relationships includes: A positive value for the impact value of a link is considered an effective impact relationship. The test type of the state data of the preceding link in the effective influence relationship is used as the head type, and the test type of the state data of the following link is used as the tail type. By concatenating different effective influence relationships with the same head and tail types in the order of the testing process, the candidate influence chain is obtained.

7. A data management method for memory chip testing according to claim 6, characterized in that, The process of calculating the link attribution value for each candidate influence chain based on a hard disk drive includes: Extract the head type of the first valid influence relationship in the candidate influence chain and the tail type of each valid influence relationship to form a candidate chain type sequence; Extract the chip identity, region, environmental conditions, and candidate chain type sequence corresponding to the candidate influence chain to obtain candidate chain matching data; multiply the influence values ​​of all links in the candidate influence chain corresponding to the same candidate chain matching data to obtain the link continuity value; The number of effective influence relationships in the candidate influence chains is counted to obtain the candidate chain length; the link continuity value is square-rooted according to the candidate chain length to obtain the link stability value; Match the candidate impact chains in each test round with the candidate chain matching data. If the candidate impact chains in the current test round have the same chip identity, region, environmental conditions and candidate chain type sequence, then the current test round is taken as the link occurrence round. In the rounds in which the hard drive exhibits abnormal behavior, the rounds in which the hard drive exhibits abnormal behavior are considered the rounds in which the hard drive exhibits abnormal behavior. The total number of abnormal test rounds is obtained by counting the number of abnormal test rounds. The total number of abnormal test rounds is obtained by counting the number of test rounds in which the chip identity, region, and environmental conditions are the same and the hard drive shows abnormal performance. The ratio of the number of abnormal link rounds to the total number of abnormal hard disk rounds is used as the hard disk abnormality coverage value; The link attribution value is obtained by multiplying the link stability value corresponding to the matching data of the same candidate link with the disk abnormal coverage value.

8. A data management method for memory chip testing according to claim 7, characterized in that, The process of obtaining the main influence chain based on the link attribution value and deriving test conclusions based on the main influence chain includes: Candidate impact chains whose link attribution values ​​reach a preset attribution threshold are selected as candidate impact chains; among the candidate impact chains, the candidate impact chain with the largest disk abnormal coverage value is extracted as the main impact chain. If there are multiple candidate impact chains with the same abnormal hard drive coverage value, the candidate impact chain with the largest link attribution value will be taken as the main impact chain. Extract candidate chain matching data corresponding to the main impact chain to obtain main chain matching data. Extract candidate chain type sequence from the main chain matching data. Take the first test type in the candidate chain type sequence as the first abnormal type. Extract hard disk performance in the link abnormal round corresponding to the main impact chain to obtain associated hard disk performance. The chip identity, region, and environmental conditions in the main chain matching data are correlated with the abnormal initial launch type and the performance of the associated hard drive, and used as the test conclusion.

9. A data management system for memory chip testing, which is applied to the data management method for memory chip testing as described in any one of claims 1-8, characterized in that: The system includes a data acquisition module, a state compression module, a link attribution module, and a conclusion generation module; The output of the data acquisition module is connected to the input of the state compression module; the output of the state compression module is connected to the input of the link attribution module; and the output of the link attribution module is connected to the input of the conclusion generation module.

10. A data management system for memory chip testing according to claim 9, characterized in that: The data acquisition module is used to acquire the memory chip under test in the mechanical hard disk, collect and preprocess the raw event data during the test process, and obtain standard event data. The state compression module is used to compress standard event data according to the order of the test process to obtain stage state data and form directed stage pairs. The link attribution module is used to obtain the influence relationship between directed link pairs, splice the directed link pairs into candidate influence chains, and calculate the link attribution value of each candidate influence chain. The conclusion generation module is used to determine the main influence chain based on the link attribution value and generate test conclusions based on the main influence chain.

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