Electrostatic protection device

Abstract

The utility model discloses an electrostatic protection device. The electrostatic protection device comprises a substrate; the P-type well region and the N-type well region are located in the substrate; the first N + doped region and the first P + doped region are located in the P-type well region; the second N + doped region and the second P + doped region are located in the N-type well region; the third N + doped region is located between the N-type well region and the P-type well region; and the blocking part is located in the P-type well region and / or the N-type well region, and the blocking part is located in at least one of the multiple gaps formed between every two adjacent doped regions. According to the electrostatic protection device, the current flowing path in the semiconductor is changed by arranging the blocking part, so that the base region width of the parasitic triode is reduced, the trigger voltage of the device is reduced, the body resistance in the well region is increased, the maintaining voltage of the device is improved, and the electrostatic protection effect of the device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to an electrostatic protection device. Background Art

[0002] ESD (Electro-Static discharge) is a natural phenomenon that accompanies the entire product cycle. It is not easily perceived by the human body, but it can pose a serious threat to semiconductor devices and integrated circuits. During the manufacturing, packaging, testing, and application stages of the chip, its external environment and internal structure will accumulate a certain amount of charge and will be threatened by static electricity at any time. Therefore, ESD protection devices need to be placed on each pin in chip design. SCR (Silicon Controlled Rectifier) ​​structure is often used as an ESD protection device. However, ESD protection devices will have problems such as high trigger voltage and low holding voltage in high current, high voltage, and strong electromagnetic interference environments.

[0003] Figure 1 The cross-sectional schematic diagram of the electrostatic protection device of the thyristor structure in the prior art is shown. Figure 1As shown, the electrostatic protection device of the SCR structure includes a P-type substrate 101, an N-type well region 103 and a P-type well region 102 adjacent to each other in the substrate 101, a P+ doping region 114 and an N+ doping region 113 are formed in the N-type well region 103, a P+ doping region 112 and an N+ doping region 111 are formed in the P-type well region 102, and an N+ doping region 121 is formed between the P-type well region 102 and the N-type well region 103. A dielectric layer 104 is formed on the surface of the substrate 101, conductive pillars 131, 132, 133 and 134 are formed inside the dielectric layer 104, and a first electrode 105 and a second electrode 106 are formed on the dielectric layer 104. The first electrode 105 is connected to the N+ doping region 111 and the P+ doping region 112 respectively through the conductive pillars 131 and 132, and the second electrode 106 is connected to the N+ doping region 113 and the P+ doping region 114 respectively through the conductive pillars 133 and 134. The passivation layer 107 covers the surfaces of the dielectric layer 104, a portion of the first electrode 105, and the second electrode 106. The first electrode 105 is, for example, a cathode, and the second electrode 106 is, for example, an anode. When a positive pulse appears at the anode, the current first passes through the voltage-stabilizing diode formed by the N+ doping region 113, the N-type well region 103, the N+ doping region 121, the P-type well region 102 and the P+ doping region 112. When the avalanche breakdown voltage of the voltage-stabilizing diode is reached, the voltage-stabilizing diode avalanches, and the current flows into the cathode through the P-type well region 102 and the P+ doping region 112. As the avalanche current increases, the current flows through the N-type well region 103 and the P-type well region 102, and a voltage drop is generated on the body resistance of the two. When the voltage drop on any body resistance reaches 0.7V, one of the transistors (NPN or PNP) in the SCR structure is turned on, and it is easier to turn on the other transistor when the ESD pulse increases. When both transistors are turned on, positive feedback is formed, and the entire SCR structure is turned on, forming a low-resistance path to discharge the electrostatic current. When working in a low-resistance state, the maintenance voltage is small, and the latch effect is prone to occur. In addition, the trigger voltage is high, and it is difficult to open the discharge circuit. Therefore, the electrostatic protection capability of the current SCR structure electrostatic protection device is relatively poor. Utility Model Content

[0004] In view of the above problems, the purpose of the present invention is to provide an electrostatic protection device to reduce the trigger voltage and increase the maintenance voltage.

[0005] According to one aspect of the utility model, an electrostatic protection device is provided, comprising: a substrate; a P-type well region and an N-type well region, located in the substrate; a first N+ doping region and a first P+ doping region, located in the P-type well region; a second N+ doping region and a second P+ doping region, located in the N-type well region; a third doping region, located between the N-type well region and the P-type well region; and a blocking portion, located in the P-type well region and / or the N-type well region, wherein the blocking portion is located in at least one of a plurality of gaps formed between each two adjacent doping regions.

[0006] Optionally, there is at least one blocking portion in each gap.

[0007] Optionally, the blocking portion extends deeper in the P-type well region and / or the N-type well region than all P+ doped regions and all N+ doped regions.

[0008] Optionally, the first N+ doping region and the first P+ doping region are in contact with each other or separated from each other; the second N+ doping region and the second P+ doping region are in contact with each other or separated from each other.

[0009] Optionally, the P-type well region and the N-type well region are in contact with each other or separated from each other. When the P-type well region and the N-type well region are in contact with each other, the third doped region spans the P-type well region and the N-type well region; when the P-type well region and the N-type well region are separated from each other, the third doped region spans the P-type well region, the substrate and the N-type well region.

[0010] Optionally, the blocking portion is a doped region, and the doping type of the blocking portion located in the same well region is the same as that of the well region in which the blocking portion is located.

[0011] Optionally, the blocking portion is an insulating structure, and the insulating structure includes an isolation groove and an insulating layer located in the isolation groove.

[0012] Optionally, the electrostatic protection device is a silicon-controlled rectifier.

[0013] Optionally, the third doping region is an N+ type doping region or a P+ type doping region.

[0014] Optionally, the second N+ doped region, the N-type well region, the third doped region, the P-type well region and the first P+ doped region constitute a Zener diode; the second P+ doped region, the N-type well region, the third doped region, the P-type well region and the first P+ doped region constitute a PNP transistor; the second N+ doped region, the N-type well region, the third doped region, the P-type well region and the first N+ doped region constitute an NPN transistor.

[0015] Optionally, the P-type well region and the N-type well region form a parasitic diode, or the substrate and the N-type well region form a parasitic diode; a first body resistor is formed in the P-type well region, and a second body resistor is formed in the N-type well region.

[0016] Optionally, the PNP transistor and the first body resistor are connected in series between the anode and the cathode, and the second body resistor and the NPN transistor are connected in series between the anode and the cathode; the common node of the PNP transistor and the first body resistor is the first node, and the common node of the second body resistor and the NPN transistor is the second node; the emitter, base and collector of the PNP transistor are connected to the anode, the second node and the first node, respectively; the emitter, base and collector of the NPN transistor are connected to the cathode, the first node and the second node, respectively; the positive and negative electrodes of the parasitic diode are connected to the cathode and the second node, respectively; the positive and negative electrodes of the Zener diode are connected to the cathode and the second node, respectively.

[0017] Optionally, the electrostatic protection device also includes: a dielectric layer, located on the substrate and covering the surfaces of the substrate, the P-type well region, the N-type well region, the first N+ doped region, the first P+ doped region, the second N+ doped region, the second P+ doped region and the third doped region; a plurality of conductive pillars, penetrating the dielectric layer and respectively contacting the first N+ doped region, the first P+ doped region, the second N+ doped region and the second P+ doped region; a first electrode and a second electrode, located on the dielectric layer, the first electrode being electrically connected to the first N+ doped region and the first P+ doped region through the conductive pillars, and the second electrode being electrically connected to the second N+ doped region and the second P+ doped region through the conductive pillars; and a passivation layer, covering the dielectric layer, the first electrode and the second electrode, the passivation layer having an opening exposing part of the surface of the first electrode and the second electrode.

[0018] The electrostatic protection device provided by the utility model has a blocking part arranged in the P-type well region and / or the N-type well region, and the blocking part is located in at least one of the multiple gaps formed between each two adjacent doping regions, so as to change the current flow path in the device so that the current can only pass through the bottom of the blocking part, thereby reducing the base width of the NPN transistor and / or the PNP transistor, improving the current amplification factor of the transistor and thus reducing the trigger voltage of the device; the current flow path is lengthened, and the body resistance of the P-type well region and / or the N-type well region is increased to improve the holding voltage of the device. Therefore, when one of the transistors is turned on, the other transistor can be turned on faster, the electrostatic discharge capability is enhanced, and the holding voltage and electrostatic protection capability of the device are improved. At the same time, the area and package size of the device can be kept unchanged, thereby reducing costs.

[0019] Furthermore, the blocking portion can be a doping region with a doping type opposite to that of the well region in which it is located, or it can be an insulating structure composed of an isolation trench and an insulating layer, which provides a variety of implementation methods for the formation of the blocking portion and broadens the application scenarios of electrostatic protection devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A cross-sectional schematic diagram showing an electrostatic protection device of a thyristor structure in the prior art;

[0022] Figure 2 A schematic cross-sectional view of an electrostatic protection device according to a first embodiment of the utility model is shown;

[0023] Figure 3 A schematic cross-sectional view of an electrostatic protection device according to a second embodiment of the present utility model is shown;

[0024] Figure 4 A schematic cross-sectional view of an electrostatic protection device according to a third embodiment of the present utility model is shown;

[0025] Figure 5 A schematic cross-sectional view of an electrostatic protection device according to a fourth embodiment of the present utility model is shown;

[0026] Figure 6 A schematic cross-sectional view of an electrostatic protection device according to a fifth embodiment of the present utility model is shown;

[0027] Figure 7 A schematic cross-sectional view of an electrostatic protection device according to a sixth embodiment of the present utility model is shown;

[0028] Figure 8 A schematic diagram showing an equivalent circuit structure of an electrostatic protection device according to the utility model is shown;

[0029] Fig. 9 A characteristic comparison diagram showing the electrostatic protection device of the prior art and the electrostatic protection device of the utility model;

[0030] Figure 10a-Figure 10e The cross-sectional schematic diagrams of various stages in the manufacturing process of the electrostatic protection device according to the embodiment of the utility model are shown. DETAILED DESCRIPTION

[0031] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0032] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly above the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0033] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0034] Unless otherwise specified below, the various layers or regions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si and Ge. The gate conductor and electrode layer may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials.

[0035] In this application, the term "semiconductor structure" refers to the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "lateral extension" refers to extension in a direction substantially perpendicular to the depth direction of the trench.

[0036] The specific implementation of the utility model is further described in detail below in conjunction with the drawings and embodiments.

[0037] The SCR (Silicon Controlled Rectifiers) structure has the advantages of high current discharge efficiency, strong anti-static ability, low static leakage, and small parasitic capacitance. It is known as one of the most efficient electrostatic protection structures. However, SCR has the disadvantages of high VT (trigger voltage) and low VH (maintaining voltage). The high trigger voltage makes the SCR structure unable to open in time, resulting in the burning of the protected device, and the maintaining voltage is lower than the working voltage of the protected circuit, which easily causes a latch effect. When the device is subjected to electrostatic shock, it cannot be turned off. Therefore, in order to improve the electrostatic protection capability of the SCR, it is necessary to reduce the trigger voltage VT of the SCR structure and increase the maintaining voltage VH, and it is also hoped that the size of the SCR structure can be kept unchanged. The electrostatic protection device provided by the utility model can reduce the trigger voltage and increase the maintaining voltage without changing the device area and package size. The following is a detailed introduction in conjunction with the accompanying drawings.

[0038] Figure 2 A schematic cross-sectional view of an electrostatic protection device according to a first embodiment of the utility model is shown.

[0039] like Figure 2As shown, the electrostatic protection device of this embodiment includes a substrate 201 and a P-type well region 202 and an N-type well region 203 located in the substrate 201, the P-type well region 202 and the N-type well region 203 are in contact with each other or separated from each other, and both the P-type well region 202 and the N-type well region 203 extend from the upper surface of the substrate 201 to the inside of the substrate 201. The first N+ doping region 211 and the first P+ doping region 212 are located in the P-type well region 202, extending from the upper surface of the substrate 201 to the inside of the P-type well region 202, and the positions of the first P+ doping region 212 and the first N+ doping region 211 can be interchanged. The second N+ doping region 213 and the second P+ doping region 214 are located in the N-type well region 203, extending from the upper surface of the substrate 201 to the inside of the N-type well region 203, and the positions of the second N+ doping region 213 and the second P+ doping region 214 can be interchanged. The second N+ doping region 213 and the second P+ doping region 214 can be in contact with each other or separated from each other. When in contact with each other, the base width of the corresponding transistor is smaller, the amplification factor β of the transistor is larger, and the trigger voltage is lower. The third doping region 221 is located at the junction of the N-type well region 203 and the P-type well region 202, and is located between the first P+ doping region 212 and the second N+ doping region 213. When the P-type well region 202 and the N-type well region 203 are in contact with each other, the third doping region 221 is located in the middle of the contact between the P-type well region 202 and the N-type well region 203, and the third doping region 221 spans the P-type well region 202 and the N-type well region 203; when the P-type well region 202 and the N-type well region 203 are separated from each other, the third doping region 221 spans the P-type well region 202, the substrate 201 and the N-type well region 203. The third doping region 221 extends from the upper surface of the substrate 201 to the inside of the P-type well region 202 and the N-type well region 203. The junction depth of the third doping region 221 is preferably greater than the junction depths of the first N+ doping region 211, the first P+ doping region 212, the second N+ doping region 213, and the second P+ doping region 214, which can improve the antistatic ability of the device. In other embodiments, the junction depth of the third doping region 221 may also be less than or equal to the junction depths of the first N+ doping region 211, the first P+ doping region 212, the second N+ doping region 213, and the second P+ doping region 214. The third doping region 212 may be a P+ doping region or an N+ doping region.

[0040] Figure 2In the embodiment, the dielectric layer 204 is located on the substrate 201, covering the surfaces of the substrate 201, the P-type well region 202, the N-type well region 203, the first N+ doping region 211, the first P+ doping region 212, the second N+ doping region 213, the second P+ doping region 214 and the third doping region 221. A plurality of contact holes are formed in the dielectric layer 204, and the positions of the contact holes correspond to the first N+ doping region 211, the first P+ doping region 212, the second N+ doping region 213 and the second P+ doping region 214. The contact holes are filled with metal to sequentially form conductive pillars 231, 232, 233 and 234, which are in contact with and electrically connected to the first N+ doping region 211, the first P+ doping region 212, the second N+ doping region 213 and the second P+ doping region 214, respectively. The first electrode 205 and the second electrode 206 are located on the dielectric layer 204. The first electrode 205 is connected to the first N+ doping region 211 and the first P+ doping region 212 through the conductive pillars 231 and 232, and the second electrode 206 is connected to the second N+ doping region 213 and the second P+ doping region 214 through the conductive pillars 233 and 234. The first electrode 205 is, for example, a cathode, and the second electrode 206 is, for example, an anode. The passivation layer 207 covers the first electrode 205, the second electrode 206 and the dielectric layer 204, and has an opening in the passivation layer 207 that exposes a portion of the surface of the first electrode 205 and the second electrode 206. The electrostatic protection device of this embodiment is, for example, a thyristor rectifier, wherein the second N+ doping region 213, the N-type well region 203, the third doping region 221, the P-type well region 202 and the first P+ doping region 212 constitute a voltage-stabilizing diode DZ; the P-type well region 202 and the N-type well region 203 constitute a parasitic diode D1 or the substrate 201 and the N-type well region 203 constitute a parasitic diode D1, and the breakdown voltage of the parasitic diode D1 is much higher than the breakdown voltage of the voltage-stabilizing diode DZ; the second P+ doping region 214, the N-type well region 203, the third doping region 221, the P-type well region 202 and the first P+ doping region 212 constitute a PNP transistor; the second N+ doping region 213, the N-type well region 203, the third doping region 221, the P-type well region 202 and the first N+ doping region 212 constitute an NPN transistor. The P-type well region 202 and the N-type well region 203 also have their own body resistors Rp and Rn, respectively. In this embodiment, the P-type well region 202 and the N-type well region 203 are in contact, and the parasitic diode D1 is formed by the P-type well region 202 and the N-type well region 203. Of course, in some embodiments, the P-type well region 202 and the N-type well region 203 may not be in contact. When the P-type well region 202 and the N-type well region 203 are not in contact, the parasitic diode D1 may be formed by the P-type well region 202 and the N-type substrate 201.

[0041] Further, the electrostatic protection device further includes a blocking portion, which is located in the P-type well region 202 and / or the N-type well region 203, and the depth of the blocking portion in the P-type well region 202 and / or the N-type well region 203 is greater than the junction depth of the first N+ doping region 211, the first P+ doping region 212, the second N+ doping region 213, the second P+ doping region 214, and the third doping region 221. In this embodiment, the example in which there is one blocking portion 208 and it is located in the gap between the first N+ doping region 211 and the first P+ doping region 212 in the P-type well region 202 is used for explanation. Of course, the blocking portion 208 can be located in at least one gap among the multiple gaps formed between each two adjacent doping regions, and there is at least one blocking portion 208 in each gap.

[0042] For this electrostatic protection device, when a forward ESD pulse comes, the positive voltage causes the Zener diode DZ to gradually enter an avalanche breakdown state, and the holes generated by the avalanche of the Zener diode DZ flow from the N-type well region 203 into the P-type well region 202 and are finally collected by the first P+ doped region 212, generating a current I PW Similarly, the generated electrons flow from the P-type well region 202 into the N-type well region 203 and are finally collected by the second N+ doped region 213, generating a current I NW . Since both the N-type well region 203 and the P-type well region 202 have parasitic resistance (body resistance Rn and Rp), a voltage drop will be formed on the N-type well region 203 and the P-type well region 202. When the voltage drop reaches a certain voltage value, the transistor NPN or PNP will be turned on. When one transistor is turned on, the voltage drop caused by the current generated on its collector will immediately turn on the other transistor. Finally, the two transistors form an open-circuit positive feedback mechanism, and the electrostatic protection device is fully turned on to discharge the electrostatic current. Due to the existence of the blocking portion 208, the current flowing from the P-type well region 202 to the first N+ doped region 211 in the P-type well region 202 will be blocked, so that the current can only flow from the bottom of the P-type well region 202, so that the base width of the NPN transistor in the P-type well region 202 becomes narrower, the current amplification factor increases, and the trigger voltage is reduced. The blocking portion 208 can be an insulating structure, for example, the blocking portion 208 includes an isolation groove and an insulating layer located in the isolation groove. The blocking portion 208 may also be, for example, a doped region, and the doping type of the blocking portion located in the same well region is the same, and opposite to the doping type of the well region in which it is located. The blocking portion 208 in this embodiment is located in the P-type well region 202, which is a doped region of N-type doping type. The function of the blocking portion 208 is to limit the current flow path so that the current can only pass from the bottom of the blocking portion 208. When the blocking portion 208 is an insulating structure, the current can only pass from the bottom of the blocking portion 208, and when the blocking portion 208 is a doped region, it can further repel the current and prevent the current from passing in a certain area around it, which is better than the insulating structure.

[0043] Therefore, the electrostatic protection device of this embodiment is provided with a blocking portion, which can significantly reduce the trigger voltage of the device, make the device more sensitive, and improve the ESD protection effect.

[0044] Figure 3 A schematic cross-sectional view of an electrostatic protection device according to a second embodiment of the present utility model is shown.

[0045] like Figure 3 As shown, the electrostatic protection device of this embodiment is basically the same as the first embodiment, and also includes a substrate 201, a P-type well region 202, an N-type well region 203, a first N+ doping region 211, a first P+ doping region 212, a second N+ doping region 213, a second P+ doping region 214, a third doping region 221, a dielectric layer 204, a conductive column 231, a conductive column 232, a conductive column 233, a conductive column 234, a first electrode 205, a second electrode 206 and a passivation layer 207, and the positions and mutual relationships between them are the same as those in the first embodiment. Figure 2 The embodiments are the same and will not be described again here.

[0046] The difference between this embodiment and the first embodiment is that the blocking portion 308 in this embodiment is located in the gap between the first P+ doping region 212 and the third doping region 221 of the P-type well region 202. The blocking portion 308 can be a doping region or an insulating structure. The blocking portion 308 can be one or more. Figure 3 Only one is shown in the figure. The function of the blocking portion 308 is similar to that of the first embodiment, allowing the current to flow along the bottom of the P-type well region 202. Not only can the base width of the NPN transistor be reduced, the current amplification factor be increased, and the trigger voltage be reduced, but at the same time, the width of the body resistance Rp of the P-type well region 202 is changed from the depth of almost the entire P-type well region 202 to the width from the bottom of the blocking portion 308 to the bottom of the P-type well region 202. Therefore, the cross-sectional area of ​​the body resistance Rp becomes smaller and the resistance value becomes larger. At the same time, as the path of the current becomes longer, the body resistance Rp will also increase. Therefore, the body resistance Rp of the P-type well region 202 increases, which increases the maintenance voltage. The second embodiment has a better electrostatic protection effect than the first embodiment.

[0047] Figure 4 A schematic cross-sectional view of an electrostatic protection device according to a third embodiment of the present utility model is shown.

[0048] like Figure 4As shown, the semiconductor device of this embodiment is basically the same as the first embodiment, and also includes a substrate 201, a P-type well region 202, an N-type well region 203, a first N+ doping region 211, a first P+ doping region 212, a second N+ doping region 213, a second P+ doping region 214, a third doping region 221, a dielectric layer 204, a conductive column 231, a conductive column 232, a conductive column 233, a conductive column 234, a first electrode 205, a second electrode 206 and a passivation layer 207. The positions and mutual relationships between them are the same as those in the first embodiment and are not repeated here.

[0049] The difference between this embodiment and the first embodiment is that in this embodiment, the blocking portion 408 is located in the N-type well region 203, and the blocking portion 408 can be a doped region or an insulating structure, and when it is a doped region, it is a P-type doped region. Of course, there can be multiple blocking portions. Furthermore, the blocking portion 408 is located between the third doped region 221 and the second N+ doped region 213, and its function is also to block or limit the current flow path in the well region. Specifically, when a forward pulse appears at the anode and reaches the avalanche breakdown voltage of the Zener diode DZ, the Zener diode DZ first undergoes avalanche breakdown, at which time holes and electrons flow to form a current, and the current flows, for example, in the direction of the dotted arrow. The current flows from the second N+ doped region 213 and the second P+ doped region 214 to the third doped region 221 and then to the P-type well region 202 and the first P+ doped region 212. Due to the existence of the blocking portion 408, the current cannot pass through the blocking portion 408, the current flow is restricted, and the current can only flow from the bottom of the blocking portion 408. The width of the body resistance Rn of the N-type well region 203 changes from the depth of almost the entire N-type well region 203 to the width from the bottom of the blocking portion 408 to the bottom of the N-type well region 203. Therefore, the cross-sectional area of ​​the body resistance Rn becomes smaller and the resistance value becomes larger. At the same time, as the path of the current becomes longer, the body resistance Rn will also increase. Therefore, the body resistance Rn of the N-type well region 203 increases, which increases the holding voltage. At the same time, the existence of the blocking portion 408 reduces the base width of the PNP transistor, increases the base width of the PNP transistor, increases the current amplification factor, and reduces the trigger voltage.

[0050] Figure 5 A schematic cross-sectional view of an electrostatic protection device according to a fourth embodiment of the present utility model is shown.

[0051] like Figure 5As shown, the semiconductor device of this embodiment is basically the same as the first embodiment, and also includes a substrate 201, a P-type well region 202, an N-type well region 203, a first N+ doping region 211, a first P+ doping region 212, a second N+ doping region 213, a second P+ doping region 214, a third doping region 221, a dielectric layer 204, a conductive column 231, a conductive column 232, a conductive column 233, a conductive column 234, a first electrode 205, a second electrode 206 and a passivation layer 207. The positions and mutual relationships between them are the same as those in the first embodiment and are not repeated here.

[0052] The difference between this embodiment and the first embodiment is that the blocking portion in this embodiment is located in the N-type well region 203 and between the second N+ doping region 213 and the second P+ doping region 214. And the blocking portion 508 is a P-type doping region when it is a doping region. The role played by the blocking portion 508 is similar to that of the first embodiment. The existence of the blocking portion reduces the base width of the PNP transistor, improves the current amplification factor of the PNP transistor, and reduces the trigger voltage. The working principle will not be repeated.

[0053] Figure 6 A schematic cross-sectional view of an electrostatic protection device according to a fifth embodiment of the present utility model is shown.

[0054] like Figure 6 As shown, the semiconductor device of this embodiment is basically the same as the first embodiment, and also includes a substrate 201, a P-type well region 202, an N-type well region 203, a first N+ doping region 211, a first P+ doping region 212, a second N+ doping region 213, a second P+ doping region 214, a third doping region 221, a dielectric layer 204, a conductive column 231, a conductive column 232, a conductive column 233, a conductive column 234, a first electrode 205, a second electrode 206 and a passivation layer 207, and the positions and mutual relationships between them are the same as those in FIG. Figure 2 The embodiments are the same and will not be described again here.

[0055] This embodiment and Figure 1The difference between the embodiments is that in this embodiment, there are 4 blocking parts, which are distributed in the P-type well region 202 and the N-type well region 203, and the 4 blocking parts are respectively located in the gap formed by each two adjacent doping regions. Specifically, the blocking part 601 is located between the first N+ doping region 211 and the first P+ doping region 212, the blocking part 602 is located between the first P+ doping region 212 and the third doping region 221, the blocking part 603 is located between the third doping region 221 and the second N+ doping region 213, and the blocking part 604 is located between the second N+ doping region 213 and the second P+ doping region 214. When the blocking part is a doping region, the blocking part located in the P-type well region 202 is N-type doped, and the blocking part located in the N-type well region 203 is P-type doped. The function of the blocking parts 601-604 is to block or limit the current flow path in the well region. Similar to the first to fourth embodiments, in this embodiment, due to the existence of the blocking parts 601-604, the current cannot pass through the blocking parts and can only flow from the bottom of the blocking parts, and the body resistances Rp and Rn of the P-type well region 202 and the N-type well region 203 will increase, so the maintenance voltage increases. At the same time, the base widths of the NPN transistor and the PNP transistor are reduced, and the current amplification factors of the NPN transistor and the PNP transistor are increased, so that the trigger voltage of the SCR structure becomes smaller, the SCR structure is opened faster, and a discharge path is formed.

[0056] Figure 7 A schematic cross-sectional view of an electrostatic protection device according to a sixth embodiment of the present utility model is shown.

[0057] like Figure 7 As shown, the semiconductor device of this embodiment is basically the same as the first embodiment, and also includes a substrate 201, a P-type well region 202, an N-type well region 203, a first N+ doping region 211, a first P+ doping region 212, a second N+ doping region 213, a second P+ doping region 214, a third doping region 221, a dielectric layer 204, a conductive column 231, a conductive column 232, a conductive column 233, a conductive column 234, a first electrode 205, a second electrode 206 and a passivation layer 207, and the positions and mutual relationships between them are the same as those in FIG. Figure 2 The embodiments are the same and will not be described again here.

[0058] The difference between this embodiment and the first embodiment is that there are two blocking parts in this embodiment, which are respectively distributed in the P-type well region 202 and the N-type well region 203, the first blocking part 708 is located between the third doping region 211 and the second N+ doping region 213, and the second blocking part 709 is located between the first N+ doping region 211 and the first P+ doping region 212. The existence of the first blocking part 708 and the second blocking part 709 increases the current amplification factor of the NPN transistor and the PNP transistor, and at the same time increases the body resistance Rn, so that the maintenance voltage is increased and the trigger voltage is reduced, and the electrostatic protection effect is good. The specific working principle will not be repeated. Of course, in other embodiments, the blocking part can also be located in any gap among the multiple gaps between each two adjacent doping regions, and the effect will not be repeated here.

[0059] Further, Figure 7 The figure also shows the position and connection relationship of each component when the electrostatic protection device is a thyristor rectifier. Figure 8 The schematic diagram of the equivalent circuit structure of the electrostatic protection device according to the utility model is shown.

[0060] Combination Figure 7 and Figure 8 The electrostatic protection device provided by the embodiment of the utility model can be equivalent to the connection of multiple components between the anode and the cathode.

[0061] The body resistor Rn and the transistor NPN are connected in series between the anode and the cathode, the transistor PNP and the body resistor Rp are also connected in series between the anode and the cathode, the base of the PNP transistor is connected to the common node of the body resistor Rn and the transistor NPN, and the base of the NPN transistor is connected to the common node of the transistor PNP and the body resistor Rp. At the same time, a parasitic diode D1 and a voltage regulator diode DZ are also connected between the body resistor Rn and the cathode. Specifically, the common node of the PNP transistor and the body resistor Rp is the first node Q1, and the common node of the body resistor Rn and the NPN transistor is the second node Q2; the emitter, base and collector of the PNP transistor are respectively connected to the anode, the second node Q2 and the first node Q1; the emitter, base and collector of the NPN transistor are respectively connected to the cathode, the first node Q1 and the second node Q2; the positive and negative electrodes of the parasitic diode D1 are respectively connected to the cathode and the second node Q2; the positive and negative electrodes of the voltage regulator diode DZ are respectively connected to the cathode and the second node Q2.

[0062] Through the above-mentioned multiple embodiments, the existence of the blocking part changes the path of the current in the well region and the width of the base region of the NPN and PNP transistors. When the current can only flow along the bottom of the blocking part, the body resistance of the well region becomes larger, and the holding voltage of the device increases after the device is triggered; and the width of the base region of the NPN and PNP transistors becomes smaller, which increases the current amplification factor of the transistor and reduces the trigger voltage of the SCR structure. The setting of the blocking part makes the device more sensitive, while increasing the holding voltage and avoiding the occurrence of the latch effect. Without changing the device area and package size, the trigger voltage of the device can be reduced and the holding voltage of the device can be increased.

[0063] Fig. 9 The following is a comparison chart of the characteristics of the electrostatic protection device of the prior art and the electrostatic protection device of the present invention. Fig. 9 As shown, a comparison diagram of the voltage and current curves (IV curves) of the electrostatic protection device of the prior art and the utility model during operation is shown, wherein the horizontal axis represents the voltage, the vertical axis represents the current, and the curve graphs of the utility model and the prior art are respectively indicated by solid lines and dotted lines. The power supply voltage for normal operation of the device is VDD, and the trigger voltage of the device is VT, and VT is higher than VDD. Generally, a maximum VT threshold is set, and the voltage difference between VDD and the VT threshold is regarded as the design window. The voltage exceeding the maximum VT threshold is regarded as failure, that is, it is in the failure area. The voltage less than the power supply voltage VDD and maintained in this area may be a latch effect, that is, it is in the latch area. Both of the above situations will cause the device to exceed the design window, causing the risk of the protected device burning or failing to work normally, so it is hoped that the voltage of the device falls within the design window when it is working.

[0064] like Fig. 9 , the SCR structure of the prior art maintains the voltage VH1 below the operating voltage VDD after being triggered, so that the protected circuit operates in a low-resistance path, latching occurs, the circuit cannot work normally, and the maintaining current IH1 is high, which is easy to damage the device. At the same time, the trigger voltage VT1 of the SCR structure of the prior art is high, and there is a risk of exceeding the design window. However, due to the provision of a blocking part, the trigger voltage VT2 of the device is lower than that of the prior art (VT2<VT1), the maintaining voltage VH2 is higher than that of the prior art (VH2>VH1), and the maintaining voltage VH2 is greater than the power supply voltage VDD. The device operates within the design window, and the latching effect will not occur, which will not affect the normal use of the circuit.

[0065] Therefore, the electrostatic protection device of the present invention has a blocking portion, which increases the maintenance voltage and reduces the trigger voltage without changing the size of the device, thereby avoiding the latch effect during electrostatic discharge and improving the electrostatic discharge effect.

[0066] Figure 10a-Figure 10eThe cross-sectional schematic diagram of each stage of the manufacturing process of the electrostatic protection device according to the embodiment of the utility model is shown. Figure 10a-Figure 10e The process steps to produce Figure 2 The structure of the electrostatic protection device shown is used as an example for explanation.

[0067] like Fig.10a As shown, first, a substrate 201 is formed, and this step is completed using a conventional process. The substrate 201 is, for example, a P-type doped substrate, and the resistivity ρ is, for example, 100Ω·cm to 2000Ω·cm, to reduce parasitic capacitance. Afterwards, a SiO2 oxide layer (not shown in the figure) may be deposited on the substrate 201, and the thickness may be, for example, The substrate 201 may also be an N-type doped substrate.

[0068] like Fig.10b As shown, ion implantation is then performed from the surface of the substrate 201 to the inside to form a P-type well region 202 and an N-type well region 203. For example, a photolithography process is used to selectively implant a certain concentration of P-type impurities and N-type impurities, and then a suitable temperature is used to form the P-type well region 202 and the N-type well region 203. The implantation dose of the P-type impurity is 1E12 cm -2 ~1E15 cm -2 The implantation dose of N-type impurities is 1E12 cm -2 ~1E15 cm -2 The annealing temperature is, for example, 1100° C. to 1180° C., the annealing time is, for example, 1 to 4 hours, the junction depth of the P-type well region 202 is, for example, 3 to 8 μm, and the junction depth of the N-type well region 203 is, for example, 3 to 8 μm.

[0069] Afterwards, a certain concentration of N-type impurities is selectively injected at high energy using a photolithography process, and the junction depth is adjusted by the energy of the high energy injection and a suitable annealing temperature to form a barrier 208. Figure 2 In the embodiment, an N-type doping region is formed in the P-type well region 202 as the blocking portion 208, and the implantation dose of the N-type impurities in the N-type doping region is, for example, 1E13 cm -2 ~1E15 cm -2 The implantation energy is, for example, 600 KeV to 2000 KeV. The annealing temperature is, for example, 1000° C. to 1100° C., and the annealing time is, for example, 0.5 to 2 hours. The junction depth of the N-type doped region is, for example, 2 to 7 μm.

[0070] like Fig.10c As shown, then, a first N+ doping region 211 and a first P+ doping region 212 are formed in the P-type well region 202 , a second P+ doping region 214 and a second N+ doping region 213 are formed in the N-type well region 203 , and a third doping region 221 is formed.

[0071] Specifically, a certain concentration of N-type impurities or P-type impurities are selectively implanted at the junction of the P-type well region 202 and the N-type well region 203 using a photolithography process, and then a suitable temperature is used to form the third doped region 221. The implantation dose of the N-type impurities is, for example, 5E12 cm -2 ~1E15 cm -2 The implantation energy is, for example, 20 KeV to 80 KeV, the annealing temperature is, for example, 900° C. to 1000° C., the annealing time is, for example, 0.5 to 2 hours, and the junction depth of the third doping region 221 is, for example, 1 to 4 μm.

[0072] After that, a certain concentration of N-type impurities and P-type impurities are selectively injected using a photolithography process, and then an appropriate temperature annealing is used to activate the impurities to form N+ doped regions and P+ doped regions. For example, a high concentration of P-type impurities is selectively injected using a photolithography process, and the injection dose is, for example, 1.0E15cm -2 ~1.0E16 cm -2 The annealing temperature is, for example, 800°C to 900°C, the annealing time is, for example, 30 to 60 minutes, the junction depth of the P+ doped region is, for example, 0.3 to 1 μm; a high concentration of N-type impurities is selectively injected using a photolithography process, and the injection dose is, for example, 1.0E15 cm -2 ~1.0E16 cm -2 The annealing temperature is, for example, 800° C. to 900° C., the annealing time is, for example, 30 to 60 minutes, and the junction depth of the N+ doped region is, for example, 0.3 to 1 μm.

[0073] like Fig.10d As shown, further, a dielectric layer 204 is deposited on the substrate 201. The dielectric layer 204 is, for example, a silicon oxide layer, and the thickness of the dielectric layer 204 is, for example, 0.5 to 3 μm. Then, a contact hole penetrating the dielectric layer 204 is formed by using a photolithography process and an etching process, and the contact holes expose the surfaces of the first N+ doping region 211, the first P+ doping region 212, the second P+ doping region 214, and the second N+ doping region 213, respectively.

[0074] like Fig.10e As shown, further, the first electrode and the second electrode of the electrostatic protection device are formed. First, a metal of appropriate thickness is deposited in the contact hole to fill the contact hole, and then the excess metal is removed by chemical mechanical polishing (CMP), leaving only the metal in the contact hole to form conductive pillars 231, 232, 233 and 234. The metal filled in the contact hole is, for example, Ti / TiN and W, and the thickness of Ti is, for example, The thickness of TiN is, for example, The thickness of W is, for example, 0.5 um to 1 μm.

[0075] Afterwards, the first electrode 205 and the second electrode 206 are formed on the dielectric layer 204 by evaporation or sputtering process. Specifically, a metal layer of a certain thickness is deposited, and then the first electrode 205 and the second electrode 206 are formed by photolithography and etching process. The metal layer is, for example, AlCu, and the thickness of the metal layer is, for example, 1 to 5 μm. Afterwards, a passivation layer 207 is formed on the first electrode 205 and the second electrode 206. The passivation layer 207 covers the surface of the dielectric layer 204, the first electrode 205 and the second electrode 206. After photolithography and etching, the passivation layer 207 is formed to form an opening exposing the first electrode 205 and the second electrode 206. Finally, the substrate 201 is thinned to a suitable thickness to adapt to different packaging forms.

[0076] The embodiments of the present invention are described above, and these embodiments do not describe all the details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modifications based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An electrostatic protection device, characterized in that: include: substrate; A P-type well region and an N-type well region are located in the substrate; A first N+ doping region and a first P+ doping region, located in the P-type well region; A second N+ doping region and a second P+ doping region are located in the N-type well region; A third doped region, located between the N-type well region and the P-type well region; as well as A blocking portion is located in the P-type well region and / or the N-type well region, wherein the blocking portion is located in at least one gap among a plurality of gaps formed between every two adjacent doping regions.

2. The electrostatic protection device according to claim 1, characterized in that: There is at least one blocking portion in each gap.

3. The electrostatic protection device according to claim 1, characterized in that: The extending depth of the blocking portion in the P-type well region and / or the N-type well region is greater than that of all P+ doping regions and all N+ doping regions.

4. The electrostatic protection device according to claim 1, characterized in that: The first N+ doping region and the first P+ doping region are in contact with each other or separated from each other; the second N+ doping region and the second P+ doping region are in contact with each other or separated from each other.

5. The electrostatic protection device according to claim 1, characterized in that: The P-type well region and the N-type well region are in contact with each other or separated from each other, When the P-type well region and the N-type well region are in contact with each other, the third doped region spans the P-type well region and the N-type well region; When the P-type well region and the N-type well region are separated from each other, the third doped region spans across the P-type well region, the substrate, and the N-type well region.

6. The electrostatic protection device according to claim 1, characterized in that: The blocking portion is a doped region, and the doping type of the blocking portion located in the same well region is the same as that of the well region in which it is located.

7. The electrostatic protection device according to claim 1, characterized in that: The blocking portion is an insulating structure, and the insulating structure includes an isolation groove and an insulating layer located in the isolation groove.

8. The electrostatic protection device according to claim 1, characterized in that: The electrostatic protection device is a silicon controlled rectifier.

9. The electrostatic protection device according to claim 1, characterized in that: The third doping region is an N+ type doping region or a P+ type doping region.

10. The electrostatic protection device according to claim 1, characterized in that: The second N+ doped region, the N-type well region, the third doped region, the P-type well region and the first P+ doped region constitute a Zener diode; the second P+ doped region, the N-type well region, the third doped region, the P-type well region and the first P+ doped region constitute a PNP transistor; the second N+ doped region, the N-type well region, the third doped region, the P-type well region and the first N+ doped region constitute an NPN transistor.

11. The electrostatic protection device according to claim 10, characterized in that: The P-type well region and the N-type well region form a parasitic diode, or the substrate and the N-type well region form a parasitic diode; a first body resistor is formed in the P-type well region, and a second body resistor is formed in the N-type well region.

12. The electrostatic protection device according to claim 11, characterized in that: The PNP transistor and the first body resistor are connected in series between the anode and the cathode, and the second body resistor and the NPN transistor are connected in series between the anode and the cathode; the common node of the PNP transistor and the first body resistor is the first node, and the common node of the second body resistor and the NPN transistor is the second node; the emitter, base and collector of the PNP transistor are connected to the anode, the second node and the first node respectively; the emitter, base and collector of the NPN transistor are connected to the cathode, the first node and the second node respectively; the positive and negative electrodes of the parasitic diode are connected to the cathode and the second node respectively; the positive and negative electrodes of the Zener diode are connected to the cathode and the second node respectively.

13. The electrostatic protection device according to claim 1, characterized in that: Also includes: a dielectric layer, located on the substrate, and covering surfaces of the substrate, the P-type well region, the N-type well region, the first N+ doping region, the first P+ doping region, the second N+ doping region, the second P+ doping region, and the third doping region; a plurality of conductive pillars, penetrating the dielectric layer and respectively contacting the first N+ doping region, the first P+ doping region, the second N+ doping region and the second P+ doping region; A first electrode and a second electrode are located on the dielectric layer, the first electrode is electrically connected to the first N+ doped region and the first P+ doped region through the conductive pillar, and the second electrode is electrically connected to the second N+ doped region and the second P+ doped region through the conductive pillar; as well as A passivation layer covers the dielectric layer, the first electrode and the second electrode, and the passivation layer has an opening exposing a portion of the surface of the first electrode and the second electrode.

Images