Vehicle-mounted 4D millimeter wave radar data acquisition circuit

Abstract

The utility model belongs to the technical field of vehicle-mounted 4D millimeter wave radars, and particularly discloses a vehicle-mounted 4D millimeter wave radar data acquisition circuit, which comprises an MMIC millimeter wave radio frequency chip and an FPGA chip. The MMIC millimeter wave radio frequency chip is electrically connected with the plurality of 4D millimeter wave receiving antennas and the plurality of 4D millimeter wave transmitting antennas; the MMIC millimeter wave radio frequency chip is electrically connected with the FPGA chip; one path of output of the FPGA chip is electrically connected with the radar signal processing chip, and the other path of output of the FPGA chip is electrically connected with the serial chip. According to the utility model, the FPGA chip is adopted to carry out one-to-two MIPI processing on an MIPI signal of the MMIC millimeter wave radio frequency chip, one path is transmitted to the radar signal processing chip SOC, the other path is provided for the serial chip Serdes to carry out serial transmission on the MIPI signal, and the transmission distance can reach more than 15 meters, so that a radar data algorithm processing function is realized, real-time acquisition is also carried out, and the real-time acquisition is realized. And transmitting to a far end for storage.

Description

Technical Field

[0001] This utility model relates to the field of vehicle-mounted 4D millimeter-wave radar technology, and in particular to a vehicle-mounted 4D millimeter-wave radar data acquisition circuit. Background Technology

[0002] Currently, automotive 4D millimeter-wave radar requires data acquisition and analysis by a host computer. The acquired real-time data needs to be stored and then returned to the laboratory for simulation and comparison. Currently, the common ADC output interface of radar RF chips (MMICs) is the MIPI interface, while the output interface of radar signal processing chips (SOCs) is AURORA. Both interfaces can be used for radar data acquisition, but they have several drawbacks: For example, using the AURORA interface of the radar signal processing chip SOC requires consuming internal hardware and software resources, and this interface cannot transmit over long distances, requiring integrated installation, which increases the size of the radar with acquisition capabilities. Due to the limited installation space inside the car bumper, this method cannot be implemented in confined spaces. If MIPI is used as the data acquisition interface, since the MMIC RF chip only provides one MIPI interface, it cannot simultaneously perform acquisition and SOC input to the MIPI interface.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this utility model, and therefore may include information that does not constitute prior art known to those skilled in the art. Utility Model Content

[0004] The purpose of this invention is to solve the technical problems existing in the background art. To this end, a vehicle-mounted 4D millimeter-wave radar data acquisition circuit is provided.

[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0006] A vehicle-mounted 4D millimeter-wave radar data acquisition circuit includes an MMIC millimeter-wave radio frequency chip and an FPGA chip.

[0007] The MMIC millimeter-wave radio frequency chip is electrically connected to multiple 4D millimeter-wave receiving antennas and multiple 4D millimeter-wave transmitting antennas.

[0008] The MMIC millimeter-wave radio frequency chip is electrically connected to the FPGA chip.

[0009] One output of the FPGA chip is electrically connected to the radar signal processing chip, and the other output of the FPGA chip is electrically connected to the serial chip.

[0010] The following is a further defined technical solution of this utility model: one MIPI output of the FPGA chip is electrically connected to the MIPI receiving interface of the radar signal processing chip, and the other MIPI output of the FPGA chip is electrically connected to the MIPI receiving interface of the serial chip.

[0011] The following is a further defined technical solution of this utility model: the serial chip is electrically connected to the GMSL connector.

[0012] Compared with the prior art, the present invention has the following technical effects:

[0013] This invention uses an FPGA chip to perform a one-to-two MIPI process on the MIPI signal of the MMIC millimeter-wave radio frequency chip. One path is transmitted to the radar signal processing chip SOC, and the other path is provided to the serial chip SerDes for serial transmission of the MIPI signal. The transmission distance can reach more than 15 meters. In this way, radar data algorithm processing function is realized, real-time acquisition is performed, and the data is transmitted to a remote location for storage.

[0014] The present invention will be further described below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a diagram showing the connection relationship between the various chips in this utility model;

[0017] Figure 2 This is a diagram of the output interface of the MMIC millimeter-wave radio frequency chip of this utility model;

[0018] Figure 3 This is a diagram of the MIPI receiver interface of the FPGA chip of this utility model;

[0019] Figure 4 This is a diagram of the two-channel MIPI interface output by the FPGA chip of this utility model;

[0020] Figure 5 This is a diagram of the MIPI input interface of the radar signal processing chip SOC of this utility model;

[0021] Figure 6 This is a diagram of the MIPI input interface of the SerDes serial chip of this utility model;

[0022] Figure 7 This is a diagram of the output interface of the Serdes serial chip of this invention after converting MIPI signals from parallel to serial. Detailed Implementation

[0023] To make the above-mentioned objects, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a full understanding of this utility model. However, this utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this utility model. Therefore, this utility model is not limited to the specific embodiments disclosed below.

[0024] In this embodiment of the invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this embodiment of the invention according to the specific circumstances.

[0025] like Figure 1-7 As shown, this embodiment provides a vehicle-mounted 4D millimeter-wave radar data acquisition circuit, including four 4D millimeter-wave receiving antennas, three 4D millimeter-wave transmitting antennas, an MMIC millimeter-wave radio frequency chip, an FPGA chip, a radar signal processing chip, a serial chip, and a GMSL connector. It should be noted that the MMIC millimeter-wave radio frequency chip is an AWR2243; the FPGA chip is an FPGA programmable logic device, specifically a LIA-MD6000-6JMG80E; the radar signal processing chip SOC is an AM2732CD; and the serial chip SerDes is a MAX9295A.

[0026] This embodiment splits the MIPI signal of the MMIC millimeter-wave radio frequency chip into two, which can be used for real-time data acquisition and real-time analysis and processing of radar. Specifically, it includes: using an FPGA chip to perform a one-to-two MIPI split on the MIPI signal of the MMIC millimeter-wave radio frequency chip, and outputting the radar data of the MMIC millimeter-wave radio frequency chip through the MIPI interface (CSI2_TXP[0] pin, CSI2_TXM[0] pin, CSI2_TXP[1] pin, CSI2_TXM[1] pin, CSI2_CLKP pin, CSI2_CLKM pin, CSI2_TXP[0] pin, CSI2_TXP[1] pin, CSI2_TXM[1] pin, CSI2_CLKP pin, CSI2_TXP[1] ... The _TXP[2] pin, CSI2_TXM[2] pin, CSI2_TXP[3] pin, and CSI2_TXM[3] pin are electrically connected to the MIPI receiving interface of the FPGA chip (PB16A / PCLKT2_0 pin, PB16B / PCLKC2_0 pin, PB6A / GR_PCLK2_0 pin, PB6B pin, PB2A pin, PB2B pin, PB6C pin, PB6D pin, PB2C / MIPI_CLKT2_0 pin, and PB2D / MIPI_CLKC2_0 pin).

[0027] The output interface of the MMIC millimeter-wave RF chip is as follows Figure 2 As shown, the MIPI receiver interface of the FPGA chip is as follows: Figure 3 As shown.

[0028] Therefore, the CSI2_TXP[0] pin of the MMIC millimeter-wave RF chip is electrically connected to the PB6C pin of the FPGA chip;

[0029] The CSI2_TXM[0] pin of the MMIC millimeter-wave RF chip is electrically connected to the PB6D pin of the FPGA chip;

[0030] The CSI2_TXP[1] pin of the MMIC millimeter-wave RF chip is electrically connected to the PB6A / GR_PCLK2_0 pin of the FPGA chip;

[0031] The CSI2_TXM[1] pin of the MMIC millimeter-wave RF chip is electrically connected to the PB6B pin of the FPGA chip;

[0032] The CSI2_CLKP pin of the MMIC millimeter-wave RF chip is electrically connected to the PB16A / PCLKT2_0 pin of the FPGA chip.

[0033] The CSI2_CLKM pin of the MMIC millimeter-wave RF chip is electrically connected to the PB16B / PCLKC2_0 pin of the FPGA chip.

[0034] The CSI2_TXP[2] pin of the MMIC millimeter-wave RF chip is electrically connected to the PB2C / MIPI_CLKT2_0 pin of the FPGA chip;

[0035] The CSI2_TXM[2] pin of the MMIC millimeter-wave RF chip is electrically connected to the PB2D / MIPI_CLKC2_0 pin of the FPGA chip;

[0036] The CSI2_TXP[3] pin of the MMIC millimeter-wave RF chip is electrically connected to the PB2A pin of the FPGA chip;

[0037] The CSI2_TXM[3] pin of the MMIC millimeter-wave RF chip is electrically connected to the PB2B pin of the FPGA chip.

[0038] The FPGA chip splits the MIPI signal into two completely identical MIPI signals for synchronous output. The two MIPI interfaces output by the FPGA chip (DPHY0_CKP pin, DPHY0_CKN pin, DPHY0_DP0 pin, DPHY0_DN0 pin, DPHY0_DP1 pin, DPHY0_DN1 pin, DPHY0_DP2 pin, DPHY0_DN2 pin, DPHY0_DP3 pin, DPHY0_DN3 pin, DPHY1_CKP pin, DPHY1_CKN pin, DPHY1_DP0 pin, DPHY1_DN0 pin, DPHY1_DP1 pin, DPHY1_DN1 pin, DPHY1_DP2 pin, DPHY1_DN2 pin, DPHY1_DP3 pin, DPHY1_DN3 pin) are as follows: Figure 4 As shown; the radar signal processing chip SOC receives one MIPI signal from the FPGA chip. The MIPI input interfaces of the radar signal processing chip SOC (CSI2_RX1P0 pin, CSI2_RX1M0 pin, CSI2_RX1P1 pin, CSI2_RX1M1 pin, CSI2_RX1P2 pin, CSI2_RX1M2 pin, CSI2_RX1P3 pin, CSI2_RX1M3 pin, CSI2_RX1CLKP pin, CSI2_RX1CLKM pin) are as follows: Figure 5 As shown; the serial chip SerDes receives another MIPI signal from the FPGA chip. The MIPI input interfaces of the serial chip SerDes (CKP pin, CKN pin, D0P pin, D0N pin, D1P pin, D1N pin, D2P pin, D2N pin, D3P pin, D3N pin) are as follows: Figure 6 As shown.

[0039] Therefore, the DPHY0_CKP pin of the FPGA chip is electrically connected to the CSI2_RX1CLKP pin of the radar signal processing chip SOC.

[0040] The DPHY0_CKN pin of the FPGA chip is electrically connected to the CSI2_RX1CLKM pin of the radar signal processing chip SOC;

[0041] The DPHY0_DP0 pin of the FPGA chip is electrically connected to the CSI2_RX1P0 pin of the radar signal processing chip SOC.

[0042] The DPHY0_DN0 pin of the FPGA chip is electrically connected to the CSI2_RX1M0 pin of the radar signal processing chip SOC;

[0043] The DPHY0_DP1 pin of the FPGA chip is electrically connected to the CSI2_RX1P1 pin of the radar signal processing chip SOC.

[0044] The DPHY0_DN1 pin of the FPGA chip is electrically connected to the CSI2_RX1M1 pin of the radar signal processing chip SOC;

[0045] The DPHY0_DP2 pin of the FPGA chip is electrically connected to the CSI2_RX1P2 pin of the radar signal processing chip SOC.

[0046] The DPHY0_DN2 pin of the FPGA chip is electrically connected to the CSI2_RX1M2 pin of the radar signal processing chip SOC;

[0047] The DPHY0_DP3 pin of the FPGA chip is electrically connected to the CSI2_RX1P3 pin of the radar signal processing chip SOC.

[0048] The DPHY0_DN3 pin of the FPGA chip is electrically connected to the CSI2_RX1M3 pin of the radar signal processing chip SOC;

[0049] The DPHY1_CKP pin of the FPGA chip is electrically connected to the CKP pin of the serial chip SerDes.

[0050] The DPHY1_CKN pin of the FPGA chip is electrically connected to the CKN pin of the serial chip SerDes.

[0051] The DPHY1_DP0 pin of the FPGA chip is electrically connected to the DOP pin of the serial chip SerDes.

[0052] The DPHY1_DN0 pin of the FPGA chip is electrically connected to the D0N pin of the serial chip SerDes.

[0053] The DPHY1_DP1 pin of the FPGA chip is electrically connected to the D1P pin of the serial chip SerDes.

[0054] The DPHY1_DN1 pin of the FPGA chip is electrically connected to the D1N pin of the serial chip SerDes.

[0055] The DPHY1_DP2 pin of the FPGA chip is electrically connected to the D2P pin of the serial chip SerDes.

[0056] The DPHY1_DN2 pin of the FPGA chip is electrically connected to the D2N pin of the serial chip SerDes.

[0057] The DPHY1_DP3 pin of the FPGA chip is electrically connected to the D3P pin of the serial chip SerDes.

[0058] The DPHY1_DN3 pin of the FPGA chip is electrically connected to the D3N pin of the serial chip Serdes.

[0059] The SerDes serial chip converts the input MIPI signal from parallel to serial and then transmits the GMSL signal via the output interface (SIOP pin, SION pin) to the GMSL connector. The SGML signal is output to connector J5, which can be connected to an external wiring harness for long-distance transmission, up to 15 meters. The circuit diagram is shown below. Figure 7 As shown. Therefore, this embodiment can achieve real-time data acquisition and long-distance transmission, improving upon the shortcomings of traditional radar data acquisition.

[0060] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model in any way. Any person skilled in the art can make many possible variations and modifications to the technical solution of this utility model using the disclosed methods and techniques, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of this utility model. Therefore, all equivalent changes made based on the shape, structure, and principle of this utility model without departing from its technical solution should be covered within the protection scope of this utility model.

Claims

1. An on-board 4D millimeter wave radar data acquisition circuit, characterized by, The MMIC millimeter wave radio frequency chip and the FPGA chip are included; The MMIC millimeter wave radio frequency chip is electrically connected with a plurality of 4D millimeter wave receiving antennas and a plurality of 4D millimeter wave transmitting antennas; The MMIC millimeter wave radio frequency chip is electrically connected with the FPGA chip; One output of the FPGA chip is electrically connected with a radar signal processing chip, and another output of the FPGA chip is electrically connected with a serial chip.

2. The vehicle-mounted 4D millimeter wave radar data acquisition circuit of claim 1, wherein, One MIPI output of the FPGA chip is electrically connected with a MIPI receiving interface of the radar signal processing chip, and another MIPI output of the FPGA chip is electrically connected with a MIPI receiving interface of the serial chip.

3. A vehicle mounted 4D millimeter wave radar data acquisition circuit as claimed in claim 2, wherein, The serial chip is electrically connected with a GMSL connector.

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