Cascaded chip with serial cascade communication interface and serial transmission component thereof

Abstract

The application provides a cascaded chip with a serial cascade communication interface and a serial transmission component thereof, which comprises a serial cascade communication interface, the serial cascade communication interface comprises a serial data input interface and a clock signal input interface for receiving input signals, and a serial data output interface and a clock signal output interface for providing output signals and being connected to a next cascaded chip, and a chip selection signal interface is omitted. The cascaded chip with the serial cascade communication interface of the application introduces a two-wire cascade serial cascade communication interface for the application of a high polling rate of a keyboard, does not need a chip selection signal, realizes automatic optimization timing and low delay through a buffer transmission mode and a pass-through transmission mode, makes the wiring simple and flexible, and realizes efficient, safe and low-power-consumption transmission.

Description

Technical Field

[0001] This invention relates to the field of communication interface technology for electronic devices, specifically to a cascaded chip with a serial cascaded communication interface and its serial transmission component, which is geared towards high polling rate application scenarios such as keyboards. Background Technology

[0002] With the booming development of the e-sports industry, e-sports gamers have increasingly higher requirements for keyboard response speed. Keyboard polling rate directly determines operation latency, and a fast response can bring even millisecond-level advantages, which can sometimes determine the outcome of an e-sports competition. Typically, keyboards have 87, 104, or 108 keys, each of which requires a separate IC chip. To meet the demands of high polling rates, this requires the chip's communication interface to support high-speed, flexible, and secure transmission methods.

[0003] Conventional keyboards use multiple independent key ICs. Traditional parallel interfaces or standard SPI (serial peripheral interface) interfaces have obvious drawbacks: a large number of chip select signal lines and complex PCB routing; cascaded transmission delay accumulation and timing alignment difficulties; chips need to be manually numbered, resulting in low production efficiency; continuous clock power supply leads to high power consumption; cascading multiple chips is prone to timing drift and communication errors, and cannot simultaneously meet the requirements of high polling rate, low latency, low power consumption, and simple routing. Summary of the Invention

[0004] The purpose of this invention is to provide a cascaded chip with a serial cascaded communication interface and its serial transmission component, which features high communication speed, simplified circuit layout, automatic timing optimization, low power consumption, and high polling rate.

[0005] To achieve the above objectives, the present invention provides a cascaded chip with a serial cascaded communication interface, including a serial data input interface and a clock signal input interface for receiving input signals, and a serial data output interface and a clock signal output interface for providing output signals and connecting to the next cascaded chip, thus eliminating the need for a chip select signal interface.

[0006] The cascaded chip with a serial cascaded communication interface is configured such that after the cascaded chip is powered on, it first transmits and executes an automatic numbering command for the cascaded chip in buffered transmission mode to achieve automatic numbering of the cascaded chip; after all cascaded chips are automatically numbered, it automatically switches to direct transmission mode to transmit and execute other commands.

[0007] In buffered transmission mode, the output signal of the serial data output interface is delayed by one field unit compared to the serial data input interface; the output signal of the clock signal output interface is delayed by half a clock cycle compared to the input signal of the clock signal input interface; the delay of one field unit is used for automatic numbering of cascaded chips.

[0008] In buffered transmission mode, the cascaded chip with serial cascaded communication interface is configured to: after receiving an automatic numbering command for the cascaded chip through the serial data input interface, obtain the number of the numbering bit and use it as its own number; before outputting the automatic numbering command for the cascaded chip through the serial data output interface, automatically increment the number of the numbering bit by 1 to achieve automatic numbering of the cascaded chip.

[0009] The sub-packet header of the automatic cascade chip numbering command stores the total number of cascade chips. The total number of cascade chips is used to automatically and uniformly switch to pass-through mode after all cascade chips are automatically numbered.

[0010] The cascaded chip is configured such that, in buffered transmission mode, when transmitting the command to automatically number the cascaded chips, an external clock with a total length equal to the total number of cascaded chips × the length of the field unit is provided, so that each cascaded chip can complete automatic numbering and determine the time when all cascaded chips complete automatic numbering based on its own number and the clock. After all cascaded chips have completed automatic numbering, it automatically switches to pass-through transmission mode.

[0011] In the direct transmission mode, the cascaded chip with the serial cascaded communication interface outputs serial data in a clock rising edge synchronization manner; and the clock signal of the clock signal output interface is delayed by half a cycle compared with the clock signal input interface.

[0012] The transmission protocol of the cascaded chip with serial cascaded communication interface includes five commands: automatic cascaded chip numbering command, cascaded chip broadcast write command, selected specific chip write command, selected specific chip read command, and high-speed chip wake-up command.

[0013] The automatic cascaded chip numbering command includes a start identifier, command header, sub-header, number bit, and stop identifier bit; the cascaded chip broadcast write command includes a start identifier, command header, data bits, and stop identifier bit; the specific chip selection write command includes a start identifier, command header, sub-header 0, sub-header 1, data bits, and stop identifier bit; the specific chip selection read command includes a start identifier, command header, sub-header 0, sub-header 1, data bits, and stop identifier bit; the high-speed chip wake-up command includes a start identifier, command header, sub-header 1, and stop identifier bit; each of the start identifier, command header, sub-header, sub-header 0, sub-header 1, number bit, and stop identifier bit is a field unit, and the length of the data bits is an integer multiple of the field unit.

[0014] On the other hand, the present invention provides a serial transmission component based on cascaded chips with serial cascaded communication interfaces, including an MCU chip and multiple cascaded chips with serial cascaded communication interfaces as described above, which are sequentially cascaded from the MCU chip.

[0015] The cascading chip with serial cascading communication interface of the present invention is designed for applications with high keyboard polling rates. It introduces a two-wire cascading serial cascading communication interface, which eliminates the need for a chip select signal. It achieves automatic timing optimization and low latency through buffered transmission mode and direct transmission mode, making the wiring simple and flexible, the transmission efficient and secure, and the power consumption low. It can support high-speed cascading of up to 128 cascading chips. Attached Figure Description

[0016] Figure 1 This is a cascading application diagram of the cascading chip with a serial cascading communication interface of the present invention.

[0017] Figure 2 This is a command format and timing diagram for the automatic numbering command for cascaded chips;

[0018] Figure 3 This is a command format diagram for selecting a specific chip to write commands and high-speed chip wake-up commands;

[0019] Figure 4 This is a schematic diagram illustrating the switching method between buffered transmission mode and direct transmission mode of a cascaded chip with a serial cascaded communication interface.

[0020] Figure 5 This is a signal timing diagram of the direct transmission mode. Detailed Implementation

[0021] The preferred embodiments of the present invention are given below with reference to the accompanying drawings and described in detail.

[0022] The cascaded chip of the present invention has a serial cascaded communication interface, which is optimized based on the traditional SPI (serial peripheral interface) to meet the requirements of high-speed keyboard response and simplified circuit layout. Figure 1 As shown, a cascaded chip with a serial cascaded communication interface includes a serial data input interface (sin) and a clock signal input interface (sclki) for receiving input signals, and a serial data output interface (sout) and a clock signal output interface (sclko) for providing output signals and connecting to the next cascaded chip, omitting the chip select signal interface.

[0023] Serial data input interface (sin): Responsible for receiving serial data (including communication data) transmitted from the previous stage chip.

[0024] Clock signal input interface (sclki): responsible for receiving the clock synchronization signal transmitted from the previous stage chip;

[0025] Serial data output interface (sout): responsible for transmitting the serial data processed by this chip to the next stage chip;

[0026] Clock signal output interface (sclko): Responsible for transmitting the clock synchronization signal processed by this chip (such as a clock signal with a half-cycle delay in Bypass mode) to the next stage chip.

[0027] The cascaded chip with a serial cascaded communication interface operates under a defined transmission protocol, which includes five commands: automatic cascaded chip numbering command, cascaded chip broadcast write command, selected specific chip write command, selected specific chip read command, and high-speed chip wake-up command (used to meet low-power chip wake-up or high-frequency ADC wake-up scenarios). The command format of the five commands, two transmission modes, and signal timing rules under the two transmission modes are also included.

[0028] like Figure 2 As shown, the automatic cascade chip numbering command includes a start identifier, command header, sub-header, number bits, and stop identifier bits. The broadcast write command to the cascade chip includes a start identifier, command header, data bits, and stop identifier bits. For example... Figure 3 As shown, the command to write to a specific chip includes a start identifier, a command header, sub-header 0, sub-header 1, data bits, and a stop identifier. The command to read from a specific chip includes a start identifier, a command header, sub-header 0, sub-header 1, data bits, and a stop identifier. The high-speed chip wake-up command includes a start identifier, a command header, sub-header 1, and a stop identifier.

[0029] In this configuration, each of the following elements—start identifier, command header, sub-header, sub-header 0, sub-header 1, number bit, and stop identifier—is a field unit. The length of the data bits is an integer multiple of the field unit length, which can be adjusted as needed. Commands in the serial cascaded communication interface are all in 12-bit or 16-bit field units. The command header identifies the command type, the sub-header stores the total number of cascaded chips, sub-header 0 stores the start chip number, sub-header 1 stores the end chip number, the data bits store the required data, and the number bit stores the cascaded chip number.

[0030] like Figure 4 As shown, the cascaded chip with a serial cascaded communication interface of the present invention is configured as follows: after the cascaded chip is powered on, it first transmits and executes the automatic cascaded chip numbering command in buffer transmission mode to achieve automatic numbering of the cascaded chips; after all cascaded chips have been automatically numbered, it automatically switches to pass-through transmission mode to transmit and execute other commands. This satisfies the requirements for high-speed transmission and automatic numbering. Because each cascaded chip receives the command at a different time, if the preceding cascaded chip switches to pass-through transmission mode directly after completing its own automatic numbering, the commands received by subsequent chips will be incorrect. Therefore, it is necessary to wait until all chips have received the automatic cascaded chip numbering command and completed the automatic numbering before automatically switching to pass-through transmission mode.

[0031] Signal timing rules in buffered transmission mode are as follows Figure 2 As shown, in buffered transmission mode, the output signal of the serial data output interface (sout) is delayed by one field unit compared to the serial data input interface (sin) to ensure sufficient data for processing; the output signal of the clock signal output interface (sclko) is delayed by half a clock cycle compared to the input signal of the clock signal input interface (sclki) to overcome placement and routing delays. The one-field-unit delay is used for automatic numbering of cascaded chips. The cascaded chip with the serial cascade communication interface is configured as follows: after receiving the automatic numbering command for cascaded chips through the serial data input interface, it obtains the number bit and uses it as its own number; before outputting the automatic numbering command for cascaded chips through the serial data output interface, the number bit is automatically incremented by 1 to achieve automatic numbering of the cascaded chips.

[0032] In this embodiment, the automatic cascade chip numbering command has a total of 5 fields (start identifier, command header, sub-header, number bit, and stop identifier bit), totaling 60 bits. Due to the timing rules mentioned above, the automatic cascade chip numbering command issued by the second cascade chip has a phase delay of one field unit (12 bits) relative to the automatic cascade chip numbering command issued by the first cascade chip. This delay time is used to obtain the current chip number and increment the number by one.

[0033] The sub-packet header of the automatic cascade chip numbering command stores the total number of cascade chips. This total number of cascade chips is used to ensure that after all cascade chips are automatically numbered, they automatically switch to pass-through mode. The cascade chip with a serial cascade communication interface of this invention only provides a clock signal when a command needs to be transmitted. However, it is configured such that, in buffered transmission mode, when transmitting the automatic cascade chip numbering command, an external source (such as an MCU chip) provides a clock with a total length equal to the total number of cascade chips × the length of the field unit. This allows each cascade chip to complete automatic numbering and determine the time when all cascade chips are automatically numbered based on its own number and the clock. After all cascade chips are automatically numbered, they automatically switch to pass-through mode. The time when all cascade chips are automatically numbered = (total number of cascade chips - current cascade chip number) × the length of the field unit (clock). The time when all cascade chips are automatically numbered refers to how many clock cycles the current cascade chip needs to wait before switching to pass-through mode.

[0034] Signal timing rules in direct transmission mode are as follows Figure 5 As shown. In pass-through mode, the output signals of the serial data output interface (sout) and clock signal output interface (sclko) are no longer delayed by one field unit compared to the input signals of the serial data input interface (sin) and clock signal input interface (sclki). In pass-through mode, cascaded chips with serial cascaded communication interfaces output serial data synchronously using the rising edge of the clock. To overcome timing issues caused by placement and routing delays, the clock signal of the clock signal output interface (sclko) is delayed by half a cycle compared to the clock signal of the clock signal input interface (sclki) (the delay circuit consists of an inverter, a D flip-flop, and an RC delay), thus achieving high-speed transmission while ensuring communication timing safety. Therefore, the sclko of the i-th cascaded chip is delayed by i / 2 clock cycles relative to the first cascaded chip. The clock signal period is between 5MHz and 40MHz.

[0035] Furthermore, the cascaded chip with a serial cascaded communication interface of the present invention only provides a clock signal when a command needs to be transmitted. When the interface does not need to transmit a transmission protocol, no clock signal is required to meet the low power consumption requirement. In other words, the clock signal does not need to be maintained continuously in the pass-through mode. For example, for 60 bits of data, only 60 clock cycles are needed, and the clock can be maintained at a low level when no command is being sent.

[0036] Please see again Figure 1 This paper illustrates an application scenario of the cascaded chip with a serial cascaded communication interface according to the present invention, namely, a serial transmission component based on the cascaded chip with a serial cascaded communication interface. The serial transmission component based on the cascaded chip with a serial cascaded communication interface includes an MCU chip 100 and multiple cascaded chips 200, described above, serially cascaded from the MCU chip 100. Each cascaded chip connects to the serial data output interface (sout) of the next cascaded chip via a serial data input interface (sin), and to the clock signal output interface (sclko) of the next cascaded chip via a clock signal input interface (sclki), thereby forming a unidirectional serial transmission path. The MCU chip 100 provides the initial clock signal and serial data. The serial transmission component based on the cascaded chip with a serial cascaded communication interface can be a keyboard, and the number of cascaded chips 200 can be 128. The serial transmission component based on the cascaded chip with serial cascaded communication interface supports a high polling rate of 1kHz–8kHz and power consumption without clock signal in idle state, thus meeting the requirements of low latency and long battery life for e-sports.

[0037] In summary, the cascaded chip with serial cascaded communication interface of the present invention is designed for applications with high keyboard polling rates. It introduces a two-wire cascaded serial cascaded communication interface, which eliminates the need for a chip select signal. Through buffered transmission mode and direct transmission mode, it achieves automatic timing optimization and low latency, making the wiring simple and flexible, the transmission efficient and secure, and the power consumption low. It can support high-speed cascading of up to 128 cascaded chips.

[0038] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the invention. Various variations can be made to the above embodiments of the present invention. All simple and equivalent changes and modifications made in accordance with the claims and description of this application fall within the protection scope of the claims of this patent. All aspects not described in detail in this invention are conventional technical content.

Claims

1. A cascaded chip with a serial cascaded communication interface, characterized in that, It includes a serial cascaded communication interface, which includes a serial data input interface and a clock signal input interface for receiving input signals, and a serial data output interface and a clock signal output interface for providing output signals and connecting to the next cascaded chip, omitting the chip select signal interface; The cascaded chip with a serial cascaded communication interface is configured as follows: after the cascaded chip is powered on, it first transmits and executes an automatic numbering command for the cascaded chip in buffered transmission mode to achieve automatic numbering of the cascaded chip; after all cascaded chips are automatically numbered, it automatically switches to direct transmission mode to transmit and execute other commands. In buffered transmission mode, the output signal of the serial data output interface is delayed by one field unit compared to the serial data input interface; the output signal of the clock signal output interface is delayed by half a clock cycle compared to the input signal of the clock signal input interface; the delay of one field unit is used for automatic numbering of cascaded chips; In the direct transmission mode, cascaded chips with serial cascaded communication interfaces output serial data using clock rising edge synchronization. Furthermore, the clock signal of the clock signal output interface is delayed by half a cycle compared to the clock signal input interface; The sub-packet header of the automatic cascade chip numbering command stores the total number of cascade chips. The total number of cascade chips is used to automatically and uniformly switch to pass-through mode after all cascade chips are automatically numbered. The cascaded chips are configured such that, in buffered transmission mode, when transmitting commands for automatically numbering the cascaded chips, an external clock with a total length equal to the total number of cascaded chips multiplied by the length of the field unit is provided. This allows each cascaded chip to complete automatic numbering and determine the time when all cascaded chips complete automatic numbering based on its own number and the clock. After all cascaded chips have completed automatic numbering, they automatically switch to pass-through transmission mode. The time when all cascaded chips complete automatic numbering is equal to (total number of cascaded chips - current cascaded chip number) multiplied by the clock length of the field unit. The time when all cascaded chips complete automatic numbering refers to how many clock cycles the current cascaded chip needs to wait before switching to pass-through transmission mode.

2. The cascaded chip with a serial cascaded communication interface according to claim 1, characterized in that, In buffered transmission mode, the cascaded chip with serial cascaded communication interface is configured to: after receiving an automatic numbering command for the cascaded chip through the serial data input interface, obtain the number of the numbering bit and use it as its own number; before outputting the automatic numbering command for the cascaded chip through the serial data output interface, automatically increment the number of the numbering bit by 1 to achieve automatic numbering of the cascaded chip.

3. The cascaded chip with a serial cascaded communication interface according to claim 1, characterized in that, The transmission protocol of the cascaded chip with serial cascaded communication interface includes five commands: automatic cascaded chip numbering command, cascaded chip broadcast write command, selected specific chip write command, selected specific chip read command, and high-speed chip wake-up command.

4. The cascaded chip with a serial cascaded communication interface according to claim 3, characterized in that, The automatic cascade chip numbering command includes a start identifier, command header, sub-header, number bits, and stop identifier bits; The broadcast write command to the cascaded chip includes a start identifier, a command header, data bits, and a stop identifier. The command to write to a specific chip includes a start identifier, a command header, sub-header 0, sub-header 1, data bits, and a stop identifier. The selected specific chip read command includes a start identifier, command header, sub-header 0, sub-header 1, data bits, and stop identifier bit; The high-speed chip wake-up command includes a start identifier, a command header, a sub-header 1, and a stop identifier bit; Each of the start identifier, command header, subheader, subheader 0, subheader 1, number bit, and stop identifier bit is a field unit, and the length of the data bits is an integer multiple of the field unit.

5. A serial transmission component based on a cascaded chip with a serial cascaded communication interface, characterized in that, It includes an MCU chip and multiple cascaded chips with a serial cascaded communication interface as described in any one of claims 1-4, which are sequentially cascaded from the MCU chip.

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