A control circuit of a multi-port ultra-thin charger

Abstract

The utility model discloses a kind of control circuit of multi-port ultra-thin charger, it is related to charger technical field, including EMI circuit, first filter circuit, planar transformer, synchronous rectifier circuit, second filter circuit, feedback circuit, PWM control circuit, first TYPE-C interface control circuit, voltage reduction circuit, second TYPE-C interface control circuit;First filter circuit is connected between EMI circuit and PWM control circuit;Planar transformer is connected with PWM control circuit;PWM control circuit is connected with feedback circuit;Synchronous rectifier circuit is connected between planar transformer and second filter circuit;Feedback circuit, first TYPE-C interface control circuit and voltage reduction circuit are connected with second filter circuit;Second TYPE-C interface control circuit is connected with voltage reduction circuit, first TYPE-C interface control circuit;Synchronous rectifier circuit includes synchronous rectification control chip U1 and MOS tube Q1.The utility model has the beneficial effect: it can satisfy charger charging efficient, charging stable, compatibility is strong and the design requirement of small and exquisite volume.

Description

Technical Field

[0001] This utility model relates to the field of charger technology, and more specifically, to a control circuit for a multi-port ultra-thin charger. Background Technology

[0002] With the widespread use of electronic devices, the functional and performance requirements of chargers are constantly increasing. Traditional charger designs often suffer from problems such as large size, low efficiency, and electromagnetic interference, especially in multi-port chargers where these issues are more pronounced. Therefore, how to reduce electromagnetic interference, improve device compatibility, and shrink the size of chargers while ensuring efficient charging has become a pressing technical challenge.

[0003] Therefore, this utility model provides a control circuit for a multi-port ultra-thin charger, which can meet the design requirements of high-efficiency charging, stable charging, strong compatibility and small size. Utility Model Content

[0004] To overcome the shortcomings of the existing technology, this utility model provides a control circuit for a multi-port ultra-thin charger, which can meet the design requirements of high-efficiency charging, stable charging, strong compatibility and small size.

[0005] The technical solution adopted by this utility model to solve its technical problem is: a control circuit for a multi-port ultra-thin charger, the improvement of which is that the control circuit of the multi-port ultra-thin charger includes an EMI circuit, a first filter circuit, a planar transformer, a synchronous rectification circuit, a second filter circuit, a feedback circuit, a PWM control circuit, a first TYPE-C interface control circuit, a step-down circuit, and a second TYPE-C interface control circuit; the first filter circuit is connected between the EMI circuit and the PWM control circuit; the primary winding and auxiliary winding of the planar transformer are both connected to the PWM control circuit; the PWM control circuit is connected to the feedback circuit via an optical signal; the synchronous rectification circuit is connected between the secondary winding of the planar transformer and the second filter circuit; the feedback circuit, the first TYPE-C interface control circuit, and the step-down circuit are all connected to the second filter circuit; the second TYPE-C interface control circuit is connected to the step-down circuit and the first TYPE-C interface control circuit;

[0006] The synchronous rectification circuit includes a synchronous rectification control chip U1 and a MOSFET Q1. The synchronous rectification control chip U1 has a GATE pin, an HV pin, an RW pin, a Vo pin, a VDD pin, and a GND pin. The GATE pin is connected to the gate of the MOSFET Q1, the RW pin, the GND pin, the VDD pin, and the Vo pin are all connected to the drain of the MOSFET Q1, and the HV pin is connected to the source of the MOSFET Q1. The drain of the MOSFET Q1 is connected to the secondary winding of the planar transformer, and the source is connected to the second filter circuit.

[0007] In the above structure, the synchronous rectification current also includes resistors R1, R4, R5, R8, capacitor C2, and capacitor C4; one end of resistor R1 is connected to the drain of MOSFET Q1, one end of resistor R8, the GND pin of synchronous rectification control chip U1, one end of capacitor C4, and the Vo pin of synchronous rectification control chip U1, and the other end of R1 is connected to one end of capacitor C2; one end of resistor R4 is connected to the other end of capacitor C2, the source of MOSFET Q1, and the second filter circuit, and the other end is connected to the HV pin of MOSFET Q1; resistor R5 is connected between the gate of MOSFET Q1 and the GATE pin of synchronous rectification control chip U1; the other end of resistor R8 is connected to the RW pin of synchronous rectification control chip U1; and the other end of capacitor C4 is connected to the VDD pin of synchronous rectification control chip U1.

[0008] In the above structure, the first filter circuit includes a bridge rectifier diode, electrolytic capacitors CE2 and CE3, capacitor C3, inductor L1, and resistor R2; the input terminal of the bridge rectifier diode is connected to the EMI circuit, and the output terminal is connected in parallel with electrolytic capacitors CE2, CE3, and C3; the inductor L1 and resistor R2 are both connected between electrolytic capacitors CE2 and CE3, and the inductor L1 is connected to the PWM control circuit.

[0009] In the above structure, the PWM control circuit includes a PWM control chip U2, diodes D1 and D2, a Zener diode ZD1, and a phototransistor PCIB. The PWM control chip U2 has an HV pin, a Drain1 pin, a Drain2 pin, a GND pin, a SW pin, and an FB pin. The HV pin of the PWM control chip U2 is connected to the inductor L1. The Drain1 and Drain2 pins are connected in parallel to the primary winding of the planar transformer. The SW and FB pins are connected in parallel to the auxiliary winding of the planar transformer. The GND pin is grounded. Diode D1 is connected between the Drain1 pin of the PWM control chip U2 and the primary winding of the planar transformer. Diode D2 is connected between the SW pin of the PWM control chip U2 and the auxiliary winding of the planar transformer. The Zener diode ZD1 is connected in parallel with the phototransistor PCIB and is also connected between the FB pin of the PWM control chip U2 and the auxiliary winding of the planar transformer. The phototransistor PCIB is connected to the feedback circuit via an optical signal.

[0010] In the above structure, the second filter circuit includes an electrolytic capacitor CE1. The positive terminal of the electrolytic capacitor CE1 is connected to the synchronous rectification circuit, the first TYPE-C interface control circuit, and the step-down circuit, while the negative terminal is grounded.

[0011] In the above structure, the feedback circuit includes resistor R13, resistor R15, capacitor C6, and photodiode PCIA; resistor R13 is connected in parallel with capacitor C6, with one end connected to the positive terminal of electrolytic capacitor CE1 and the other end connected to the anode of photodiode PCIA; the cathode of photodiode PCIA is connected to the first TYPE-C interface control circuit, and photodiode PCIA is connected to phototransistor PCIB via optical signal; resistor R15 is connected in parallel with photodiode PCIA.

[0012] In the above structure, the first TYPE-C interface control circuit includes a first protocol IC chip U5, a first TYPE-C connector J1, a MOSFET Q3, and a MOSFET Q7. The first protocol IC chip U5 is provided with a VIN pin, a GC pin, a VOUT pin, a CSP pin, a CSN pin, a PFC pin, and an OPTO pin. The VIN pin is connected to the drain of MOSFET Q3, the drain of MOSFET Q7, and the positive terminal of electrolytic capacitor CE1. The GC pin is connected to the gate and source of MOSFET Q3, the VOUT pin, and the first TYPE-C connector J1. The GSP pin and the CSN pin are both connected to the first TYPE-C connector J1. The FPC pin is connected to the gate of MOSFET Q7. The OPTO pin is connected to the cathode of a photodiode. The source of MOSFET Q7 is grounded.

[0013] In the above structure, the buck circuit includes a buck chip U7, a MOSFET Q4, and a MOSFET Q6. The buck chip includes a VIN pin, an EN pin, an HD pin, an ISNS1 pin, an ISNS2 pin, a SW pin, a PGND pin, an LD pin, a BT pin, a VOUT pin, and an FB pin. Specifically, the VIN pin of the buck chip U7 is connected to the drain of the MOSFET Q4 and the VIN pin of the first protocol IC chip U5; the HD pin is connected to the gate of the MOSFET Q4; the ISNS1 pin is connected to the source of the MOSFET Q4, the ISNS2 pin, the SW2 pin and the BT pin of the buck chip, the drain of the MOSFET Q6, and the second TYPE-C interface control circuit; the PGND pin is grounded; the LD pin is connected to the gate of the MOSFET Q6; and the VOUT and FB pins of the buck chip U7 are connected to the second TYPE-C interface control circuit. The source of the MOSFET Q6 is grounded.

[0014] In the above structure, the second TYPE-C interface control circuit includes a second protocol IC chip, a second TYPE-C connector J2, and a MOSFET Q8; the second protocol IC chip U6 has twenty-one pins, wherein the fourth pin of the second protocol IC chip U6 is connected to the VOUT pin of the buck chip U7, the seventh pin of the second protocol IC chip U6 is connected to the eighth pin and the second TYPE-C connector J2, the eighteenth pin of the second protocol IC chip U6 is connected to the source of the MOSFET Q8 and the second TYPE-C connector J2, the nineteenth pin of the second protocol IC chip U6 is connected to the gate of the MOSFET Q8, and the twentieth pin of the second protocol IC chip U6 is connected to the twenty-first pin, the drain of the MOSFET Q6, and the drain of the MOSFET Q8.

[0015] In the above structure, the EMI circuit includes a common-mode inductor LF1, a capacitor CX1, a resistor RX1, a resistor RX2, a resistor RX3, and a resistor RX4. The input terminal of the common-mode inductor LF1 is connected to the power supply, and its output terminal is connected in parallel with the capacitor CX1. The resistors RX1 and RX2 are connected in parallel, with one end of the resistor RX2 connected to one end of the capacitor CX1 and the other end of the resistor RX2 connected to one end of the resistor RX4. The resistors RX3 and RX4 are connected in parallel, with the other end of the resistor RX4 connected to the other end of the capacitor CX1.

[0016] The beneficial effects of this invention are as follows: the EMI circuit in this invention can avoid mutual interference when charging multiple electronic devices in parallel, providing a clearer power signal to effectively reduce electromagnetic interference, thereby improving the stability and compatibility of the charger; the synchronous rectification circuit adopts the design of synchronous rectification control chip U1 and MOSFET Q1, which can reduce heat generation and energy loss, thereby improving the power conversion efficiency of the charger; the use of a planar transformer can achieve high power output in a small volume, to meet the design requirements of a small and ultra-thin charger; therefore, this invention can meet the design requirements of chargers that are efficient, stable, highly compatible, and compact. Attached Figure Description

[0017] Figure 1 This is a block diagram of the control circuit of a multi-port ultra-thin charger according to the present invention;

[0018] Figure 2 This is a connection diagram of the planar transformer in a multi-port ultra-thin charger according to this utility model;

[0019] Figure 3 This is a connection diagram of the first TYPE-C interface control circuit of a multi-port ultra-thin charger according to this utility model;

[0020] Figure 4 This is a connection diagram of the second TYPE-C interface control circuit of a multi-port ultra-thin charger according to this utility model. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] The following will clearly and completely describe the concept, specific structure, and technical effects of this utility model in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of this utility model. Obviously, the described embodiments are only a part of the embodiments of this utility model, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are all within the scope of protection of this utility model. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this utility model can be combined interactively without contradicting each other.

[0023] Reference Figure 1 and Figure 2As shown, this utility model discloses a control circuit for a multi-port ultra-thin charger. The control circuit includes an EMI circuit 1, a first filter circuit 2, a planar transformer 3, a synchronous rectification circuit 4, a second filter circuit 6, a feedback circuit 7, a PWM control circuit 5, a first Type-C interface control circuit 8, a step-down circuit 9, and a second Type-C interface control circuit 10. The first filter circuit 2 is connected between the EMI circuit 1 and the PWM control circuit 5. Both the primary winding and auxiliary winding of the planar transformer 3 are connected to the PWM control circuit 5. The control circuit 5 is connected to the feedback circuit 7 via an optical signal; the synchronous rectification circuit 4 is connected between the secondary winding of the planar transformer 3 and the second filter circuit 6; the feedback circuit 7, the first TYPE-C interface control circuit 8, and the step-down circuit 9 are all connected to the second filter circuit 6; the second TYPE-C interface control circuit 10 is connected to the step-down circuit 9 and the first TYPE-C interface control circuit 8; the synchronous rectification circuit 4 includes a synchronous rectification control chip U1, a MOSFET Q1, resistors R1, R4, R5, and R8, capacitors C2 and C4, and the synchronous rectification... The current control chip U1 has a GATE pin, an HV pin, an RW pin, a Vo pin, a VDD pin, and a GND pin. The GATE pin is connected to the gate of the MOSFET Q1. The RW, GND, VDD, and Vo pins are all connected to the drain of the MOSFET Q1. The HV pin is connected to the source of the MOSFET Q1. The drain of the MOSFET Q1 is connected to the secondary winding of the planar transformer 3, and the source is connected to the second filter circuit 6. One end of resistor R1 is connected to the drain of the MOSFET Q1, one end of resistor R8, and the GND pin of the synchronous rectification control chip U1. One end of resistor R1 is connected to one end of capacitor C4 and the Vo pin of synchronous rectification control chip U1; the other end of resistor R1 is connected to one end of capacitor C2; one end of resistor R4 is connected to the other end of capacitor C2, the source of MOSFET Q1 and the second filter circuit 6, and the other end is connected to the HV pin of MOSFET Q1; resistor R5 is connected between the gate of MOSFET Q1 and the GATE pin of synchronous rectification control chip U1; the other end of resistor R8 is connected to the RW pin of synchronous rectification control chip U1; and the other end of capacitor C4 is connected to the VDD pin of synchronous rectification control chip U1.

[0024] It should be noted that in this embodiment, the EM circuit is used to handle electromagnetic interference that may be generated in the power supply, preventing these interferences from affecting the stability of the charger circuit and the normal operation of other electronic devices. When the charger is working, especially with high-frequency switching power supplies, radiated or conducted interference may be generated. The EMI circuit 1 eliminates noise through filtering, shielding, and current limiting. The first filter circuit 2 is used to perform preliminary filtering of high-frequency interference and fluctuations in the input power supply to remove high-frequency noise in the power supply, making it more stable and providing a stable DC voltage signal to subsequent circuits, avoiding the impact of high-frequency noise on other circuits. The planar transformer 3 plays a voltage conversion role in the charger. The high-voltage input current is converted into the required low-voltage current to adapt to the voltage and current requirements of different devices. The planar transformer 3 is small in size, highly efficient, and highly adaptable, making it suitable for the ultra-thin design of chargers. The synchronous rectification current is used to improve power conversion efficiency and reduce energy loss. Traditional rectifier circuits use diodes, while the synchronous rectifier circuit 4 uses MOSFETs instead of diodes to reduce switching losses and improve efficiency. Specifically, the synchronous rectifier circuit 4 includes a synchronous rectification control chip U1, a MOSFET Q1, resistors R1, R4, R5, and R8, and capacitors C2 and C4. In this design of the synchronous rectifier circuit 4, the MOSFET Q1 is used to convert the high-voltage input current into the required low-voltage current. Alternating current (AC) is converted to direct current (DC). The synchronous rectification control chip U1 controls the switching of the MOSFET. The source of MOSFET Q1 is connected to the second filter circuit 6, and the drain is connected to the secondary winding of the planar transformer 3. Resistors R1, R4, R5, and R8 help control and adjust the operating state of the MOSFET, while capacitors C2 and C4 are used for filtering to ensure stable output voltage. The PWM control circuit 5 is used to adjust the operating mode of the planar transformer 3, mainly by controlling the switching frequency and duty cycle. The PWM circuit realizes voltage regulation, power control, and load adjustment. It can dynamically adjust the operating state according to the input voltage and output demand to ensure stable output. The second filter circuit 6 is used to further purify the power. The circuit eliminates voltage fluctuations and high-frequency noise in the power source, ensuring a more stable output voltage. The feedback circuit 7 monitors the stability of the output voltage or current and feeds real-time data back to the PWM control circuit 5, thereby adjusting the output voltage and current to ensure that the output voltage is always within a stable range, avoiding damage to the equipment caused by overvoltage or overcurrent. The first TYPE-C interface control circuit 8 and the second TYPE-C interface control circuit 10 are mainly responsible for managing the output of the two TYPE-C interfaces. Each TYPE-C interface requires a separate control circuit to manage the output voltage and current, ensuring that different devices can obtain the required stable power when charging through these two interfaces.The step-down circuit 9 is used to reduce the high-voltage current to a voltage suitable for the device. Chargers typically need to convert from standard mains voltage to a lower voltage, and the step-down circuit 9 helps convert the high input voltage to the required low output voltage. In specific implementations of this invention, the control circuit of the multi-port ultra-thin charger, through the EMI circuit 1, can avoid mutual interference when charging multiple electronic devices in parallel, providing a clearer power signal to effectively reduce electromagnetic interference, thereby improving the charger's stability and compatibility. The synchronous rectification circuit 4, using a synchronous rectification control chip U1 and a MOSFET Q1, reduces heat generation and energy loss, improving the charger's energy conversion efficiency. The use of the planar transformer 3 enables high power output within a small volume, meeting the charger's small size and ultra-thin design requirements. Therefore, this invention satisfies the design requirements of a charger with high charging efficiency, stable charging, strong compatibility, and compact size.

[0025] Reference Figure 2 As shown, the first filter circuit 2 includes a bridge rectifier diode, electrolytic capacitors CE2 and CE3, capacitor C3, inductor L1, and resistor R2; the input terminal of the bridge rectifier diode is connected to the EMI circuit 1, and the output terminal is connected in parallel with electrolytic capacitors CE2, CE3, and C3; the inductor L1 and resistor R2 are both connected between electrolytic capacitors CE2 and CE3, and the inductor L1 is connected to the PWM control circuit 5.

[0026] It should be noted that, in this embodiment, the bridge rectifier diode is used to rectify the AC power supply (such as AC mains) into pulsating DC power. Specifically, the bridge rectifier diode is a bridge structure composed of four diodes, which can convert both the positive and negative half-cycles of the input AC power into unidirectional current, and the output is pulsating DC. The electrolytic capacitors CE2 and CE3 and capacitor C3 are used to filter and smooth the pulsating DC after bridge rectification. The inductor L1 is an important component of the filter circuit, which can effectively suppress the conduction of high-frequency noise and prevent high-frequency AC components from passing through through its own inductance characteristics, thereby further purifying the current. The resistor R2 plays the role of limiting surge current and stabilizing the circuit.

[0027] Continue to refer to Figure 2As shown, the PWM control circuit 5 includes a PWM control chip U2, diodes D1 and D2, a Zener diode ZD1, and a phototransistor PCIB. The PWM control chip U2 has an HV pin, a Drain1 pin, a Drain2 pin, a GND pin, a SW pin, and an FB pin. The HV pin of the PWM control chip U2 is connected to the inductor L1. The Drain1 and Drain2 pins are connected in parallel to the primary winding of the planar transformer 3. The SW and FB pins are connected in parallel to the auxiliary winding of the planar transformer 3. The GND pin is grounded. Diode D1 is connected between the Drain1 pin of the PWM control chip U2 and the primary winding of the planar transformer 3. Diode D2 is connected between the SW pin of the PWM control chip U2 and the auxiliary winding of the planar transformer 3. The Zener diode ZD1 is connected in parallel with the phototransistor PCIB and is also connected between the FB pin of the PWM control chip U2 and the auxiliary winding of the planar transformer 3. The phototransistor PCIB is connected to the feedback circuit 7 via an optical signal.

[0028] It should be noted that, in this embodiment, the PWM control chip U2 is used to control the current flow in the primary and auxiliary windings of the planar transformer 3 by adjusting the pulse width modulation (PWM) signal, thereby regulating the output voltage of the planar transformer 3 and achieving a stable power output. The diode D1 is connected between the Drain1 pin of the PWM control chip U1 and the primary winding of the planar transformer 3 to prevent reverse current generated by changes in the magnetic field of the planar transformer 3 or load variations. Since reverse current can damage the PWM control chip U1 and the planar transformer 3, diode D1 is designed to prevent the generation of such current. The diode D2 is connected between the SW pin of the PWM control chip and the auxiliary winding of the planar transformer 3, similarly preventing reverse current and ensuring that the current flows in the correct direction. The Zener diode ZD1 is used to stabilize the voltage, avoid excessive voltage, and ensure that the circuit components are not damaged. The phototransistor PCIB converts the light signal into an electrical signal through the photoelectric effect, thereby affecting the feedback current. Specifically, it precisely adjusts the current in the feedback circuit 7 by receiving the light signal, thereby regulating the working state of the PWM control chip U1 and ultimately ensuring the stability of the output voltage.

[0029] Continue to refer to Figure 2 As shown, the second filter circuit 6 includes an electrolytic capacitor CE1. The positive terminal of the electrolytic capacitor CE1 is connected to the synchronous rectification circuit 4, the first TYPE-C interface control circuit 8, and the step-down circuit 9, while the negative terminal is grounded.

[0030] It should be noted that in this embodiment, the second filter circuit 6 smooths the voltage through the electrolytic capacitor CE1, reduces fluctuations and noise in the current, and provides a stable power supply.

[0031] Continue to refer to Figure 2 As shown, the feedback circuit 7 includes resistor R13, resistor R15, capacitor C6, and photodiode PCIA; resistor R13 is connected in parallel with capacitor C6, with one end connected to the positive terminal of electrolytic capacitor CE1 and the other end connected to the anode of photodiode PCIA; the cathode of photodiode PCIA is connected to the first TYPE-C interface control circuit 8, and photodiode PCIA is connected to phototransistor PCIB via optical signal; resistor R15 is connected in parallel with photodiode PCIA.

[0032] It should be noted that in this embodiment, the feedback circuit 7 achieves precise control of the circuit output by converting and amplifying the optical signal and electrical signal between the photodiode PCIA and the phototransistor PCIB; the resistors R13 and R15 and the capacitor C6 play the roles of filtering, stabilizing and regulating in the circuit to ensure the smooth transmission of the feedback signal.

[0033] Reference Figure 3 As shown, the first TYPE-C interface control circuit 8 includes a first protocol IC chip U5, a first TYPE-C connector J1, a MOSFET Q3, and a MOSFET Q7. The first protocol IC chip U5 is provided with a VIN pin, a GC pin, a VOUT pin, a CSP pin, a CSN pin, a PFC pin, and an OPTO pin. The VIN pin is connected to the drain of MOSFET Q3, the drain of MOSFET Q7, and the positive terminal of electrolytic capacitor CE1. The GC pin is connected to the gate and source of MOSFET Q3, the VOUT pin, and the first TYPE-C connector J1. The GSP pin and the CSN pin are both connected to the first TYPE-C connector J1. The FPC pin is connected to the gate of MOSFET Q7. The OPTO pin is connected to the cathode of a photodiode. The source of MOSFET Q7 is grounded.

[0034] It should be noted that, in this embodiment, the first protocol IC chip U5 is used to process protocol signals, control the transmission of current and voltage, and communicate with other components; the function of the MOSFETs Q3 and Q7 is to control the current switching between the source and drain through the gate; the part of the TYPE-C connector J1 circuit that is electrically connected to the external device is responsible for transmitting power and data to the external device.

[0035] Reference Figure 4As shown, the step-down circuit 9 includes a step-down chip U7, a MOSFET Q4, and a MOSFET Q6. The step-down chip includes a VIN pin, an EN pin, an HD pin, an ISNS1 pin, an ISNS2 pin, a SW pin, a PGND pin, an LD pin, a BT pin, a VOUT pin, and an FB pin. The VIN pin of the step-down chip U7 is connected to the drain of the MOSFET Q4 and the VIN pin of the first protocol IC chip U5. The HD pin is connected to the gate of the MOSFET Q4. The ISNS1 pin is connected to the source of the MOSFET Q4, the ISNS2 pin, the SW2 pin and the BT pin of the step-down chip, the drain of the MOSFET Q6, and the second TYPE-C interface control circuit 10. The PGND pin is grounded. The LD pin is connected to the gate of the MOSFET Q6. The VOUT and FB pins of the step-down chip U7 are connected to the second TYPE-C interface control circuit 10. The source of the MOSFET Q6 is grounded.

[0036] It should be noted that in this embodiment, the step-down chip U7 is used to regulate the input voltage and output a lower stable voltage; the MOSFETs Q4 and Q6 function as a current switch and current control, respectively. The drain of MOSFET Q4 is connected to the VIN pin of the step-down chip, and its source is connected to the ISNS1 pin of the step-down chip. The gate of MOSFET Q4 is controlled by the HD pin of the step-down chip U7 to regulate the current flow. The gate of MOSFET Q6 is controlled by the LD pin of the step-down chip U7. The source of MOSFET Q6 is grounded, and its drain is connected to the output terminal of the circuit to control the output current flow and voltage stability.

[0037] Continue to refer to Figure 4 As shown, the second TYPE-C interface control circuit 10 includes a second protocol IC chip, a second TYPE-C connector J2, and a MOSFET Q8. The second protocol IC chip U6 has twenty-one pins, wherein the fourth pin of the second protocol IC chip U6 is connected to the VOUT pin of the step-down chip U7, the seventh pin of the second protocol IC chip U6 is connected to the eighth pin and the second TYPE-C connector J2, the eighteenth pin of the second protocol IC chip U6 is connected to the source of the MOSFET Q8 and the second TYPE-C connector J2, the nineteenth pin of the second protocol IC chip U6 is connected to the gate of the MOSFET Q8, and the twentieth pin of the second protocol IC chip U6 is connected to the twenty-first pin, the drain of the MOSFET Q6, and the drain of the MOSFET Q8.

[0038] It should be noted that, in this embodiment, the second protocol chip U6 is used to parse the data protocol of the TYPE-C interface and interact with other circuit modules; the second TYPE-C connector J2 serves as the external connection interface of the circuit, providing power and signal interaction with external devices; the MOS transistor Q8 is used to control the switching of current through the gate, ensuring stable transmission of power and signals.

[0039] Reference Figure 2 As shown, the EMI circuit 1 includes a common-mode inductor LF1, a capacitor CX1, a resistor RX1, a resistor RX2, a resistor RX3, and a resistor RX4. The input terminal of the common-mode inductor LF1 is connected to the power supply, and its output terminal is connected in parallel with the capacitor CX1. The resistors RX1 and RX2 are connected in parallel, with one end of the resistor RX2 connected to one end of the capacitor CX1 and the other end of the resistor RX2 connected to one end of the resistor RX4. The resistors RX3 and RX4 are connected in parallel, with the other end of the resistor RX4 connected to the other end of the capacitor CX1.

[0040] It should be noted that, in this embodiment, the input terminal of the common-mode inductor LF1 is connected to the power supply to filter the power signal entering the circuit and prevent high-frequency noise from entering; the output terminal of the common-mode inductor LF1 is connected in parallel with the capacitor CX1 to filter out high-frequency common-mode interference signals, thereby reducing electromagnetic interference; the capacitor CX1 is used to filter out high-frequency noise because it allows low-frequency signals to pass through while guiding high-frequency signals to ground, reducing the impact of noise; the resistors RX1, RX2, RX3, and RX4 are used to provide damping, helping to absorb and dissipate the energy of electromagnetic interference, while limiting the flow of current to ensure that the voltage and current in the circuit are within an appropriate range.

[0041] The above is a detailed description of the preferred embodiments of the present utility model. However, the present utility model is not limited to the described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present utility model. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A control circuit for a multi-port ultra-thin charger, characterized in that, The control circuit of the multi-port ultra-thin charger includes an EMI circuit, a first filter circuit, a planar transformer, a synchronous rectification circuit, a second filter circuit, a feedback circuit, a PWM control circuit, a first Type-C interface control circuit, a buck circuit, and a second Type-C interface control circuit. The first filter circuit is connected between the EMI circuit and the PWM control circuit. The primary winding and auxiliary winding of the planar transformer are both connected to the PWM control circuit. The PWM control circuit is connected to the feedback circuit via an optical signal. The synchronous rectification circuit is connected between the secondary winding of the planar transformer and the second filter circuit. The feedback circuit, the first Type-C interface control circuit, and the buck circuit are all connected to the second filter circuit. The second Type-C interface control circuit is connected to the buck circuit and the first Type-C interface control circuit. The synchronous rectification circuit includes a synchronous rectification control chip U1 and a MOSFET Q1. The synchronous rectification control chip U1 has a GATE pin, an HV pin, an RW pin, a Vo pin, a VDD pin, and a GND pin. The GATE pin is connected to the gate of the MOSFET Q1, the RW pin, the GND pin, the VDD pin, and the Vo pin are all connected to the drain of the MOSFET Q1, and the HV pin is connected to the source of the MOSFET Q1. The drain of the MOSFET Q1 is connected to the secondary winding of the planar transformer, and the source is connected to the second filter circuit.

2. The control circuit of a multi-port ultra-thin charger according to claim 1, characterized in that, The synchronous rectification current also includes resistors R1, R4, R5, R8, capacitors C2 and C4; one end of resistor R1 is connected to the drain of MOSFET Q1, one end of resistor R8, the GND pin of synchronous rectification control chip U1, one end of capacitor C4, and the Vo pin of synchronous rectification control chip U1, and the other end of R1 is connected to one end of capacitor C2; one end of resistor R4 is connected to the other end of capacitor C2, the source of MOSFET Q1, and the second filter circuit, and the other end is connected to the HV pin of MOSFET Q1; resistor R5 is connected between the gate of MOSFET Q1 and the GATE pin of synchronous rectification control chip U1; the other end of resistor R8 is connected to the RW pin of synchronous rectification control chip U1; and the other end of capacitor C4 is connected to the VDD pin of synchronous rectification control chip U1.

3. The control circuit of a multi-port ultra-thin charger according to claim 1, characterized in that, The first filter circuit includes a bridge rectifier diode, electrolytic capacitors CE2 and CE3, capacitor C3, inductor L1, and resistor R2; the input terminal of the bridge rectifier diode is connected to the EMI circuit, and the output terminal is connected in parallel with electrolytic capacitors CE2, CE3, and C3; inductor L1 and resistor R2 are both connected between electrolytic capacitors CE2 and CE3, and inductor L1 is connected to the PWM control circuit.

4. The control circuit of a multi-port ultra-thin charger according to claim 3, characterized in that, The PWM control circuit includes a PWM control chip U2, diodes D1 and D2, a Zener diode ZD1, and a phototransistor PCIB. The PWM control chip U2 has an HV pin, a Drain1 pin, a Drain2 pin, a GND pin, a SW pin, and an FB pin. The HV pin of the PWM control chip U2 is connected to inductor L1; the Drain1 and Drain2 pins are connected in parallel to the primary winding of the planar transformer; the SW and FB pins are connected in parallel to the auxiliary winding of the planar transformer; and the GND pin is grounded. Diode D1 is connected between the Drain1 pin of the PWM control chip U2 and the primary winding of the planar transformer. Diode D2 is connected between the SW pin of the PWM control chip U2 and the auxiliary winding of the planar transformer. The Zener diode ZD1 is connected in parallel with the phototransistor PCIB and is also connected between the FB pin of the PWM control chip U2 and the auxiliary winding of the planar transformer. The phototransistor PCIB is connected to the feedback circuit via an optical signal.

5. The control circuit of a multi-port ultra-thin charger according to claim 4, characterized in that, The second filter circuit includes an electrolytic capacitor CE1. The positive terminal of the electrolytic capacitor CE1 is connected to the synchronous rectification circuit, the first TYPE-C interface control circuit, and the step-down circuit, while the negative terminal is grounded.

6. The control circuit of a multi-port ultra-thin charger according to claim 5, characterized in that, The feedback circuit includes resistors R13 and R15, capacitor C6, and photodiode PC IA; resistor R13 is connected in parallel with capacitor C6, with one end connected to the positive terminal of electrolytic capacitor CE1 and the other end connected to the anode of photodiode PC IA; the cathode of photodiode PC IA is connected to the first TYPE-C interface control circuit, and photodiode PC IA is connected to phototransistor PCIB via an optical signal; resistor R15 is connected in parallel with photodiode PC IA.

7. The control circuit of a multi-port ultra-thin charger according to claim 6, characterized in that, The first TYPE-C interface control circuit includes a first protocol IC chip U5, a first TYPE-C connector J1, a MOSFET Q3, and a MOSFET Q7. The first protocol IC chip U5 is provided with a VIN pin, a GC pin, a VOUT pin, a CSP pin, a CSN pin, a PFC pin, and an OPTO pin. The VIN pin is connected to the drain of MOSFET Q3, the drain of MOSFET Q7, and the positive terminal of electrolytic capacitor CE1. The GC pin is connected to the gate and source of MOSFET Q3, the VOUT pin, and the first TYPE-C connector J1. The GSP pin and the CSN pin are both connected to the first TYPE-C connector J1. The FPC pin is connected to the gate of MOSFET Q7. The OPTO pin is connected to the cathode of a photodiode. The source of MOSFET Q7 is grounded.

8. The control circuit of a multi-port ultra-thin charger according to claim 7, characterized in that, The step-down circuit includes a step-down chip U7, a MOSFET Q4, and a MOSFET Q6. The step-down chip includes a VIN pin, an EN pin, an HD pin, an ISNS1 pin, an ISNS2 pin, a SW pin, a PGND pin, an LD pin, a BT pin, a VOUT pin, and an FB pin. Specifically, the VIN pin of the step-down chip U7 is connected to the drain of the MOSFET Q4 and the VIN pin of the first protocol IC chip U5; the HD pin is connected to the gate of the MOSFET Q4; the ISNS1 pin is connected to the source of the MOSFET Q4, the ISNS2 pin, the SW2 pin and the BT pin of the step-down chip, the drain of the MOSFET Q6, and the second TYPE-C interface control circuit; the PGND pin is grounded; the LD pin is connected to the gate of the MOSFET Q6; and the VOUT and FB pins of the step-down chip U7 are connected to the second TYPE-C interface control circuit. The source of the MOSFET Q6 is grounded.

9. The control circuit of a multi-port ultra-thin charger according to claim 8, characterized in that, The second TYPE-C interface control circuit includes a second protocol IC chip, a second TYPE-C connector J2, and a MOSFET Q8. The second protocol IC chip U6 has twenty-one pins, wherein the fourth pin of the second protocol IC chip U6 is connected to the VOUT pin of the buck chip U7, the seventh pin of the second protocol IC chip U6 is connected to the eighth pin and the second TYPE-C connector J2, the eighteenth pin of the second protocol IC chip U6 is connected to the source of the MOSFET Q8 and the second TYPE-C connector J2, the nineteenth pin of the second protocol IC chip U6 is connected to the gate of the MOSFET Q8, and the twentieth pin of the second protocol IC chip U6 is connected to the twenty-first pin, the drain of the MOSFET Q6, and the drain of the MOSFET Q8.

10. The control circuit of a multi-port ultra-thin charger according to claim 1, characterized in that, The EMI circuit includes a common-mode inductor LF1, a capacitor CX1, resistors RX1, RX2, RX3, and RX4. The input terminal of the common-mode inductor LF1 is connected to the power supply, and its output terminal is connected in parallel with the capacitor CX1. Resistors RX1 and RX2 are connected in parallel, with one end of RX2 connected to one end of the capacitor CX1 and the other end of RX2 connected to one end of the resistor RX4. Resistors RX3 and RX4 are connected in parallel, with the other end of RX4 connected to the other end of the capacitor CX1.

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