DISPLAY DEVICE

Abstract

A display device (110) may have the following: a first insulating layer (223r1) in a first subpixel (SP1) with a first aperture (PH1); a second insulating layer (223r2) in a second subpixel (SP2) with a first groove (PG1); a first pixel electrode (PEr1) in the first subpixel (SP1) located at the first aperture (PH1) and extending along an inner lateral surface of the first insulating layer (223r1); a second pixel electrode (PEr2) in the second subpixel (SP2) located at a lower surface of the first groove (PG1) and extending along an inner lateral surface of the first groove (PG1); a first bank (231) arranged on the first and second pixel electrode (PEr1, PEr2) and having a first hole (BH1) that overlaps the first opening (PH1) and is smaller than it, and a second hole (BH2) that overlaps the first groove (PG1) and is smaller than it;and a common electrode (CE) on a first and a second light-emitting layer (EML1, EML2) extending along the respective inner lateral surfaces of the first and second holes (BH1, BH2) of the first bank (231) to a top surface of the first bank (231).

Description

TECHNICAL AREA Embodiments of the present disclosure relate to a display device. BACKGROUND Display devices that show different types of information on a screen are a core technology in the age of information and communication technology and serve to provide users with diverse information. Display devices may be required to offer excellent display quality and high light emission efficiency. In particular, it may be necessary for the display device to maintain excellent display quality while a user views the screen. However, the light reflected from identical pixels of the display device can experience constructive and destructive interference, leading to a problem where ring-shaped mura occurs due to the reflected light. The description in the "Background" section should not be considered prior art solely because it is mentioned in or associated with this section. The description in the "Background" section contains information that describes one or more aspects of the technology in question, and the description in this section does not limit the scope of the invention. SUMMARY Embodiments of the present disclosure can provide a display device capable of converting reflected light, which causes constructive and destructive interference between pixels, into reflected light that causes only destructive interference. Embodiments of the present disclosure may include a display device having a first pixel and a second pixel in which no ring-shaped mura appears even at a wide viewing angle. The aspects of the embodiments of this disclosure are not limited to those described herein, and other, unmentioned aspects will be clearly understandable to the person skilled in the art from this disclosure. Embodiments of this disclosure may provide a display device according to claim 1. Further embodiments are described in the dependent claims. Embodiments of the present disclosure can provide a display device comprising: a substrate; a first planarization layer arranged on the substrate; a second planarization layer arranged on the first planarization layer; a first insulating layer arranged on the second planarization layer, located in a first subpixel region and having a first opening; a second insulating layer arranged on the second planarization layer, located in a second subpixel region and having a first groove; a first pixel electrode arranged in the first subpixel region, located on the second planarization layer at the first opening and extending along an inner lateral surface of the first insulating layer;a second pixel electrode located in the second subpixel region, situated on a lower surface of the first groove and extending along an inner lateral surface of the first groove; a first bank located on the first and second pixel electrodes, comprising a first hole overlapping the first opening and smaller than the first opening, and a second hole overlapping the first groove and smaller than the first groove; a first light-emitting layer located on the first pixel electrode; a second light-emitting layer located on the second pixel electrode; and a common electrode located on the first and second light-emitting layers, extending along the respective inner lateral surfaces of the first and second holes of the first bank to the upper surface of the first bank. According to embodiments of the present disclosure, a display device can be provided which is able to suppress annular mura even at a wide viewing angle, including a first pixel and a second pixel. According to embodiments of the present disclosure, a display device with improved reflection visibility can be provided by providing different distances between the substrate and the pixel electrodes in a first subpixel of the first pixel and a second subpixel of the second pixel. According to embodiments of the present disclosure, a display device can be provided which enables low power consumption by improving the reflectivity. According to embodiments of the present disclosure, a display device can be provided which also has excellent luminance and color properties in a lateral viewing angle direction, including a first subpixel having a first partial aperture and a second partial aperture, and a second subpixel having a first sub-groove and a second sub-groove. According to embodiments of the present disclosure, a display device can be provided which, due to excellent luminosity characteristics at a lateral viewing angle, enables low-power control. The advantages of the embodiments of the present disclosure are not limited to those described above, and other, unmentioned advantages will be clearly apparent to the person skilled in the art from the present disclosure. Further features, advantages, and aspects of the present disclosure are partly set forth in the following description and partly become apparent from the present disclosure or can be learned through the practical application of the inventive concepts provided herein. Further features, advantages, and aspects of the present disclosure can be realized and achieved through the descriptions provided in or derivable from the present disclosure, as well as through the claims and drawings thereto. It is intended that all such features, advantages, and aspects are contained in this description, fall within the scope of the present disclosure, and are protected by the following claims. Nothing in this section should be considered a limitation of these claims. Further features, advantages, and aspects are discussed below in connection with embodiments of the present disclosure. It is understood that both the foregoing description and the following description of the present disclosure are examples and serve to further explain the disclosure according to the claims. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, included for a better understanding of the present disclosure, form part of this disclosure and are incorporated herein. They illustrate aspects and embodiments of the present disclosure and, together with the description, serve to explain principles and examples of the disclosure. Fig. 1 illustrates a top view of a display device according to embodiments of the present disclosure. Fig. 2 illustrates a display device according to embodiments of the present disclosure. Fig. 3 illustrates a cross-section of a display device according to embodiments of the present disclosure. Fig. 4 illustrates a cross-section of a first subpixel and a second subpixel of a display device according to embodiments of the present disclosure.Figure 5 illustrates a cross-section of a first subpixel and a second subpixel of a display device according to embodiments of the present disclosure. Figure 6 illustrates a top view of a first subpixel and a second subpixel of a display device according to embodiments of the present disclosure. Figure 7 illustrates a cross-section of a first subpixel and a second subpixel of a display device according to embodiments of the present disclosure. Figure 8 illustrates a top view of a first subpixel and a second subpixel of a display device according to embodiments of the present disclosure. Figure 9 illustrates a pixel arrangement of a display device according to embodiments of the present disclosure. Figures 10, 11, 12 to 13 illustrate cross-sections of a first pixel and a second pixel of a display device according to embodiments of the present disclosure.Figure 14 illustrates a cross-section of a first subpixel and a second subpixel of a display device according to embodiments of the present disclosure. Figure 15 illustrates a top view of a first subpixel and a second subpixel of a display device according to embodiments of the present disclosure. Figure 16 illustrates a cross-section of a first subpixel and a second subpixel of a display device according to embodiments of the present disclosure. Figure 17 illustrates a top view of a first subpixel and a second subpixel of a display device according to embodiments of the present disclosure. Unless otherwise specified, the same drawing reference symbols in the drawings and the detailed description refer to the same elements, features, and structures. The sizes, lengths, and thicknesses of layers, areas, and elements, as well as their representation, may be exaggerated for clarity, illustration, and / or convenience. DETAILED DESCRIPTION Detailed reference will now be made to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, a detailed description of known processes, functions, structures, or configurations may unnecessarily obscure aspects of the present disclosure, so that such a detailed description may have been omitted for the sake of brevity. Furthermore, repetitive descriptions may be omitted for the sake of brevity. The sequence of the described processing steps and / or operations is a non-limiting example. The sequence of steps and / or operations is not limited to that set forth here and may be modified to occur in a different order than that described herein, with the exception of those steps and / or operations that must necessarily be performed in a specific sequence. In one or more examples, two successive operations may be performed essentially simultaneously, or the two operations may be performed in reverse order or in a different order altogether, depending on the function or operation in question. Unless otherwise specified, identical reference numerals can refer to identical elements, even if they are shown in different drawings. Unless otherwise specified, identical reference numerals can be used to refer to identical or substantially identical elements throughout the description and drawings. In one or more aspects, identical elements (or elements with identical names) in different drawings can have the same or substantially the same functions and properties, unless otherwise specified. The names of the respective elements used in the following explanations have been chosen for simplicity only and may therefore differ from those in actual products. The advantages and features of the present disclosure, as well as its implementation methods, are explained with reference to the embodiments of the present disclosure, which are described with reference to the accompanying drawings. However, the present disclosure can be embodied in different forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are examples and are provided to ensure that this disclosure is complete and comprehensive, to help those skilled in the art understand the inventive concepts, without limiting the scope of protection of the present disclosure. The shapes, dimensions (e.g., sizes, lengths, widths, heights, thicknesses, positions, radii, diameters, and areas), proportions, ratios, angles, numbers, the number of elements, and the like disclosed herein, including those illustrated in the drawings, are merely examples, and therefore the present disclosure is not limited to the illustrated details. It is noted, however, that the relative dimensions of the components illustrated in the drawings are part of the present disclosure. When the terms “have”, “have”, “contain”, “include”, “form”, “consist of”, “formed of”, “composed of”, or similar terms are used in reference to one or more elements (e.g., layers, films, components, electrodes, structures, transistors, sections, elements, parts, areas, surfaces, segments, steps, processes, and / or similar), one or more other elements may be added unless a term such as “only” or similar is used. The terms used in this disclosure serve only to describe certain embodiments and are not intended to limit the scope of this disclosure. Singular terms may also have plural forms unless the context clearly indicates otherwise. For example, an element may be one or more elements. An element may have a plurality of elements.The word "exemplary" is used in the sense of "serving as an example or illustration." Embodiments are exemplary embodiments. Aspects are exemplary aspects. In one or more implementations, "embodiments," "examples," "aspects," and the like should not be interpreted as being preferable or advantageous over other implementations. An embodiment, an example, an exemplary embodiment, an aspect, or the like may refer to one or more embodiments, one or more examples, one or more exemplary embodiments, one or more aspects, or the like, unless otherwise specified. Furthermore, the term "may" encompasses all meanings of the term "can." In one or more aspects, unless explicitly stated otherwise, an element, feature, or corresponding piece of information (e.g., a level, range, dimension, size, or the like) is interpreted as having a margin of error or tolerance, even if no explicit description of such a margin of error or tolerance is provided. A margin of error or tolerance can be caused by various factors (e.g., process factors, internal or external influences, noise, or the like). When interpreting a numerical value, that value is interpreted as having a margin of error unless explicitly stated otherwise. When a positional relationship between two elements (e.g., layers, films, components, electrodes, structures, transistors, sections, parts, parts, areas, surfaces, subsections, and / or the like) is described using any term such as "on," "on a top surface of," "there," "on a top surface of," "above," "below," "above," "upper," "at an upper part," "on a top surface," "below," "lower," "at a lower part," "on a lower surface," "below," "near," "in the vicinity of," "adjacent to," "next to," "beside," "on or on one side of," "along," and / or similar terms denoting a position or location, one or more other elements may be located between the two elements unless a more restrictive term such as "immediately," "directly," or "near" is used.For example, when one element and another element are described using one of the preceding terms, this description should be interpreted as including both a case where the elements are in direct contact with each other and a case where one or more additional elements are positioned between or between them. Furthermore, spatially relative terms such as those above, as well as other terms like "front," "back," "rear," "left," "right," "above," "below," "upper / upper / upper," "lower / lower / lower," "downward," "upward," "upward," "downward," "column," "row," "vertical," "horizontal," "diagonal," and the like, refer to a frame of reference. These terms can be used, for example, to illustrate a relative relationship between elements, including any correlation, as shown in the drawings.The embodiments of the disclosure are not limited thereto. The spatially relative terms are to be understood as terms that, in addition to the orientation shown in the drawings or described herein, also encompass different orientations of the elements in use or operation. For example, if a lower element or an element positioned below another element is inverted, the element may be referred to as an upper element or as an element positioned above another element. Thus, for example, the term "below" or "underneath" may, in its meaning, encompass the term "above" or "above." An example term such as "below" can encompass all directions, including "below," "above," and diagonal. Likewise, an example term such as "above," "on," or similar can encompass all directions, including "above," "on," "below," and diagonal. When describing a temporal relationship, if the temporal sequence is described as, for example, "after", "following", "subsequent", "next", "before", "preceding", "before", or similar, it may include a case that is not consecutive or sequential, and thus one or more other events may occur in between, unless a more restrictive term such as "just", "immediately", or "directly" is used. It is understood that while the terms "first," "second," and the like may be used here to describe various elements (e.g., layers, films, components, electrodes, structures, transistors, sections, elements, parts, regions, surfaces, parts, steps, processes, and / or the like), these elements should not be restricted by these terms to any particular order, priority, or number. These terms are used only to distinguish one element from another. For example, a first element may denote a second element, and likewise a second element may denote a first element, without deviating from the scope of this disclosure. Furthermore, the first element, the second element, and the like may be named according to the prior art without deviating from the scope of this disclosure.For clarity, the functions or structures of these elements (e.g., the first element, the second element, and so on) are not restricted by ordinal numbers or the names preceding the elements. Furthermore, a first element contains one or more first elements. Similarly, a second element, or so on, contains one or more second elements, or so on. In describing the elements of this revelation, the terms “first,” “second,” “A,” “B,” “(a), “(b),” or the like may be used. These terms serve to distinguish the respective element(s) from the other elements and are not used to define the nature, basis, order, or number of the elements. The expression that an element (e.g., layer, film, component, electrode, structure, transistor, section, element, part, area, surface, or the like) is "engaged" with another element can be understood, for example, to mean that the element may engage with the other element either directly or indirectly. The term "engaged" or similar expressions may refer to terms such as "covered," "surrounded," "in contact," "overlapped," "crossed," "cut," "connected," "coupled," "attached," "attached," "glued," "combined," "connected," "provided," "arranged," "interacted," or the like. The engagement may include one or more intervening elements arranged between or between the element and the other element, unless otherwise specified.Furthermore, the element may interfere at least partially or completely (or entirely) with the other element, unless otherwise specified. In addition, the element may be contained within at least one of two or more elements that are in interaction with each other. Likewise, the other element may be contained within at least one of two or more elements that are in interaction with each other. If the element is in interaction with the other element, at least a part of the element may be in interaction with at least a part of the other element. The phrase "with another element" or similar expressions may be understood, depending on the context, as "another element" or "with, to, in, or on top of another element." Similarly, the phrase "together" may be understood, depending on the context, as "each other" or "with, to, or upon each other." The expression "by" can, for example, be understood as at least partially or completely by. Terms such as "line" or "direction" should not be interpreted solely based on a geometric relationship in which the respective lines or directions are parallel, perpendicular, diagonal, or oblique to one another, but can also be understood as lines or directions with a wider range of directions within the scope in which the components of this revelation can function. For example, the terms "first direction," "second direction," and the like should not be interpreted solely based on a geometric relationship in which the respective directions are parallel, perpendicular, diagonal, or oblique to one another, but can also be understood as directions with a wider range of directions within the scope in which the components of this revelation can function. The term "at least one" should be understood to include any and all combinations of one or more of the listed elements. For example, each of the expressions "at least one of a first element, a second element, or a third element" and "at least one of a first element, a second element, and a third element" can represent (i) a combination of elements consisting of two or more of the first element, the second element, and the third element, or (ii) only one of the first element, the second element, or the third element. Furthermore, "at least one of a plurality of elements" can represent (i) one element of the plurality of elements, (ii) some elements of the plurality of elements, or (iii) all elements of the plurality of elements.Furthermore, “at least some”, “at least some parts”, “at least some parts”, “at least one part”, “at least one or more parts”, “at least one part”, “at least one or more parts”, “at least some elements”, “one or more”, or the like of a plurality of elements can represent (i) one element of the plurality of elements, (ii) a part (or a share) of the plurality of elements, (iii) one or more shares (or parts) of the plurality of elements, (iv) several elements of the plurality of elements, or (v) all elements of the plurality of elements.Furthermore, “at least some”, “at least some parts”, “at least some parts”, “at least one part”, “at least one or more parts”, “at least one part” or “at least one or more parts” or the like of an element can represent (i) a part (or part) of the element, (ii) one or more parts (or parts) of the element, (iii) the element or (iv) all parts of the element. The expression "and / or" of a first element, a second element, or a third element should be understood as any one of the first, second, and third elements, or as any or all combinations of the first, second, and third elements. Similar interpretations apply to the use of "and / or" with two elements or with more than three elements. For example, A, B, and / or C may refer to A only; B only; C only; any one of A, B, and C (e.g., A, B, or C); any combination of A, B, and C (e.g., A and B; A and C; or B and C); or all of A, B, and C. Furthermore, the expression "A / B" may be understood as A and / or B. For example, the expression "A / B" may refer to A only; B only; A or B; or A and B. In one or more aspects, the terms "between" and "under" can simply be used synonymously for the sake of simplicity, unless otherwise specified. For example, an expression "between a plurality of elements" can be understood as "under a plurality of elements." In another example, an expression "under a plurality of elements" can be understood as "between a plurality of elements." In one or more examples, the number of elements can be two. In one or more examples, the number of elements can be more than two. When an element is described as "between" at least two elements, the element can be the only element between the at least two elements, or there can be one or more elements in between. In one or more aspects, the expressions "of each other" and "one from the other" can simply be used synonymously for the sake of simplicity, unless otherwise specified. For example, an expression "different from each other" can be understood as one different from the other. In another example, an expression "different from each other" can be understood as different from each other. In one or more examples, the number of elements contained in the preceding expression can be two. In one or more examples, the number of elements contained in the preceding expression can be more than two. In one or more aspects, the expressions “one or more of under” and “one or more of” can be used synonymously for the sake of simplicity, unless otherwise stated. The term "or" means "inclusive or" and not "exclusive or". That is, unless otherwise stated or clear from the context, the expression "x uses a or b" means any natural inclusive permutation. For example, "a or b" can mean "a", "b", or "a and b". For example, "a, b, or c" can mean "a", "b", "c", "a and b", "b and c", "a and c", or "a, b, and c". The terms “essentially the same” or “almost the same” can indicate a degree of equivalence, taking into account minor differences due to errors in the manufacturing process. Features of different embodiments of the present disclosure may be partially or completely coupled or combined, technically associated with one another, and operated, linked, or jointly controlled in different ways. Embodiments of the present disclosure may be implemented or executed independently of one another or may be implemented or executed together in a codependent or linked relationship. In one or more aspects, the components of each device and each apparatus according to different embodiments of the present disclosure are functionally coupled and configured. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as they are generally understood by a person skilled in the art in the field to which the embodiments belong. It is further understood that terms as defined in common dictionaries should be interpreted in accordance with their meaning in the context of the relevant prior art, for example, and not in an idealized or overly formal sense, unless expressly defined otherwise herein. The terms used here were chosen as general terms from the relevant technical field; however, depending on the development and / or change of technology, conventions, preferences of engineers, etc., other terms may exist. Therefore, the terms used here should not be understood as limiting technical ideas, but rather as examples of terms for describing embodiments. Furthermore, in a specific case, a term may be arbitrarily chosen by the applicant, and in that case, its precise meaning will be described herein. Therefore, the terms used herein should be understood not only based on their designation but also based on their meaning and the content of this description. The following description details various embodiments of the present disclosure with reference to the accompanying drawings. With regard to the reference numerals for elements in each of the drawings, identical or similar elements may be illustrated in other drawings, and identical reference numerals may refer to identical or similar elements unless otherwise specified. Identical or similar elements may be designated by the same reference numerals even if they are illustrated in different drawings. Repeated descriptions of the same or similar elements may be omitted for brevity, and the descriptions for elements in one or more figures may also apply to elements in other figures that use the same or similar reference numerals unless otherwise specified.Furthermore, the scales, dimensions, sizes and thicknesses of the individual elements illustrated in the accompanying drawings may differ from the actual scales, dimensions, sizes and thicknesses, so that the embodiments of the present disclosure are not limited to the scales, dimensions, sizes and thicknesses illustrated in the drawings. Fig. 1 is a diagram illustrating an example of a bending structure and a wiring structure in a planar structure of a display device 110 according to embodiments of the present disclosure. With reference to Fig. 1, a substrate 111 of the display device 110 according to embodiments of the present disclosure can have a display area DA and a non-display area NDA. The display area DA and the non-display area NDA can also be referred to as areas of the display device 110. All wiring and all electrodes can be formed on the substrate 111. In the display device 110 according to embodiments of the present disclosure, the substrate 111 can be a flexible substrate that can be bent. In the present disclosure, "bend" can have the same meaning as "fold" or "flexible". The non-display area (NDA) is an area where no image is displayed and can be an area that excludes the display area (DA). It is possible that no subpixels (SP) are located in the non-display area (NDA). However, at least one dummy subpixel, which is not directly involved in image display, can be located in the non-display area (NDA). The non-display area NDA can have a first non-display area NDA1, a bending area BA and a second non-display area NDA2. The first non-display area NDA1 can be located around the display area DA and can be the area of ​​the first non-display area NDA1, the bending area BA and the second non-display area NDA2 that is closest to the display area DA. The second non-display area NDA2 can have pad areas PA1 and PA2 in which different pads are arranged, and can be the area of ​​the first non-display area NDA1, the bending area BA and the second non-display area NDA2 that is furthest from the display area DA. The bending area BA is an area in which the substrate 111 is bent and can be located between the first non-display area NDA1 and the second non-display area NDA2. Substrate 111 can have a display area DA, in which an image is displayed, and a non-display area NDA, which surrounds the display area DA. A plurality of subpixels SP can be arranged in the display area DA. The non-display area NDA can have a GIP (Gate-In-Panel) area in which a GIP-type gate drive circuit is formed, a bending area BA through which various wires run and in which a data drive circuit is electrically connected, and a second non-display area NDA2. For example, the GIP area can be located on a left and / or right exterior area of ​​the display area DA. The non-display area NDA can be located on a top or bottom exterior area of ​​the display area DA. The second non-display area NDA2 can be an exterior area beyond the bending area BA and may include pad areas PA1 and PA2 to which a circuit board or other circuit configurations are electrically connected. As described above, the substrate (SUB) 111 can have the bending area BA, which is bent and folded, and the bending area BA can be located on a lower surface of an unbent part or the like. The bending area BA can be part of the non-display area NDA and be located between the drive circuit area and the display area DA. To control the subpixels SP, a plurality of control voltage lines DVL for supplying a control voltage VDD to the several subpixels SP and one or more base voltage lines VSSL for applying a base voltage VSS to a common electrode (CE) of the light-emitting device ED in each subpixel SP can also be arranged on the substrate SUB 111. With reference to Fig. 1, for example, the majority of the control voltage lines DVL can be arranged in one column direction, but embodiments of the present disclosure are not limited thereto. To efficiently supply the control voltage VDD via the majority of the control voltage lines DVL, a control voltage structure, which is integrally formed with or electrically connected to the majority of the control voltage lines DVL, can be arranged in the non-display area NDA. The majority of the control voltage lines DVL can be electrically connected to a data control circuit or a circuit board, which is connected via the bending area BA to the pad areas PA1 and PA2 via the control voltage structure. The one or more base voltage lines (VSSL) can be located in the non-display area (NDA) to surround the outer area of ​​the display area (DA) in order to efficiently supply the base voltage (VSS). The one or more base voltage lines (VSSL) can also pass through the bending area (BA) and be electrically connected to the data drive circuitry or the board connected to the drive circuitry area. A crack prevention structure (PCD) can be formed on the substrate SUB 111. The crack prevention structure (PCD) can be formed outside the base voltage line (VSSL) in the non-indicating region (NDA), but the embodiments of the present disclosure are not limited thereto. For example, the crack prevention structure PCD can be formed in a zigzag pattern to prevent cracks in the wiring running through the substrate SUB 111, but embodiments of the present disclosure are not limited thereto. For example, some of the signal lines running through the bending region BA may break (become electrically open) or short-circuit with adjacent signal lines when the bending region BA is bent. In such cases, accurate signals may not be transmitted over the broken (open) or short-circuited signal lines, leading to problems in driving the display and a significant degradation of image quality. Accordingly, the crack-prevention structure PCD may be included to prevent such problems, but embodiments of the present disclosure are not limited to this. In the display device 110 mentioned above, a portion of the flexible substrate SUB 111 is folded backwards by using a flexible substrate SUB 111 and bending the bending area BA, to which the data control circuitry is connected. The folded bending area BA is an area where the image cannot be displayed and is not visible from the front. By using the bending structure and wiring arrangement illustrated in Fig. 1, it is thus possible to significantly reduce the size of the bezel of the display device 110, resulting in a narrow frame design and providing a highly aesthetically pleasing appearance. Fig. 2 illustrates the display device 110 according to embodiments of the present disclosure. With reference to Fig. 2, the display device 110 according to embodiments of the present disclosure can comprise the substrate 111, a plurality of subpixels SP, and the encapsulation layer 200 arranged on the substrate 111. The encapsulation layer 200 can also be referred to as the encapsulation substrate or encapsulation part. In one aspect, the plurality of the subpixels SP can be arranged on the substrate 111. With reference to Fig. 2, if the display device 110 according to embodiments of the present disclosure is a self-illuminating display device, each of the plurality of subpixels SP can have a light-emitting device ED and a subpixel control circuit SPC for controlling the light-emitting device ED. With reference to Fig. 2, the subpixel circuit SPC can comprise a plurality of transistors for controlling the light-emitting device ED and at least one capacitor, but embodiments of the present disclosure are not limited thereto. In the present disclosure, the subpixel circuit SPC can control the light-emitting device ED by supplying a control current to the light-emitting device ED at a predetermined timing. The light-emitting device ED can emit light by being driven by the control current. Most of the transistors contain a control transistor DT for controlling the light-emitting device ED and a sampling transistor ST, which is switched on or off according to a sampling signal SC. The control transistor DT can supply a control current to the light-emitting device ED. The sampling transistor ST can be configured to control the electrical state of a corresponding node in the subpixel circuit SPC or to control the state or operation of the control transistor DT. The at least one capacitor can include a storage capacitor Cst to maintain a specific voltage during a frame. To control the subpixel, a data signal VDATA, which is an image signal, and a sampling signal SC, which is a type of gate signal, can be applied to the subpixel SP. Additionally, a common control signal, comprising a control voltage VDD and a base voltage VSS, can be applied to the subpixel SP to control it. The light-emitting device ED can comprise a pixel electrode PE, an intermediate layer EL, and a common electrode (CE). The intermediate layer EL can be positioned between the pixel electrode PE and the common electrode CE. For example, the pixel electrode PE can be an electrode located in each subpixel SP, and the common electrode (CE) can be an electrode located across a plurality of subpixels SP. In one example, the pixel electrode PE can be an anode and the common electrode (CE) a cathode. In another example, the pixel electrode PE can be a cathode and the common electrode (CE) an anode. For the sake of simplicity, the pixel electrode PE will be described as the anode and the common electrode (CE) as the cathode in the following explanation. If the light-emitting device ED is an organic light-emitting device, the intermediate EL can comprise an emitting layer EML, a first common intermediate COM1 between the pixel electrode PE and the emitting layer EML, and a second common intermediate COM2 between the emitting layer EML and the common electrode CE. The first common intermediate COM1 and the second common intermediate COM2 can be collectively referred to as the common intermediate EL_COM. The emitting layer EML can be arranged for each subpixel SP or jointly across a plurality of subpixels SP. The common intermediate layer EL_COM can be arranged jointly across a plurality of subpixels SP, but the embodiments of the present disclosure are not limited thereto. This means that the emitting layer EML can be arranged for each emission region or jointly over a plurality of emission regions. The common intermediate layer EL_COM can be arranged jointly over a plurality of emission and non-emission regions, but embodiments of the present disclosure are not limited thereto. For example, the first common intermediate layer COM1 can comprise a hole injection layer HIL, an electron blocking layer EBL, and a hole transport layer HTL, but embodiments of the present disclosure are not limited thereto. The second common intermediate layer COM2 can comprise an electron transport layer ETL, a hole blocking layer HBL, and an electron injection layer EIL, but embodiments of the present disclosure are not limited thereto. The hole injection layer (HIL) can inject holes from the pixel electrode (PE) into the hole transport layer (HTL), the hole transport layer (HTL) can transport holes to the emitting layer (EML), the electron injection layer (EIL) can inject electrons from the common electrode (CE) into the electron transport layer (ETL), and the electron transport layer (ETL) can transport electrons to the emitting layer (EML). For example, the common electrode (CE) can be electrically connected to the base voltage line VSSL. A base voltage VSS, which is a type of common voltage, can be applied to the common electrode (CE) via the base voltage line VSSL. The pixel electrode PE can be electrically connected either directly or indirectly (via another transistor) to a first node Na of the drive transistor DT in each subpixel SP. In this disclosure, the base voltage VSS can also be referred to as the first common voltage, the low-voltage supply voltage, or the low-potential voltage, and the base voltage line VSSL can also be referred to as the first common voltage line, the low-voltage supply voltage line, or the low-potential voltage line. Each light-emitting device (ED) can be formed by an overlapping portion of the pixel electrode (PE), the emitting layer (EML) in the intermediate layer (EL), and the common electrode (CE). A predetermined emitting area can be formed by each light-emitting device (ED). For example, the emitting area of ​​each light-emitting device (ED) can comprise an overlapping portion of the pixel electrode (PE), the emitting layer (EML) in the intermediate layer (EL), and the common electrode (CE). The light-emitting device ED can be, for example, an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a quantum dot light-emitting device, a micro-LED, or a mini-LED, but the embodiments of the present disclosure are not limited thereto. If the light-emitting device ED is, for example, an organic light-emitting diode (OLED), the intermediate layer EL of the light-emitting device ED can comprise an intermediate layer containing organic material. The control transistor DT can be used to supply a control current to the light-emitting device ED. The control transistor DT can be connected between the control voltage line VDDL and the light-emitting device ED. The control transistor DT can have a first node Na, a second node Nb, and a third node Nc. The first node Na can be electrically connected to the light-emitting device ED, the second node Nb can receive a data signal VDATA, and the third node Nc can receive a control voltage VDD, which is another type of common voltage, from the control voltage line VDDL. The control transistor DT can be connected between the first node Na and the third node Nc. In the present disclosure, the control voltage VDD can also be referred to as the second common voltage, high-potential supply voltage, or high-potential voltage, and the control voltage line VDDL can also be referred to as the second common voltage line, high-potential supply voltage line, or high-potential voltage line. In the control transistor DT, the second node Nb can be a gate node, the first node Na can be a source or a drain node, and the third node Nc can be a drain or a source node. For the sake of simplicity, it is assumed in the following explanation that in the control transistor DT the second node Nb is a gate node, the first node Na is a source node, and the third node Nc is a drain node, but the embodiments of the present disclosure are not limited thereto. In the example shown in Fig. 2, a sampling transistor ST contained in the subpixel circuit SPC can be a switching transistor for supplying a data signal VDATA, which is an image signal, to the second node Nb, which is the gate node of the driver transistor DT. The sampling transistor ST can be controlled to be switched on or off by a sampling signal SC, which is a type of gate signal, applied via a sampling line SCL, which is a type of gate line GL, and can control the electrical connection between the second node Nb of the driver transistor DT and a data line DL.A drain electrode or source electrode of the sampling transistor ST can be electrically connected to the data line DL, a source electrode or drain electrode of the sampling transistor ST can be electrically connected to the second node Nb of the drive transistor DT, and a gate electrode of the sampling transistor ST can be electrically connected to the scan line SCL. The storage capacitor Cst can be electrically connected between the first node Na and the second node Nb of the control transistor DT. The storage capacitor Cst can have at least one capacitor electrode that is electrically connected to or corresponds to the first node Na of the control transistor DT, and at least one capacitor electrode that is electrically connected to or corresponds to the second node Nb of the control transistor DT. The storage capacitor Cst can be an external capacitor that is intentionally placed outside the drive transistor DT, rather than an internal capacitor (e.g. parasitic capacitances such as Cgs and Cgd) that may be located between the first node Na and the second node Nb of the drive transistor DT, but embodiments of the present disclosure are not limited thereto. The control transistor DT and the sampling transistor ST can each be an n-type or a p-type transistor, but the embodiments of the present disclosure are not limited thereto. For example, one of the control transistor DT and one of the sampling transistors ST can be an n-type or a p-type transistor. The display device 110 can have a top-side emission structure or a bottom-side emission structure. If the display device 110 has a top-side emission structure, at least part of the subpixel circuit SPC can vertically overlap with the light-emitting device ED. Accordingly, the emission area can be increased and the aperture ratio improved. If the display device 110 has a bottom-side emission structure, the subpixel circuit SPC may not be able to vertically overlap with the light-emitting device ED. The SPC subpixel circuit can have a 2T1C structure, comprising two transistors DT and ST and one capacitor Cst, as shown in Fig. 2. In some cases, the SPC subpixel circuit further includes one or more transistors and / or one or more capacitors. In one example, the subpixel circuit SPC can have a 3T1C structure with three transistors and one capacitor. In another example, the subpixel circuit SPC can have an 8T1C structure with eight transistors and one capacitor. In yet another example, the subpixel circuit SPC can have a 6T2C structure with six transistors and two capacitors. In a further example, the subpixel circuit SPC can have a 7T1C structure comprising seven transistors and one capacitor. The embodiments of the present disclosure are not limited thereto. Depending on the structure of the subpixel circuit SPC, the types and number of gate lines for supplying gate signals to the subpixel SP can vary. Likewise, the types and number of common drive signals supplied to the subpixel SP can vary depending on the structure of the subpixel circuit SPC. Since circuit elements (for example, light-emitting devices ED implemented as organic light-emitting diodes (OLEDs) with organic materials) in each subpixel are susceptible to external moisture and oxygen, the encapsulation layer 200 can be arranged in the display device 110. The encapsulation layer 200 can prevent external moisture or oxygen from penetrating the circuit elements (e.g., the light-emitting device ED). The encapsulation layer 200 can be configured in various ways so that the light-emitting devices ED are not exposed to moisture or oxygen. For example, the encapsulation layer 200 can consist of two or more layers stacked alternately with an organic film and an inorganic film, but the embodiments of the present disclosure are not limited thereto. With reference to Fig. 2, the display device 110 according to embodiments of the present disclosure can further comprise a touch sensor layer 210 for providing a touch detection function and a touch detection circuit for detecting a touch sensor formed on the touch sensor layer 210 and for determining the presence of a touch or touch coordinates. Here, the touch sensor layer 210 can also be referred to as the touch element or touch detection element. For example, the touch detection circuit can include a touch control circuit 260 configured to control and sample a touch sensor formed on the touch sensor layer 210 and to generate and output touch data, and a touch control device 270 configured to determine the presence of a touch or touch coordinates based on the touch data provided by the touch control circuit 260. The touch sensor layer 210 is a layer on which a touch sensor is formed, and the touch sensor can be equipped with a plurality of touch electrodes. In one example, the touch sensor layer 210 can be located outside the display device 110 and configured as a separate touch panel, distinct from the display device 110. In this case, the touch panel and the display device 110 can be manufactured separately and combined during the assembly process. In another example, the touch sensor layer 210 can be embedded in the display device 110. When the touch sensor layer 210 is embedded in the display device 110, it can be formed on the substrate 111 during the manufacturing process of the display device 110, along with signal lines and electrodes related to the control system. For example, the touch sensor layer 210 can be arranged on the encapsulation layer 200. For the sake of simplicity, the following example uses the case where the touch sensor layer 210 is embedded in the display device 110. When the touch sensor layer 210 is embedded in the display device 110, the display device 110 can, in addition to the multiple touch electrodes corresponding to the touch sensor, have a plurality of touch pads TP to which the touch control circuit 260 is electrically connected, and a plurality of touch lines TL that electrically connect the multiple touch electrodes and the multiple touch pads TP. Here, the plurality of touch lines TL can also be referred to as a plurality of touch lines. Furthermore, the plurality of touch lines TL can correspond to a plurality of touch channels. The touch control circuit 260 can supply a touch control signal to at least one of the plurality of touch electrodes and sample at least one of the plurality of touch electrodes to generate touch detection data. The touch detection circuit can perform touch detection using a self-capacitance detection method or a mutual-capacitance detection method. If the touch detection circuit performs touch detection using a self-capacitance detection method, it can perform touch detection based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self-capacitance detection method, each of the multiple touch electrodes can act as both a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all or some of the multiple touch electrodes and can also sensing all or some of the multiple touch electrodes. If the touch detection circuit performs touch detection using a mutual capacitance detection method, it can detect touch based on the capacitance between two adjacent touch electrodes. According to the mutual capacitance detection method, the majority of touch electrodes can be divided into driving touch electrodes and detecting touch electrodes. The touch control circuit can drive the driving touch electrodes and sample the detecting touch electrodes. Touch leads connected to the driving touch electrodes can be called driving touch leads, and touch leads connected to the detecting touch electrodes can be called detecting touch leads. The touch control circuit 260 and the touch control device 270 can be implemented as separate devices or as a single device. Furthermore, the touch control circuit 260 and the data control circuit 120 can be implemented as separate devices or as a single device. The display unit 110 may also include a power supply circuit for providing different types of current to the display control circuit and / or the touch detection circuit. The power supply circuit may provide different voltages and currents related to the control of the display control circuit or the display unit 110. Fig. 3 illustrates an example of a cross-sectional structure of the display device 110 according to embodiments of the present disclosure. With reference to Fig. 3, the display device 110 according to embodiments of the present disclosure can comprise the substrate 111, a transistor part, a part with the light-emitting device and an encapsulation part, but embodiments of the present disclosure are not limited thereto. The substrate 111 can have a single-layer or a multi-layer structure. In the case of a multi-layer structure, the substrate 111 can have a first substrate 201, an intermediate substrate layer 202, and a second substrate 203. The intermediate substrate layer 202 can be arranged between the first substrate 201 and the second substrate 203. For example, both the first substrate 201 and the second substrate 203 can be a polyimide (PI) layer, but embodiments of the present disclosure are not limited to this. The intermediate substrate layer 202 can be an inorganic insulating layer, but embodiments of the present disclosure are not limited to this.If a charge accumulates in the first substrate 201, which consists of a polyimide layer, the intermediate substrate layer 202 can prevent the charge from affecting transistors arranged on the second substrate 203, which consists of another polyimide layer. Furthermore, the intermediate substrate layer 202 can prevent moisture from penetrating upwards through the first substrate 201. For example, the intermediate substrate layer 202 can be formed from a single layer or a plurality of layers of silicon nitride (SiNx) or silicon oxide (SiOx), or a bilayer structure of silicon dioxide (SiO2) and silicon nitride (SiNx), but embodiments of the present disclosure are not limited thereto. The transistor section can include insulating layers 211, 212, 213, 214, 215, 216 and 220 on the substrate 111, thin-film transistors TFT1 and TFT2, a storage capacitor Cst and various electrodes or signal lines. The thin-film transistors contained in the transistor section can have a first thin-film transistor TFT1 and a second thin-film transistor TFT2. The first thin-film transistor TFT1 can have a first active layer ACT1, a first electrode E1a, a second electrode E1b and a third electrode E1c. The first electrode E1a can be a gate electrode, the second electrode E1b can be a source electrode or a drain electrode, and the third electrode E1c can be a drain electrode or a source electrode. For the sake of simplicity, the first electrode E1a will henceforth be referred to as the first gate electrode E1a, the second electrode E1b as the first source electrode E1b, and the third electrode E1c as the first drain electrode E1c. However, the embodiments of the present disclosure are not limited to these. The first active layer ACT1 can comprise a first semiconductor material. The first semiconductor material can, for example, be an oxide semiconductor, amorphous silicon, polysilicon, or low-temperature polysilicon (LTPS), but the embodiments of the present disclosure are not limited thereto. The first thin-film transistor TFT1 can be configured as a p-channel transistor or as an n-channel transistor, but the embodiments of the present disclosure are not limited thereto. The second thin-film transistor TFT2 can have a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b and a sixth electrode E2c. The fourth electrode E2a can be a gate electrode, the fifth electrode E2b can be a source electrode or a drain electrode, and the sixth electrode E2c can be a drain electrode or a source electrode. For the sake of simplicity, the fourth electrode E2a will henceforth be referred to as the second gate electrode E2a, the fifth electrode E2b as the second source electrode E2b, and the sixth electrode E2c as the second drain electrode E2c. However, the embodiments of the present disclosure are not limited to these. The second active layer ACT2 can comprise a second semiconductor material. For example, the second semiconductor material can be an oxide semiconductor, amorphous silicon, polysilicon, or low-temperature polysilicon (LTPS), but the embodiments described in this disclosure are not limited thereto. The second thin-film transistor TFT2 can be configured as a p-channel transistor or as an n-channel transistor, but embodiments described in this disclosure are not limited thereto. The types of semiconductor materials for the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2 can be as follows. In one example, the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2 can both be oxide semiconductor materials. In another example, the first active layer ACT1 and the second active layer ACT2 can both be low-temperature polysilicon semiconductor materials. In yet another example, the first active layer ACT1 can be a low-temperature polysilicon semiconductor material and the second active layer ACT2 can be an oxide semiconductor material. In yet another example, the first active layer ACT1 can be an oxide semiconductor material and the second active layer ACT2 can be a low-temperature polysilicon semiconductor material. In Fig. 3, the second thin-film transistor TFT2, which is connected to the pixel electrode PE of the light-emitting device ED, can be the driver transistor DT according to the configuration of the subpixel circuit SPC, or another transistor different from the driver transistor DT. For example, in Fig. 3, the second thin-film transistor TFT2, which is connected to the pixel electrode PE of the light-emitting device ED ( ), can be a light emission control transistor connected between the driver transistor DT and the light-emitting device ED. The second active layer ACT2 of the second thin-film transistor TFT2 can be positioned higher than the first active layer ACT1 of the first thin-film transistor TFT1 on substrate 111. A first buffer layer 211 can be arranged below the first active layer ACT1 of the first thin-film transistor TFT1, and a second buffer layer 214 can be arranged below the second active layer ACT2 of the second thin-film transistor TFT2. For example, the first active layer ACT1 can be arranged on top of the first buffer layer 211, and the second active layer ACT2 can be arranged on top of the second buffer layer 214. The first buffer layer 211 can be positioned higher than the second buffer layer 214. The storage capacitor Cst can be arranged in different metal layers within the display device 110. For example, the storage capacitor Cst can have a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. The portion containing the light-emitting device can comprise a plurality of light-emitting devices ED arranged on the planarization layer 220. Each of the plurality of light-emitting devices ED can comprise a pixel electrode PE and an emitting layer EML. Although not shown in Fig. 3, each of the plurality of light-emitting devices ED can further comprise a common electrode (CE). The encapsulation part can include the encapsulation layer 200, which is arranged over the plurality of light-emitting devices ED. The encapsulation layer 200 can be a single-layer structure or a multi-layer structure, but embodiments of the present disclosure are not limited thereto. The encapsulation part can further include at least one dam (DAM) for preventing overflow of the encapsulation material. In particular, if a second encapsulation layer 242 contained within the encapsulation layer 200 is an organic encapsulation layer made of an organic material, the dam DAM can prevent overflow of the organic material. The structure or vertical structure of the display device 110 according to embodiments of the present disclosure is described in more detail below with reference to Fig. 3. With reference to Fig. 3, a first buffer layer 211 can be arranged on the substrate 111. The first buffer layer 211 can be a single-layer structure or a multi-layer structure, but embodiments of the present disclosure are not limited thereto. In the case of a multi-layer structure, the first buffer layer 211 can have a lower buffer layer 211a and an upper buffer layer 211b. A first active layer ACT1 of the first thin-film transistor TFT1 can be arranged on the first buffer layer 211. The first active layer ACT1 can have a channel region in which a channel is formed, a source terminal region on one side of the channel region, and a drain terminal region on the other side of the channel region. A first gate insulating layer 212 can be arranged on the first active layer ACT1 of the first thin-film transistor TFT1. A first gate electrode E1a of the first thin-film transistor TFT1 can be arranged on the first gate insulating layer 212. A first insulating intermediate layer 213 can be arranged on the first gate electrode E1a of the first thin-film transistor TFT1. Here, the metal layer in which the first gate electrode E1a is arranged can be referred to as the first gate metal layer. A second buffer layer 214 can be arranged on top of the first insulating intermediate layer 213. A second active layer ACT2 of the second thin-film transistor TFT2 can be arranged on the second buffer layer 214. The second active layer ACT2 can have a channel region in which a channel is formed, a source terminal region on one side of the channel region, and a drain terminal region on the other side of the channel region. A second gate insulating layer 215 can be arranged on the second active layer ACT2 of the second thin-film transistor TFT2. A second gate electrode E2a of the second thin-film transistor TFT2 can be arranged on it. A second insulating intermediate layer 216 can be arranged on the second gate electrode E2a of the second thin-film transistor TFT2. Here, the second gate electrode E2a of the second thin-film transistor TFT2 can be referred to as the second gate metal layer. A first source electrode E1b and a first drain electrode E1c of the first thin-film transistor TFT1 as well as a second source electrode E2b and a second drain electrode E2c of the second thin-film transistor TFT2 can be arranged on the second insulating intermediate layer 216. The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1 can be connected to the source region and the drain region of the first active layer ACT1, respectively, via holes formed in the second insulating layer 216, the second gate insulating layer 215, the second buffer layer 214, the first insulating layer 213 and the first gate insulating layer 212. The second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2 can be connected to the source region and the drain region of the second active layer ACT2, respectively, via holes formed in the second insulating intermediate layer 216 and the second gate insulating layer 215. The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1, as well as the second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2, can have a first source-drain metal and be arranged in a first source-drain metal layer. Referring to Fig. 3, in one example the storage capacitor Cst can be formed by a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In some cases, the storage capacitor Cst can be formed by three or more capacitor electrodes and have a structure in which two or more capacitors are connected in parallel. The first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 can each be arranged in different metal layers in the display device 110. For example, the first capacitor electrode CAPE1 can have the same first gate metal as the first gate electrode E1a of the first thin-film transistor TFT1, which is arranged on the first gate insulating layer 212, and can be located within the first gate metal layer, but embodiments of the present disclosure are not limited thereto. For example, the second capacitor electrode CAPE2 can be arranged on the first insulating intermediate layer 213. The second source electrode E2b of the second thin-film transistor TFT2 can be electrically connected to the second capacitor electrode CAPE2 via holes formed in the second insulating intermediate layer 216, the second gate insulating layer 215 and the second buffer layer 214. With reference to Fig. 3, the transistor portion can further comprise a first shielding structure BSM1 arranged on the substrate 111. The first shielding structure BSM1 can overlap the first active layer ACT1 of the first thin-film transistor TFT1. The first shielding structure BSM1 can be arranged beneath the first active layer ACT1 of the first thin-film transistor TFT1. For example, the first shielding structure BSM1 can be arranged between the substrate 111 and the first buffer layer 211 or between the lower buffer layer 211a and the upper buffer layer 211b. The transistor portion can further comprise a second shielding structure BSM2 arranged on the substrate 111. The second shielding structure BSM2 can overlap the second active layer ACT2 of the second thin-film transistor TFT2. The second shielding structure BSM2 can be arranged beneath the second active layer ACT2 of the second thin-film transistor TFT2. For example, the second shielding structure BSM2 can be arranged in a metal layer between the first insulating intermediate layer 313 and the second buffer layer 321. The second shielding structure BSM2 can be arranged in the same metal layer as the second capacitor CAPE2, but embodiments of the present disclosure are not limited to this. Alternatively, the second shielding structure BSM2 can be arranged in the same first gate metal layer as the first gate electrode E1a of the first thin-film transistor TFT1. A planarization layer 220 can be arranged on the first thin-film transistor TFT1 and the second thin-film transistor TFT2 and under the light-emitting device ED. The planarization layer 220 can be an organic insulating layer comprising an organic insulating material. In one example, the planarization layer 220 can be formed as a single layer. In another example, the planarization layer 220 can have three layers. The planarization layer 220 can have a first planarization layer 221, a second planarization layer 222, and a third planarization layer 223. In yet another example, the planarization layer 220 can have three or more layers, but the embodiments of the present disclosure are not limited thereto. Referring to Fig. 3, a connecting electrode RE can be arranged on the first planarization layer 221. The connecting electrode RE can electrically connect the second source electrode E2b of the second thin-film transistor TFT2 to the pixel electrode PE. The connecting electrode RE can be electrically connected to the second source electrode E2b of the second thin-film transistor TFT2 via a hole in the first planarization layer 221. The second source electrode E2b of the second thin-film transistor TFT2 can be electrically connected to the second capacitor electrode CAPE2 of the storage capacitor Cst. The connecting electrode RE can be arranged in the second source-drain metal layer on the first planarization layer 211 and may have a second source-drain metal. A second planarization layer 222 can be arranged on the connecting electrode RE. A third planarization layer 223 can be arranged on top of the second planarization layer 222. The third planarization layer 223 can have an opening. The opening of the third planarization layer 223 can correspond to a light-emitting area. Referring to Fig. 3, the portion containing the light-emitting device can be arranged on the second planarization layer 222 and the third planarization layer 223. The light-emitting device ED can be formed on the second planarization layer 222 and the third planarization layer 223. The light-emitting device ED can comprise a pixel electrode PE and a light-emitting layer EML. Although not shown in Fig. 3, the light-emitting device ED can further comprise an intermediate layer EL, as shown in Fig. 2. A light-emitting region of the light-emitting device ED can be formed in a region where the pixel electrode PE and the light-emitting layer EML overlap and are in contact. The pixel electrode PE can be arranged on the second planarization layer 222 and the third planarization layer 223. The pixel electrode PE can be electrically connected to the connecting electrode RE via the opening of the second planarization layer 222 and the third planarization layer 223. A bank 230 can be arranged on the pixel electrode PE. The bank 230 can have a first bank 231 and a second bank 232. An opening in the bank 230 can expose part of the pixel electrode PE to form a light-emitting area. The opening in the bank 230 can overlap part of the pixel electrode PE. For example, the first bank 231 can be formed from an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, or a photosensitive polymer, but embodiments of the present disclosure are not limited thereto. The second bank 232 can be formed from a material containing a black pigment or the like. If the second bank 232 is formed from a material containing a black pigment or a black dye, it can be a black bank. If the second bank 232 is made from a material containing a black pigment or a black dye, external light or reflected external light can be blocked, thereby improving the luminosity of the display device 110. The light-emitting layer EML of the light-emitting device ED can be arranged on the pixel electrode PE. Referring to Fig. 3, the encapsulation part can be arranged on the part with the light-emitting device and positioned on the bench 230. The encapsulation part can have the encapsulation layer 200 formed on the bench 230. The encapsulation layer 200 can prevent moisture or oxygen from penetrating the light-emitting device ED. For example, the encapsulation layer 200 can prevent moisture or oxygen from penetrating the organic material contained in the intermediate layer EL of the light-emitting device ED. The encapsulation layer 200 can be arranged as a single-layer structure or as a multi-layer structure, but embodiments of the present disclosure are not limited thereto. In one example, the encapsulation layer 200 includes a first encapsulation layer 241, a second encapsulation layer 242, and a third encapsulation layer 243, but embodiments of the present disclosure are not limited thereto. For example, the first encapsulation layer 241 and the third encapsulation layer 243 may comprise inorganic encapsulation layers, and the second encapsulation layer 242 may comprise an organic encapsulation layer, but embodiments of the present disclosure are not limited thereto. The display device 110 according to embodiments of the present disclosure can further comprise an embedded touch sensor. In this case, the display device 110 can comprise the touch sensor layer 210, which is arranged on the encapsulation layer 200 in which the touch sensor is formed. With reference to Fig. 3, the touch sensor layer 210 can have a plurality of touch electrodes TE corresponding to a touch sensor and at least one touch metal layer for forming the plurality of touch electrodes TE. For example, to form the majority of the contact electrodes TE, the contact sensor layer 210 can have a first contact metal layer in which a majority of first contact metals TM1 are arranged, and a second contact metal layer in which a majority of second contact metals TM2 are arranged. In this case, the contact sensor layer 210 can further have a contact insulating intermediate layer arranged between the first contact metal layer and the second contact metal layer. For example, one of the first contact metal layer and the second contact metal layer can be a sensor metal layer, and the other can be a bridge metal layer. In one example, the first contact metal layer can be the bridge metal layer and the second contact metal layer the sensor metal layer. In this case, the majority of second contact metals TM2 arranged in the second contact metal layer can be sensor metals forming the contact sensor, and the majority of first contact metals TM1 arranged in the first contact metal layer can be bridge metals electrically connecting the sensor metals, i.e., the second contact metals TM2. For example, two or more second contact metals TM2 and at least one first contact metal TM1 can form a first contact electrode TE1. In this case, two or more second contact electrodes TE2 can be electrically connected via at least one first contact metal TM1. In another example, the first contact metal layer can be the sensor metal layer and the second contact metal layer the bridge metal layer. In this case, the majority of first contact metals TM1 arranged in the first contact metal layer can be sensor metals forming the touch sensor, and the majority of second contact metals TM2 arranged in the second contact metal layer can be bridge metals electrically connecting the sensor metals, i.e., the first contact metals TM1. In another example, the first contact metal layer and the second contact metal layer can be a sensor metal layer and a bridge metal layer, respectively. For example, the first contact metal layer can contain both sensor metal and bridge metal, and the second contact metal layer can also contain both sensor metal and bridge metal. In this case, a plurality of first contact metals TM1 arranged within the first contact metal layer can contain sensor metals and bridge metals, and a plurality of second contact metals TM2 arranged within the second contact metal layer can also contain sensor metals and bridge metals. With reference to Fig. 3, the touch sensor layer 210 can further comprise a touch buffer layer 251 arranged on the encapsulation layer 200. The touch buffer layer 251 can be arranged between the encapsulation layer 200 and the touch metal layer. For example, the first touch metal layer can be arranged on the touch buffer layer 251, and the touch insulating layer 252 can be arranged on the first touch metal layer. With reference to Fig. 3, the touch sensor layer 210 can further comprise a touch protection layer 253 arranged to cover the touch metal layer. For example, the touch protection layer 253 can be arranged on the second touch metal layer. For example, the contact buffer layer 251 can be an inorganic layer having an inorganic insulating material, or an organic layer having an organic insulating material; the contact insulating intermediate layer 252 can be an inorganic layer having an inorganic insulating material, or an organic layer having an organic insulating material; and the contact protection layer 253 can be an inorganic layer having an inorganic insulating material, or an organic layer having an organic insulating material. For example, at least one of the touch buffer layer 251 and the touch insulating intermediate layer 252 can be extended from the display area DA to the non-display area NDA. The touch protection layer 253 can be extended from the display area DA to the non-display area NDA. The touch lead TL can electrically connect the touch electrodes TE and the touch pads TP. The touch lead TL can be configured with at least one of the first touch metal TM1 and the second touch metal TM2. For example, a touch line TL can have multiple wiring sections, and each of the multiple wiring sections can be a single wiring section or a double wiring section. Here, the single wiring section can be a wiring section with one signal path, and the double wiring section can be a wiring section in which two signal paths are connected in parallel. The touch line TL can be arranged along the inclined surface of the encapsulation layer 200 and extend across the dams DAM1 and DAM2 to the touch pad TP. The touch buffer layer 251 may have an opening that exposes at least part of the touch pad TP. The touch line TL may be electrically connected to the touch pad TP via the opening in the touch buffer layer 251. The touch insulating intermediate layer 252 may be arranged on the touch buffer layer 251 and extend to the area where the touch pad TP is located. The touch protection layer 253 may be arranged only in the display area DA or extend to the non-display area NDA to cover the touch line TL. In some cases, the touch protection layer 253 may extend further over the touch pad TP. Each of the plurality of contact electrodes TE can be a mesh-like electrode with multiple openings. In this case, each of the plurality of contact electrodes TE can be formed with at least one of the second contact metals TM2. However, the embodiments of the present disclosure are not limited thereto. For example, the majority of touch electrodes TE can have a first touch electrode TE1 and a second touch electrode TE2. If the first touch metal layer is a bridge metal layer and the second touch metal layer is a sensor metal layer, two or more second touch metals TM2, forming the first touch electrode TE1 according to the touch sensor, can be electrically connected via at least one first touch metal TM1 acting as a bridge metal. For example, two spaced-apart second touch metals TM2 can be electrically connected by a first touch metal TM1 to form a first touch electrode TE1. Referring to Fig. 3, the majority of first contact metals TM1 and the majority of second contact metals TM2 can be arranged such that they do not overlap the light-emitting device ED. The majority of first contact metals TM1 and the majority of second contact metals TM2 can overlap bank 200. Accordingly, the light emission efficiency of the light-emitting device ED can be improved. Referring to Fig. 3, the touch line TL can connect the touch pad TP, which is located in the pad area PA in the non-display area NDA, and the touch electrode TE, which is located in the display area DA. For this purpose, the touch line TL can be arranged across the non-display area NDA. Fig. 4 illustrates a cross-section of a first subpixel SP1 and a second subpixel SP2 of the display device 110 according to embodiments of the present disclosure. In one or more aspects, a subpixel may sometimes be referred to as a subpixel area and vice versa. For example, a first subpixel may sometimes be referred to as a first subpixel area and vice versa. For example, a second subpixel may sometimes be referred to as a second subpixel area and vice versa. A first planarization layer 221 can be arranged on the substrate 111. In Fig. 4, the first thin-film transistor TFT1 and the second thin-film transistor TFT2 are included in the display device 110; however, for the sake of simplicity, the first thin-film transistor TFT1 and the second thin-film transistor TFT2 can be omitted from the representation between the substrate 111 and the first planarization layer 221. A second planarization layer 222 can be arranged on top of the first planarization layer 221. In the first subpixel region SP1, a first insulating layer 223r1 with a first opening PH1 can be arranged on the second planarization layer 222. A first pixel electrode PErl can be arranged on the second planarization layer 222 at the first opening PH1 and extend along an inner lateral surface of the first opening PH1 of the first insulating layer 223r1 (or extend along an inner lateral surface of the first insulating layer 223r1). In the second subpixel area SP2, a second insulating layer 223r2 with a first groove PG1 can be arranged on the second planarization layer 222. A second pixel electrode PEr2 can be arranged on the second insulating layer 223r2 at the first groove PG1 and extend along an inner lateral surface of the first groove PG1 of the second insulating layer 223r2 (or extend along an inner lateral surface of the second insulating layer 223r2). The width of the first aperture PH1 of the first subpixel SP1 can be equal to the width of the first groove PG1 of the second subpixel SP2. The first groove PG1 can have a depth DT2 that is smaller than the depth DT1 of the first aperture PH1. The depth DT1 of the first aperture PH1 can correspond to a distance between an upper surface of the first insulating layer 223r1 (surrounding the first aperture PH1) and the upper position of a first height H1. The depth DT2 of the first groove PG1 can correspond to a distance between an upper surface of the second insulating layer 223r2 (surrounding the first groove PG1) and the upper position of a second height H2. The upper position of the first height H1 can be or correspond to a lower surface of the first insulating layer 223r1. The upper position of the second height H2 can be or correspond to a lower surface of the second insulating layer 223r2. In a top view, the size of the area occupied by the first groove PG1 can be identical to the size of the area occupied by the first opening PH1. A second bank 232 can be arranged between the common electrode CE and the first pixel electrode PEr1, as well as between the common electrode CE and the second pixel electrode PEr2, and can be located outside the first opening PH1 and the first groove PG1. A first distance D1 (see e.g. Fig. 5) between an end of an inclined surface of the first bank 231 and an end of an inclined surface of the first insulating layer 223r1 in the first subpixel SP1 can be equal to a second distance D2 (see e.g. Fig. 5) between an end of an inclined surface of the first bank 231 and an end of an inclined surface of the second insulating layer 223r2 in the second subpixel SP2. The second hole BH2 can have an area identical to the area of ​​the first hole BH1. The first hole BH1 and the second hole BH2 can have the same width. A first interlayer and a second interlayer can be arranged on the first pixel electrode PEr1 and the second pixel electrode PEr2, respectively, and extend along the inner lateral surfaces of the first bank 231 to the upper surface of the first bank 231. The first interlayer can include a first light-emitting layer EML1, and the second interlayer can include a second light-emitting layer EML2. For example, a first interlayer (see, e.g., EL of SP1) can be arranged on the first pixel electrode PEr1. The first interlayer can be located at the first hole BH1 and extend along an inner lateral surface of the first hole BH1 (or the first bank 231) to the top surface of the first bank 231. The first interlayer can include a first light-emitting layer EML1. For example, a second interlayer (see, e.g., EL of SP2) can be arranged on the second pixel electrode PEr2. The second interlayer can be located at the second hole BH2 and extend along an inner lateral surface of the second hole BH2 (or the first bank 231) to the top surface of the first bank 231. The second interlayer can include a second light-emitting layer EML2. A common electrode (CE) can be placed on the first intermediate layer and the second intermediate layer. The encapsulation layer 200 can be arranged on the common electrode CE. A first color filter CF1, overlapping the first pixel electrode PEr1, can be arranged on the encapsulation layer 200. A second color filter CF2, overlapping the second pixel electrode PEr2, can be arranged on the encapsulation layer 200. The first pixel electrode PEr1 can have a first inclined part extending along an inner lateral surface of the first insulating layer 223r1, and the second pixel electrode PEr2 can have a second inclined part extending along an inner lateral surface of the second insulating layer 223r2. The first color filter CF1 can overlap the first inclined part, and the second color filter CF2 can overlap the second inclined part. Black matrices BM can be positioned at opposite ends of the first color filter CF1 and the second color filter CF2. The black matrices BM can be positioned so that they overlap the first bank 231. A shortest distance between a lower surface of substrate 111 and the first pixel electrode PEr1 can correspond to a first height H1. A shortest distance between a lower surface of substrate 111 and the second pixel electrode PEr2 can correspond to a second height H2. The second height H2 of the second subpixel SP2 can be greater than the first height H1 of the first subpixel SP1. Fig. 5 illustrates a cross-section of the first subpixel SP1 and the second subpixel SP2 of the display device 110 according to embodiments of the present disclosure. Descriptions of contents that are essentially those explained in Fig. 4 may be omitted. Unless otherwise stated, descriptions given for elements in one or more figures (e.g., Fig. 1–Fig. 4) may also apply to elements in other figures (e.g., Fig. 5) that use the same reference numerals. In the area of ​​the first subpixel SP1, the distance between the ends of the inclined surfaces of the second bank 232 is designated as A1. In the area of ​​the second subpixel SP2, a distance between the ends of the inclined surfaces of the second bank 232 is designated as A2. In the area of ​​the first subpixel SP1, the distance between the ends of the inclined surfaces of the first bank 231 is referred to as B1. In the area of ​​the second subpixel SP2, the distance between the ends of the inclined surfaces of the first bank 231 is referred to as B2. In the area of ​​the first subpixel SP1, the distance between the ends of the inclined surfaces of the first insulating layer 223r1 is referred to as C1. In the area of ​​the second subpixel SP2, the distance between the ends of the inclined surfaces of the second insulating layer 223r2 is referred to as C2. In the region of the first subpixel SP1, the distance between one end of an inclined surface of the first insulating layer 223r1 and one end of an inclined surface of the first bank 231 is designated as D1. The distance D1 can correspond to a first separation distance and can correspond to the difference between the distances C1 and B1. In the region of the second subpixel SP2, the distance between one end of an inclined surface of the second insulating layer 223r2 and one end of an inclined surface of the first bank 231 is designated as D2. The distance D2 can correspond to a second separation distance and can correspond to a difference between the distances C2 and B2. Referring to Fig. 5, the respective lengths of A1, B1, C1 and D1 in the first subpixel SP1 can be identical to the respective lengths of A2, B2, C2 and D2 in the second subpixel SP2. In the display device 110, in which arranged subpixels have an identical first height H1 and second height H2, the problem can occur that some of the light is subject to destructive interference and other light is subject to constructive interference, resulting in a ring-shaped Mura phenomenon. To prevent ring-shaped Mura phenomena, the display device 110 according to an embodiment of the present disclosure can have a structure in which externally incident light reflected from an area of ​​the first subpixel SP1 and externally incident light reflected from an area of ​​the second subpixel SP2 undergo destructive interference. For the externally incident light reflected from the region of the first subpixel SP1 and the externally incident light reflected from the region of the second subpixel SP2 to experience destructive interference, the path difference between the two reflected lights can be an odd multiple of λ / 2 (λ / 2 is used as an example below for the sake of simplicity). In one aspect, λ can represent a wavelength of one of the two reflected lights. To ensure that the externally incident light reflected from the region of the first subpixel SP1 and the externally incident light reflected from the region of the second subpixel SP2 have a path difference of λ / 2, twice the difference between a first height H1 and a second height H2 can be equal to λ / 2. In other words, the difference between the first height H1 and the second height H2 can be λ / 4. The difference between the first height H1 and the second height H2 can correspond to the thickness of the second insulating layer 223r2, which has the first groove PG1 in the region of the second subpixel SP2. In this case, a step difference of the third planarization layer 223 between the first subpixel SP1 and the second subpixel SP2 can correspond to the thickness of the second insulating layer 223r2 with the first groove PG1 in the second subpixel SP2. If the thickness of the second insulating layer 223r2 with the first groove PG1 in the region of the second subpixel SP2 (i.e., the difference between the first height H1 and the second height H2) is λ / 4, the incident light reflected from the region of the first subpixel SP1 and the incident light reflected from the region of the second subpixel SP2 can undergo destructive interference, thus preventing the formation of annular mura. As a result, the reflectance visibility of the display device 110 can be improved. The structure of the display device 110 is described in more detail below. Fig. 6 illustrates a top view of the display device 110 according to embodiments of the present disclosure. Referring to Fig. 6, the area of ​​the first subpixel SP1 can have A1, B1, C1, and D1. A1 can correspond to the width of a hole in the second bank 232. B1 can correspond to the width of the first hole BH1 in the first bank 231. C1 can correspond to the width of the first opening PH1 in the first insulating layer 223r1. D1 can correspond to a difference between C1 and B1. D1 can correspond to a second separation distance between one end of an inclined surface in the first insulating layer 223r1 and the other end of an inclined surface in the first bank 231. Referring to Fig. 6, the area of ​​the second subpixel SP2 can comprise A2, B2, C2, and D2. A2 can correspond to the width of a hole in the second bank 232. B2 can correspond to the width of the second hole BH2 in the first bank 231. C2 can correspond to the width of the first groove PG1 in the second insulating layer 223r2. D2 can correspond to a difference between C2 and B2. D2 can correspond to a second separation distance between one end of an inclined surface in the second insulating layer 223r2 and one end of an inclined surface in the first bank 231. The respective widths of A1, B1, C1 and D1 of the first subpixel SP1 can be identical to the respective widths of A2, B2, C2 and D2 of the second subpixel SP2. An area occupied by the first opening PH1 can be identical to an area occupied by the first groove PG1. The first hole BH1 can have an area that is identical to the area of ​​the second hole BH2. The dimensions A1, B1, C1, D1, A2, B2, C2 and D2 shown in Fig. 6 can correspond to or be the same as the dimensions A1, B1, C1, D1, A2, B2, C2 and D2 shown in Fig. 5. Fig. 7 illustrates a cross-section of a first subpixel and a second subpixel of the display device 110 according to embodiments of the present disclosure. For the sake of brevity, a detailed description of elements that are essentially identical to those described with reference to Figures 4 and 5 can be omitted. Unless otherwise stated, the descriptions given for elements in one or more figures (e.g., Figures 1-6) may also apply to elements in other figures (e.g., Figure 7) that use the same reference numerals. Referring to Fig. 7, the respective lengths of A1 and B1 of the first subpixel SP1 can be identical to the respective lengths of A2 and B2 of the second subpixel SP2. C2 and D2 of the second subpixel SP2 can have lengths that are smaller than the lengths of C1 and D1, respectively, of the first subpixel SP1. A second height H2 of the second subpixel SP2 shown in Fig. 7 can be formed such that it has the same height as the second height H2 shown in Fig. 5. A first groove PG1 of the second subpixel SP2 shown in Fig. 7 can have a smaller width than a first aperture PH1 of the first subpixel SP1 shown in Fig. 7. Thus, C2, which corresponds to the width of the first groove PG1 of the second subpixel SP2 shown in Fig. 7, can be smaller than C1, which corresponds to the width of the first aperture PH1 of the first subpixel SP1 shown in Fig. 7. Since a second height H2 is formed in the second subpixel SP2, which is greater than a first height H1, the OLED side mirror effect (OSM effect) can be reduced. Accordingly, the reduced OSM effect can be compensated for by forming a second separation distance D2, which is smaller than a first separation distance D1. In the display device 110, in which subpixels with the same first height H1 and the same second height H2 are arranged, light can experience both destructive and constructive interference, leading to a problem with ring-shaped mura. To prevent ring-shaped mura, the display device 110 according to an embodiment of the present disclosure can have a structure in which externally incident light reflected from areas of the first subpixel SP1 and the second subpixel SP2 experiences destructive interference. For the externally incident light reflected from the area of ​​the first subpixel SP1 and the externally incident light reflected from the area of ​​the second subpixel SP2 to experience destructive interference, a path difference between the two reflected lights can be an odd multiple of λ / 2 (in the following, λ / 2 is used for the sake of simplicity). For the reflected lights to have a path difference of λ / 2, a value obtained by doubling the difference between the first height H1 and the second height H2 can be λ / 2. That is, the difference between the first height H1 and the second height H2 can be λ / 4. The difference between the first height H1 and the second height H2 can correspond to the thickness of the second insulating layer 223r2, which has the first groove PG1 in the region of the second subpixel SP2. Here, the step difference in the third planarization layer 223 between the first subpixel SP1 and the second subpixel SP2 can correspond to the thickness of the second insulating layer 223r2 with the first groove PG1. If the thickness of the second insulating layer 223r2 with the first groove PG1 (i.e., the difference between the first height H1 and the second height H2) is λ / 4, the externally incident light rays reflected from the areas of the first subpixel SP1 and the second subpixel SP2 can be subject to destructive interference, thus preventing annular mura. This can improve the reflectivity of the display device 110. Fig. 8 illustrates a top view of the display device 110 according to embodiments of the present disclosure. A1 can correspond to a hole in the second bank 232. A2 can correspond to a hole in the second bank 232. B1 can correspond to the first hole BH1 of the first bank 231. B2 can correspond to the second hole BH2 of the first bank 231. C1 can correspond to the first opening PH1 of the first insulating layer 223r1. C2 can correspond to the first groove PG1 of the second insulating layer 223r2. D1 can correspond to a difference between B1 and C1. D1 can correspond to a first separation distance between an end of an inclined surface of the first insulating layer 223r1 and an end of an inclined surface of the first bank 231. D2 can correspond to a difference between B2 and C2. D2 can correspond to a second separation distance between one end of an inclined surface of the second insulating layer 223r2 and one end of an inclined surface of the first bank 231. The area occupied by the first groove PG1 does not have to be identical to the area occupied by the first opening PH1. The area occupied by the first groove PG1 can be smaller than the area occupied by the first opening PH1. The width of the first groove PG1 (e.g. C2) can be smaller than the width of the first opening PH1 (e.g. C1). The second hole BH2 can have an area that corresponds to the area of ​​the first hole BH1. The width of the second hole BH2 can be identical to the width of the first hole BH1. Fig. 9 illustrates a pixel arrangement of the display device 110 according to embodiments of the present disclosure. A pixel (or each pixel) can have a red subpixel, a green subpixel, and a blue subpixel. The display device 110 according to embodiments of the present disclosure can further have a first to fourth pixel (or a plurality of first to fourth pixels), and the first subpixel SP1 can be contained in each of the first pixel P1 and the third pixel P3 (or in each of the first pixels P1 and each of the third pixels P3), while the second subpixel SP2 can be contained in each of the second pixel P2 and the fourth pixel P4 (or in each of the second pixels P2 and each of the fourth pixels P4). The distance between the first pixel P1 and the third pixel P3 can differ from the distance between the second pixel P2 and the fourth pixel P4. The first pixel P1 and the third pixel P3 may or may not be adjacent to the second pixel P2 and the fourth pixel P4. Fig. 10 illustrates a cross-section of the first pixel P1 and the second pixel P2 of the display device 110 according to embodiments of the present disclosure. Unless otherwise stated, the descriptions for elements in one or more figures (e.g., Fig. 1-Fig. 6) may also apply to elements in other figures (e.g., Fig. 10) that use the same reference numerals. Referring to Fig. 10, the first pixel P1 can have a first red subpixel SPr1, a first green subpixel SPg1, and a first blue subpixel SPb1. The second pixel P2 can have a second red subpixel SPr2, a second green subpixel SPg2, and a second blue subpixel SPb2. In the following, the first red subpixel SPr1 of the first pixel P1 can be referred to as the first subpixel SP1, and the second red subpixel SPr2, the second green subpixel SPg2 and the second blue subpixel SPb2 of the second pixel P2 can be referred to as the second subpixel SP2, the third subpixel SP3 and the fourth subpixel SP4 respectively. The display device 110 according to embodiments of the present disclosure can comprise the substrate 111. A first planarization layer 221 can be arranged on the substrate 111. A second planarization layer 222 can be arranged on the first planarization layer 221. A first insulating layer 223r1 can be arranged on the second planarization layer 222, which is located in a region of the first subpixel SP1, and can have a first opening PH1. A second insulating layer 223r2 can be arranged on the second planarization layer 222, which is located in a region of the second subpixel SP2, and can have a first groove PG1. The width of the first aperture PH1 of the first subpixel SP1 can be identical to the width of the first groove PG1 of the second subpixel SP2. A distance D1 between an end of an inclined surface of the first insulating layer 223r1 and an end of an inclined surface of the first bank 231 can be identical to a distance D2 between an end of an inclined surface of the second insulating layer 223r2 and an end of an inclined surface of the first bank 231. The first groove PG1 can have a depth that is less than the depth of the first opening PH1. A first pixel electrode PErl can be arranged in the region of the first subpixel SP1, which is located on the second planarization layer 222 at the first opening PH1, and can extend along an inner lateral surface of the first insulating layer 223r1. A second pixel electrode PEr2 can be arranged in the region of the second subpixel SP2, which is located on a lower surface of the first groove PG1, and can extend along an inner lateral surface of the first groove PG1. A second bank 232 can be arranged on the first pixel electrode PErl and the second pixel electrode PEr2 and be located outside the first opening PH1 and the first groove PG1. A first bank 231 can be arranged on the first pixel electrode PEr1 and the second pixel electrode PEr2 and have a first hole BH1 that overlaps the first opening PH1 and is smaller than the first opening PH1, and a second hole BH2 that overlaps the first groove PG1 and is smaller than the first groove PG1. The second hole BH2 can have an area identical to the area of ​​the first hole BH1. A first light-emitting layer EMLr1 can be arranged on the first pixel electrode PErl. A second light-emitting layer EMLr2 can be arranged on the second pixel electrode PEr2. Although not illustrated in Fig. 10, a common electrode (CE) can be arranged on the first light-emitting layer EMLr1 and the second light-emitting layer EMLr2 and extend along the inner lateral surfaces of the first hole BH1 and the second hole BH2 of the first bank 231 to a top surface of the first bank 231 (or extend along the inner lateral surfaces of the first bank 231 to a top surface of the first bank 231). The display device 110 according to embodiments of the present disclosure can further comprise the encapsulation layer 200 arranged on the first bank 231 and the common electrode CE, the first color filter CF1 arranged on the encapsulation layer 200 and overlapping the first pixel electrode PErl, and a second color filter CF2 arranged on the encapsulation layer 200 and overlapping the second pixel electrode PEr2. The first pixel electrode PEr1 can have a first inclined part extending along an inner lateral surface of the first insulating layer 223r1, and the second pixel electrode PEr2 can have a second inclined part extending along an inner lateral surface of the second insulating layer 223r2. The first color filter CF1 can overlap the first inclined part, and the second color filter CF2 can overlap the second inclined part. A first separation distance D1 between an end of an inclined surface of the first bank 231 and an end of an inclined surface of the first insulating layer 223r1 in the first subpixel SP1 can be identical to a second distance D2 between an end of an inclined surface of the first bank 231 and an end of an inclined surface of the second insulating layer 223r2 in the second subpixel SP2. The first subpixel SP1 and the second subpixel SP2 can emit light of the same color, and the first color filter CF1 can have a thickness identical to that of the second color filter CF2. In a region of a third subpixel SP3 of the display device 110 according to embodiments of the present disclosure, a third insulating layer 223g2 with a second groove PG2 can be arranged on the second planarization layer 222. A third pixel electrode PEg2 can be arranged in the region of the third subpixel SP3, located on the third insulating layer 223g2 at the second groove PG2 (or on a lower surface of the second groove PG2) and extending along an inner lateral surface of the third insulating layer 223g2. The second bank 232 can be located on the third pixel electrode PEg2 and outside the second groove PG2. The first bank 231 can be arranged on the third pixel electrode PEg2 and have a third hole BH3 that overlaps the second groove PG2, with the third hole BH3 being smaller than the second groove PG2. A third light-emitting layer EMLg2 can be arranged on the third pixel electrode PEg2. Although not illustrated in Fig. 10, the common electrode (CE) can be located on the third light-emitting layer EMLg2 and extend along an inner lateral surface of the third hole BH3 of the first bank 231 to a top surface of the first bank 231 (or extend along an inner lateral surface of the first bank 231 to a top surface of the first bank 231). The display device 110 according to embodiments of the present disclosure can further comprise the encapsulation layer 200 arranged on the first bank 231 and the common electrode CE and a third color filter CF3 which is arranged on the encapsulation layer 200 and overlaps the third pixel electrode PEg2. The third pixel electrode PEg2 can have a third inclined part extending along an inner lateral surface of the third insulating layer 223g2. The third color filter CF3 can overlap the third inclined part. The distance between the lower surface of the first groove PG1 and the back of the second insulating layer 223r2 can have a first thickness T1, and the distance between the lower surface of the second groove PG2 and the back of the third insulating layer 223g2 can have a second thickness T2, which differs from the first thickness T1. The back of the second insulating layer 223r2 and the back of the third insulating layer 223g2 can face the first planarization layer 221 and / or the substrate 111. The thickness (e.g., T1, T2, and T3) can vary according to the wavelength of the light emitted by each subpixel. Thickness and wavelength can be proportional to each other. Thickness can increase with increasing wavelength. The wavelength of red light can be longer than that of green and blue light, and vice versa. The second subpixel SP2 can emit red light, the third subpixel SP3 can emit green light, and the first thickness T1 can be greater than the second thickness T2. The display device 110 according to embodiments of the present disclosure can have a fourth insulating layer 223b2 arranged on the second planarization layer 222 in a region of a fourth subpixel SP4. The fourth insulating layer 223b2 can have a third groove PG3. A fourth pixel electrode PEb2 can be arranged in the region of the fourth subpixel SP4, located on the fourth insulating layer 223b2 at the third groove PG3 and extending along an inner lateral surface of the fourth insulating layer 223b2. The first bank 231 can be arranged on the fourth pixel electrode PEb2 and have a fourth hole BH4 that overlaps the third groove PG3, with the fourth hole BH4 being smaller than the third groove PG3. A fourth light-emitting layer EMLb2 can be arranged on the fourth pixel electrode PEb2. Although not illustrated in Fig. 10, the common electrode (CE) can be located on the fourth light-emitting layer EMLb2 and extend along an inner lateral surface of the fourth hole BH4 of the first bank 231 to a top surface of the first bank 231 (or extend along an inner lateral surface of the first bank 231 to a top surface of the first bank 231). The display device 110 according to embodiments of the present disclosure may further comprise the encapsulation layer 200 arranged on the first bank 231 and the common electrode CE and a fourth color filter CF4 which is arranged on the encapsulation layer 200 and overlaps the fourth pixel electrode PEb2. The fourth pixel electrode PEb2 can have a fourth inclined part extending along an inner lateral surface of the fourth insulating layer 223b2. The fourth color filter CF4 can overlap the fourth inclined part. A gap between a lower surface of the second groove PG2 and a back side of the third insulating layer 223g2 can have a second thickness T2, and a gap between a lower surface of the third groove PG3 and a back side of the fourth insulating layer 223b2 can have a third thickness T3, which is different from the second thickness T2. The third subpixel SP3 can emit green light, the fourth subpixel SP4 can emit blue light, and the second thickness T2 can be greater than the third thickness T3. Fig. 11 illustrates a cross-section of the first pixel P1 and the second pixel P2 of the display device 110 according to embodiments of the present disclosure. Unless otherwise stated, the descriptions for elements in one or more figures (e.g., Fig. 1 to Fig. 10) may also apply to elements in other figures (e.g., Fig. 11) that use the same reference numerals. Referring to Fig. 11, the first pixel P1 can have a first red subpixel SPr1, a first green subpixel SPg1, and a first blue subpixel SPb1. The second pixel P2 can have a second red subpixel SPr2, a second green subpixel SPg2, and a second blue subpixel SPb2. In the following, the first red subpixel SPr1 of the first pixel P1 can be referred to as the first subpixel SP1, and the second red subpixel SPr2, the second green subpixel SPg2 and the second blue subpixel SPb2 of the second pixel P2 can be referred to as the second subpixel SP2, the third subpixel SP3 and the fourth subpixel SP4 respectively. The display device 110 according to embodiments of the present disclosure can comprise the substrate 111. A first planarization layer 221 can be arranged on the substrate 111. A second planarization layer 222 can be arranged on the first planarization layer 221. A first insulating layer 223r1 can be arranged on the second planarization layer 222 and be located in a region of the first subpixel SP1 and have a first opening PH1. A second insulating layer 223r2 can be arranged on the second planarization layer 222 and be located in a region of the second subpixel SP2 and have a first groove PG1. The width of the first groove PG1 of the second subpixel SP2 can be smaller than the width of the first aperture PH1 of the first subpixel SP1. The first groove PG1 can have a depth that is smaller than that of the first opening PH1. The first pixel electrode PEr1 can be arranged on the second planarization layer 222 in the first opening PH1, which is located in a region of the first subpixel SP1, and can extend along an inner lateral surface of the first insulating layer 223r1. The second pixel electrode PEr2 can be arranged on a lower surface of the first groove PG1, which is located in a region of the second subpixel SP2, and can extend along an inner lateral surface of the first groove PG1. The second bank 232 can be arranged on the first pixel electrode PEr1 and the second pixel electrode PEr2 and be located outside the first opening PH1 and the first groove PG1. The first bank 231 can be arranged on the first pixel electrode PEr1 and the second pixel electrode PEr2. The first bank 231 can have a first hole BH1 that overlaps the first opening PH1 and is smaller than it, as well as a second hole BH2 that overlaps the first groove PG1 and is smaller than it. In the first subpixel SP1, a first separation distance D1 between an end of an inclined surface of the first bank 231 and an end of an inclined surface of the first insulating layer 223r1 can be larger than a second separation distance D2 between an end of an inclined surface of the first bank 231 and an end of an inclined surface of the second insulating layer 223r2 in the second subpixel SP2. The second hole BH2 can have an area identical to the area of ​​the first hole BH1. A first light-emitting layer EMLr1 can be arranged on the first pixel electrode PEr1. A second light-emitting layer can be arranged on the second pixel electrode PEr2. Although not illustrated in Fig. 11, the common electrode (CE) can be arranged on the first light-emitting layer EMLr1 and the second light-emitting layer EMLr2 and extend along the inner lateral surfaces of the first hole BH1 and the second hole BH2 of the first bank 231 to a top surface of the first bank 231 (or extend along the inner lateral surfaces of the first bank 231 to a top surface of the first bank 231). The display device 110 according to embodiments of the present disclosure can further comprise the encapsulation layer 200 arranged on the first bank 231 and the common electrode CE, the first color filter CF1 arranged on the encapsulation layer 200 and overlapping the first pixel electrode PEr1, and a second color filter CF2 arranged on the encapsulation layer 200 and overlapping the second pixel electrode PEr2. The first pixel electrode PEr1 can have a first inclined part extending along an inner lateral surface of the first insulating layer 223r1, and the second pixel electrode PEr2 can have a second inclined part extending along an inner lateral surface of the second insulating layer 223r2. The first color filter CF1 can overlap the first inclined part, and the second color filter CF2 can overlap the second inclined part. The first subpixel SP1 and the second subpixel SP2 can emit light of the same color, and the second color filter CF2 can have the same thickness as the first color filter CF1. In the region of the third subpixel P3, the display device 110, according to embodiments of the present disclosure, can have a third insulating layer 223g2. The third insulating layer 223g2 can have a second groove PG2 and be arranged on the second planarization layer 222. A third pixel electrode PEg2 can be arranged in the region of the third subpixel SP3 and on the third insulating layer 223g2 in the second groove PG2 (or on a lower surface of the second groove PG2) and extend along an inner lateral surface of the third insulating layer 223g2. The second bank 232 can be located on the third pixel electrode PEg2 and outside the second groove PG2. The first bank 231 can be arranged on the third pixel electrode PEg2 and have a third hole BH3 that overlaps the second groove PG2 and is smaller than the second groove PG2. A third light-emitting layer EMLg2 can be arranged on the third pixel electrode PEg2. Although not illustrated in Fig. 11, the common electrode (CE) can be located on the third light-emitting layer EMLg2 and extend along an inner lateral surface of the third hole BH3 of the first bank 231 to a top surface of the first bank 231 (or extend along an inner lateral surface of the first bank 231 to a top surface of the first bank 231). A gap between a lower surface of the first groove PG1 and a back side of the second insulating layer 223r2 can have a first thickness T1, and a gap between a lower surface of the second groove PG2 and a back side of the third insulating layer 223g2 can have a second thickness T2, which is different from the first thickness T1. The second subpixel SP2 can emit red light, the third subpixel SP3 can emit green light, and the first thickness T1 can be greater than the second thickness T2. In the region of the fourth subpixel SP4, the display device 110, according to embodiments of the present disclosure, can have a fourth insulating layer 223b2 arranged on the second planarization layer 222. A fourth pixel electrode PEb2 can be arranged in the region of the fourth subpixel SP4 and on the fourth insulating layer 223b2 at the third groove PG3, which extends along an inner lateral surface of the fourth insulating layer 223b2. The first bank 231 can be arranged on the fourth pixel electrode PEb2 and have a fourth hole BH4 that overlaps the third groove PG3 and is smaller than the third groove PG3. A fourth light-emitting layer EMLb2 can be arranged on the fourth pixel electrode PEb2. Although not illustrated in Fig. 11, the common electrode (CE) can be located on the fourth light-emitting layer EMLb2 and extend along an inner lateral surface of the fourth hole BH4 of the first bank 231 to a top surface of the first bank 231 (or extend along an inner lateral surface of the first bank 231 to a top surface of the first bank 231). A gap between a lower surface of the first groove PG1 and a back side of the second insulating layer 223r2 can have a first thickness T1, and a gap between a lower surface of the second groove PG2 and a back side of the third insulating layer 223g2 can have a second thickness T2, which is different from the first thickness T1. The second subpixel SP2 can emit red light, the third subpixel SP3 can emit green light, and the first thickness T1 can be greater than the second thickness T2. A gap between a lower surface of the third groove PG3 and a back side of the fourth insulating layer 223b2 can have a third thickness T3 that is different from the second thickness T2. The third subpixel SP3 can emit green light, the fourth subpixel SP4 can emit blue light, and the second thickness T2 can be greater than the third thickness T3. Fig. 12 illustrates a cross-section of the first pixel P1 and the second pixel P2 of the display device 110 according to embodiments of the present disclosure. For content that is essentially identical to that described with reference to Fig. 10, a detailed description may be omitted. Descriptions for elements in one or more figures (e.g., Fig. 10) may also apply to elements in other figures (e.g., Fig. 12) that use the same reference symbols, unless otherwise indicated. The first subpixel SP1 and the second subpixel SP2 can emit light of different colors, and the first color filter CF1 can have a different thickness than the second color filter CF2. Fig. 13 illustrates a cross-section of the first pixel P1 and the second pixel P2 of the display device 110 according to embodiments of the present disclosure. For content that is essentially identical to that described with reference to Fig. 11, a detailed description may be omitted. Descriptions for elements in one or more figures (e.g., Fig. 11) may also apply to elements in other figures (e.g., Fig. 13) that use the same reference symbols, unless otherwise indicated. The first subpixel SP1 and the second subpixel SP2 can emit light of different colors, and the first color filter CF1 can have a different thickness than the second color filter CF2. Fig. 14 illustrates a cross-section of the first subpixel SP1 and the second subpixel SP2 of the display device 110 according to embodiments of the present disclosure. The descriptions for elements in one or more figures (e.g., Fig. 1-Fig. 13) may apply to elements in other figures (e.g., Fig. 14) that use the same or similar reference numerals, unless otherwise specified. With reference to Fig. 14, the display device 110 can have a first subpixel SP1 corresponding to a first color and a second subpixel SP2 corresponding to a second color. The first subpixel SP1, corresponding to the first color, can mean that light of the first color is emitted from the light-emitting region located in the first subpixel SP1. The light-emitting region can include an area in which a light-emitting layer is arranged and can further include an area in which an inclined portion of the first pixel electrode PEr1 is located. Similarly, the second subpixel SP2, corresponding to the second color, can mean that light of the second color is emitted from a light-emitting region located in the second subpixel SP2. The first color and the second color can be the same color.In such an example, the first subpixel SP1 can be a subpixel that forms the first pixel P1, and the second subpixel SP2 can be a subpixel that forms the second pixel P2. In Fig. 14, the first aperture PH1 can have a first partial aperture PH1a, located in one region of the first subpixel SP1, and a second partial aperture PH1b, located in another region of the first subpixel SP1. The first partial aperture PH1a and the second partial aperture PH1b of the first subpixel SP1 can correspond to principal light emission regions of the first subpixel SP1. Thus, the first subpixel SP1 has two principal light emission regions. Since, in this example, the first subpixel SP1 corresponds to the first color, both principal light emission regions can emit light of the first color. By including two principal light emission regions in the first subpixel SP1, it is possible to reduce the color coordinate deviation in the direction of the complementary color of the first color in the lateral viewing angle direction. The first subpixel SP1 can have two apertures. In this case, the first partial aperture PH1a and the second partial aperture PH1b can have essentially the same shape and area when viewed in the same plane of the display area. Here, "essentially the same" can encompass minor differences within manufacturing tolerances. The first insulating layer 223r1 can furthermore be arranged between the first partial opening PH1a and the second partial opening PH1b. The first pixel electrode PEr1 can be arranged on the second planarization layer 222 in or on the regions of the first partial opening PH1a and the second partial opening PH1b, extend beyond the outer boundaries of the first partial opening PH1a and the second partial opening PH1b, and be arranged along the inner lateral surfaces of the first insulating layer 223r1. The first pixel electrode PEr1 can be located on the second planarization layer 222 within the first partial opening PH1a and the second partial opening PH1b, extend beyond the outer boundaries of the first partial opening PH1a and the second partial opening PH1b, and be located along the inner lateral surfaces of the first insulating layer 223r1. The first hole BH1 can have a first sub-hole BH1a located in one area of ​​the first subpixel SP1, and a second sub-hole BH1b located in another area of ​​the first subpixel SP1. The first bank 231 and the second bank 232 can furthermore be arranged between the first partial hole BH1a and the second partial hole BH1b. The first light-emitting layer EMLr1 can have a first light-emitting sublayer EML1a arranged in or on the first partial hole BH1a, and a second light-emitting sublayer EML1b arranged in or on the second partial hole BH1b. The first groove PG1 in Fig. 14 can have a first sub-groove PG1a, located in one region of the second subpixel SP2, and a second sub-groove PG1b, located in another region of the second subpixel SP2. The first sub-groove PG1a and the second sub-groove PG1b of the second subpixel SP2 can each correspond to a principal light emission region in the second subpixel SP2. Thus, the second subpixel SP2 has two principal light emission regions. Since, in this example, the second subpixel SP2 corresponds to the second color, both principal light emission regions can emit light of the second color. By including two principal light emission regions in the second subpixel SP2, it is possible to reduce the color coordinate deviation in the direction of the complementary color of the second color in the lateral viewing angle direction. The second subpixel SP2 can have two grooves. In this case, the first subgroove PG1a and the second subgroove PG1b can have essentially the same shape and area when viewed in a plane of the display area. Here, "essentially the same shape" can encompass minor differences within manufacturing tolerances. The second insulating layer 223r2 can furthermore be arranged between the first lower groove PG1a and the second lower groove PG1b. The second insulating layer 223r2 can have an upper surface that is higher than the lower surfaces of the first lower groove PG1a and the second lower groove PG1b. The second pixel electrode PEr2 can be arranged on the lower surfaces of the first sub-groove PG1a and the second sub-groove PG2b, extend beyond the outer boundaries of the first sub-groove PG1a and the second sub-groove PG2b and be arranged along the inner lateral surfaces of the second insulating layer 223r2. The second hole BH2 can have a third sub-hole BH2a located in one area of ​​the second subpixel SP2, and a fourth sub-hole BH2b located in another area of ​​the second subpixel SP2. The first bank 231 and the second bank 232 can furthermore be arranged between the third partial hole BH2a and the fourth partial hole BH2b. The second light-emitting layer EMLr2 can include a third light-emitting sublayer EML2a, which is located in or on the third subhole BH2a, and a fourth light-emitting sublayer EML2b, which is located in or on the fourth subhole BH2b. The distance between the first pixel electrode PErl, which is arranged in or on the first partial opening PH1a, and the substrate 111 (e.g., a lower surface of the substrate 111) can correspond to a first partial height H1a; the distance between the first pixel electrode PEr1, which is arranged in or on the second partial opening PH1b, and the substrate 111 (e.g., the lower surface of the substrate 111) can correspond to a second partial height H1b; the distance between the second pixel electrode PEr2, which is arranged in or on the first lower groove PG1a, and the substrate 111 (e.g., the lower surface of the substrate 111) can correspond to a third partial height H2a; and the distance between the second pixel electrode PEr2, which is arranged in or on the second lower groove PG1b, and the substrate 111 (e.g., the lower surface of the substrate 111) can correspond to a fourth partial height H2b.The first partial height H1a and the second partial height H1b can be identical, and the third partial height H2a and the fourth partial height H2b can be identical. In one example, the first partial height H1a and the second partial height H1b can be the same, and the third partial height H2a and the fourth partial height H2b can be the same. At least one of the third partial height H2a and the fourth partial height H2b can be greater than each of the first partial height H1a and the second partial height H1b, and the first partial height H1a and the second partial height H1b can be equal to each other. Each of the third partial height H2a and the fourth partial height H2b can be greater than each (or one of the respective) of the first partial height H1a and the second partial height H1b, and the third partial height H2a and the fourth partial height H2b can be equal to each other. Fig. 15 illustrates a top view of the first subpixel SP1 and the second subpixel SP2 of the display device 110 according to embodiments of the present disclosure. Unless otherwise stated, the descriptions for elements in one or more figures (e.g., Fig. 1-Fig. 14) may also apply to elements in other figures (e.g., Fig. 15) that use the same or similar reference numerals. The areas of the first partial opening PH1a and the second partial opening PH1b can be the same. The surfaces of the first lower groove PG1a and the second lower groove PG1b can be the same. The area of ​​the first lower groove PG1a can be smaller than the area of ​​the first partial opening PH1a. The area of ​​the second lower groove PG1b can be smaller than the area of ​​the first partial opening PH1b. The width B1a of the first partial hole BH1a can be the same as the width B1b of the second partial hole BH1b. The width B2a of the second partial hole BH2a can be the same as the width B2b of the fourth partial hole BH2b. The width C1a of the first partial opening PH1a can be the same as the width C1b of the second partial opening PH1b. The width C2a of the first lower groove PG1a can be the same as the width C2b of the second lower groove PG1b. The width C2a of the first lower groove PG1a can be smaller than the width C1a of the first partial opening PH1a. The width C2b of the second lower groove PG1b can be smaller than the width C1b of the second partial opening PH1b. Each of the distances D2a and D2b between the end of the inclined surface of the first bank 231 and the end of the inclined surface of the second insulating layer 223r2 can be smaller than each of the distances D1a and D1b between the end of the inclined surface of the first bank 231 and the end of the inclined surface of the first insulating layer 223r1. Fig. 16 illustrates a cross-section of the first subpixel SP1 and the second subpixel SP2 of the display device 110 according to embodiments of the present disclosure. For content that is essentially identical to that described with reference to Fig. 14, a detailed description may be omitted. Descriptions for elements in one or more figures (e.g., Fig. 1–Fig. 15) may also apply to elements in other figures (e.g., Fig. 16) that use the same or similar reference symbols, unless otherwise indicated. The first aperture PH1 can have a first partial aperture PH1a, which is located in one area of ​​the first subpixel SP1, and a second partial aperture PH1b, which is located in another area of ​​the first subpixel SP1. The first groove PG1 can have a first sub-groove PG1a, which is located in one area of ​​the second subpixel SP2, and a second sub-groove PG1b, which is located in another area of ​​the second subpixel SP2. The first hole BH1 can have a first sub-hole BH1a located in one area of ​​the first subpixel SP1, and a second sub-hole BH1b located in another area of ​​the first subpixel SP1. The first light-emitting layer EMLr1 can have a first light-emitting sublayer EML1a located in or on the first subhole BH1a, and a second light-emitting sublayer EML1b located in or on the second subhole BH1b, and the second hole BH2 can have a third subhole BH2a located in one region of the second subpixel SP2, and a fourth subhole BH2b located in another region of the second subpixel SP2. The second light-emitting layer EMLr2 can include a third light-emitting sublayer EML2a, which is located in or on the third subhole BH2a, and a fourth light-emitting sublayer EML2b, which is located in or on the fourth subhole BH2b. The distance between the first pixel electrode PEr1, located in or on the first partial opening PH1a, and the substrate 111 can correspond to a first partial height H1a; the distance between the first pixel electrode PEr1, located in or on the second partial opening PH1b, and the substrate 111 can correspond to a second partial height H1b; the distance between the second pixel electrode PEr2, located in or on the first lower groove PG1a, and the substrate 111 can correspond to a third partial height H2a; and the distance between the second pixel electrode PEr2, located in or on the second lower groove PG1b, and the substrate 111 can correspond to a fourth partial height H2b. The first partial height H1a and the second partial height H1b can correspond to each other, and the third partial height H2a and the fourth partial height H2b need not correspond to each other.In one example, the first partial height H1a and the second partial height H1b can be the same, and the third partial height H2a and the fourth partial height H2b can be different from each other. At least one of the third partial height H2a and the fourth partial height H2b can be greater than each of the first partial height H1a and the second partial height H1b, and the first partial height H1a and the second partial height H1b can be equal to each other. The third partial height H2a and the fourth partial height H2b may each be larger than the first partial height H1a and the second partial height H1b (or either of them), and the third partial height H2a and the fourth partial height H2b may not be equal to each other. The third partial height H2a and the fourth partial height H2b can each be larger than the first partial height H1a and the second partial height H1b (or either of them), and the third partial height H2a and the fourth partial height H2b can be different. Fig. 17 illustrates a top view of the first subpixel SP1 and the second subpixel SP2 of the display device 110 according to embodiments of the present disclosure. Unless otherwise stated, the descriptions for elements in one or more figures (e.g., Fig. 1-Fig. 16) may also apply to elements in other figures (e.g., Fig. 17) that use the same or similar reference numerals. The areas of the first partial opening PH1a and the second partial opening PH1b can be the same. The surfaces of the first lower groove PG1a and the second lower groove PG1b do not necessarily have to be the same. The area of ​​the first lower groove PG1a can be smaller than the area of ​​the first partial opening PH1a. The area of ​​the second lower groove PG1b can be smaller than the area of ​​the second partial opening PH1b. The area of ​​the first lower groove PG1a can be smaller than the area of ​​the second lower groove PG1b. The width B3 of the first partial hole BH1a can be equal to the width B3 of the second partial hole BH1b. The width B4 of the third partial hole BH2a can be equal to the width B4 of the fourth partial hole BH2b. The widths of the first partial hole BH1a, the second partial hole BH1b, the third partial hole BH2a, and the fourth partial hole BH2b can all be the same. B3 and B4 can be the same. The width C3 of the first partial opening PH1a can be the same as the width C3 of the second partial opening PH1b. The width C4 of the first lower groove PG1a may not be the same as the width C5 of the second lower groove PG1b. The width C4 of the first lower groove PG1a can be smaller than the width C3 of the first partial opening PH1a. The width C4 of the first lower groove PG1a can be smaller than the width C3 of the second partial opening PH1b. Each of the distances D4 and D5 between the end of the inclined surface of the first bank 231 and the end of the inclined surface of the second insulating layer 223r2 can be smaller than the distance D3 between the end of the inclined surface of the first bank 231 and the end of the inclined surface of the first insulating layer 223r1. The following are various examples and aspects of the present revelation. These serve as examples and do not limit the scope of the present revelation. A display device according to embodiments of the present disclosure may comprise: a substrate; a first planarization layer arranged on the substrate; a second planarization layer arranged on the first planarization layer; a first insulating layer arranged on the second planarization layer, positioned in a region of a first subpixel and having a first opening; a second insulating layer arranged on the second planarization layer, positioned in a region of a second subpixel and having a first groove; a first pixel electrode positioned in the region of the first subpixel, arranged on the second planarization layer within the first opening and extending along an inner wall of the first insulating layer;a second pixel electrode positioned in the region of the second subpixel, located on the lower surface of the first groove and extending along an inner wall of the first groove; a first bank located on the first and second pixel electrodes, comprising a first hole overlapping the first opening but smaller than the first opening, and a second hole overlapping the first groove but smaller than the first groove; a first light-emitting layer located on the first pixel electrode; a second light-emitting layer located on the second pixel electrode; and a common electrode located on the first and second light-emitting layers and extending along the inner walls of the first and second holes to the upper surface of the first bank. In the display device according to embodiments of the present disclosure, the second hole can have the same area as the first hole. The width of the first opening of the first subpixel can be the same as the width of the first groove of the second subpixel, and a first separation distance between an end of an inclined surface of the first bank and an end of an inclined surface of the first insulating layer in the first subpixel can be the same as a second separation distance between an end of an inclined surface of the first bank and an end of an inclined surface of the second insulating layer in the second subpixel. The width of the first opening of the first subpixel can be larger than the width of the first groove of the second subpixel. The first separation distance between the end of the inclined surface of the first bank and the end of the inclined surface of the first insulating layer in the first subpixel can be larger than the second separation distance between the end of the inclined surface of the first bank and the end of the inclined surface of the second insulating layer in the second subpixel. The first groove of the display device according to embodiments of the present disclosure may have a shallower depth than the first opening. The distance between the first pixel electrode, which is located at the first opening, and the substrate can be a first height, the distance between the second pixel electrode, which is located at the first groove, and the substrate can be a second height, and the second height can be greater than the first height. The display device according to embodiments of the present disclosure may further comprise an encapsulation layer arranged on the common electrode, a first color filter arranged on the encapsulation layer and overlapping the first pixel electrode, and a second color filter arranged on the encapsulation layer and overlapping the second pixel electrode. The first pixel electrode may have a first inclined portion extending along the inner wall of the first insulating layer, and the second pixel electrode may have a second inclined portion extending along the inner wall of the second insulating layer. The first color filter may overlap the first inclined portion, and the second color filter may overlap the second inclined portion. The first and second subpixels can emit light of different colors, and the first color filter can have a different thickness than the second color filter. The first and second subpixels can emit light of the same color, and the first color filter can have the same thickness as the second color filter. The area occupied by the first groove can be the same as the area occupied by the first opening. The area occupied by the first groove can be smaller than the area occupied by the first opening. The display device according to embodiments of the present disclosure may further comprise a second bank arranged between the common electrode and the first pixel electrode and between the common electrode and the second pixel electrode, and positioned around the outer edges of the first opening and the first groove. The display device according to embodiments of the present disclosure can further comprise a first to fourth pixel, wherein the first subpixel can be contained in each of the first and the third pixel and the second subpixel can be contained in each of the second and the fourth pixel. The distance between the first and third pixels can differ from the distance between the second and fourth pixels. The display device according to embodiments of the present disclosure may further comprise a third insulating layer arranged on the second planarization layer, positioned in a region of a third subpixel and having a second groove; a third pixel electrode positioned in the region of the third subpixel, arranged on the third insulating layer in or on the second groove and extending along an inner wall of the third insulating layer; the first bank arranged on the third pixel electrode and having a third hole that overlaps the second groove but is smaller than it; a third light-emitting layer arranged on the third pixel electrode; and the common electrode arranged on the third light-emitting layer and extending along the inner walls of the third hole to the upper surface of the first bank. A distance between the lower surface of the first groove and a back side of the second insulating layer can correspond to a first thickness, and a distance between a lower surface of the second groove and a back side of the third insulating layer can correspond to a second thickness that differs from the first thickness. The second subpixel can emit red light, the third subpixel can emit green light, and the first thickness can be greater than the second thickness. The display device according to embodiments of the present disclosure may further comprise a fourth insulating layer arranged on the second planarization layer, positioned in a region of a fourth subpixel and having a third groove; a fourth pixel electrode positioned in the region of the fourth subpixel, arranged in the third groove on the fourth insulating layer and extending along an inner wall of the fourth insulating layer; the first bank arranged on the fourth pixel electrode and having a fourth hole that overlaps the third groove but is smaller than it; a fourth light-emitting layer arranged on the fourth pixel electrode; and the common electrode arranged on the fourth light-emitting layer and extending along the respective inner walls of the first bank to the upper surface of the first bank. The distance between a lower surface of the third groove and a back side of the fourth insulating layer can have a third thickness that differs from the second thickness. The third subpixel can emit green light, and the fourth subpixel can emit blue light, and the second thickness can be greater than the third thickness. The first opening can have a first partial opening positioned in one part of the first subpixel and a second partial opening positioned in another part of the first subpixel. The first insulating layer can be located between the first and second partial openings. The first pixel electrode can be located on the second planarization layer in the first and second partial openings, extending beyond the outer boundaries of the first and second partial openings and along the inner walls of the first insulating layer. The first groove can have a first sub-groove positioned in one part of the second subpixel and a second sub-groove positioned in another part of the second subpixel. The second insulating layer can have an upper surface between the first and second grooves that is higher than the lower surfaces of the first and second grooves.The second pixel electrode can be located on the lower surfaces of the first and second grooves, extend beyond the outer boundaries of the first and second grooves, and be located along the inner walls of the second insulating layer. The first hole can have a first sub-hole located in one part of the first subpixel and a second sub-hole located in another part of the first subpixel. The first bank can further be positioned between the first and second sub-holes. The first light-emitting layer can have a first light-emitting sublayer located in the first sub-hole and a second light-emitting sublayer located in the second sub-hole. The second hole can have a third sub-hole located in one part of the second subpixel and a fourth sub-hole located in another part of the second subpixel. The first bank can further be positioned between the third and fourth sub-holes.The second light-emitting layer can have a third light-emitting sublayer located in the third sub-hole and a fourth light-emitting sublayer located in the fourth sub-hole. A distance between the first pixel electrode, located in the first partial opening, and the substrate (e.g., a lower surface of the substrate) can correspond to a first partial height. A distance between the first pixel electrode, located in the second partial opening, and the substrate (e.g., a lower surface of the substrate) can correspond to a second partial height. A distance between the second pixel electrode, located in the first lower groove, and the substrate (e.g., a lower surface of the substrate) can correspond to a third partial height. A distance between the second pixel electrode, located in the second lower groove, and the substrate (e.g., a lower surface of the substrate) can correspond to a fourth partial height. The first and second partial heights can be equal to each other, and at least one of the third and fourth partial heights can be greater than either (or both) of the first and second partial heights. The third and fourth partial heights can each be greater than either (or a respective) of the first and second partial heights, and the third and fourth partial heights can be equal to each other. The third and fourth partial heights can each be greater than either (or a respective) of the first and second partial heights, and the third and fourth partial heights can be different from each other. A display device according to embodiments of the present disclosure may comprise: a substrate; a first insulating layer arranged on the substrate, located in a first subpixel and having a first opening; a second insulating layer arranged on the substrate, located in a second subpixel and having a first groove; a first electrode located in the first subpixel, arranged at the first opening and extending along an inner lateral surface of the first insulating layer; a second electrode located in the second subpixel, arranged at the first groove and extending along an inner lateral surface of the second insulating layer; a first bank arranged on the first electrode and the second electrode and having a first hole and a second hole; a first light-emitting layer arranged between the first electrode and a third electrode;and a second light-emitting layer arranged on the second electrode. The first hole can overlap the first opening, and the second hole can overlap the first groove. The distance between the substrate and the second electrode at the first groove can be greater than the distance between the substrate and the first electrode at the first opening. The first electrode can extend along an inner lateral surface of the first opening, and the second electrode can extend along an inner lateral surface of the first groove. The first opening and the first groove can each have an inclined side section. The first hole and the second hole can each have an inclined side section. The first light-emitting layer can be located in a lower region of the first hole, and the second light-emitting layer can be located in a lower region of the second hole. In one example, the first light-emitting layer does not extend upwards along the inner side of the first hole. In another example, the second light-emitting layer does not extend upwards along the inner side of the second hole. A first gap can be provided between the lowest edge of the first opening and the lowest edge of the first hole that is closest to the lowest edge of the first opening. A second gap can be provided between the lowest edge of the first groove and the lowest edge of the second hole that is closest to the lowest edge of the first groove. The first gap can be larger than the second gap.

Claims

A display device (110) comprising: a substrate (111); a first planarization layer (221) arranged on the substrate (111); a second planarization layer (222) arranged on the first planarization layer (221); a first insulating layer (223r1) arranged on the second planarization layer (222), located in a first subpixel region (SP1) and having a first aperture (PH1); a second insulating layer (223r2) arranged on the second planarization layer (222), located in a second subpixel region (SP2) and having a first groove (PG1); a first pixel electrode (PEr1) located in the first subpixel region (SP1) on the second planarization layer (222) at the first aperture (PH1) and extending along an inner lateral surface of the first insulating layer (223r1);a second pixel electrode (PEr2) located in the second subpixel region (SP2) on a lower surface of the first groove (PG1) and extending along an inner lateral surface of the first groove (PG1); a first bank (231) arranged on the first pixel electrode (PEr1) and the second pixel electrode (PEr2) and having a first hole (BH1) and a second hole (BH2), wherein the first hole (BH1) overlaps the first opening (PH1) and is smaller than the first opening (PH1), and the second hole (BH2) overlaps the first groove (PG1) and is smaller than the first groove (PG1); a first light-emitting layer (EML1) arranged on the first pixel electrode (PEr1); a second light-emitting layer (EML2) arranged on the second pixel electrode (PEr2);and a common electrode (CE) located on the first light-emitting layer (EML1) and the second light-emitting layer (EML2) and extending along the respective inner lateral surfaces of the first hole (BH1) and the second hole (BH2) of the first bank (231) to the upper surface of the first bank (231). The display device (110) according to claim 1, wherein the width of the first opening (PH1) of the first subpixel area (SP1) is greater than the width of the first groove (PG1) of the second subpixel area (SP2), and a first distance (D1) between an end of an inclined surface of the first bank (231) and an end of an inclined surface of the first insulating layer (223r1) in the first subpixel area (SP1) is greater than a second distance (D2) between an end of an inclined surface of the first bank (231) and an end of an inclined surface of the second insulating layer (223r2) in the second subpixel area (SP2). The display device (110) according to claim 1 or 2, wherein the first groove (PG1) has a depth (DT2) that is less than a depth (DT1) of the first opening (PH1). The display device (110) according to one of claims 1 to 3, wherein a distance between the first pixel electrode (PEr1) arranged at the first opening (PH1) and a lower surface of the substrate (111) has a first height (H1), wherein a distance between the second pixel electrode (PEr2) arranged at the first groove (PG1) and the lower surface of the substrate (111) has a second height (H2), and wherein the second height (H2) is greater than the first height (H1). The display device (110) according to any one of claims 1 to 4, further comprising: an encapsulation layer (200) arranged on the common electrode (CE); a first color filter (CF1) arranged on the encapsulation layer (200) and overlapping the first pixel electrode (PEr1); and a second color filter (CF2) arranged on the encapsulation layer (200) and overlapping the second pixel electrode (PEr2), wherein the first pixel electrode (PEr1) has a first inclined portion extending along the inner lateral surface of the first insulating layer (223r1), wherein the second pixel electrode (PEr2) has a second inclined portion extending along an inner lateral surface of the second insulating layer (223r2), wherein the first color filter (CF1) overlaps the first inclined portion, and wherein the second color filter (CF2) overlaps the second inclined portion. The display device (110) according to claim 5, wherein the first subpixel area (SP1) and the second subpixel area (SP2) are configured to emit light of different colors, and wherein the first color filter (CF1) has a thickness that differs from the thickness of the second color filter (CF2). The display device (110) according to claim 5, wherein the first subpixel area (SP1) and the second subpixel area (SP2) are configured to emit light of the same color, and wherein the first color filter (CF1) has the same thickness as the second color filter (CF2). The display device (110) according to any one of claims 1 to 7, wherein an area occupied by the first groove (PG1) is smaller than an area occupied by the first opening (PH1). The display device (110) according to one of claims 1 to 8, which further comprises a second bank (232) arranged between the common electrode (CE) and the first pixel electrode (PEr1) and between the common electrode (CE) and the second pixel electrode (PEr2) and located outside the first opening (PH1) and the first groove (PG1). The display device (110) according to one of claims 1 to 9, further comprising a first pixel (P1), a second pixel (P2), a third pixel (P3) and a fourth pixel (P4), wherein the first subpixel area (SP1) is contained in each of the first pixel (P1) and third pixel (P3), wherein the second subpixel area (SP2) is contained in each of the second pixel (P2) and fourth pixel (P4), and wherein a distance between the first pixel (P1) and the third pixel (P3) differs from a distance between the second pixel (P2) and the fourth pixel (P4). The display device (110) according to any one of claims 1 to 10, further comprising: a third insulating layer (223g2) arranged on the second planarization layer (222), located in a third subpixel area (SP3) and having a second groove (PG2); a third pixel electrode (PEg2) arranged in the third subpixel area (SP3), located on the third insulating layer (223g2) at the second groove (PG2) and extending along an inner lateral surface of the third insulating layer (223g2);and a third light-emitting layer (EMLg2) arranged on the third pixel electrode (PEg2), wherein the first bank (231) is arranged on the third pixel electrode (PEg2) and has a third hole (BH3) that overlaps the second groove (PG2) and is smaller than the second groove (PG2), and wherein the common electrode (CE) is arranged on the third light-emitting layer (EMLg2) and extends along an inner lateral surface of the third hole (BH3) of the first bank (231) to a top surface of the first bank (231). The display device (110) according to claim 11, wherein a distance between the lower surface of the first groove (PG1) and a back side of the second insulating layer (223r2) has a first thickness (T1), and wherein a distance between a lower surface of the second groove (PG2) and a back side of the third insulating layer (223g2) has a second thickness (T2) which is different from the first thickness (T1). The display device (110) according to claim 12, wherein the second subpixel area (SP2) is configured to emit red light, wherein the third subpixel area (SP3) is configured to emit green light, and wherein the first thickness (T1) is greater than the second thickness (T2). The display device (110) according to claim 12 or 13, further comprising: a fourth insulating layer (223b2) arranged on the second planarization layer (222), located in a fourth subpixel area (SP4) and having a third groove (PG3); a fourth pixel electrode (PEb2) arranged in the fourth subpixel area (SP4), located on the fourth insulating layer (223b2) at the third groove (PG3) and extending along an inner lateral surface of the fourth insulating layer (223b2);and a fourth light-emitting layer (EMLb2) arranged on the fourth pixel electrode (PEb2), wherein the first bank (231) is arranged on the fourth pixel electrode (PEb2) and has a fourth hole (BH4) that overlaps the third groove (PG3) and is smaller than the third groove (PG3), and wherein the common electrode (CE) is arranged on the fourth light-emitting layer (EMLb2) and extends along an inner lateral surface of the fourth hole (BH4) of the first bank (231) to a top surface of the first bank (231). The display device (110) according to claim 14, wherein a distance between a lower surface of the third groove (PG3) and a rear side of the fourth insulating layer (223b2) has a third thickness (T3) that is different from the second thickness (T2), wherein the third subpixel area (SP3) is configured to emit green light, wherein the fourth subpixel area (SP4) is configured to emit blue light, and wherein the second thickness (T2) is greater than the third thickness (T3). The display device (110) according to any one of claims 1 to 15, wherein the first opening (PH1) has a first partial opening (PH1a) arranged in one region of the first subpixel area (SP1) and a second partial opening (PH1b) arranged in another region of the first subpixel area (SP1), wherein the first insulating layer (223r1) is further arranged between the first partial opening (PH1a) and the second partial opening (PH1b), wherein the first pixel electrode (PEr1) on the second planarization layer (222) is arranged at the first partial opening (PH1a) and the second partial opening (PH1b), extends to the outer sides of the first partial opening (PH1a) and the second partial opening (PH1b), and is arranged along the inner lateral surfaces of the first insulating layer (223r1), wherein the first groove (PG1) has a first subgroove (PG1a) arranged in one region of the second is arranged in the subpixel area (SP2), and has a second sub-groove (PG1b),which is located in a different area of ​​the second subpixel area (SP2), wherein the second insulating layer (223r2) has an upper surface that is higher than the lower surfaces of the first sub-groove (PG1a) and the second sub-groove (PG1b) and is located between the first sub-groove (PG1a) and the second sub-groove (PG1b), and wherein the second pixel electrode (PEr2) is located on the lower surfaces of the first sub-groove (PG1a) and the second sub-groove (PG1b), extends to the outer surfaces of the first sub-groove (PG1a) and the second sub-groove (PG1b) and is located along the inner lateral surfaces of the second insulating layer (223r2). The display device (110) according to claim 16, wherein the first hole (BH1) comprises a first partial hole (BH1a) located in one region of the first subpixel area (SP1) and a second partial hole (BH1b) located in another region of the first subpixel area (SP1), wherein the first bank (231) is further arranged between the first partial hole (BH1a) and the second partial hole (BH1b), wherein the first light-emitting layer (EML1) comprises: a first light-emitting sublayer (EML1a) arranged in the first partial hole (BH1a);and a second light-emitting sublayer (EML1b) located in the second subhole (BH1b), wherein the second hole (BH2) has a third subhole (BH2a) located in one region of the second subpixel region (SP2), and a fourth subhole (BH2b) located in the other region of the second subpixel region (SP2), wherein the first bank (231) is further arranged between the third subhole (BH2a) and the fourth subhole (BH2b), and wherein the second light-emitting layer (EML2) has: a third light-emitting layer (EML2a) located in the third subhole (BH2a); and a fourth light-emitting layer (EML2b) located in the fourth subhole (BH2b). The display device (110) according to claim 16 or 17, wherein a distance between the first pixel electrode (PEr1) arranged at the first partial opening (PH1a) and a lower surface of the substrate (111) is a first partial height (H1a), wherein a distance between the first pixel electrode (PEr1) arranged at the second partial opening (PH1b) and the lower surface of the substrate (111) is a second partial height (H2a), wherein a distance between the second pixel electrode (PEr2) arranged at the first groove (PG1a) and the lower surface of the substrate (111) is a third partial height (H2a), wherein a distance between the second pixel electrode (PEr2) arranged at the second lower groove (PG1b) and the lower surface of the substrate (111) is a fourth partial height (H2b), wherein the first partial height (H1a) and the second partial height (H1b) correspond to each otherand where at least one of the third partial height (H2a) and the fourth partial height (H2b) is greater than the first partial height (H1a) and the second partial height (H1b). The display device (110) according to claim 18, wherein each of the third partial height (H2a) and the fourth partial height (H2b) is greater than each of the first partial height (H1a) and the second partial height (H1b), and wherein the third partial height (H2a) and the fourth partial height (H2b) are equal to each other. The display device (110) according to claim 18, wherein each of the third partial height (H2a) and the fourth partial height (H2b) is greater than each of the first partial height (H1a) and the second partial height (H1b), and wherein the third partial height (H2a) and the fourth partial height (H2b) are different from each other.

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