DISPLAY DEVICE

Abstract

A display device comprises: a substrate (110) with an active area (AA), a first non-active area (NA1) enclosing the active area (AA), a bending area extending from the first non-active area (NA1) and configured to bend, and a second non-active area (NA2) extending from the bending area; a plurality of light-emitting diodes (120) arranged in the active area (AA) on the substrate (110); a touch sensing unit arranged above the plurality of light-emitting diodes (120); a first planarization layer (118c) arranged on the touch sensing unit; a first dam (DAM1) arranged in the first non-active area (NA1) such that it encloses the active area (AA); a second planarization layer (119) arranged on top of the first dam (DAM1) and the first planarization layer (118c);and a second dam (DAM2) located along a boundary between the first non-active area (NA1) and the bending area within the first non-active area (NA1). Furthermore, the second dam (DAM2) has the same material on the same layer as the first planarization layer (118c).

Description

BACKGROUND Area The present disclosure relates to a display device, and in particular a display device in which an excessive application of an organic material that planarizes an upper section of a display device is minimized to a bending area. Description of the related technique With the advent of the current information age, the field of display devices that visually express electrical information signals has developed rapidly, and studies and research have further improved the performance of various display devices, such as low thickness, low weight, and low power consumption. A representative display device of such various display devices may include, among others, a liquid crystal display device (LCD), a field emission display device (FED), an electrowetting display device (EWD), and an organic light-emitting display device (OLED). Among such various display devices, an electroluminescent display device is represented by an organic light-emitting display device. The organic light-emitting display device is a self-emitting display device that eliminates the need for a separate light source, thus differing from a liquid crystal display device, which requires a separate light source. Therefore, the electroluminescent display device can be manufactured to be lightweight and thin by eliminating the need for a separate light source.Since the electroluminescent display device is advantageous not only in terms of power consumption due to the low voltage drive, but also in terms of color implementation, response speed, viewing angle and contrast ratio (CR), it is expected that the organic light-emitting display device will be used in various fields in the future. BRIEF EXPLANATION OF THE REVELATION One problem to be solved by the present disclosure is to provide a display device in which excessive application of an organic material that planarizes an upper section of a display device is minimized to a bending area. Another problem to be solved by the present disclosure is to provide a display device that expands a space for receiving an excessively applied organic material. A further problem to be solved by the present disclosure is to provide a low-energy indicator device in which excessive application of organic material to a bending area is minimized in order to improve service life, thereby improving the reliability of the indicator device in order to reduce energy consumption. The tasks of this disclosure are not limited to those mentioned above, and other tasks not mentioned above can be clearly understood by the person skilled in the art from the following descriptions. According to one aspect of this disclosure, display devices are provided in accordance with the independent claims. Further embodiments are described in the dependent claims. According to one aspect of the present disclosure, a display device comprises a substrate having an active region, a first non-active region enclosing the active region, a bending region extending from the first non-active region for bending, and a second non-active region extending from the bending region; a plurality of light-emitting diodes arranged on the substrate in the active region; a touch sensing unit arranged above the plurality of light-emitting diodes; a first planarization layer arranged on the touch sensing unit; a first dam arranged in the non-active region such that it encloses the active region; and a second planarization layer arranged on top of the first dam and the first planarization layer.and a second dam arranged along a boundary of the first non-active area and the bending area in the first non-active area, the second dam being formed with the same material on the same layer as the first planarization layer. According to another aspect of the present disclosure, a display device comprises: a substrate having an active area in which a plurality of subpixels are arranged, a first inactive area enclosing the active area, and a bending area extending from the first inactive area to be bent; a plurality of light-emitting diodes arranged in each of the plurality of subpixels on the substrate; a touch detection unit arranged above the plurality of light-emitting diodes; a first planarization layer arranged on the touch detection unit; a first dam arranged in the inactive area such that it encloses the active area; a second planarization layer arranged on top of the first dam and the first planarization layer;and a second dam located in the first non-active area along a boundary between the first non-active area and the bending area, wherein the second dam is located on the same layer as the first planarization layer and is formed with the same material as the first planarization layer. Further detailed aspects of the exemplary embodiments are included in the detailed description and drawings. In the display device of the present disclosure, excessive application of organic material to the bending area is minimized in order to improve the reliability of the display device. In the display device of the present disclosure, a space for receiving excess organic material is enlarged in order to further minimize the excess application of the organic material. In the display device according to the present disclosure, excessive application of the organic material to the bending area is minimized in order to improve the reliability and lifetime of the display device, thereby implementing a low-energy display device with reduced energy consumption. The effects according to the present revelation are not limited to the contents exemplified above, and other various effects are included in the present revelation. BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which: Fig. 1A is a top view of a mother substrate used for a manufacturing process of a display device according to an exemplary embodiment of the present disclosure; Fig. 1B is an enlarged top view of a region B of Fig. 1A; Fig. 1C is a top view of a display device according to an exemplary embodiment of the present disclosure; Fig. 1D is an enlarged top view of a region E of Fig. 1C; Fig. 2 is a cross-sectional view along AA' of Fig. 1A; Fig. 3A is a cross-sectional view along CC' of Fig. 1B; Fig. 3B is a cross-sectional view along line FF' of Fig. 1D; Fig. 4A is a cross-sectional view along DD' of Fig. 1B; Fig.4B is a cross-sectional view along GG' of Fig. 1D; Fig. 5 is a cross-sectional view along HH' of Fig. 1D; Fig. 6 is an enlarged top view of area I of Fig. 1A; and Fig. 7 is a cross-sectional view along JJ' of Fig. 6. DETAILED DESCRIPTION OF THE EXECUTION FORMS The advantages and properties of the present disclosure and a method for achieving these advantages and properties will become clear by reference to the exemplary embodiments described in detail below, together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but is implemented in various forms. The exemplary embodiments are provided only as examples so that the person skilled in the art can fully understand the disclosures and the scope of the present disclosure. The shapes, sizes, ratios, angles, numbers, and the like shown in the accompanying drawings to describe exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited to them. Throughout the disclosure, the same reference numerals generally denote the same elements. Furthermore, in order to avoid unnecessarily obscuring the subject matter of the present disclosure, a detailed explanation of known related technologies may be omitted in the following description of the present disclosure. Terms such as "feature," "have," and "include" used herein are generally intended to permit the addition of other components unless the terms are used with the term "only." Any singular references may include the plural unless expressly stated otherwise. Components are interpreted as including a normal error range, even if this is not explicitly stated. When the positional relationship between two parts is described using terms such as "on", "above", "below", "next", one or more parts may be positioned between the two parts unless the terms are used with the term "immediately" or "directly". If one element or layer is placed “on” another element or layer, that other layer or element can be placed directly on top of the other element or in between. Although the terms "first," "second," and the like are used to describe different components, these components are not limited by these terms. These terms are merely used to distinguish one component from the other components. Therefore, in a technical concept of the present disclosure, a first component mentioned below may be a second component. Throughout the entire revelation, the same reference symbols generally denote the same elements. The size and thickness of each component shown in the drawing are indicated for the sake of simplicity, and the present disclosure is not limited to the size and thickness of the component shown. The term "may" encompasses all meanings of the term "is permitted" and covers it. The term "made of" for an element can fully encompass the meaning that it is formed entirely of the element or simply that it has the element. The features of different embodiments of the present disclosure can be partially or completely related to one another or combined with one another, and can be interlocked and operated in various technical ways, and the embodiments can be carried out independently of one another or in combination with one another. Various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Fig. 1A is a top view of a mother substrate used for a manufacturing process of a display device according to an exemplary embodiment of the present disclosure; Fig. 1B is an enlarged top view of area B of Fig. 1A; Fig. 1C is a top view of a display device according to an exemplary embodiment of the present disclosure; Fig. 1D is an enlarged top view of area E of Fig. 1C; Fig. 1A is a top view of a mother substrate SUB before a trimming process of a manufacturing process of a display device, and Fig. 1C is a top view of a substrate 110 after the trimming process. All components of each display device according to all embodiments of the present disclosure are operationally coupled and configured. The display device 100 is a device for displaying images to a user. The display device 100 can include a display element that shows images, a driver element that controls the display element, and wiring lines that transmit various signals to the display element and the driver element. The display element can be defined in different ways depending on the type of display device 100. For example, if the display device 100 is an organic light-emitting diode (OLED), the display element can be an OLED comprising an anode, an organic emission layer, and a cathode. If the display device 100 is a liquid crystal display device, the display element can be a liquid crystal display element. Hereinafter, the display device 100 is assumed to be an organic light-emitting diode, but the display device 100 is not limited to organic light-emitting diodes. With reference to Figures 1A to 1D, during the manufacturing process of a display device 100, a step of forming a substrate 110 can be carried out by performing a trimming process on a parent substrate SUB. The trimming process can, for example, be a cutting process using a laser or a scribing process that directly applies a physical force to the parent substrate SUB using a tool such as a cutting device, but embodiments of the present disclosure are not limited thereto. The trimming process can be carried out along a predetermined trimming line a. The substrate 110 is a component for supporting various components contained in the display device 100 and can be made of an insulating material. The substrate 110 is arranged to support components on the lowest section of the display device 100, so that the substrate can also be referred to as a lower substrate, but is not limited to this term. Substrate 110 has an active region AA and a non-active region. The active area AA is an area where images are displayed on substrate 110. Within the active area AA, a multitude of subpixels SP, which configure a multitude of pixels, and a driver circuit for controlling the multitude of subpixels SP can be arranged. The plurality of subpixels SP are minimal units that configure the active area AA, and a display element can be located in any of the plurality of subpixels SP. For example, an organic light-emitting diode (OLED) having an anode, an organic emission layer, and a cathode can be located in any of the plurality of subpixels SP, but is not limited to doing so. Furthermore, the driver circuit for controlling the plurality of subpixels SP can include a driver element and a wiring line. For example, the driver circuit can be configured by, but is not limited to, a thin-film transistor, a storage capacitor, a gate line, and a data line. The inactive region is an area where no image is displayed. The inactive region can refer to an outer circumferential section of substrate 110 that surrounds the active region AA. The inactive region can overlap a black matrix. Numerous wiring lines and circuits for driving an organic light-emitting diode (OLED) in the active region AA are located within the inactive region. For example, the inactive region may contain, but is not limited to, a connecting line that transmits signals to the multitude of subpixels SP, driver circuits for the active region AA, or a driver IC (D-IC), such as a gate driver IC or a data driver IC. The non-active area has a first non-active area NA1, a bending area BA and a second non-active area NA2. The first non-active region NA1 is a region that surrounds and extends from the active region AA. The bending region BA can extend from one side of the first non-active region NA1 and may be curved. The second non-active region NA2 is a region that extends from the bending region BA to be positioned below the active region. Meanwhile, with reference to Fig. 1A and Fig. 1C, the first non-active region NA1 and the second non-active region NA2 can be arranged on the same plane as the active region AA, or arranged to be parallel to the active region AA and to maintain a flat state. For example, the first non-active region NA1 can be arranged to be flat on the same plane as the active region AA, and the second non-active region NA2 can be arranged below the active region AA to be parallel to the active region AA and to be flat, but embodiments of the present disclosure are not limited thereto. Therefore, the active region AA, the first non-active region NA1, and the second non-active region NA2 can, for example, be referred to as non-bending regions, but are not limited thereto. Referring to Fig. 1A and Fig. 1C, the driver IC D-IC is arranged in the second non-active area NA2. The driver IC D-IC can provide a data signal to the plurality of subpixels SP. For example, the driver IC D-IC samples and stores the data signal provided by the timing controller in response to a data timing signal provided by the timing controller in order to convert the data signal into a gamma reference voltage and output the converted gamma reference voltage, but embodiments of the present disclosure are not limited thereto. The driver IC D-IC can output a data signal through the plurality of data lines.For example, in the second non-active area NA2, where the driver IC D-IC is located, a pad unit is arranged, and a printed circuit board, electrically connected to the pad unit, is further arranged to provide a signal to the driver IC D-IC, but is not limited to doing so. However, the driver IC D-IC is arranged on one side of the display panel PN in a chip-on-panel (COP) manner to be connected to the display panel PN, or is arranged in a separate flexible film to be connected to the substrate 110 in a chip-on-film (COF) manner. In the display device 100 according to the exemplary embodiment of the present disclosure, the driver IC D-IC is assumed to be arranged in the COP manner, but is not limited to this. At this point, when the substrate 110 is bent, the driver IC D-IC, located in the second non-active region NA2, can be positioned beneath the active region AA. For example, the driver IC D-IC and the printed circuit board connected to the pad unit of the substrate 110 can move to the rear face of the substrate 110 and overlap the active region AA. Therefore, from the top of the substrate 110, circuit elements such as the driver IC D-IC and the printed circuit board need not be visible. Accordingly, the size of the non-active region visible from the top of the substrate 110 is reduced to implement a narrow border, but embodiments of the present disclosure are not limited to this. A through-hole can be located within the active area AA. For example, no image needs to be displayed in an area within the active area AA where a through-hole is located. The through-hole can be a hole that passes through the substrate 110. The through-hole can be designed to cover a camera or photosensor. Therefore, in the display device 100, the through-hole is located within the active area AA to reduce a border area that is a non-active area and to maximize the active area AA. As described above, a product with a design that maximizes the active area AA can be aesthetically preferred by maximizing the user's screen immersion. Referring to Figures 1A to 1D, a second dam DAM2 is arranged in the first non-active region NA1 in a region adjacent to the bending region BA. The second dam DAM2 is arranged along a boundary between the first non-active region NA1 and the bending region BA within the first non-active region NA1. The second dam DAM2 can restrict or block the position of the planarization layer to prevent the planarization layer, which planars an upper section of the component of the display device 100, from extending into the bending region BA, the active region AA, and the first non-active region NA1. However, with reference to Fig. 1A, the second dam DAM2 can be arranged such that, before the trimming process, it just crosses one side of the mother substrate SUB along a boundary between the first non-active area NA1 and the bending area BA. With reference to Fig. 1C, the second dam DAM2 can be partially removed so that, after the trimming process, it is only located in an area adjacent to the bending area BA. The second dam DAM2 after the trimming process is described in detail below with reference to Figs. 3, 4, 5, 6 to 7. As shown in Figs. 1C and 1D, end sections of the second dam DAM2 that have been trimmed by the trimming process can have a curvature that follows the predetermined trim line a. The following section describes a cross-sectional structure of the active area AA with reference to Fig. 2. Fig. 2 is a cross-sectional view along AA' of Fig. 1A. Fig. 2 is a cross-sectional view showing a cross-sectional structure of a subpixel SP located in an active region AA according to an embodiment of the present disclosure. Referring to Fig. 2, the display device 100 according to the embodiment of the present disclosure comprises in the active area AA a substrate 110, a light-shielding layer LS, a first buffer layer 111, a first thin-film transistor TR1, a second thin-film transistor TR2, a first gate insulating layer 112a, a first intermediate insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, a second intermediate insulating layer 113b, a connecting electrode CE, a first planarizing layer 115a, a second planarizing layer 115b, an auxiliary electrode AE, a wall 116a, a spacer 116b, a light-emitting diode 120, an encapsulation unit 117, a touch buffer layer 118a, a touch sensing unit, a touch intermediate insulating layer 118b, a third Planarization layer 118c and a fourth planarization layer 119 were arranged. The substrate 110 serves to support and protect components of the display device 100 that are arranged above it. The substrate 110 is a component for supporting various components present in the display device 100 and can be made of an insulating material. The substrate 110 is arranged to support components on the lowest section of the display device 100, so that the substrate can also be referred to as a lower substrate, but is not limited to this. The substrate 110 can comprise a first substrate 110a, a second substrate 110b, and an intermediate insulating film 110c. The intermediate insulating film 110c can be positioned between the first substrate 110a and the second substrate 110b. As described above, the substrate 110 is configured by the first substrate 110a, the second substrate 110b, and the intermediate insulating film 110c to suppress moisture permeation. However, the substrate 110 can be arranged as a single layer, but is not limited to this configuration. For example, the first substrate 110a and the second substrate 110b can be polyimide (PI) substrates, and the intermediate insulating film 110c can be formed from a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or several layers thereof, but embodiments of the present disclosure are not limited thereto. The intermediate insulating film 110c need not be arranged in at least one sub-region. For example, the intermediate insulating film 110c need not be formed in a region where a stress is concentrated, such as a bending region BA or an outermost region, but embodiments of the present disclosure are not limited thereto. The light-shielding layer LS can be arranged on the substrate 110. The light-shielding layer LS can be a protective layer formed from metal, arranged beneath the semiconductor layers A1 and A2 of a plurality of transistors TR1 and RT2 to shield external light in the display device 100. The light-shielding layer LS can minimize damage to the semiconductor layers A1 and A2 caused by the external light. The first buffer layer 111 can be arranged on the substrate 110, covering the light-shielding layer LS. In particular, a multiple buffer layer 111a can be arranged on the substrate 110, covering the light-shielding layer LS, and an active buffer layer 111b can be arranged on the multiple buffer layer 111a. The multiple buffer layer 111a can delay the diffusion of moisture or oxygen penetrating the substrate 110 and can comprise at least one of silicon nitride SiNx and silicon oxide SiOx. The active buffer layer 111b can protect the first semiconductor layer A1 and block various types of defects introduced into the substrate 110. For example, the active buffer layer 111b can comprise at least one of amorphous silicon (a-Si), silicon nitride (SiNx), and silicon oxide (SiOx), but embodiments of the present disclosure are not limited thereto. The first thin-film transistor TR1 can be located on the first buffer layer 111. The first thin-film transistor TR1 can have the first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. Depending on the pixel circuit design, the first source electrode S1 can serve as a first drain electrode, and vice versa. The first semiconductor layer A1 can be arranged on the first buffer layer 111 such that it overlaps the light-shielding layer LS. The first semiconductor layer A1 can comprise amorphous silicon or polycrystalline silicon. For example, the first semiconductor layer A1 can comprise low-temperature polycrystalline silicon (LTPS). For example, the polycrystalline silicon material has a high mobility (100 cm² / Vs or higher), so that the power consumption is low and the reliability is excellent, but embodiments of the present disclosure are not limited thereto.Therefore, the polysilicon material can be deposited on a gate driver for driving elements that drive thin-film transistors for a display element and / or a multiplexer (MUX), and can also be deposited as a first semiconductor layer A1 of a driver thin-film transistor of the display device 100 according to the exemplary embodiment, but is not limited thereto. For example, the polycrystalline silicon material can also be deposited as a second semiconductor layer A2 of the switching thin-film transistor according to the feature of the display device 100. An amorphous silicon (a-Si) material is deposited on the first buffer layer 111, and a dehydration and crystallization process is carried out to form polycrystalline silicon, and the polycrystalline silicon is structured to form the first semiconductor layer A1, but embodiments of the present disclosure are not limited thereto.Here, the first semiconductor layer A1 can have a first channel region, in which a channel is formed when the first thin-film transistor TR1 is driven, and a first source region and a first drain region on either side of the first channel region. The first source region refers to a portion of the first semiconductor layer A1 connected to the first source electrode S1, and the first drain region refers to a portion of the first semiconductor layer A1 connected to the first drain electrode D1. For example, the first source region and the first drain region can be configured by ion doping (impurity doping) of the first semiconductor layer A1.The first source region and the first drain region can be generated by doping ions into the polycrystalline silicon material, and the first channel region can refer to a part that is not doped with ions but remains as the polycrystalline silicon material, but embodiments of the present disclosure are not limited thereto. The first gate isolation layer 112a can be arranged on the first semiconductor layer A1. The first gate isolation layer 112a can be configured as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or as a multiple layer thereof. A contact hole can be formed in the first gate isolation layer 112a, through which the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1 are connected to the first source region and the first drain region, respectively, of the first semiconductor layer A1 of the first thin-film transistor TR1. The first gate electrode G1 of the first thin-film transistor TR1 and a first capacitor electrode C1 of the storage capacitor Cst can be arranged on the first gate insulation layer 112a. At this stage, the first gate electrode G1 and the first capacitor electrode C1 can be formed by a single layer or a multiple layer composed of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first gate electrode G1 can be formed on the first gate insulating layer 112a such that it overlaps the first channel region of the first semiconductor layer A1 of the first thin-film transistor TR1. The first capacitor electrode C1 can be omitted based on a driver characteristic of the display device 100 and a structure and type of thin-film transistor. The first gate electrode G1 and the first capacitor electrode C1 can be formed by the same process. Furthermore, the first gate electrode G1 and the first capacitor electrode C1 can be formed from the same material on the same layer. The first interlayer insulating layer 113a can be arranged above the first gate insulating layer 112a, the first gate electrode G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a can be configured as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or as a multiple layer thereof. A contact hole can be formed in the first interlayer insulating layer 113a to expose the first source region and the first drain region of the first semiconductor layer A1 of the first thin-film transistor TR1. A second capacitor electrode C2 of the storage capacitor Cst can be arranged on the first intermediate insulating layer 113a. The second capacitor electrode C2 can be formed by a single layer or multiple layers made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The second capacitor electrode C2 can be formed on the first intermediate insulating layer 113a such that it overlaps the first capacitor electrode C1. Furthermore, the second capacitor electrode C2 can be made of the same material as the first capacitor electrode C1. The second capacitor electrode C2 can be omitted based on a driver characteristic of the display device 100 and a structure and type of thin-film transistor. The second buffer layer 114 can be arranged on the first intermediate insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 can be configured as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or as a multiple layer thereof. A contact hole for exposing the first source region and the first drain region of the first semiconductor layer A1 of the first thin-film transistor TR1 can be formed in the second buffer layer 114. Furthermore, a contact hole for exposing the second capacitor electrode C2 of the storage capacitor Cst can be formed in the second buffer layer 114. The second buffer layer 114 can be formed by several layers, but is not limited to this. The second semiconductor layer A2 of the second thin-film transistor TR2 can be arranged on the second buffer layer 114. Here, the second thin-film transistor TR2 can have the second semiconductor layer A2, a second gate insulating layer 112b, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. Depending on the pixel circuit design, the second source electrode S2 can function as a drain electrode, and the second drain electrode D2 can function as a source electrode. Furthermore, the second semiconductor layer A2 can have a second channel region, in which a channel is formed when the second thin-film transistor TR2 is driven, and a second source region and a second drain region on both sides of the second channel region. The second source region can refer to a portion of the second semiconductor layer A2 that is connected to the second source electrode S2, and the second drain region can refer to a portion of the second semiconductor layer A2 that is connected to the second drain electrode D2. The second semiconductor layer A2 can be made of an oxide semiconductor. The oxide semiconductor material has a larger band gap than silicon, so electrons cannot jump across the band gap in a reverse state. Therefore, the oxide semiconductor material has a low reverse current. Thus, a thin-film transistor with a semiconductor layer made of an oxide semiconductor can be suitable for, but is not limited to, a switching thin-film transistor that keeps the on-time short and the off-time long. Depending on the characteristics of the display device 100, a thin-film transistor having a semiconductor layer formed from an oxide semiconductor can be used as a driver thin-film transistor. Furthermore, due to the low reverse current, the size of the secondary capacitance can be reduced, making the oxide semiconductor suitable for a high-resolution display element. For example, the second semiconductor layer A2 can be formed from a metal oxide, such as indium gallium zinc oxide (IGZO). The description here assumes, but is not limited to, that the second semiconductor layer A2 of the second thin-film transistor TR2 is configured with various metal oxides, including IGZO.Therefore, the second semiconductor layer A2 can be formed from a different metal oxide such as indium zinc oxide (IZO), indium gallium tin oxide (IGTO) or indium gallium oxide (IGO) instead of IGZO. The second semiconductor layer A2 can be formed by depositing the metal oxide on the second buffer layer 114, performing a heat treatment to stabilize and then structuring the metal oxide. The second gate insulating layer 112b can be arranged on the entire substrate 110, which has the second semiconductor layer A2. For example, the second gate insulating layer 112b can be configured as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or as a multiple layer thereof, but embodiments of the present disclosure are not limited thereto. The second gate electrode G2 can be arranged on the second gate insulation layer 112b. The second gate electrode G2 can be formed by a single layer or a multiple layer made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or an alloy thereof. For example, a metal material is formed on the second gate insulating layer 112b, a photoresist structure is formed on the metal material, and then the metal material is wet-etched using the photoresist structure as a mask to form the second gate electrode G2. A wet etchant for etching the metal material can be a material that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof, forming the metal material but not etching the insulating material; however, embodiments of the present disclosure are not limited thereto. The second interlayer insulating layer 113b can be arranged on the second gate insulating layer 112b and the second gate electrode G2. A contact hole for exposing the first semiconductor layer A1 of the first thin-film transistor TR1 and the second semiconductor layer A2 of the second thin-film transistor TR2 can be formed in the second interlayer insulating layer 113b. For example, a contact hole for exposing the first source region and the first drain region of the first semiconductor layer A1 of the first thin-film transistor TR1 can be formed in the second interlayer insulating layer 113b. A contact hole for exposing the second source region and the second drain region of the second semiconductor layer A2 of the second thin-film transistor TR2 can be formed in the second interlayer insulating layer 113b, but embodiments of the present disclosure are not limited thereto. The second intermediate insulating layer 113b can be configured as a single layer of silicon nitride SiNx or silicon oxide SiOx, or as a multiple layer thereof. The connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1 and the second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2 can be arranged on the second interlayer insulating layer 113b. The connecting electrode CE can be electrically connected to the second drain electrode D2 of the second thin-film transistor TR2. Furthermore, the connecting electrode CE can be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through the contact holes formed in the second buffer layer 114 and the second intermediate insulating layer 113b. For example, the connecting electrode CE can serve to electrically connect the second capacitor electrode C2 of the storage capacitor Cst and the second drain electrode D2 of the second thin-film transistor TR2, but embodiments of the present disclosure are not limited thereto. Here, the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1 can be connected to the first semiconductor layer A1 of the first thin-film transistor TR1 through the contact holes formed in the first gate insulating layer 112a, the first intermediate insulating layer 113a, the second buffer layer 114 and the second intermediate insulating layer 113b. The second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2 can be connected to the second semiconductor layer A2 through the contact hole formed in the second gate insulating layer 112b. The connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1 and the second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2 can be formed from the same material by the same process. For example, the connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2 can be formed by a single layer or a multiple layer composed of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof, but embodiments of the present disclosure are not limited thereto. For example, the connecting electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2 can be formed from a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but are not limited thereto. The connecting electrode CE can be integrally formed to be connected to the second drain electrode D2 of the second thin-film transistor TR2, but is not limited to this. The first planarization layer 115a can be arranged on the junction electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin-film transistor TR1, the second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2 and the second interlayer insulating layer 113b. The first planarization layer 115a can be an organic layer that planars and protects the upper sections of the first thin-film transistor TR1 and the second thin-film transistor TR2. For example, the first planarization layer 115a can be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but embodiments of the present disclosure are not limited thereto. The secondary electrode AE ​​can be arranged on the first planarization layer 115a. The secondary electrode AE ​​can be connected to the second drain electrode D2 of the second thin-film transistor TR2 through the contact hole of the first planarization layer 115a. The secondary electrode AE ​​can serve to electrically connect the second thin-film transistor TR2 and the anode 121. The secondary electrode AE ​​can be formed from a single layer or a multiple layer made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The secondary electrode AE ​​can be made of the same material as the second source electrode S2 and the second drain electrode D2 of the second thin-film transistor TR2. The second planarization layer 115b can be arranged above the secondary electrode AE ​​and the first planarization layer 115a. For example, the second planarization layer 115b can be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but embodiments of the present disclosure are not limited thereto. The light-emitting diode 120 can be arranged on the second planarization layer 115b. The light-emitting diode 120 has an anode 121, an emission layer 122 and a cathode 123. The anode 121 can be arranged on the second planarization layer 115b. At this point, the anode 121 can be electrically connected to the secondary electrode AE ​​through the contact hole provided in the second planarization layer 115b. The anode 121 can be made of a metallic material. If the display device 100 is of a top-emission type, in which light emitted by the LED 120 is emitted above the substrate 110 on which the LED 120 is mounted, the anode 121 can have a reflective layer and a transparent conductive layer arranged on top of the reflective layer. The transparent conductive layer can be formed from a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the reflective layer can be formed from, but is not limited to, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof. The wall unit 116 is arranged on the anode 121. The wall unit 116 has a wall 116a and a spacer 116b. Wall 116a can be arranged so that it covers one end of anode 121. A portion of wall 116a corresponding to an emission region of the subpixel may be open. A portion of anode 121 may be exposed through the open portion of wall 116a (hereinafter referred to as an open region). At this point, wall 116a may be formed from, but is not limited to, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as benzocyclobutene resin, acrylic resin, or imide resin. The spacer 116b can further be arranged on the wall 116a. The spacer 116b can serve to maintain a predetermined gap to allow a mask to be out of contact with a substrate during a manufacturing process of an emission layer 122 of the light-emitting diode 120, which is formed from an organic material. For example, the spacer 116b can be made from an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material, such as benzocyclobutene resin, acrylic resin or imide resin, but is not limited to this. The emission layer 122 is arranged on the anode 121, the wall 116a, and the spacer 116b. The emission layer 122 can be located in the open area of ​​the wall 116a and in the vicinity of the open area of ​​the wall. Therefore, the emission layer 122 can be located on the anode 121, which is exposed by the open area of ​​the wall 116a. The emission layer 122 can comprise a variety of organic material layers. For example, the emission layer 122 can comprise an organic material layer such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, but embodiments of the present disclosure are not limited thereto. However, if the emission layer 122 emits white light, the light emitted by the emission layer 122 can be converted into light of different colors by a variety of color filters CF, but is not limited thereto. The cathode 123 is arranged on the emission layer 122. The cathode 123 provides electrons to the emission layer 122, so the cathode can be formed from a conductive material with a low work function. The cathode 123 can be formed as a layer over the plurality of subpixels SP. For example, the cathodes 123 of the plurality of subpixels SP can be connected to form an integral structure. For example, the cathode 123 can be made of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or ytterbium (Yb) alloy and may also have a metal doping layer, but is not limited to this. The encapsulation unit 117 is arranged on the light-emitting diode 120. The encapsulation unit 117 can have a single-layer or a multi-layer structure. For example, the encapsulation unit 117 can have a multi-layer structure comprising a first encapsulation layer 117a, a second encapsulation layer 117b, and a third encapsulation layer 117c. However, the encapsulation unit can also be formed with a single-layer structure, but is not limited to this. The first encapsulation layer 117a and the third encapsulation layer 117c can be made of inorganic materials, and the second encapsulation layer 117b can be made of an organic material. The second encapsulation layer 117b can be the thickest among the first encapsulation layer 117a, the second encapsulation layer 117b, and the third encapsulation layer 117c. The second encapsulation layer 117b can planarize an upper section of the light-emitting diode 120. The first encapsulation layer 117a can be arranged on the cathode 123 and positioned such that it is closest to the light-emitting diode 120 in the encapsulation unit 117. For example, the first encapsulation layer 117a can be configured with silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3), but is not limited to these materials. The second encapsulation layer 117b can be formed such that it has a smaller area than the first encapsulation layer 117a. In this case, the second encapsulation layer 117b can be formed such that it exposes both ends of the first encapsulation layer 117a. The second encapsulation layer 117b can serve as a buffer to reduce stress between the layers due to bending of the flexible display device and improve planarization. For example, the second encapsulation layer 117b can be formed from an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC), but embodiments of the present disclosure are not limited thereto. For example, the second encapsulation layer 117b can be formed by an inkjet process, but is not limited thereto. The third encapsulation layer 117c can be formed over the substrate 110, on which the second encapsulation layer 117b is formed such that it covers the top and side surfaces of the second encapsulation layer 117b and the first encapsulation layer 117a. At this point, the third encapsulation layer 117c can minimize or block the permeation of external moisture or oxygen into the first encapsulation layer 117a and the second encapsulation layer 117b. For example, the third encapsulation layer 117c can be configured with, but is not limited to, an inorganic insulating material such as silicon nitride (SiNx), silicon dioxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). The touch detection unit can be arranged on the encapsulation unit 117. The touch detection unit can comprise the touch buffer layer 118a, the touch intermediate layer insulating layer 118b, the touch electrode TE, the third planarization layer 118c, and a touch routing line TL. The touch electrode TE can comprise a touch sensor electrode TS and a touch bridge electrode TB, which are arranged on different layers. For example, the contact buffer layer 118a can be arranged above the third encapsulation layer 117c, and the contact bridge electrode TB can be arranged on the contact buffer layer 118a. The contact interlayer insulating layer 118b can be arranged on the contact bridge electrode TB, and the contact sensor electrode TS can be arranged on the contact interlayer insulating layer 118b. The third planarization layer 118c is arranged on the touch sensor electrode TS. The third planarization layer 118c can be an organic layer that planars and protects an upper section of the touch sensor electrode TS. Therefore, the third planarization layer 118c can be positioned to be in contact with the touch sensor electrode TS. For example, the third planarization layer can be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited to this. For example, the touch buffer layer 118a, the touch intermediate insulating layer 118b, and the third planarization layer 118c can be formed from an inorganic insulating material or an organic insulating material.Therefore, the touch buffer layer 118a, the touch intermediate layer insulating layer 118b and the third planarization layer 118c can minimize a step at a location where the touch electrode TE is positioned and electrically isolate the touch sensor electrode TS from the touch bridge electrode TB. The fourth planarization layer 119 is arranged on top of the third planarization layer 118c. The fourth planarization layer 119 can planarize upper sections of the plurality of contact electrodes TE. In particular, the fourth planarization layer 119 can be configured to completely planarize upper sections of the active region AA, the first non-active region NA1, and the second non-active region NA2 on the substrate 110. Therefore, the fourth planarization layer 119 can be, but is not limited to, a configuration arranged on the topmost layer of the substrate 110. The fourth planarization layer 119 can be formed from, but is not limited to, an organic material such as an epoxy-based resin. The following section describes a cross-sectional structure of the first non-active area NA1 adjacent to the bending area BA with reference to Figs. 3A to 7. Fig. 3A is a cross-sectional view along CC' of Fig. 1B. Fig. 3B is a cross-sectional view along FF' of Fig. 1D. Fig. 4A is a cross-sectional view along DD' of Fig. 1B. Fig. 4B is a cross-sectional view along GG' of Fig. 1D. Fig. 5 is a cross-sectional view along HH' of Fig. 1D. Fig. 6 is an enlarged top view of region I of Fig. 1A. Fig. 7 is a cross-sectional view along JJ' of Fig. 6. Figs. 3A to 7 are cross-sectional and top views of each region of the first non-active region NA1 according to an exemplary embodiment of the present disclosure. Figs. 3A and 3B are cross-sectional views showing the same region, and Figs. 4A and 4B are cross-sectional views showing the same region. Fig. 3A and Fig. 4A are cross-sectional views before the trimming process and Fig. 3B and Fig. 4B are cross-sectional views after the trimming process. With reference to Figs. 3A to 7, in the display device 100 according to the exemplary embodiment of the present disclosure, a current line PL, a first dam DAM1, a second dam DAM2, a third planarization layer 118c and a fourth planarization layer 119 are arranged in the first non-active area NA1 of the substrate 110. In the first non-active region NA1, the power line PL can be located on the second intermediate insulating layer 113b. For example, a low-potential or a high-potential voltage can be supplied to the subpixel SP of the display device 100 via the power line PL. At this point, the power line PL can be formed on the same layer as the first gate electrode G1, which is located in the active region AA, and with the same material, but is not limited to this. Meanwhile, with reference to Fig. 3A and Fig. 3B, the power conductor PL can have a plurality of holes. Therefore, gas generated by the first gate insulating layer 112a or the first interlayer insulating layer 113a during the manufacturing process can be easily released to the outside through the plurality of holes in the power conductor PL. Referring to Fig. 3A and Fig. 3B, a plurality of dams are arranged in the first non-active region NA1 in a region adjacent to one end of the substrate 110. Each of the plurality of dams is arranged such that it encloses the active region AA in the first non-active region NA1. The multiple dams can have a first dam DAM1 and a second dam DAM2. The multitude of first dams DAM1 is arranged so that it is adjacent to the active area AA in order to suppress excessive deposition of the second encapsulation layer 117b. The first dam DAM1 shown in Fig. 3A and Fig. 3B can be the outermost dam among the plurality of first dams DAM1, arranged in the outermost perimeter of the substrate 110. Subsequently, the first dam DAM1 can cover, but is not limited to, the ends of the plurality of inorganic insulating layers arranged in the first non-active region NA1. The multitude of first dams DAM1 can have a structure in which a multitude of organic layers, formed from the same material as components arranged in the active area AA, are laminated. For example, each of the multitude of first dams DAM1 can be formed with the same material by the same process as the second planarization layer 115b and the wall 116a, and can be formed by the same process as the spacer 116b, but is not limited to this. Although Fig. 3A and Fig. 3B show that the plurality of first dams DAM1 is configured as one, this is not limited to this, and the number of plurality of dams can be changed if required. With reference to Fig. 3A, Fig. 4A, Fig. 4B and Fig. 5, the first dam DAM1 can be arranged such that its ends are covered or partially covered by one or more of the plurality of inorganic insulating layers, such as the first buffer layer 111, the first and second gate insulating layers 112a and 112b, the first and second intermediate layer insulating layers 113a and 113b, the contact buffer layer 118a or others. For example, a first side of the first dam DAM1 can be arranged on a surface of one of the plurality of inorganic insulating layers, such as the contact buffer layer 118a, and a second side of the first dam DAM1 can be arranged, for example, on a surface of the second substrate 110b, but embodiments of the present disclosure are not limited thereto.In other embodiments of the present disclosure, an outermost first dam DAM1 need not be arranged along an edge of the first non-active region NA1 that abuts the bending region BA along a circumference of the active region AA. In such an embodiment of the present disclosure, the first dam DAM1 may be arranged along the edges of the non-active region NA1 on opposite lateral sides (i.e., left and right sides) and the lower side of the first non-active region NA1, and may not be arranged on the upper side of the first non-active region NA1 (see Fig. 1A and Fig. 1B). In such a case, the upper side of the first non-active region NA1 may include the second dam DAM2 and not the first dam DAM1, but embodiments of the present disclosure are not limited to this.In other embodiments of the present disclosure, the outermost first dam DAM1 can also be arranged on the upper side of the first non-active region NA1, which abuts the bending region BA along the circumference of the active region AA, in addition to the opposite lateral sides (i.e., left and right side) and the lower side of the first non-active region NA1. Referring to Fig. 3A, Fig. 4A, Fig. 4B, and Fig. 5, the second dam DAM2 is arranged to be adjacent to the bending region BA in the first non-active region NA1. For example, the second dam DAM2 can be formed on the same layer with the same material as the third planarization layer 118c. One end of the fourth planarization layer 119 can be located within the second dam DAM2. The fourth planarization layer 119 can be filled into a space between the first dam DAM1 and the second dam DAM2. The second dam DAM2 can be configured to be adjacent to the bending region BA in the first non-active region NA1 to minimize excessive application of the fourth planarization layer 119.Therefore, the second dam DAM2 can minimize faulty operations of components located in the bending area BA and the second non-active area NA2 due to the fourth planarization layer 119. Furthermore, with reference to Fig. 3A and Fig. 3B, one end of the third planarization layer 118c can be located further inward than a point of the first dam DAM1. The fourth planarization layer 119 can also be filled in a space between the end of the third planarization layer 118c and the first dam DAM1. At this stage, with reference to Fig. 3A, Fig. 4A, Fig. 4B, and Fig. 5, the second dam DAM2 can be arranged to be spaced apart from the plurality of inorganic insulating layers whose ends are covered by the first dam DAM1 in the first non-active region NA1. For example, the plurality of inorganic insulating layers can be arranged not beneath the second dam DAM2. Furthermore, at this stage, the fourth planarization layer 119 can be filled into a space between the first dam DAM1 and the second dam DAM2, extending to a distance from the inorganic insulating layer. With reference to Fig. 3A, Fig. 4A, Fig. 4B, Fig. 5 and Fig. 7, the height of the second dam DAM2 can be approximately equal to or equal to the height of the third planarization layer 118c, but embodiments of the present disclosure are not limited thereto. For example, the height of the second dam DAM2 can differ from the height of the third planarization layer 118c. Furthermore, the height of the first dam DAM1 can differ from the height of the second dam DAM2 and / or the height of the third planarization layer 118c. For example, the height of the first dam DAM1 may be less than the height of the second dam DAM2 and / or the height of the third planarization layer 118c, but embodiments of the present disclosure are not limited thereto, and the height of the first dam DAM1 may be equal to or greater than the height of the second dam DAM2 and / or the height of the third planarization layer 118c. However, with reference to Fig. 3A, Fig. 4A, Fig. 4B, Fig. 5 and Fig. 7, an additional inorganic layer 118a-1 can be arranged beneath the second dam DAM2. The additional inorganic layer 118a-1 can be formed with the same material on the same layer as the contact buffer layer 118a. For example, the additional inorganic layer 118a-1 can be deposited on the same layer by the same process as the contact buffer layer 118a and can then be etched to be formed together with the second dam DAM2 in the process of forming the second dam DAM2, but is not limited to this. The additional inorganic layer 118a-1 can be arranged to improve the bond strength to the second dam DAM2. For example, the additional inorganic layer 118a-1 can improve the bond strength between the substrate 110 or the wall unit 116 and the second dam DAM2 to minimize deviation of the second dam DAM2, but is not limited to this. However, with reference to Figures 3A to 5, in the first non-active region NA1 adjacent to the bending region BA, the fourth planarization layer 119 can have different cross-sections in a region where the second dam DAM2 is located and in a region where the second dam DAM2 is not located. For example, as shown in Figures 3A and 3B, in the first non-active region NA1 adjacent to the bending region BA, in a region from which the second dam DAM2 is removed by the trimming process, one end of the fourth planarization layer 119 can be located on the same plane as the end of the substrate 110. Furthermore, the thickness of the fourth planarization layer 119 can decrease towards one end of the fourth planarization layer 119. As shown in Figures 4A, 4B, and 5, the thickness of the fourth planarization layer 119 can decrease.As shown in Figure 5, in the first non-active area NA1 adjacent to the bending area BA in an area from which the second dam DAM2 is not removed by the trimming process, an end of the fourth planarization layer 119 can be located further inwards than the end of the substrate 110. Referring to Figures 3A to 5, a region of layers located outside the ends of the plurality of inorganic insulating layers arranged in the first non-active region NA1 may be exposed. For example, the region of the entire substrate 110 located outside the ends of the plurality of inorganic insulating layers arranged in the first non-active region NA1 may be exposed. In the embodiments shown in Figures 3A to 5, an upper surface of the second substrate 110b between the ends of the plurality of inorganic insulating layers and the second dam DAM2, or a trimmed end of the entire substrate 110 at the predetermined trim line a, is exposed, but is not limited to this, and an upper surface of the first substrate 110a or of the interlayer insulating film 110c may be a section that is exposed. In various embodiments of the present disclosure, the exposed section of the entire substrate 110 between the ends of the plurality of inorganic insulating layers and the second dam DAM2 can be a groove or a recess to accommodate the fourth planarization layer 119, and can vary the depth of the groove or recess in the exposed section of the entire substrate 110 between a bottom of the exposed section of the entire substrate 110 and an upper surface of the fourth planarization layer 119 that overlaps the exposed section of the entire substrate 110.In this respect, a top surface of the second dam DAM2 may be higher than the end of the top surface of the fourth planarization layer 119 contacting the second dam DAM2, and a top surface of the first dam DAM1 may be lower than the top surface of the fourth planarization layer 119 overlapping the exposed section of the entire substrate 110. Referring to Fig. 6 and Fig. 7, the touch detection unit further comprises a plurality of touch detection lines TD and a plurality of touch routing lines TL, which are arranged in the first non-active area NA1. The multitude of touch sensing lines TD is connected to the multitude of touch electrodes TE, which are arranged in the active area AA, and extends to the first non-active area NA1 adjacent to the bending area BA. For example, the multitude of touch sensing lines TD can be formed with the same material on the same layer as the touch sensor electrode TS, which is arranged in the active area AA, but is not limited to it. The multitude of touch routing lines TL can extend to the first non-active area NA1, the bending area BA, and the second non-active area NA2. Each of the multiple touch routing lines TL can be connected to a multiple of touch sensing lines TD in the first non-active area NA1. For example, the multiple of touch routing lines TL can be formed with the same material on the same layer as the secondary electrode AE ​​located in the active area AA, but is not limited to this. The multiple touch detection lines TD and the multiple touch routing lines TL can, for example, be configured to transmit a touch detection signal to and receive a touch driver circuit that controls the touch detection unit. However, with reference to Figs. 6 and 7, the plurality of touch routing lines TL can be arranged such that they overlap the second dam DAM2. For example, the second dam DAM2 can be arranged such that it overlaps the plurality of touch routing lines TL in the first inactive area NA1 adjacent to the bending area BA. At this point, the fourth planarization layer 119 can be filled into a space between the end of the third planarization layer 118c and the second dam DAM2. At this point, with reference to Fig. 7, the third planarization layer 118c is arranged in a region adjacent to the plurality of touch routing lines TL to expose one end of the touch buffer layer 118a. For example, in a region adjacent to the plurality of touch routing lines TL, the third planarization layer 118c can be partially removed to a region that exposes one end of the touch buffer layer 118a. Accordingly, a space between the end of the third planarization layer 118c and the second dam DAM2 can be further extended, and the fourth planarization layer 119 can be further filled into the space between the end of the third planarization layer 118c and the second dam DAM2. However, with reference to Fig. 7, numerous wiring lines VL can also be arranged in the first non-active region NA1 adjacent to the plurality of touch routing lines TL. The wiring line VL can be located further inward than the ends of the plurality of touch sensing lines TD. For example, the wiring line VL can be a power line that provides a low-potential or high-potential voltage to the subpixel SP. The wiring line VL can be formed with the same material on the same layer as, but is not limited to, the source electrodes S1 and S2 and the drain electrodes D1 and D2, which are located in the active region AA. In the display device, a through-hole, shaped to accommodate the camera or photosensor, may be located in the active area. At this point, if the camera or photosensor is positioned in the through-hole, an additional planarization layer, such as an encapsulation layer, may be placed alongside the component to planarize its upper portion. However, if the additional planarization layer is located in the inactive area, the added planarization layer may be excessively applied in an area where the multitude of pads or driver ICs are located, causing faulty operation of these pads or driver ICs. In the display device 100 according to the exemplary embodiment of the present disclosure, the second dam DAM2 is arranged in a region of the first non-active region NA1 adjacent to the bending region BA in order to minimize excessive application of the fourth planarization layer 119. In the display device 100 according to the exemplary embodiment of the present disclosure, the second dam DAM2 is arranged in the first non-active region NA1 in a region adjacent to the bending region BA. The second dam DAM2 can be formed with the same material on the same layer as the third planarization layer 118c, which planarizes an upper section of the plurality of touch electrodes TE. Therefore, the second dam DAM2 can be formed above the touch routing line TL, which is arranged in the first non-active region NA1 adjacent to the bending region BA. Accordingly, the second dam DAM2 can be configured to minimize excessive deposition of the fourth planarization layer, which is arranged on the top layer on the substrate 110.In the display device 100 according to the exemplary embodiment of the present disclosure, the second dam DAM2 is arranged in a region of the first non-active region NA1 adjacent to the bending region BA in order to minimize excessive application of the fourth planarization layer 119. Furthermore, the reliability of the display device can be improved. Exemplary embodiments of the present disclosure can also be described as follows: According to one aspect of the present disclosure, a display device comprises a substrate having an active region, a first non-active region enclosing the active region, a bending region extending from the first non-active region for bending, and a second non-active region extending from the bending region; a plurality of light-emitting diodes arranged on the substrate in the active region; a touch sensing unit arranged above the plurality of light-emitting diodes; a first planarization layer arranged on the touch sensing unit; a first dam arranged in the non-active region such that it encloses the active region; and a second planarization layer arranged on top of the first dam and the first planarization layer.and a second dam arranged along a boundary of the first non-active area and the bending area in the first non-active area, the second dam being formed with the same material on the same layer as the first planarization layer. One end of the second planarization layer can be located within the second dam. In the first non-active area adjacent to the bending area, where the second dam is not located, one end of the second planarization layer may be located on the same plane as one end of the substrate. In the first non-active area, where the second dam is not located, the thickness of the second planarization layer can decrease towards the end of the second planarization layer. The display device may further comprise an encapsulation layer arranged between the plurality of light-emitting diodes and the touch detection unit, a touch buffer layer arranged between the encapsulation layer and the touch detection unit, and an additional inorganic layer arranged under the second dam and formed with the same material on the same layer as the touch buffer layer. The touch detection unit can have a plurality of touch electrodes arranged in the active area, a plurality of touch detection lines extending from the plurality of touch electrodes to the first non-active area adjacent to the bending area, and a plurality of touch routing lines connected to the plurality of touch detection lines in the first non-active area and extending to the bending area and the second non-active area. The multitude of touch routing lines can be arranged in such a way that they overlap with the second dam. In an area adjacent to the multitude of touch routing lines, the first planarization layer can be arranged such that it covers one end of the touch detection line and exposes one end of the touch buffer layer. The second planarization layer can be filled into a space between one end of the first planarization layer and the second dam. The display device can further comprise a plurality of inorganic insulating layers arranged between the substrate and the plurality of light-emitting diodes. In the first non-active area, the multitude of inorganic insulation layers can be arranged further inwards than the second dam and are spaced away from the second dam. In the first non-active area, the ends of the multitude of inorganic insulation layers may be covered by the first dam, and the second planarization layer may be located in a space between the first dam and the second dam. One end of the first planarization layer may be located further inwards than the first dam, and the second planarization layer may also be filled into a space between the end of the first planarization layer and the first dam. According to another aspect of the present disclosure, a display device comprises: a substrate having an active area in which a plurality of subpixels are arranged, a first inactive area enclosing the active area, and a bending area extending from the first inactive area to be bent; a plurality of light-emitting diodes arranged in each of the plurality of subpixels on the substrate; a touch detection unit arranged above the plurality of light-emitting diodes; a first planarization layer arranged on the touch detection unit; a first dam arranged in the inactive area such that it encloses the active area; a second planarization layer arranged on top of the first dam and the first planarization layer;and a second dam arranged along a boundary of the first non-active area and the bending area in the first non-active area, wherein the second dam is arranged on the same layer as the first planarization layer and is formed with the same material as the first planarization layer. One end of the second planarization layer can be located within the second dam. In the first non-active area adjacent to the bending area, where the second dam is not located, the thickness of the second planarization layer can decrease towards one end of the second planarization layer. In the first non-active area, where the second dam is not located, the end of the second planarization layer may be located on the same level as an end of the substrate. The display device may further comprise an encapsulation layer arranged between the plurality of light-emitting diodes and the touch detection unit, a touch buffer layer arranged between the encapsulation layer and the touch detection unit, and an additional inorganic layer arranged under the second dam and formed with the same material on the same layer as the touch buffer layer. The substrate may also have a second non-active area extending from the bending area. The touch detection unit can have a plurality of touch electrodes arranged in the active area and a plurality of touch routing lines electrically connected to the plurality of touch electrodes and extending to the bending area and the second non-active area in the first non-active area. The multitude of touch routing lines can be arranged so that they overlap with the second dam, and in an area adjacent to the multitude of touch routing lines, the first planarization layer can be arranged so that it exposes one end of the touch buffer layer.

Claims

A display device comprising: a substrate (110) with an active area (AA), a first non-active area (NA1) enclosing the active area (AA), a bending area (BA) extending from the first non-active area (NA1) and configured to bend, and a second non-active area (NA2) extending from the bending area (BA); a plurality of light-emitting diodes (LEDs) arranged in the active area (AA) on the substrate (110); a touch sensing unit arranged above the plurality of LEDs (120); a first planarization layer (118c) arranged on the touch sensing unit; a first dam (DAM1) arranged in the first non-active area (NA1) such that it encloses the active area (AA); a second planarization layer (119) arranged on the first dam (DAM1) and the first planarization layer (118c) is ordered;and a second dam (DAM2) located in the first non-active area (NA1) along a boundary between the first non-active area (NA1) and the bending area (BA), wherein the second dam (DAM2) has the same material on the same layer as the first planarization layer (118c). The display device according to claim 1, wherein one end of the second planarization layer (119) is arranged within the second dam (DAM2). The display device according to claim 1 or 2, wherein in the first non-active area (NA1) adjacent to the bending area (BA) in which the second dam (DAM2) is not arranged, an end of the second planarization layer (119) is arranged on the same plane as an end of the substrate (110). The display device according to claim 3, wherein in the first non-active area (NA1) in which the second dam (DAM2) is not arranged, the thickness of the second planarization layer (119) decreases in the direction towards the end of the second planarization layer (119). The display device according to one of claims 1 to 4, further comprising: an encapsulation layer (117a, 117b, 117c) arranged between the plurality of light-emitting diodes (120) and the touch detection unit; a touch buffer layer (118a) arranged between the encapsulation layer (117a, 117b, 117c) and the touch detection unit; and an additional inorganic layer (118a-1) arranged under the second dam (DAM2) and comprising the same material on the same layer as the touch buffer layer (118a). The display device according to claim 5, wherein the touch detection unit comprises: a plurality of touch electrodes (TE) arranged in the active area (AA); a plurality of touch detection lines (TD) extending from the plurality of touch electrodes (TE) to the first non-active area (NA1) adjacent to the bending area (BA); and a plurality of touch routing lines (TL) connected to the plurality of touch detection lines (TD) in the first non-active area (NA1) and extending to the bending area (BA) and the second non-active area (NA2), wherein the plurality of touch routing lines (TL) is arranged such that it overlaps with the second dam (DAM2). The display device according to claim 6, wherein in an area adjacent to the plurality of touch routing lines (TL) the first planarization layer (118c) is arranged such that it covers one end of a touch detection line (TD) of the plurality of touch detection lines (TD) and exposes one end of the touch buffer layer (118a). The display device according to claim 7, wherein the second planarization layer (119) is filled into a space between one end of the first planarization layer (118c) and the second dam (DAM2). The display device according to one of claims 1 to 8, further comprising: a plurality of inorganic insulating layers (111a, 111b, 112a, 113a, 112b, 113b) arranged between the substrate (110) and the plurality of light-emitting diodes (120), wherein in the first non-active area (NA1) the plurality of inorganic insulating layers (111a, 111b, 112a, 113a, 112b, 113b) is arranged further inwards than the second dam (DAM2) and is spaced apart from the second dam (DAM2). The display device according to claim 9, wherein in the first non-active area (NA1) ends of the plurality of inorganic insulating layers (111a, 111b, 112a, 113a, 112b, 113b) are covered by the first dam (DAM1) and the second planarization layer (119) is arranged in a space between the first dam (DAM1) and the second dam (DAM2). The display device according to claim 10, wherein an end of the first planarization layer (118c) is arranged further inwards than the first dam (DAM1) and the second planarization layer (119) is also filled into a space between the end of the first planarization layer (118c) and the first dam (DAM1). A display device comprising: a substrate (110) with an active area (AA), a first non-active area (NA1) adjacent to the active area (AA), a bending area (BA) extending from the first non-active area (NA1) and configured to be bent, and a second non-active area (NA2) extending from the bending area (BA); a plurality of light-emitting diodes (120) arranged in the active area (AA) on the substrate (110); a planarization layer (118c) arranged on the plurality of light-emitting diodes (120) and having a first height; and a dam (DAM2) arranged along a boundary of the first non-active area (NA1) and the bending area (BA) and located in the first non-active area (NA1), wherein the dam (DAM2) has the same material as the planarization layer (118c) and has a second height approximately equal to the first height. The display device according to claim 12, further comprising a further planarization layer (119) arranged on the planarization layer (118c), wherein the dam (DAM2) prevents the further planarization layer (119) from overflowing from the active area (AA) into the bending area (BA). The display device according to claim 13, wherein an upper surface of the substrate (110) is exposed to and contacts the further planarization layer (119).

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