DISPLAY DEVICE AND CONTROL METHOD FOR IT

Abstract

A display device comprises a display panel containing subpixels, a gate driver connected to the subpixels, and a voltage control circuit comprising at least one control transistor controlled based on the operation of the gate driver, each subpixel having a first capacitor having one end connected to a gate electrode of a drive transistor and the other end connected to a first node defined as a second electrode of the drive transistor, and a second capacitor having one end connected to an output terminal of the voltage control circuit and the other end connected to the first node, and which switches on the at least one control transistor based on the operation of the gate driver to apply a reference voltage to the subpixels.

Description

This application claims priority over Korean patent application No. 10-2024-0196942, filed on December 26, 2024, which is incorporated herein in its entirety by reference. BACKGROUND OF THE REVELATION Territory of Revelation The present disclosure relates to a display device and a control method for it. Discussion of the related field With the development of information technology, the market for display devices used to transmit information to users is growing. Accordingly, the use of display devices such as light-emitting displays (LED devices), quantum dot displays (QDD devices), and liquid crystal displays (LCD devices) is increasing. The display devices described above include a display panel containing subpixels, a driver that outputs control signals to control the display panel, and a power supply that generates power to be supplied to the display panel or the driver. The display devices described above can display images by causing selected subpixels to transmit light or emit light directly when control signals such as a scanning signal and a data signal are supplied to the subpixels formed on the display panel. SUMMARY OF THE REVELATION Accordingly, the present disclosure relates to a display device and a method for controlling it, which substantially avoid one or more problems due to limitations and disadvantages of the related field. One objective of the present disclosure is to solve problems (voltage noise and luminance deviation, etc.) caused by a high-voltage level deviation (EVDD deviation due to IR drop) in a display panel by sequentially applying a reference voltage to horizontal lines of the display panel. Another objective of the present disclosure is to simplify a circuit contained in a subpixel and to improve the aperture ratio and lifetime by integrating a circuit for applying a reference voltage to the horizontal lines of the display panel into a sampling signal generator or by arranging the circuit adjacent to the sampling signal generator. Additional advantages, functions, and features of the present disclosure are partly set forth in the following description and partly become apparent to those skilled in the art upon study of the following or can be learned from practical application of the present disclosure. The functions and further advantages of the present disclosure can be realized and achieved through the structure that is shown in particular in the written description and its claims, as well as in the accompanying drawings. To achieve these tasks and further advantages, and in accordance with the purpose of the present disclosure, which is embodied and roughly described herein, a display device comprises a display panel containing subpixels, a gate driver connected to the subpixels, and a voltage control circuit comprising at least one control transistor controlled on the basis of an operation of the gate driver, each of the subpixels having a first capacitor having one end connected to a gate electrode of a drive transistor and the other end connected to a first node defined as a second electrode of the drive transistor, and a second capacitor having one end connected to an output terminal of the voltage control circuit and the other end connected to the first node.contains and which switches on at least one control transistor based on the operation of the gate driver in order to apply a reference voltage to the subpixels. The gate driver can include a first sample generator configured to generate a first sample signal, a second sample generator configured to generate a second sample signal, a third sample generator configured to generate a third sample signal, and a fourth sample generator configured to generate a fourth sample signal, wherein the at least one control transistor is turned on based on an operation of the fourth sample generator to apply the reference voltage to the subpixels. The fourth sampling signal does not need to be applied to the subpixels. The at least one control transistor may include a first control transistor having a gate electrode connected to an output terminal of the fourth sample signal generator, a first electrode connected to a reference voltage line through which the reference voltage is passed, and a second electrode connected to one end of the second capacitor. The first control transistor can be switched on during a period in which the voltage of a Q node of the fourth sampling signal generator is a low voltage. The fourth sampled signal generator may include a first transistor having a gate electrode connected to the Q node, a first electrode connected to a line of low gate voltage, and a second electrode connected to the output terminal; a second transistor having a gate electrode connected to a QB node operating opposite to the Q node, a first electrode connected to a line of high gate voltage, and a second electrode connected to the output terminal; and a node control circuit configured to control the Q node and the QB node. The at least one control transistor can include a first control transistor having a gate electrode connected to the QB node of the gate driver, a first electrode connected to the reference voltage line through which the reference voltage is passed, and a second electrode connected to one end of the second capacitor. The first control transistor can be switched on during a period in which the voltage of the QB node of the fourth sampled signal generator is a low voltage. The reference voltage can be applied sequentially to one end of the second capacitor for a gate line based on the operation of the voltage control circuit. In another aspect of the present disclosure, a method for controlling a display device comprising a display panel containing subpixels, a gate driver connected to the subpixels, and a voltage control circuit comprising at least one control transistor controlled based on the operation of the gate driver, includes an initialization step for initializing nodes of the subpixels, a sampling step for sampling threshold voltages of drive transistors contained in the subpixels, a data voltage write step for applying a data voltage to the subpixels, and an emission step for causing the subpixels to emit light, wherein the voltage control circuit is switched on based on the operation of the gate driver to apply a reference voltage to the subpixels during the initialization step, the sampling step, and the data voltage write step. Each of the subpixels contains a first capacitor having one end connected to a gate electrode of a drive transistor and the other end connected to a first node defined as a second electrode of the drive transistor, and a second capacitor having one end connected to an output terminal of the voltage control circuit and the other end connected to the first node, with the reference voltage applied to one end of the second capacitor. The reference voltage is applied sequentially to one end of the second capacitor for each gate line based on the operation of the voltage control circuit. It is to be understood that both the preceding general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide a further explanation of the present disclosure that is claimed. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a better understanding of the present disclosure and are incorporated into the application as a part thereof, illustrate one or more embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. They show: Fig. 1 a block diagram schematically depicting a display device; Fig. 2 a block diagram showing a configuration of a gate driver in the display device; Fig. 3 an exemplary diagram showing some elements contained in a subpixel and a voltage control circuit that controls an output of a reference voltage according to a first embodiment; Fig. 4 an exemplary diagram showing the voltage control circuit and a shift register that controls the voltage control circuit according to the first embodiment; Fig.5. Drive waveforms of the shift register shown in Fig. 4; Fig. 6. A circuit configuration diagram of a subpixel according to a second embodiment; Fig. 7. Drive waveforms of the subpixel shown in Fig. 6; Fig. 8. An exemplary diagram showing a voltage control circuit and a shift register controlling the voltage control circuit according to the second embodiment; Fig. 9. Drive waveforms of the shift register shown in Fig. 8; Figs. 10 and 11. Diagrams showing operating states of the voltage control circuit and the shift register according to the drive waveforms of Fig. 8; Fig. 12. An exemplary diagram showing a voltage control circuit and a shift register controlling the voltage control circuit according to a third embodiment; Fig. 13. Drive waveforms of the shift register shown in Fig. 12; and Figs. 14 and 15.15 diagrams showing the operating states of the voltage control circuit and the shift register according to the control waveforms of Fig. 13. DETAILED DESCRIPTION OF THE REVELATION A display device according to the present disclosure can be implemented as a light-emitting display device (LED device), a quantum dot display device (QDD device), or the like. However, for the sake of simplicity, a light-emitting display device that directly emits light based on inorganic or organic light-emitting diodes is used below as an example of the display device. Additionally, a light-emitting indicator device, described below, can be implemented using an n-type thin-film transistor, a p-type thin-film transistor, or a combination of n-type and p-type thin-film transistors. A thin-film transistor is a three-electrode device containing a gate, a source, and a drain. The source is an electrode that supplies charge carriers to the transistor. In the thin-film transistor, charge carriers begin to flow from the source. The drain is an electrode through which charge carriers are discharged from the thin-film transistor. In other words, charge carriers flow from the source to the drain in the thin-film transistor. In the case of a p-type thin-film transistor, the charge carriers are holes, and therefore the source voltage is greater than the drain voltage, allowing the holes to flow from the source to the drain. Since the holes in a p-type thin-film transistor flow from the source to the drain, the current flows from the source to the drain. Conversely, in the case of an n-type thin-film transistor, the charge carriers are electrons, and therefore the source voltage is less than the drain voltage, allowing the electrons to flow from the source to the drain. Since the electrons in an n-type thin-film transistor flow from the source to the drain, the current flows from the drain to the source. However, the source and drain positions of the thin-film transistor can be changed depending on the applied voltage.Taking this into account, in the following description one of the source and drain is described as a first electrode and the other of the source and drain is described as a second electrode. Fig. 1 is a block diagram schematically showing a display device. Fig. 2 is a block diagram showing a configuration of a gate driver in the display device. As shown in Fig. 1, the display device 10 can include a display panel 100 containing several subpixels P, a control unit 200, a gate driver 300 that supplies a gate signal to the several subpixels P, a data driver 400 that supplies a data signal (or a data voltage) to the several subpixels P, and a power supply 500 that supplies power to the several subpixels P. The display panel 100 can include an active area (see AA in Fig. 2) in which the multiple subpixels P are arranged, and a non-active area (see NA in Fig. 2) which is arranged to surround the active area AA and includes the gate driver 300 and the data driver 400, which are arranged in it. In the display panel 100, several gate lines GL and several data lines DL intersect, with the several subpixels P being able to be connected to the gate lines GL and the data lines DL. Specifically, a subpixel P can receive a gate signal from the gate driver 300 via a gate line GL, receive a data voltage (a data signal) from the data driver 400 via a data line DL, and receive a high-level voltage EVDD and a low-level voltage EVSS from the power supply 500. The gate lines GL can transmit a sampling signal SC and an emission control signal EM to the multiple subpixels P, and the data lines DL can transmit a data voltage Vdata to the multiple subpixels P. According to various embodiments, the gate lines GL can contain multiple sampling lines SCL for supplying the sampling signal SC and multiple emission control lines EML for supplying the emission control signal EM. The multiple subpixels P can receive voltages Vref and Var from multiple voltage lines VL. The voltages Vref and Var applied by the multiple voltage lines VL are described below. Each of the multiple subpixels P can contain a subpixel driver circuit. The subpixel driver circuit can contain several switching elements, a driver element, a capacitor, etc. The switching elements and the driver element can be configured as thin-film transistors. A switching transistor can be activated according to a sampling signal SC supplied via a sampling line SCL and an emission control signal EM supplied via an emission control line EML. A driver transistor can control the amount of current supplied to a light-emitting element OLED according to a data voltage Vdata (emission level control). The scoreboard 100 can be implemented as a non-transparent or a translucent scoreboard. The translucent scoreboard can be applied to a transparent display device, where an image is displayed on a screen and an actual object is visible in the background. The scoreboard 100 can also be implemented as a flexible scoreboard. The flexible scoreboard can use a plastic substrate. The multiple subpixels P can be subdivided into a red subpixel, a green subpixel, and a blue subpixel for color expression. The multiple subpixels P can further include a white subpixel. Touch sensors can be arranged on the display panel 100. A touch input can be detected using separate touch sensors or can be detected by the multiple subpixels P. The touch sensors can be implemented as surface-mounted or supplementary touch sensors and arranged on the display panel screen, or they can be implemented as in-cell touch sensors built into the display panel 100. The control unit 200 can process externally inputted RGB image data such that the RGB image data is suitable for the size and resolution of the display panel 100 and feed it to the data driver 400. The control unit 200 can generate a gate control signal GCS and a data control signal DCS using externally input synchronization signals, such as a clock signal CLK, a data activation signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. The control unit 200 can control the operating timing of the gate driver 300 by supplying the gate control signal GCS to the gate driver 300. The control unit 200 can control the operating timing of the data driver 400 by supplying the data control signal DCS to the data driver 400.The control unit 200 can synchronize the operating timing of the gate driver 300 with the operating timing of the data driver 400 using the gate control signal GCS and the data control signal DCS. The Control Unit 200 can be configured by combining it with various processors, such as a microprocessor, a mobile processor, or an application processor, depending on the device to be mounted in the display unit. A host system located in front of the Control Unit 200 can be a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a portable device, or a vehicle system. The control unit 200 can multiply an input frame rate by i and control the operating timing of a display driver at a frame rate of input frame rate × i Hz (where i is a positive integer greater than 0). The input frame rate can be 60 Hz in the case of NTSC (National Television Standards Committee) and 50 Hz in the case of PAL (Phase-Alternating Line). The control unit 200 can control the display board 100 at different update rates. The control unit 200 can control the display board 100 in a variable update rate mode (VRR mode), i.e., in a mode in which the display board 100 can be switched between a first update rate and a second update rate. For example, the control unit 200 can control the display panel 100 by simply changing the rate of a clock signal, configuring a synchronization signal to generate a horizontal or vertical output period, or controlling the gate driver 300 in a mask-like fashion at different update rates. The vertical output period can be defined as a period for aligning the time of input of a data signal and the time of output (display) of an image on the display panel. The vertical output period can be repeated in a frame cycle, and various signals for the operation of the display device can be synchronized during this period. The voltage level of the gate control signal GCS, output by the control unit 200, can be converted by a level shifter (not shown) into low gate voltages VGL and VEL and high gate voltages VGH and VEH, and fed to the gate driver 300. The level shifter can convert a low-level voltage of the gate control signal GCS into the low gate voltages VGL and VEL, and vice versa. The gate control signal GCS can contain a start pulse and a switching clock. The gate driver 300 can supply a gate signal to the gate line GL according to the gate control signal GCS supplied by the control unit 200. The gate driver 300 can be arranged on one or both sides of the display panel 100 in a gate-in-panel configuration. The Gate Driver 300 can sequentially output a gate signal to multiple gate lines GL under the control of the Control Unit 200. The Gate Driver 300 can shift the gate signal using a shift register to sequentially feed the signal to the gate lines GL. Gate signals in an organic light-emitting display device can include a sampling signal SC and an emission control signal EM. The sampling signal SC can contain a sampling pulse oscillating between a first low gate voltage VGL and a first high gate voltage VGH. The emission control signal EM can contain an emission control signal pulse oscillating between a second low gate voltage VEL and a second high gate voltage VEH. The sampling pulse can be used to select subpixels P of a line onto which a data voltage Vdata is to be written. The emission control signal EM can define an emission time for the subpixels P. The gate driver 300 can include an emission control signal driver 310 and at least one sampling driver 320. The emission control signal driver 310 can output an emission control signal pulse in response to a start pulse and a switching clock from the control unit 200 and sequentially shift the emission control signal pulse according to the switching clock. The at least one sampling driver 320 can output a sampling pulse in response to the start pulse and the switching clock from the control unit 200 and shift the sampling pulse according to the switching clock timing. The data driver 400 can convert RGB image data according to the data control signal DCS, which is supplied by the control unit 200, into a data voltage Vdata and output this via the data line DL. Although Fig. 1 illustrates that the data driver 400 is arranged on one side of the display panel 100, the number and positions of the data drivers 400 are not limited to this. That is, the data driver 400 can be configured as multiple integrated circuits (ICs) and arranged in separate positions on one side of the display panel 100. The Power Supply 500 can generate the DC power required to drive the subpixel array of the Display Panel 100 and the display panel driver using a DC-to-DC converter. The DC-to-DC converter can include a charge pump, a regulator, a step-down converter, and a step-up converter. The Power Supply 500 can receive a DC input voltage applied by a host system (not shown) and generate various types of DC voltages, including VGL / VEL, VGH / VEH, EVDD, and EVSS. As shown in Fig. 1 and Fig. 2, the gate driver 300 can include the emission control signal driver 310 and the sampler driver 320. The sampler driver 320 can include first to fourth samplers 321, 322, 323, and 324. The first sampler driver 321 can include an odd-numbered first sampler driver 321_O and an even-numbered first sampler driver 321_E. The emission control signal driver 310 can include a first emission control signal driver 311 and a second emission control signal driver 312. The shift registers forming the gate driver 300 can be configured to be symmetrical on both sides of the active region AA. The shift register on one side can contain the first sample drivers 321_O and 321_E, the second sample driver 322, and the third sample driver 323, and the shift register on the other side can contain the fourth sample driver 324, the first emission control signal driver 311, and the second emission control signal driver 312. Meanwhile, in Fig. 2, the odd-numbered first sampler 321_O and the even-numbered first sampler 321_E are examples of a case where an odd-numbered subpixel and an even-numbered subpixel share the first sampler 321. Accordingly, the drivers contained in the gate driver 300 can be arranged differently and are not limited to this. The stages STG1 to STGn of the shift register can each contain first sampling signal generators SC1_O(1) to SC1_O(n) and SC1_E(1) to SC1_E(n), second sampling signal generators SC2(1) to SC2(n), third sampling signal generators SC3(1) to SC3(n), fourth sampling signal generators SC4(1) to SC4(n), first emission control signal generators EM1(1) to EM1(n) and second emission control signal generators EM2(1) to EM2(n). The first sampling signal generators SC1(1) to SC1(n) can output first sampling signals SC1(1) to SC1(n) via the first sampling lines SC1 of display panel 100. The second sampling signal generators SC2(1) to SC2(n) can output second sampling signals SC2(1) to SC2(n) via the second sampling lines SC2 of display panel 100. The third sampling signal generators SC3(1) to SC3(n) can output third sampling signals SC3(1) to SC3(n) via the third sampling line SC3 of display panel 100. The fourth sampling signal generators SC4(1) to SC4(n) can output fourth sampling signals SC4(1) to SC4(n) via a line connected to a voltage control circuit (described below). The first emission control signal generators EM1(1) to EM1(n) can output first emission control signals EM1(1) to EM1(n) via first emission control lines EM1 of the display panel 100.The second emission control signal generators EM2(1) to EM2(n) can output second emission control signals EM2(1) to EM2(n) via second emission control lines EM2 of the display panel 100. A reference voltage line VrefL, through which a reference voltage Vref is passed, and an initialization voltage line VaraL, through which an initialization voltage Var is passed, can be arranged between the gate driver 300 and the active area AA. In the drawing, the reference voltage line VrefL and the initialization voltage line VaraL are illustrated as being located on the left and right sides of the active area AA, respectively, but this is not the only possible arrangement. One or more optical areas OA1 and OA2 can be arranged within the active area AA. The optical areas OA1 and OA2 can be arranged to overlap with one or more optical electronic devices, such as an imaging device like a camera (an image sensor) and a detection sensor like a proximity sensor or an illuminance sensor. The optical areas OA1 and OA2 can have a transmissive structure formed within them to provide a transmission level of a certain degree or more for the operation of the optical electronic devices. In other words, the number of subpixels P per unit area in the optical areas OA1 and OA2 can be less than the number of subpixels P per unit area in a general area, excluding optical areas OA1 and OA2 within the active area AA.In other words, the resolution of the optical areas OA1 and OA2 can be smaller than the resolution of the general area in the active area AA. In optical regions OA1 and OA2, the translucent structure can be formed by patterning on a cathode in an area where the subpixels P are not located. Currently, the cathode to be patterned can be removed using a laser, or the cathode can be selectively formed and patterned using a material such as an anti-deposition layer. Additionally, the translucent structure in optical areas OA1 and OA2 can be formed by separately creating a light-emitting element and a subpixel driver circuit contained within subpixel P. In other words, the light-emitting element of subpixel P can be positioned on optical areas OA1 and OA2, several transistors forming the subpixel driver circuit can be arranged around optical areas OA1 and OA2, and the light-emitting element and the subpixel driver circuit can be electrically connected by a transparent metal layer. Fig. 3 is an exemplary diagram showing some elements contained in a subpixel and a voltage control circuit that controls an output of the reference voltage according to a first embodiment. Fig. 4 is an exemplary diagram showing the voltage control circuit and a shift register that controls the voltage control circuit according to the first embodiment. Fig. 5 shows drive waveforms of the shift register shown in Fig. 4. As shown in Fig. 3, an N-th subpixel P(n) according to the first embodiment can contain a first transistor T1, a switching transistor T5, a first capacitor CST, a second capacitor CA and a light-emitting element OLED. The first transistor, T1, can be implemented as an n-type transistor. This first n-type transistor, T1, operates based on a data voltage applied as a high voltage and can generate a drive current that is supplied to the light-emitting element, the OLED. The first transistor, T1, can be defined as a drive transistor. The switching transistor T5 can be implemented as a p-type transistor. Switching of the p-type transistor T5 is based on the first emission control signal EM1, which is applied as a low voltage, and can pass a high-level voltage EVDD to the first transistor T1. The switching transistor T5 can be defined as an emission control transistor. The first capacitor, CST, can store a data voltage to be applied to the gate electrode of the first transistor, T1. The second capacitor, CA, can store a reference voltage to uniformly balance the data voltage stored in the first capacitor, CST, across the entire display panel (or across all subpixels). The light-emitting element, OLED, can emit light in response to the drive current generated by the operation of the first transistor, T1, and the switching transistor, T5. As described above, the Nth subpixel P(n) can be implemented using two types of transistors and can further include a circuit for balancing the first transistor T1 or the light-emitting element OLED. Therefore, the circuit contained in the Nth subpixel P(n) can be implemented in various ways, and thus Fig. 3 should be considered an example. The Nth subpixel P(n) can be connected to an Nth voltage control circuit VrefC(n) that controls the output of the reference voltage (controls whether the reference voltage is applied). The Nth voltage control circuit VrefC(n) can include an Nth control transistor TC(n) that is switched on or off such that the reference voltage, passed through the reference voltage line VrefL, is applied to the subpixel P or not. The reference voltage can be applied to sample the threshold voltage of the first transistor T1. The Nth control transistor TC(n) is illustrated as an example implementation of a p-type transistor, but it can also be implemented as an n-type transistor. The Nth control transistor TC(n) can have a gate electrode connected to an Nth control sampling line CS(n), to which an Nth control sampling signal is applied, a first electrode connected to the reference voltage line VrefL, through which the reference voltage is passed, and a second electrode connected to one end of the second capacitor CA contained in the Nth subpixel P. In other words, an output terminal of the Nth voltage control circuit VrefC(n) can be connected to one end of the second capacitor CA contained in the Nth subpixel P. Meanwhile, the voltage control circuit, which includes the Nth voltage control circuit VrefC(n), can be arranged for each gate line to apply the reference voltage to each subpixel for each horizontal line. Therefore, n in the Nth voltage control circuit VrefC(n) and the Nth control transistor TC(n) can be any number, and the arbitrary number n can increase or decrease by at least 1 with respect to the gate line to which the Nth subpixel P(n) is connected. For the sake of simplicity, the term "Nth" will be omitted in the following description, and a component will be described as a single unit. As illustrated in Fig. 4, the voltage control circuit VrefC(n) according to the first embodiment can be connected to the fourth sample signal generator SC4(n), which is contained in the shift register. The voltage control circuit VrefC(n) can be switched on or off based on a fourth sample signal output from the fourth sample signal generator SC4(n). For this purpose, the gate electrode of the control transistor TC(n), which is contained in the voltage control circuit VrefC(n), can be connected to the output terminal of the fourth sample signal generator SC4(n). The fourth sample signal, which is output from the output terminal of the fourth sample signal generator SC4(n), is a signal for controlling the voltage control circuit VrefC(n) and can only be applied to the voltage control circuit VrefC(n). That is, the fourth sample signal does not have to be applied to the subpixel P. The fourth sampling signal generator SC4(n) can include a first sampling transistor T1 through a sixth sampling transistor T6, a balancing transistor TA, a first sampling capacitor CB, a second sampling capacitor CQB, and a third sampling capacitor CO. An example is described below in which the first sampling transistor T1 through the sixth sampling transistor T6 are implemented as p-type transistors, but the present disclosure is not limited thereto. The first sampling transistor T1 can have a gate electrode connected to a Q node Q, a first electrode connected to a low-gate voltage line VGL, and a second electrode connected to the output terminal. The first sampling transistor T1 can be turned on based on the voltage of the Q node Q and can output the fourth sample signal at a low voltage based on a low-gate voltage applied via the low-gate voltage line VGL. The first sampling transistor T1 can be defined as a first output transistor. The first sampling capacitor CB can have a first electrode connected to the Q node Q and a second electrode connected to the output terminal. The first sampling capacitor CB can serve to maintain a stable voltage across the Q node Q. The second sampling transistor T2 can have a gate electrode connected to a QB node QB, a first electrode connected to a high gate voltage line VGH, and a second electrode connected to the output terminal. The second sampling transistor T2 can be turned on based on the voltage of the QB node QB and can output the fourth sample signal at a high voltage based on a high gate voltage applied via the high gate voltage line VGH. The second sampling transistor T2 can also be defined as a second output transistor. The second sampling capacitor CQB can have a first electrode connected to the QB node and a second electrode connected to the output terminal. The second sampling capacitor CQB can serve to maintain a stable voltage across the QB node. The third sampling transistor T3 can have a gate electrode connected to a clock signal line GCLK, a first electrode connected to a start signal line VST (a carry output terminal CRY or an output terminal of the preceding stage), and a second electrode connected to a Q2 node Q2. The third sampling transistor T3 can be turned on based on a clock signal applied via the clock signal line GCLK to pass a start signal applied via the start signal line VST to the Q2 node Q2. The fourth sampling transistor T4 can have a gate electrode connected to the clock signal line GCLK, a first electrode connected to a high gate voltage line VGH, and a second electrode connected to a Q3 node. The fourth sampling transistor T4 is switched on based on the clock signal applied via the clock signal line GCLK to pass the high gate voltage, applied via the high gate voltage line VGH, to the Q3 node Q3. The fifth sampling transistor T5 can have a gate electrode connected to node Q3, a first electrode connected to the clock signal line GCLK, and a second electrode connected to node QB. The fifth sampling transistor T5 is switched on based on the voltage at node Q3 to pass the clock signal, applied via the clock signal line GCLK, to node QB. The third sampling capacitor CO can have a first electrode connected to the clock signal line GCLK and a second electrode connected to the Q3 node Q3. The third sampling capacitor CO can be used to maintain a stable voltage at the Q3 node Q3. The sixth sampling transistor T6 can have a gate electrode connected to the Q2 node Q2, a first electrode connected to the high gate voltage line VGH, and a second electrode connected to the QB node QB. The sixth sampling transistor T6 can be turned on based on the voltage at the Q2 node Q2 to pass the high gate voltage applied via the high gate voltage line VGH to the QB node QB. The balancing transistor TA can have one gate electrode connected to a low gate voltage (VGL) line, a first electrode connected to node Q2, and a second electrode connected to node Q. The balancing transistor TA can be switched on based on the low gate voltage and can serve to electrically stabilize node Q2 and node Q. Meanwhile, in the fourth sampling signal generator SC4(n), the third sampling transistor T3 to the sixth sampling transistor T6, with the exception of the first sampling transistor T1 and the second sampling transistor T2, which are defined as output transistors, and the balancing transistor TA, can define a node control circuit that controls the Q node Q, the Q2 node Q2, the Q3 node Q3 and the QB node QB. As illustrated in Fig. 4 and Fig. 5, the fourth sampling signal generator SC4(n) according to the first embodiment can start operation on the basis of a fourth clock signal GCLK4 at a low voltage, which is generated at the same time as the start signal GVST is applied at a low voltage. When the third sampling transistor T3 is switched on at a low voltage based on the fourth clock signal GCLK4, the voltage Q-node of Q node Q reaches a low voltage. At this point, since the sixth sampling transistor T6 is switched on at the low voltage Q-node of Q node Q, the voltage QB-node of QB node QB reaches a high voltage. When the Q-node voltage of Q node Q is low, the first sampling transistor T1 can be switched on. Since the QB-node voltage of QB node QB is high, the second sampling transistor T2 can be switched off. The fourth sampling signal generator SC4(n) can output the fourth sample signal via the output terminal through the switched-on first sampling transistor T1 when the voltage is low. The control transistor TC(n), contained in the voltage control circuit VrefC(n), can be switched on based on the fourth sample signal at a low voltage, which is output via the output terminal of the fourth sample signal generator SC4(n). When the control transistor TC(n) is switched on, the reference voltage Vref_out, applied via the reference voltage line VrefL, can be output via a reference voltage output terminal Vref_out(n). As can be seen in a reference voltage output period VARD of Fig. 5, the period in which the voltage Q-node of Q-node Q is a low voltage and the period in which the reference voltage Vref_out is output in response to it can occur simultaneously. The voltage control circuit VrefC(n) according to the present disclosure can be applied to various subpixels that require a reference voltage, and only a section of the circuit contained in subpixel P is as illustrated above. However, examples of subpixels to which the voltage control circuit VrefC(n) according to the present disclosure can be applied are as follows. Fig. 6 is a circuit diagram of a subpixel according to a second embodiment and Fig. 7 shows drive waveforms of the subpixel illustrated in Fig. 6. As illustrated in Fig. 6, the subpixel P according to the second embodiment can contain a first transistor T1 to a sixth transistor T6, a first capacitor CST, a second capacitor CA, and a light-emitting element OLED. The first transistor T1 to the fourth transistor T4 and the sixth transistor T6 can be implemented as n-type transistors, and the fifth transistor T5 can be implemented as a p-type transistor; however, the present disclosure is not limited thereto. The first transistor T1 can have a gate electrode connected to a second node N2, a first electrode connected to a third node N3, and a second electrode connected to a first node N1. The first transistor T1 operates based on a data voltage stored in the first capacitor CST and can generate a drive current. The first transistor T1 can be defined as a drive transistor. The second transistor T2 can have a gate electrode connected to a first sampling line SC1, a first electrode connected to a data line DL, and a second electrode connected to the second node N2. The second transistor T2 can be switched on based on a first sampling signal applied via the first sampling line SC1, in order to pass a data voltage applied via the data line DL to the second node N2. The third transistor T3 can have a gate electrode connected to a second sampling line SC2, a first electrode connected to a reference voltage line VrefL, and a second electrode connected to the second node N2. The third transistor T3 can be switched on based on a second sampling signal applied via the second sampling line SC2, in order to pass a reference voltage applied via the reference voltage line VrefL to the second node N2. The fourth transistor T4 can have a gate electrode connected to a third sampling line SC3, a first electrode connected to an initialization voltage line VaraL, and a second electrode connected to a fourth node N4. The fourth transistor T4 can be switched on based on a third sampling signal applied via the third sampling line SC3, in order to pass an initialization voltage applied via the initialization voltage line VaraL to the fourth node N4. The fifth transistor T5 can have a gate electrode connected to a first emission control line EM1, a first electrode connected to a high-level voltage line EVDD, and a second electrode connected to the third node N3. The fifth transistor T5 can be switched on based on a first emission control signal applied via the first emission control line EM1, in order to pass a high-level voltage applied via the high-level voltage line EVDD to the third node N3. The sixth transistor T6 can have a gate electrode connected to a second emission control line EM2, a first electrode connected to the first node N1, and a second electrode connected to the fourth node N4. The sixth transistor T6 can be switched on based on a second emission control signal applied via the second emission control line EM2 to pass a drive current generated by the first transistor T1 to the fourth node N4. The first capacitor CST can have a first electrode connected to the second node N2 and a second electrode connected to the first node N1. The first capacitor CST can store a data voltage applied by the second transistor T2. The data voltage stored in the first capacitor CST can be applied to the gate electrode of the first transistor T1. The second capacitor CA can have a first electrode connected to the first node N1 and a second electrode connected to a fifth node N5. The second capacitor CA can store a reference voltage applied across the fifth node N5. This reference voltage can be applied to the first node N1. The reference voltage stored in the second capacitor CA can be used to uniformly (symmetrically) equalize the data voltage stored in the first capacitor CST across the entire display panel (or across all subpixels). The OLED light-emitting element can have an anode connected to the fourth node N4 and a cathode connected to a low-level voltage line EVSS. The OLED can emit light based on the drive current passed through the sixth transistor T6. A parasitic capacitor CO can be present between the anode and cathode of the OLED. As illustrated in Fig. 6 and Fig. 7, the subpixel P according to the second embodiment can operate in the sequence of an initialization period INIT, a sampling period SAMP, a data write period WRT and an emission period EMI. The initialization period (INIT) can be defined as the period for initializing the first node N1 and the fourth node N4 of subpixel P. The sampling period (SAMP) can be defined as the period for sampling the threshold voltage of the first transistor (the driver transistor) T1 of subpixel P. The data write period (WRT) can be defined as the period for applying a data voltage to the first capacitor CST of subpixel P. The emission period (EMI) can be defined as the period for causing the light-emitting element OLED of subpixel P to emit light. The first sampling signal, SC1, can be generated as a high voltage during the WRT data write period and then maintained as a low voltage. The second sampling signal, SC2, can be generated as a high voltage during the INIT and SAMP sampling periods and then maintained as a low voltage. The third sampling signal, SC3, can be generated as a high voltage during the INIT, SAMP, WRT, and EMI emission periods and then maintained as a low voltage. The first emission control signal, EM1, can be generated as a high voltage during the initialization period (INIT), the data write period (WRT), and the emission period (EMI), and as a low voltage during the sampling period (SAMP). The second emission control signal, EM2, can be generated as a high voltage during the initialization period (INIT) and the emission period (EMI), and as a low voltage during the data write period (WRT) and the sampling period (SAMP). The reference voltage, Vref, can be applied during the initialization period (INIT), the sampling period (SAMP), and the data write period (WRT). Fig. 7 illustrates an example in which, with reference to the description of Fig. 2, the odd-numbered first sampler 321_O outputs an odd-numbered first sampler signal SC1(1) to be applied to an odd-numbered subpixel, and the even-numbered first sampler 321_E outputs an even-numbered first sampler signal SC1(2) to be applied to an even-numbered subpixel. Except for the first scanning drivers 321_O and 321_E, the remaining drivers can apply a common scanning and emission signal without distinguishing between odd and even-numbered subpixels. Additionally, depending on the control method of the display panel 100, the first scanning drivers 321_O and 321_E can output a common scanning signal without distinguishing between odd and even-numbered subpixels. Therefore, taking this into account, Fig. 7 illustrates that signals applied jointly, without distinguishing between odd and even subpixels, are specified as "SC2(1,2), EM1(1,2), EM2(1,2) and SC3(1,2)". It is also mentioned that the reference voltage is applied based on the sampling method, but is applied jointly without distinguishing between odd and even subpixels, and is therefore specified as "Vref(1,2)". Meanwhile, according to the second embodiment, the subpixel P can receive the reference voltage Vref via the second node N2 and the fifth node N5 during the initialization period INIT, the sampling period SAMP, and the data write period WRT. Since the reference voltage Vref is applied to sample the threshold voltage of the first transistor T1, which is defined as a drive transistor, it can affect image quality if a deviation is induced for each horizontal line (or subpixel). Therefore, the reference voltage Vref can be applied, while controlled by a voltage control circuit, which will be described below, to be applied uniformly to the subpixels P arranged on the display panel. Fig. 8 is an exemplary diagram showing a voltage control circuit and a shift register for controlling it according to the second embodiment, Fig. 9 shows control waveforms of the shift register shown in Fig. 8, and Figs. 10 and 11 are diagrams showing operating states of the voltage control circuit and the shift register according to the control waveforms of Fig. 8. As shown in Fig. 8, according to the second embodiment, a fourth sampling signal generator SC4(n), which is contained in the shift register, is the same as the one described in the first embodiment of Fig. 4. Therefore, the description will focus on the voltage control circuit VrefC(n), which contains various sections from the first embodiment of Fig. 4. According to the second embodiment, the voltage control circuit VrefC(n) can include a first control transistor T7 and a second control transistor T8. The first control transistor T7 and the second control transistor T8 can be implemented as p-type transistors, but are not limited to this. The first control transistor T7 can have a gate electrode connected to an output terminal of the fourth sampled signal generator SC4(n), a first electrode connected to a reference voltage line VrefL, and a second electrode connected to a reference voltage output terminal Vref_out(n). The first control transistor T7 can be turned on based on a fourth sampled signal at a low voltage, output via the output terminal of the fourth sampled signal generator SC4(n), and can output a reference voltage via the reference voltage output terminal Vref_out(n).The reference voltage can have a voltage level, e.g., in the range of 1 V to 2 V. The second control transistor T8 can have a gate electrode connected to a QB node QB of the fourth sampled signal generator SC4(n), a first electrode connected to a compensating voltage line CVL, and a second electrode connected to the reference voltage output terminal Vref_out(n). The second control transistor T8 can be switched on based on the voltage of the QB node QB of the fourth sampled signal generator SC4(n) and can output a compensating voltage via the reference voltage output terminal Vref_out(n). Meanwhile, Fig. 8 illustrates an example where the first electrode of the second control transistor T8 is connected to the balancing voltage line CVL. Here, the balancing voltage can have a level lower than, for example, the lowest level of the reference voltage, 1 V, and will not affect image quality when the subpixel SP emits light. Additionally, the first electrode of the second control transistor T8 can be set to an electrically floating potential (or can be in a state where no voltage is applied to it) without being connected to the balancing voltage line CVL. As illustrated in Figures 9 and 10, a fourth clock signal CLK4 at a low voltage and a start signal GVST at a low voltage can be applied to the fourth sampler SC4(n) during a first period. The third sampler T3, the fourth sampler T4, the balancing transistor TA, the sixth sampler T6, and the first sampler T1 of the fourth sampler SC4(n) can be switched on during the first period. The fourth sampler SC4(n) can output a fourth sample at a low voltage via the output terminal based on the first sampler T1 being switched on. During the first period, the voltage control circuit VrefC(n) can output the reference voltage via the reference voltage output terminal Vref_out(n) based on the first control transistor T7 being switched on. As illustrated in Figures 9 and 11, the fourth clock signal CLK4 at a low voltage and the start signal GVST at a high voltage can be applied to the fourth sampler SC4(n) during a second period. The third sampler T3, the fifth sampler T5, the balancing transistor TA, and the second sampler T2 of the fourth sampler SC4(n) can be switched on during the second period. The fourth sampler SC4(n) can output the fourth sample at a high voltage via the output terminal based on the second sampler T2 being switched on. The first sampler T1 can be switched off during the second period due to the fourth sample at a high voltage.On the other hand, the voltage control circuit VrefC(n) can output a balancing voltage via the reference voltage output terminal Vref_out(n) or, based on the second control transistor T8, which is switched on by the low voltage of the QB node QB, it can output no voltage. As described above, the reference voltage can be applied sequentially to the horizontal lines of the display panel based on the voltage control circuit VrefC(n) and the fourth sample signal generator SC4(n), which is contained in the shift register. Additionally, applying the reference voltage sequentially to the horizontal lines of the display panel minimizes the line load and allows for stable voltage transmission, thus resolving problems (such as voltage noise and brightness deviation) caused by high-voltage level deviation (EVDD deviation due to IR drop-off) in the display panel. Furthermore, integrating the voltage control circuit VrefC(n) into or placing it adjacent to the fourth sample signal generator SC4(n) simplifies the subpixel circuitry, thereby improving the aperture ratio and lifetime. Fig. 12 is an exemplary diagram showing a voltage control circuit and a shift register that controls it, according to a third embodiment; Fig. 13 shows control waveforms of the shift register shown in Fig. 12; and Figs. 14 and 15 are diagrams showing operating states of the voltage control circuit and the shift register according to the control waveforms of Fig. 13. As illustrated in Fig. 12, according to the third embodiment, the fourth sampling signal generator SC4(n), which is contained in the shift register, can include a first sampling transistor T1 up to a seventh sampling transistor T7 and a first capacitor CQ. An example is described below in which the first sampling transistor T1, the second sampling transistor T2, the fourth sampling transistor T4, the sixth sampling transistor T6, and the seventh sampling transistor T7 are implemented as p-type transistors, and the third sampling transistor T3 and the fifth sampling transistor T5 are implemented as n-type transistors; however, the present disclosure is not limited thereto. The first sampling transistor T1 can have a gate electrode connected to a Q node Q, a first electrode connected to a gate voltage line VGL, and a second electrode connected to the output terminal. The first sampling transistor T1 can be turned on based on the voltage of the Q node Q and output a fourth sample signal at a low voltage based on a low gate voltage applied via a compensating voltage line CVL. The first sampling transistor T1 can be defined as a first output transistor. The first capacitor CQ can have a first electrode connected to the Q node Q and a second electrode connected to the output terminal. The first capacitor CQ can serve to maintain a stable voltage across the Q node Q. The second sampling transistor T2 can have a gate electrode connected to a QB node QB, a first electrode connected to a high gate voltage line VGH, and a second electrode connected to the output terminal. The second sampling transistor T2 is turned on based on the voltage of the QB node QB and can output the fourth sample signal at a high voltage based on a high gate voltage applied via the high gate voltage line VGH. The second sampling transistor T2 can be defined as a second output transistor. The third sampling transistor T3 can have a gate electrode connected to the QB node QB, a first and second gate electrode (or body electrode) connected to the first electrode of the first sampling transistor T1, and a second electrode connected to the second electrode of the first sampling transistor T1. The third sampling transistor T3 can be switched on during a period when the voltage at the QB node QB is high, in order to pass a low gate voltage to the output terminal. The third sampling transistor T3 can also serve to maintain or compensate for the output such that the fourth sample signal is stably output at a low voltage across the output terminal. The fourth sampling transistor T4 can have a gate electrode connected to the gate voltage line VGL, a first electrode connected to a Q2 node Q2, and a second electrode connected to the Q node Q. The fourth sampling transistor T4 can be switched on based on the low gate voltage applied via the gate voltage line VGL and can serve to electrically stabilize the Q2 node Q2 and the Q node Q. The fifth sampling transistor T5 can have a gate electrode connected to the Q node Q, a first and second gate electrode (or body electrode) connected to the gate voltage line VGL, and a second electrode connected to the QB node QB. The fifth sampling transistor T5 can be turned on based on the voltage of the Q node Q to pass the low gate voltage applied via the gate voltage line VGL to the QB node QB. The fifth sampling transistor T5 can remain on during periods when the voltage of the Q node Q is high to maintain a stable voltage at the QB node QB when the voltage is low. The sixth sampling transistor T6 can have a gate electrode connected to the Q2 node Q2, a first electrode connected to the high gate voltage line VGH, and a second electrode connected to the QB node QB. The sixth sampling transistor T6 can be switched on based on the voltage of the Q2 node Q2 to pass the high gate voltage applied via the high gate voltage line VGH to the QB node QB. The seventh sampling transistor T7 can have a gate electrode connected to a clock signal line GCLK, a first electrode connected to a start signal line VST (a carry output terminal CRY or an output terminal of the preceding stage), and a second electrode connected to the Q2 node Q2. The seventh sampling transistor T7 can be turned on based on a clock signal applied via the clock signal line GCLK to pass a start signal applied via the start signal line VST to the Q2 node Q2. According to the third embodiment, the voltage control circuit VrefC(n) can include a first control transistor T9 and a second control transistor T8. The first control transistor T9 and the second control transistor T8 can be implemented as p-type transistors, but this disclosure is not limited to them. The first control transistor T9 can have a gate electrode connected to the QB node QB of the fourth sampled signal generator SC4(n), a first electrode connected to the reference voltage line VrefL, and a second electrode connected to the reference voltage output terminal Vref_out(n). The first control transistor T9 can be switched on based on the voltage of the QB node QB of the fourth sampled signal generator SC4(n) to output the reference voltage via the reference voltage output terminal Vref_out(n). The second control transistor T8 can have a gate electrode connected to the output terminal of the fourth sampled signal generator SC4(n), a first electrode connected to the balancing voltage line CVL, and a second electrode connected to the reference voltage output terminal Vref_out(n). Based on the fourth sampled signal output via the output terminal of the fourth sampled signal generator SC4(n), the second control transistor T8 can be switched on to output a balancing voltage via the reference voltage output terminal Vref_out(n). Meanwhile, Fig. 12 illustrates an example where the first electrode of the second control transistor T8 is connected to the compensating voltage line CVL. Here, the compensating voltage can have a level lower than the reference voltage and will not affect image quality when the subpixel SP emits light. Additionally, the first electrode of the second control transistor T8 can be set to an electrically floating potential (or can be in a state where no voltage is applied to it) without being connected to the compensating voltage line CVL. Accordingly, the second control transistor T8 can be turned on based on the fourth sample output signal via the output terminal of the fourth sample generator SC4(n) to output the compensating voltage via the reference output terminal Vref_out(n), or it may not output any voltage. Meanwhile, the fourth sampling transistor T4 up to the seventh sampling transistor T7, with the exception of the first sampling transistor T1, the second sampling transistor T2 and the third sampling transistor T3, which are defined as output transistors in the fourth sampling signal generator SC4(n), can define a node control circuit that controls the Q node Q, the Q2 node Q2 and the QB node QB. As illustrated in Fig. 13 and Fig. 14, during a first period a first clock signal GCLK1 at a low voltage and a start signal GVST at a high voltage can be applied to the fourth sample signal generator SC4(n). When the seventh sampling transistor T7 is switched on at a low voltage based on the first clock signal GCLK1, the voltage at the Q2 node of node Q2 and the voltage at the QB node of node Q can reach a high voltage. Currently, when the fifth sampling transistor T5 is switched on at a high voltage at the QB node of node Q, the voltage at the QB node of node QB can reach a low voltage. Since the voltage at QB node QB reaches a low voltage, the second sampling transistor T2 and the third sampling transistor T3 can be switched on. Conversely, since the voltage at Q2 node Q2 and the voltage at Q node Q are high voltages, the first sampling transistor T1 can be switched off. The fourth sampling signal generator SC4(n) can output the fourth sampled signal at a high voltage via the output terminal, based on the second sampling transistor T2 being switched on. The second control transistor T8, included in the voltage control circuit VrefC(n), can be switched off based on the fourth sample signal at a high voltage, which is output via the output terminal of the fourth sample signal generator SC4(n). Conversely, the first control transistor T9, included in the voltage control circuit VrefC(n), can be switched on based on the low voltage of the QB node QB to output the reference voltage Vref_out via the reference voltage output terminal Vref_out(n). As illustrated in Fig. 13 and Fig. 15, during a second period a first clock signal GCLK1 at a low voltage and a start signal GVST at a low voltage can be applied to the fourth sample signal generator SC4(n). When the seventh sampling transistor T7 is switched on at a low voltage based on the first clock signal GCLK1, the voltage at Q2-node of node Q2 and the voltage at Q2-node of node Q2 reach a low voltage. At this point, the fifth sampling transistor T5 can be switched off based on the low voltage at Q2-node of node Q5. Since the voltage QB-node of QB node QB reaches a high voltage due to the activation of the sixth sampling transistor T6, the second sampling transistor T2 and the first control transistor T9 can be deactivated. Conversely, when the voltage Q2-node of Q2 node Q2 and the voltage Q-node of Q node Q reach a low voltage, the first sampling transistor T1 can be activated. The fourth sampling signal generator SC4(n) can output the fourth sampled signal via its output terminal at a low voltage, based on the activation of the first sampling transistor T1. The second control transistor T8, included in the voltage control circuit VrefC(n), can be switched on based on the fourth sampled signal at a low voltage, which is output via the output terminal of the fourth sampled signal generator SC4(n). Accordingly, the second control transistor T8, included in the voltage control circuit VrefC(n), can output a balancing voltage via the reference voltage output terminal Vref_out(n) or it may not output any voltage at all. As can be seen in a reference voltage output period VARD of Fig. 13, the period in which the voltage QB-node of the QB node QB is a low voltage and the period in which the reference voltage Vref_out is output in response to it can occur simultaneously. The present disclosure discloses the effect of solving problems (voltage noise, luminance deviation, etc.) caused by a high-voltage level deviation (EVDD deviation due to IR drop) in the display panel by sequentially applying a reference voltage to the respective horizontal lines of the display panel. Additionally, the present disclosure discloses the effects of simplifying a circuit contained within a subpixel and improving the aperture ratio and lifetime by integrating a circuit for applying the reference voltage to the respective horizontal lines of the display panel into a sampling signal generator or by arranging the circuit adjacent to the sampling signal generator. It is apparent to those skilled in the art that various modifications and variations of the present disclosure are possible without altering the concept or scope of the present disclosure. Therefore, the present disclosure is intended to cover such modifications and variations as fall within the scope of the attached claims and their equivalents. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature KR 10-2024-0196942

[0001]

Claims

A display device comprising: a display panel containing subpixels; a gate driver connected to the subpixels; and a voltage control circuit comprising at least one control transistor controlled based on the operation of the gate driver, wherein each of the subpixels has a first capacitor having one end connected to a gate electrode of a drive transistor and the other end connected to a first node defined as a second electrode of the drive transistor, and a second capacitor having one end connected to an output terminal of the voltage control circuit and the other end connected to the first node, and the at least one control transistor configured to be switched on based on the operation of the gate driver to apply a reference voltage to the subpixels. Display device according to claim 1, wherein the gate driver comprises: a first sample signal generator configured to generate a first sample signal; a second sample signal generator configured to generate a second sample signal; a third sample signal generator configured to generate a third sample signal; and a fourth sample signal generator configured to generate a fourth sample signal, wherein the at least one control transistor is configured to be switched on based on an operation of the fourth sample signal generator in order to apply the reference voltage to the subpixels. Display device according to claim 2, wherein the fourth scanning signal is not applied to the subpixels. Display device according to claim 2, wherein the at least one control transistor comprises a first control transistor having a gate electrode connected to an output terminal of the fourth sampling signal generator, a first electrode connected to a reference voltage line through which the reference voltage is passed, and a second electrode connected to one end of the second capacitor. Display device according to claim 4, wherein the first control transistor is switched on during a period in which a voltage of a Q node of the fourth sampling signal generator is a low voltage. Display device according to claim 5, wherein the fourth sampling signal generator comprises: a first transistor having a gate electrode connected to a Q node, a first electrode connected to a low gate voltage line, and a second electrode connected to the output terminal; a second transistor having a gate electrode connected to a QB node operating opposite to the Q node, a first electrode connected to a high gate voltage line, and a second electrode connected to the output terminal; and a node control circuit configured to control the Q node and the QB node. Display device according to claim 2, wherein the at least one control transistor comprises a first control transistor having a gate electrode connected to a QB node of the gate driver, a first electrode connected to a reference voltage line through which the reference voltage is passed, and a second electrode connected to one end of the second capacitor. Display device according to claim 7, wherein the first control transistor is switched on during a period in which a voltage of a QB node of a fourth sampling signal generator is a low voltage. Display device according to claim 1, wherein the reference voltage is applied sequentially to one end of the second capacitor for a gate line based on the operation of the voltage control circuit. A method for controlling a display device according to claim 1, wherein the method comprises: an initialization operation for initializing nodes of the subpixels; a sampling operation for sampling threshold voltages of drive transistors contained in the subpixels; a data voltage write operation for applying a data voltage to the subpixels; and an emission operation for causing the subpixels to emit light, wherein the voltage control circuit is switched on based on the operation of the gate driver to apply the reference voltage to the subpixels during the initialization operation, the sampling operation, and the data voltage write operation. Method according to claim 10, wherein the reference voltage is applied to one end of the second capacitor. Method according to claim 11, wherein the reference voltage is applied sequentially to one end of the second capacitor for each gate line based on an operation of the voltage control circuit.

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