Semiconductor device and method for manufacturing the same
A delay circuit with selectable paths and a selection signal addresses timing clock defects and electromigration in semiconductor devices, enhancing precision and reducing rework in the manufacturing process.
DE102025150327A1Pending Publication Date: 2026-06-11RENESAS ELECTRONICS CORP
Patent Information
- Application Number
- DE102025150327
- Authority / Receiving Office
- DE · DE
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-12-03
- Publication Date
- 2026-06-11
Smart Images
Figure 00000000_0000_ABST
Abstract
A semiconductor device and its manufacturing process are provided that are capable of designing the intended delay with high precision in just a few steps.The semiconductor device fabrication method disclosed herein arranges several circuits on one plane and connects a wiring system to each, comprising: a placement step of arranging a digital circuit operating on the basis of timing signals and a delay circuit configured with several delay paths having different input / output delay amounts, wherein one of the several delay paths can be selected by a selection signal; a wiring step of connecting the output of the delay circuit so that it becomes the timing signal of the digital circuit; and a delay setting step of selecting one of the several delay paths by connecting a predetermined voltage as the selection signal and selecting the delay amount so that the input / output timing of the digital circuit satisfies predetermined conditions.
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Citation Information
Patent Citations
2024-216428
146047
JP2010S
JP2024216428A
JP146047S