A signal generation circuit

Abstract

The embodiment of the present application discloses a signal generation circuit. The circuit comprises a delay-locked loop module, a counting unit, a comparison unit, a first voltage-controlled delay line, a second voltage-controlled delay line, a gating unit and an output logic unit. The delay-locked loop module generates a control voltage according to a reference clock signal, which is used to adjust the delay amount of the first voltage-controlled delay line and the second voltage-controlled delay line; the comparison unit is used to output a period trigger signal and a duty cycle trigger signal; the gating unit selects the corresponding delay output according to the low bit value of the period control value and the duty cycle control value; the upper limit value of the counting unit and the duty cycle control value are dynamically adjusted according to whether the accumulated delay amount reaches a preset threshold. In the above manner, the embodiment of the present application can ensure stable performance of the delay line, reduce the maximum delay amount required by the delay line, reduce the chip area overhead, and realize generation of a pulse width modulation signal with adjustable duty cycle and adjustable period and high precision.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of switching power supplies, and in particular to a signal generation circuit. Background Technology

[0002] Modern switching power supplies typically use square wave drives with adjustable duty cycles or adjustable periods to operate. The resolution of the duty cycle and the resolution of the period directly determine the output voltage resolution of the power supply, and to some extent, also affect the control design of the power supply.

[0003] Modern power supplies are trending towards miniaturization, with increasingly higher switching frequencies. For traditional hardware that generates pulse-width modulation (PWM) signals using clock division, the period resolution and duty cycle resolution are limited by the counter clock frequency. High-frequency counter clocks pose challenges to manufacturing processes and may even be impractical. Therefore, generating high-resolution PWM signals at low-frequency counter clocks is an essential requirement.

[0004] Existing solutions achieve high-precision pulse width modulation (PWM) signal generation through clock phase shifting and delay lines. For clock phase shifting systems, only 90° phase shifts are typically implemented, resulting in limited accuracy improvement. Delay line solutions, or delay lines combined with clock phase shifting, are common implementations for high-precision PWM signals. A delay line is a circuit composed of multiple delay blocks connected in series, introducing an additional delay between the input and output signals.

[0005] However, due to limitations in process technology, ambient temperature, and manufacturing variations, the consistency and temperature drift of delay lines are quite poor. Any solution based on this technology requires an additional self-calibration circuit, which typically uses a known clock as a reference to calculate the delay line delay or the required number of delay blocks. These self-calibration circuits introduce additional hardware division and an extra set of delay lines. Furthermore, due to their poor temperature characteristics, the delay line length may even require double the redundancy. These additional circuits and delay blocks will increase chip area and introduce more design complexity.

[0006] Furthermore, while ensuring the performance of the delay line, high-precision pulse width modulation signals require adjustment of the duty cycle and period. Adjusting the duty cycle is obvious, but period adjustment still requires additional circuitry for calculation and still requires a certain amount of delay line redundancy. Summary of the Invention

[0007] The main technical problem solved by the embodiments of the present invention is to provide a signal generation circuit that can solve at least some of the defects of existing pulse width drive signal generation circuits.

[0008] In a first aspect, embodiments of the present invention provide a signal generation circuit, comprising: a delay phase-locked loop module for generating a control voltage based on a reference clock signal; the control voltage being used to ensure the delay of all delay lines; a counting unit for counting under the drive of the reference clock signal; the upper limit of the counting unit being determined by a preset period control value; a comparison unit for outputting a period trigger signal when the count value reaches a period start value; and comparing the count value with a preset duty cycle control value to output a duty cycle trigger signal; a first voltage-controlled delay line, the delay of which is adjusted by the control voltage, the first voltage-controlled delay line being used to delay the period trigger signal; and a second voltage-controlled delay line, the delay of which is adjusted by the control voltage. The system includes a voltage control unit, whereby the second voltage-controlled delay line is used to delay the duty cycle trigger signal; a gating unit is used to select the corresponding delayed output of the first voltage-controlled delay line based on the low-order value of the period control value, and to select the corresponding delayed output of the second voltage-controlled delay line based on the low-order value of the duty cycle control value; and an output logic unit is used to generate a pulse width modulation signal based on the delayed period trigger signal and the duty cycle trigger signal. The upper limit of the count is adjusted based on whether the cumulative delay of the first voltage-controlled delay line reaches a preset threshold, thereby reducing the maximum delay required by the first voltage-controlled delay line. The duty cycle control value is calculated based on the cumulative delay of the first voltage-controlled delay line and the low-order value of the duty cycle control value, thereby reducing the maximum delay required by the second voltage-controlled delay line.

[0009] Optionally, the delay phase-locked loop module includes a reference delay line connected to the reference clock signal, used to generate the control voltage through phase-locked regulation.

[0010] Optionally, the comparison unit includes: a first comparator for comparing the count value with the period start value and outputting the period trigger signal; the period start value is zero; and a second comparator for comparing the count value with the high-order bit of the duty cycle control value and outputting the duty cycle trigger signal.

[0011] Optionally, both the period control value and the duty cycle control value include a high-order bit value and a low-order bit value, wherein the high-order bit value is used to control the comparison operation of the comparison unit, and the low-order bit value is used to control the gating of the gating unit.

[0012] Optionally, the gating unit includes: a first gating unit, used to select the delay output of the corresponding voltage-controlled delay line according to the low-order value of the period control value; and a second gating unit, used to select the delay output of the corresponding voltage-controlled delay line according to the low-order value of the duty cycle control value.

[0013] Optionally, the output logic unit is an SR flip-flop. The set terminal of the SR flip-flop receives the cycle trigger signal after delay processing, and the reset terminal of the SR flip-flop receives the duty cycle trigger signal after delay processing.

[0014] Optionally, both the first voltage-controlled delay line and the second voltage-controlled delay line are composed of a plurality of delay blocks connected in series, and the delay amount of each delay block is adjusted by the control voltage.

[0015] Optionally, the calculation method of the cumulative delay amount is as follows: cnt_d = (cnt_d_last + ARRn) % M; where cnt_d is the current cumulative delay amount, cnt_d_last is the cumulative delay amount of the previous cycle, ARRn is the low-order value of the cycle control value, and M is the modulus of the low-order value.

[0016] Optionally, the adjustment method of the counting upper limit value is as follows: When cnt_d_last + ARRn ≥ M, the counting upper limit value is ARRN + 1; When cnt_d_last + ARRn < M, the counting upper limit value is ARRN; where ARRN is the high-order value of the cycle control value.

[0017] Optionally, the maximum delay amount required by the first voltage-controlled delay line is (M - 1) / M times the reference clock period.

[0018] The beneficial effects of the embodiments of the present invention are as follows: Different from the prior art, the embodiments of the present invention can ensure the stable performance of the delay line, reduce the maximum delay amount required by the delay line, reduce the chip area overhead, and realize the generation of a pulse width modulation signal with a high-precision adjustable duty cycle and adjustable period. Description of the Drawings

[0019] One or more embodiments are exemplarily illustrated by corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements unless otherwise stated. The drawings in the figures do not constitute a proportional limitation.

[0020] Figure 1 is a schematic structural diagram of a signal generation circuit provided by an embodiment of the present invention; Figure 2 is a schematic circuit diagram of a signal generation circuit provided by an embodiment of the present invention; Figure 3 is a schematic diagram of the data format of a cycle control value and a duty cycle control value provided by an embodiment of the present invention; Figure 4 This is a timing waveform diagram of a signal generation circuit provided by the present invention operating under integer periods; Figure 5 This is a timing waveform diagram of a signal generation circuit provided by the present invention operating under a non-integer period (first period); Figure 6 This is a timing waveform diagram of a signal generation circuit provided by the present invention operating under a non-integer period (second period); Figure 7 This is a schematic flowchart of a signal generation method provided by the present invention. Detailed Implementation

[0021] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0023] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0024] The technical solutions in this application will be described below with reference to the accompanying drawings.

[0025] Please see Figure 1 , Figure 1 This is a schematic diagram of a signal generation circuit provided in an embodiment of the present invention.

[0026] In some embodiments of this application, the signal generation circuit includes a delay phase-locked loop module 100, a counting unit 210, a comparison unit 220, a first voltage-controlled delay line 230, a second voltage-controlled delay line 240, a gating unit 250, and an output logic unit 260.

[0027] Specifically, the delay phase-locked loop module 100 generates a control voltage based on a reference clock signal. This control voltage is used to ensure the delay of all delay lines. The delay phase-locked loop module 100 generates a stable control voltage through phase-locked regulation, which is then used by the subsequent voltage-controlled delay lines.

[0028] In some embodiments of this application, the delay phase-locked loop module 100 is connected to the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240. The control voltage generated by the delay phase-locked loop module 100 is output to the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240 to adjust the delay amount of the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240.

[0029] Specifically, the counting unit 210 is used to perform counting under the drive of a reference clock signal. The upper limit of the counting unit 210 is determined by a preset period control value. The period control value determines the counting range of the counting unit 210, thereby affecting the period of the pulse width modulation signal.

[0030] In some embodiments of this application, the counting unit 210 is connected to the comparison unit 220, and the counting unit 210 outputs the count value to the comparison unit 220 for comparison and operation.

[0031] Specifically, the comparison unit 220 is used to output a period trigger signal when the count value reaches the period start value; and to compare the count value with a preset duty cycle control value and output a duty cycle trigger signal. The period trigger signal generated by the comparison unit 220 marks the start of the pulse width modulation signal period, and the duty cycle trigger signal is used to control the duty cycle of the pulse width modulation signal.

[0032] In some embodiments of this application, the comparison unit 220 is connected to the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240. Specifically, the comparison unit 220 outputs a periodic trigger signal to the first voltage-controlled delay line 230 and a duty cycle trigger signal to the second voltage-controlled delay line 240.

[0033] Specifically, the delay of the first voltage-controlled delay line 230 is adjusted by the control voltage, and the first voltage-controlled delay line 230 is used to delay the periodic trigger signal. Similarly, the delay of the second voltage-controlled delay line 240 is also adjusted by the control voltage, and the second voltage-controlled delay line 240 is used to delay the duty cycle trigger signal. It is easy to understand that both the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240 are adjusted by the control voltage generated by the delay phase-locked loop module 100, thereby ensuring the stability and consistency of the delay.

[0034] In some embodiments of this application, the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240 are connected to the gating unit 250. Specifically, the first voltage-controlled delay line 230 outputs the delayed periodic trigger signal to the gating unit 250, and the second voltage-controlled delay line 240 outputs the delayed duty cycle trigger signal to the gating unit 250.

[0035] Specifically, the gating unit 250 is used to select the corresponding delayed output of the first voltage-controlled delay line 230 based on the low-order value of the period control value, and to select the corresponding delayed output of the second voltage-controlled delay line 240 based on the low-order value of the duty cycle control value. The low-order values ​​of the period control value and the duty cycle control value determine the delayed output selected by the gating unit 250, thereby achieving high-precision delay control.

[0036] In some embodiments of this application, the gating unit 250 is connected to the output logic unit 260. Specifically, the gating unit 250 outputs the gating periodic trigger signal and duty cycle trigger signal to the output logic unit 260.

[0037] Specifically, the output logic unit 260 is used to generate a pulse width modulation signal based on the delayed periodic trigger signal and the duty cycle trigger signal. The output logic unit 260 receives the periodic trigger signal and the duty cycle trigger signal after being selected by the gating unit 250, and generates the final pulse width modulation signal output accordingly.

[0038] As an example, and not a limitation, the upper limit of the count is adjusted based on whether the cumulative delay of the first voltage-controlled delay line 230 reaches a preset threshold, thereby reducing the maximum delay required by the first voltage-controlled delay line 230. By dynamically adjusting the upper limit of the count, the cumulative delay can be prevented from exceeding the maximum delay that the voltage-controlled delay line can provide, thus reducing the requirement for delay line length and reducing chip area overhead. In addition, the duty cycle control value is calculated based on the cumulative delay of the first voltage-controlled delay line 230 and the lower value of the duty cycle control value, in order to reduce the maximum delay required by the second voltage-controlled delay line 240.

[0039] In some embodiments of this application, since the control voltage generated by the delay phase-locked loop module 100 simultaneously adjusts the delay amount of the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240, the problem of unstable delay time of the delay line can be improved, so that the performance of the delay line is not affected by factors such as process and temperature, and the accuracy of the pulse width modulation signal is guaranteed.

[0040] Please see Figure 2 , Figure 2 This is a circuit diagram of a signal generation circuit provided in an embodiment of the present invention.

[0041] In some embodiments of this application, the delay phase-locked loop module 100 includes a reference delay line 110. Specifically, the reference delay line 110 is connected to a reference clock signal and is used to generate a control voltage Vctrl through phase-locked regulation. It is easy to understand that the reference delay line 110 receives the reference clock signal CLK, generates a stable control voltage Vctrl through the phase-locked loop's phase-locked regulation mechanism, and outputs it to 120.

[0042] Specifically, the reference delay line 110 is composed of multiple delay blocks connected in series. Figure 2 Delay blocks U7, U8, U9, and U10 are shown. In some embodiments of this application, the number of delay blocks in the reference delay line 110 can be set according to actual needs. It is easy to understand that the output and input terminals of the reference delay line 110 form a closed loop, and the total delay of the reference delay line 110 is matched with the period of the reference clock signal through phase-locked loop regulation, thereby generating a stable control voltage Vctrl.

[0043] In some embodiments of this application, the control voltage Vctrl is simultaneously output to the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240 to adjust the delay amount of each delay block in the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240.

[0044] Please see Figure 3 , Figure 3 This is a schematic diagram of the data format of a periodic control value and a duty cycle control value provided by an embodiment of the present invention.

[0045] In some embodiments of this application, both the period control value and the duty cycle control value include a high-order bit value and a low-order bit value. Specifically, the high-order bit value is used to control the comparison operation of the comparison unit 220, and the low-order bit value is used to control the gating of the gating unit 250. This is an example and not a limitation. Figure 3 The diagram illustrates a data format where the high-order value N occupies bits 31 to 16, the low-order value n occupies bits 15 to 13, and bits 12 to 0 are unused. It is easy to understand that the bit width of the high-order value is N bits (16 bits), and the bit width of the low-order value is n bits (3 bits).

[0046] Specifically, the comparison unit 220 includes a first comparator COMP1 and a second comparator COMP2. In some embodiments of this application, the first comparator COMP1 is used to compare the count value with the period start value and output a period trigger signal. Specifically, the period start value is zero. It is easy to understand that when the count value of the counting unit 210 is equal to zero, the first comparator COMP1 outputs the period trigger signal, marking the start of the pulse width modulation signal period.

[0047] In some embodiments of this application, the second comparator COMP2 is used to compare the count value with the high-order bit of the duty cycle control value and output a duty cycle trigger signal. It is easy to understand that when the count value of the counting unit 210 is equal to the high-order bit of the duty cycle control value, the second comparator COMP2 outputs a duty cycle trigger signal to control the pulse width modulation signal to change from a high level to a low level.

[0048] Specifically, the first comparator COMP1 is connected to the counting unit 210, receives the count value output by the counting unit 210, and compares it with the cycle start value. The second comparator COMP2 is connected to the counting unit 210, receives the count value output by the counting unit 210, and compares it with the high-order value of the duty cycle control value.

[0049] In some embodiments of this application, both the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240 are composed of multiple delay blocks connected in series, and the delay amount of each delay block is adjusted by the control voltage Vctrl. Specifically, Figure 2 The diagram shows that the first voltage-controlled delay line 230 includes delay blocks U1, U2, and U3, and the second voltage-controlled delay line 240 includes delay blocks U4, U5, and U6. It is easy to understand that the number of delay blocks in the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240 can be set according to actual needs.

[0050] Specifically, the output of the first comparator COMP1 is connected to the input of the first voltage-controlled delay line 230, and the periodic trigger signal output by the first comparator COMP1 is delayed sequentially through delay blocks U1, U2, and U3. In some embodiments of this application, the output of the second comparator COMP2 is connected to the input of the second voltage-controlled delay line 240, and the duty cycle trigger signal output by the second comparator COMP2 is delayed sequentially through delay blocks U4, U5, and U6.

[0051] In some embodiments of this application, the gating unit 250 includes a first gating unit U11 and a second gating unit U12. Specifically, the first gating unit U11 is used to select the corresponding delayed output of the first voltage-controlled delay line 230 according to the low-order value of the period control value. The second gating unit U12 is used to select the corresponding delayed output of the second voltage-controlled delay line 240 according to the low-order value of the duty cycle control value.

[0052] Specifically, the first selector U11 is connected to the first voltage-controlled delay line 230, and the output terminals of each delay block in the first voltage-controlled delay line 230 are respectively connected to the input terminals of the first selector U11. In some embodiments of this application, the first selector U11 selects the corresponding delay output from multiple delay outputs of the first voltage-controlled delay line 230 according to the low-order value of the period control value. It is easy to understand that the low-order value of the period control value determines the delay amount selected by the first selector U11, thereby achieving high-precision delay control of the periodic trigger signal.

[0053] Specifically, the second selector U12 is connected to the second voltage-controlled delay line 240, and the output terminals of each delay block in the second voltage-controlled delay line 240 are respectively connected to the input terminals of the second selector U12. In some embodiments of this application, the second selector U12 selects the corresponding delay output from multiple delay outputs of the second voltage-controlled delay line 240 based on the low-order value of the duty cycle control value. It is easy to understand that the low-order value of the duty cycle control value determines the delay amount selected by the second selector U12, thereby achieving high-precision delay control of the duty cycle trigger signal.

[0054] In some embodiments of this application, the output logic unit 260 is an SR flip-flop U13. Specifically, the set terminal S of the SR flip-flop U13 receives a delayed periodic trigger signal, and the reset terminal R of the SR flip-flop U13 receives a delayed duty cycle trigger signal. It is easy to understand that when the set terminal S of the SR flip-flop U13 receives the periodic trigger signal, the output terminal Q of the SR flip-flop U13 outputs a high level; when the reset terminal R of the SR flip-flop U13 receives the duty cycle trigger signal, the output terminal Q of the SR flip-flop U13 outputs a low level, thereby generating a pulse width modulation signal.

[0055] Specifically, the output of the first selector U11 is connected to the set terminal S of the SR flip-flop U13, and the output of the second selector U12 is connected to the reset terminal R of the SR flip-flop U13. In some embodiments of this application, the output terminal Q of the SR flip-flop U13 outputs a pulse width modulation signal.

[0056] In some embodiments of this application, the cumulative delay is calculated as follows: cnt_d = (cnt_d_last + ARRn) % M Where cnt_d is the current cumulative delay, cnt_d_last is the cumulative delay of the previous cycle, ARRn is the low-order bit of the cycle control value, and M is the modulus of the low-order bit. It's easy to understand that the cumulative delay cnt_d represents the percentage of delay required in the current cycle, obtained by summing the cumulative delay cnt_d_last of the previous cycle with the low-order bit ARRn of the cycle control value and then taking the modulo operation.

[0057] By way of example and not limitation, when the bit width nbits of the low - order value is 3, M = pow(2, nbits)=8. Specifically, if the value of ARRn is 4 and the value of cnt_d_last is 0, then cnt_d=(0 + 4)%8 = 4, indicating that the current period needs to delay 0.5 times the reference clock period.

[0058] In some embodiments of the present application, the adjustment method of the counting upper limit value is as follows: When cnt_d_last + ARRn ≥ M, the counting upper limit value is ARRN + 1; When cnt_d_last + ARRn < M, the counting upper limit value is ARRN; Where ARRN is the high - order value of the cycle control value. It is easy to understand that when the cumulative delay amount reaches or exceeds the modulus M, by increasing the counting upper limit value by 1 to compensate for the delay, the cumulative delay amount is made to return to the range of the modulus M again, so as to avoid the cumulative delay amount exceeding the maximum delay that the voltage - controlled delay line can provide.

[0059] By way of example and not limitation, when M = 4, ARRN = 4, ARRn = 1, if cnt_d_last = 3, then cnt_d_last + ARRn = 4 ≥ M, and the counting upper limit value is ARRN + 1 = 5; if cnt_d_last = 2, then cnt_d_last + ARRn = 3 < M, and the counting upper limit value is ARRN = 4.

[0060] In some embodiments of the present application, the maximum delay amount required by the first voltage - controlled delay line 230 is (M - 1) / M times the reference clock period. By dynamically adjusting the duty - cycle control value of the comparator, the delay amount required by the second voltage - controlled delay line 240 will also always be kept within the range of 0 to M - 1. It is easy to understand that by dynamically adjusting the counting upper limit value, the maximum value of the cumulative delay amount is M - 1, and the corresponding maximum delay time is (M - 1) / M times the reference clock period, thereby reducing the requirement for the length of the delay line. By way of example and not limitation, when M = 4, the maximum delay amount required by the first voltage - controlled delay line 230 is (4 - 1) / 4 = 0.75 times the reference clock period, that is, 3 / 4 times the reference clock period. Specifically, compared with the scheme that requires a complete reference clock period delay, this embodiment reduces the requirement for the delay line length by 25%, thereby reducing the chip area overhead.

[0061] Please refer to Figure 4 , Figure 4 which is the timing waveform diagram of a signal generation circuit provided by an embodiment of the present invention operating in integer cycles.

[0062] In some embodiments of this application, taking M = 4 as an example, when the period control value ARR is set to 16, the high-order bit value ARRN = 16 ÷ 4 = 4, the low-order bit value ARRn = 0, and the period of the pulse width modulation signal is 4 times the reference clock period, i.e., 4T. Specifically, the count values ​​of the counting unit 210 are 0, 1, 2, and 3 in sequence. When the count value reaches the upper limit of 4, the counting unit 210 restarts counting from 0.

[0063] As an example, and not a limitation, when the duty cycle control value CMP is set to 10, the high-order bit of the duty cycle control value is 10 ÷ 4 = 2, and the low-order bit is 10 % 4 = 2. It's easy to understand that the high-order bit of the duty cycle control value is used for the comparison operation of the second comparator COMP2, and the low-order bit is used for the gating control of the second selector U12.

[0064] In some embodiments of this application, when the count value of the counting unit 210 is equal to 0, the first comparator COMP1 outputs a periodic trigger signal PWM SET. Specifically, since the low-order value of the periodic control value ARRn = 0, the first selector U11 selects the first output of the first voltage-controlled delay line 230, i.e., the delay is 0. It is easy to understand that the periodic trigger signal PWM SET is aligned with the ZERO signal generated when the count value is equal to 0, and the pulse width modulation signal PWM outputs a high level.

[0065] Specifically, when the count value of the counting unit 210 is equal to 2, the second comparator COMP2 outputs a duty cycle trigger signal CMP. In some embodiments of this application, since the low-order value of the duty cycle control value is 2, the second selector U12 selects the third output of the second voltage-controlled delay line 240, i.e., the delay is 0.5T. It is easy to understand that after the duty cycle trigger signal CMP is delayed by 0.5T through the second voltage-controlled delay line 240, the PWM RST signal is obtained and sent to the reset terminal R of the SR flip-flop U13, and the pulse width modulation signal PWM outputs a low level.

[0066] In some embodiments of this application, the high-level time of the pulse width modulation signal (PWM) is 2.5T, and the duty cycle is 2.5T ÷ 4T = 62.5%. Specifically, when the upper limit of the count is 4, the duty cycle resolution of the PWM signal is 25% under the counter clock. It is easy to understand that higher precision duty cycle adjustment is achieved through the delay line, and the duty cycle resolution is improved to 12.5%.

[0067] Please see Figure 5 , Figure 5 This is a timing waveform diagram of a signal generation circuit operating under a non-integer period (first period) according to an embodiment of the present invention.

[0068] In some embodiments of the present application, taking M = 4 as an example, when the value of the cycle control value ARR is set to 17, the high-order value ARRN of the cycle control value is 17 ÷ 4 = 4, and the low-order value ARRn of the cycle control value is 17 % 4 = 1. The cycle of the pulse width modulation signal is 4.25 times the reference clock cycle, that is, 4.25T.

[0069] As an example rather than a limitation, when the value of the duty cycle control value CMP is set to 10, a duty cycle of 50% is generated, and the high-order value of the duty cycle control value is 2. Specifically, at the beginning of the first cycle, the initial value of the cumulative delay amount cnt_d_last is 0.

[0070] In some embodiments of the present application, according to the calculation method of the cumulative delay amount, cnt_d = (cnt_d_last + ARRn) % M = (0 + 1) % 4 = 1. Specifically, the cumulative delay amount cnt_d of the current cycle is 1, indicating that a delay of 0.25T is required. It is easy to understand that since cnt_d_last + ARRn = 0 + 1 = 1 < M = 4, the counting upper limit value is ARRN = 4.

[0071] Specifically, when the count value of the counting unit 210 is equal to 0, the first comparator COMP1 outputs a cycle trigger signal. In some embodiments of the present application, the PWM SET signal after delay processing is aligned with the ZERO signal, and the pulse width modulation signal PWM outputs a high level.

[0072] In some embodiments of the present application, when the count value of the counting unit 210 is equal to 2, the second comparator COMP2 outputs a duty cycle trigger signal CMP. Specifically, the duty cycle trigger signal CMP is delayed by 0.5T through the second voltage-controlled delay line 240 and then outputs a PWM RST signal, and the pulse width modulation signal PWM outputs a low level. It is easy to understand that the high-level time of the pulse width modulation signal PWM is 2.5T.

[0073] Specifically, at the end of the first cycle, the next ZERO pulse needs to be delayed by 0.25T before output to achieve a cycle of 4.25T. In some embodiments of the present application, the first selector U11 selects the second output of the first voltage-controlled delay line 230 according to the cumulative delay amount cnt_d = 1, that is, the delay amount is 0.25T.

[0074] In some embodiments of the present application, the calculation method of the delay amount of the duty cycle trigger signal is: cmp_d = (cnt_d + CMPn) % M Among them, cmp_d is the delay amount required for the duty cycle trigger signal, cnt_d is the cumulative delay amount of the current cycle, and CMPn is the low value of the duty cycle control value. It is not difficult to understand that since the delay time of the duty cycle trigger signal is affected by the cumulative delay amount of the cycle trigger signal, by taking the modulo operation after summing the cumulative delay amount cnt_d and the low value CMPn of the duty cycle control value, the delay amount required for the duty cycle trigger signal can be obtained, so that the maximum delay amount required for the second voltage-controlled delay line 240 also remains within the range of (M - 1) / M times the reference clock period.

[0075] Please refer to Figure 6 , Figure 6 is the timing waveform diagram of a signal generation circuit provided by an embodiment of the present invention when operating in a non-integer cycle (the second cycle).

[0076] In some embodiments of the present application, at the beginning of the second cycle, since the previous cycle has been delayed by 0.25T, the cumulative delay amount cnt_d_last = 1. Specifically, according to the calculation method of the cumulative delay amount, cnt_d = (cnt_d_last + ARRn) % M = (1 + 1) % 4 = 2. It is not difficult to understand that the cumulative delay amount cnt_d of the current cycle = 2, indicating that a delay of 0.5T is required.

[0077] Specifically, since cnt_d_last + ARRn = 1 + 1 = 2 < M = 4, the counting upper limit value remains ARRN = 4. In some embodiments of the present application, the first selector U11 selects the third output of the first voltage-controlled delay line 230 according to the cumulative delay amount cnt_d = 2, that is, the delay amount is 0.5T.

[0078] In some embodiments of the present application, since the cycle start has been delayed by 0.25T, if a high-level time of 2.5T is required, the PWM RST signal should be delayed by 0.75T. Specifically, the second selector U12 selects the fourth output of the second voltage-controlled delay line 240, that is, the delay amount is 0.75T. It is not difficult to understand that the high-level time of the pulse width modulation signal PWM remains 2.5T, and the cycle remains 4.25T.

[0079] As an example rather than a limitation, as the cycles accumulate, the cumulative delay amount cnt_d will continuously increase. In some embodiments of the present application, when the cumulative delay amount reaches or exceeds M, the counting upper limit value is increased by 1 to compensate for the delay.

[0080] Specifically, assuming that in a certain period, cnt_d_last = 3 and ARRn = 1, then cnt_d_last + ARRn = 3 + 1 = 4 ≥ M = 4. In some embodiments of this application, the upper limit of the count is adjusted to ARRN + 1 = 5, and the cumulative delay cnt_d = (3 + 1) % 4 = 0. It is easy to understand that by increasing the upper limit of the count by 1, the effect of a 1T delay is achieved. At this time, the ZERO signal is re-aligned with the counter clock, the cumulative delay is reset to 0, and the state returns to the initial state.

[0081] In some embodiments of this application, by dynamically adjusting the upper limit of the count, the cumulative delay is always kept within the range of 0 to M-1. Specifically, the maximum delay required by the first voltage-controlled delay line 230 is (M-1) / M times the reference clock cycle. It is easy to understand that when M = 4, the maximum delay is 0.75T, which reduces the delay line length requirement by 25% compared to the scheme requiring a full 1T delay. Similarly, by dynamically adjusting the comparator's comparison threshold (i.e., the duty cycle control value), the delay required by the second voltage-controlled delay line 240 will also always be kept within the range of 0 to M-1, which can also reduce the delay line length requirement by 25%.

[0082] As an example and not a limitation, since the control voltage Vctrl generated by the delay phase-locked loop module 100 simultaneously adjusts the delay amount of each delay block in the reference delay line 110, the first voltage-controlled delay line 230 and the second voltage-controlled delay line 240, the delay amount of each delay block can remain consistent when the process, temperature and operating voltage change, thereby ensuring the accuracy and stability of the pulse width modulation signal.

[0083] In some embodiments of this application, a switching power supply is also provided, which includes the signal generation circuit described in the above embodiments.

[0084] Specifically, the signal generation circuit generates a pulse width modulation (PWM) signal, which drives the switching devices in the switching power supply. It's easy to understand that the duty cycle and period of the PWM signal determine the output voltage of the switching power supply. The high-precision PWM signal generated by the signal generation circuit improves the output voltage resolution of the switching power supply.

[0085] In some embodiments of this application, the switching power supply further includes a switching device, an inductor, a capacitor, and a load. Specifically, the output terminal of the signal generation circuit is connected to the control terminal of the switching device, and the pulse width modulation signal output by the signal generation circuit controls the switching device to turn on and off. It is easy to understand that by controlling the switching device to turn on and off, the input voltage is converted into the required output voltage to supply the load.

[0086] By way of example and not limitation, the switching power supply can be a buck switching power supply, a boost switching power supply, or a buck-boost switching power supply. In some embodiments of this application, the signal generation circuit can be applied to the pulse width modulation signal generation module in the digital power chip, serving as a key module of the digital power chip.

[0087] Please see Figure 7 , Figure 7 This is a schematic flowchart of a signal generation method provided by an embodiment of the present invention.

[0088] In some embodiments of this application, the signal generation method includes steps S100 to S700.

[0089] Step S100: Generate a control voltage through a delay phase-locked loop based on the reference clock signal.

[0090] In some embodiments of this application, a delay phase-locked loop (PLL) receives a reference clock signal and generates a stable control voltage through phase-locked regulation. Specifically, the control voltage is used to adjust the delay of the subsequent voltage-controlled delay line. It is easy to understand that the control voltage generated by the PLL ensures the stability of the delay of the voltage-controlled delay line, unaffected by factors such as process technology and temperature.

[0091] Step S200: Counting is performed under the drive of the reference clock signal, and the upper limit of the count is determined by a preset period control value.

[0092] In some embodiments of this application, the count value increments in each clock cycle of the reference clock signal. Specifically, when the count value reaches the upper limit, the count value is reset to zero, and a new round of counting begins. It is easy to understand that the period control value determines the range of the count, thereby affecting the period of the pulse width modulation signal.

[0093] Step S300: When the count value reaches the cycle start value, output the cycle trigger signal.

[0094] In some embodiments of this application, a count value is compared with a period start value, and a period trigger signal is output when the count value equals the period start value. Specifically, the period start value is zero. It is easy to understand that the period trigger signal marks the beginning of the pulse width modulation signal period.

[0095] Step S400: Compare the count value with the preset duty cycle control value and output the duty cycle trigger signal.

[0096] In some embodiments of this application, the count value is compared with the high-order bit of the duty cycle control value. When the count value equals the high-order bit of the duty cycle control value, a duty cycle trigger signal is output. Specifically, the duty cycle trigger signal is used to control the pulse width modulation signal to transition from a high level to a low level. It is easy to understand that the duty cycle control value determines the duty cycle of the pulse width modulation signal.

[0097] Step S500: Delay the periodic trigger signal through the first voltage-controlled delay line, and delay the duty cycle trigger signal through the second voltage-controlled delay line.

[0098] In some embodiments of this application, the delay amounts of both the first and second voltage-controlled delay lines are adjusted by a control voltage. Specifically, the periodic trigger signal is delayed by the first voltage-controlled delay line, and the duty cycle trigger signal is delayed by the second voltage-controlled delay line. It is easy to understand that since both the first and second voltage-controlled delay lines are adjusted by the same control voltage, the consistency and stability of the delay amounts can be guaranteed.

[0099] Step S600: Select the delay output of the first voltage-controlled delay line based on the low value of the period control value, and select the delay output of the second voltage-controlled delay line based on the low value of the duty cycle control value.

[0100] In some embodiments of this application, both the period control value and the duty cycle control value include a high-order bit and a low-order bit. Specifically, based on the low-order bit of the period control value, a corresponding delay output is selected from multiple delay outputs of the first voltage-controlled delay line; based on the low-order bit of the duty cycle control value, a corresponding delay output is selected from multiple delay outputs of the second voltage-controlled delay line. It is easy to understand that the low-order bit determines the selected delay amount, thereby achieving high-precision delay control.

[0101] Step S700: Generate a pulse width modulation signal based on the delayed periodic trigger signal and the duty cycle trigger signal.

[0102] In some embodiments of this application, when a delayed periodic trigger signal is received, the pulse width modulation signal outputs a high level; when a delayed duty cycle trigger signal is received, the pulse width modulation signal outputs a low level. Specifically, the delayed periodic trigger signal and the duty cycle trigger signal are combined to generate a pulse width modulation signal with high-precision duty cycle and period.

[0103] In some embodiments of this application, the upper limit of the count is adjusted based on whether the cumulative delay of the first voltage-controlled delay line reaches a preset threshold, so as to reduce the maximum delay required by the first voltage-controlled delay line.

[0104] Specifically, the cumulative delay is calculated as follows: cnt_d = (cnt_d_last + ARRn) % M where cnt_d is the current cumulative delay amount, cnt_d_last is the cumulative delay amount in the previous cycle, ARRn is the low-order value of the cycle control value, and M is the modulus of the low-order value.

[0105] In some embodiments of the present application, the adjustment method of the counting upper limit value is as follows: When cnt_d_last + ARRn ≥ M, the counting upper limit value is ARRN + 1; When cnt_d_last + ARRn < M, the counting upper limit value is ARRN; where ARRN is the high-order value of the cycle control value.

[0106] By dynamically adjusting the counting upper limit value, the cumulative delay amount always remains within the range of 0 to M - 1, thereby reducing the maximum delay amount required by the first voltage-controlled delay line. By way of example and not limitation, the maximum delay amount required by the first voltage-controlled delay line is (M - 1) / M times the reference clock period; by dynamically adjusting the duty cycle control value of the comparator, the delay amount required by the second voltage-controlled delay line 240 will also always remain within the range of 0 to M - 1.

[0107] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other variations in different aspects of the present application as described above. For the sake of brevity, they are not provided in detail; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal generation circuit, characterized in that, include: The delay phase-locked loop module is used to generate control voltage based on a reference clock signal; The control voltage is used to ensure the delay of all delay lines; A counting unit is used to count under the drive of the reference clock signal; the upper limit of the counting unit is determined by a preset period control value. The comparison unit is used to output a periodic trigger signal when the count value reaches the period start value; And compare the count value with a preset duty cycle control value, and output a duty cycle trigger signal; A first voltage-controlled delay line, the delay of which is adjusted by the control voltage, is used to delay the periodic trigger signal. The second voltage-controlled delay line, the delay of which is adjusted by the control voltage, is used to delay the duty cycle trigger signal. The gating unit is used to select the corresponding delay output of the first voltage-controlled delay line according to the low-order value of the period control value, and to select the corresponding delay output of the second voltage-controlled delay line according to the low-order value of the duty cycle control value. The output logic unit is used to generate a pulse width modulation signal based on the delayed periodic trigger signal and the duty cycle trigger signal. The upper limit of the count is adjusted according to whether the cumulative delay of the first voltage-controlled delay line reaches a preset threshold, so as to reduce the maximum delay required by the first voltage-controlled delay line. The duty cycle control value is calculated based on the cumulative delay of the first voltage-controlled delay line and the low-order value of the duty cycle control value, in order to reduce the maximum delay required by the second voltage-controlled delay line.

2. The circuit according to claim 1, characterized in that, The delay phase-locked loop module includes a reference delay line, which is connected to the reference clock signal and is used to generate the control voltage through phase-locked regulation.

3. The circuit according to claim 1, characterized in that, The comparison unit includes: A first comparator is used to compare the count value with the period start value and output the period trigger signal; the period start value is zero. The second comparator is used to compare the count value with the high-order value of the duty cycle control value and output the duty cycle trigger signal.

4. The circuit according to claim 1, characterized in that, Both the period control value and the duty cycle control value include a high-order value and a low-order value, wherein the high-order value is used to control the comparison operation of the comparison unit, and the low-order value is used to control the gating of the gating unit.

5. The circuit according to claim 1, characterized in that, The gating unit includes: The first selector is used to select the delay output of the corresponding voltage-controlled delay line according to the low-order value of the periodic control value; The second selector is used to select the delay output of the corresponding voltage-controlled delay line based on the low-order value of the duty cycle control value.

6. The circuit according to claim 1, characterized in that, The output logic unit is an SR flip-flop. The set terminal of the SR flip-flop receives a delayed periodic trigger signal, and the reset terminal of the SR flip-flop receives a delayed duty cycle trigger signal.

7. The circuit according to claim 1, characterized in that, Both the first and second voltage-controlled delay lines are composed of multiple delay blocks connected in series, and the delay of each delay block is adjusted by the control voltage.

8. The circuit according to claim 1, characterized in that, The cumulative delay is calculated as follows: cnt_d = (cnt_d_last + ARRn) % M; Among them, cnt_d is the current cumulative delay amount, cnt_d_last is the cumulative delay amount of the previous cycle, ARRn is the low-order value of the cycle control value, M is the modulus of the low-order value, and % is the modulo operation symbol.

9. The circuit according to claim 8, characterized in that, The adjustment method of the counting upper limit value is as follows: When cnt_d_last + ARRn ≥ M, the counting upper limit value is ARRN + 1; When cnt_d_last + ARRn < M, the counting upper limit value is ARRN; Among them, ARRN is the high-order value of the cycle control value.

10. The circuit according to claim 8, characterized in that, The maximum delay amounts required by the first voltage-controlled delay line and the second voltage-controlled delay line are (M - 1) / M times the reference clock period.

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