Power control circuit and input / output circuitry

Abstract

This application discloses a power control circuit and an input / output circuit system. The power control circuit generates intermediate voltages with different voltage values ​​through the coordinated operation of a bias current generation module and a voltage divider generation module. The power supply terminal of the first-level logic unit of the multi-level logic conversion module is coupled to the intermediate voltage terminal corresponding to the minimum intermediate voltage. This ensures that the voltage difference between the intermediate voltage terminal and the first voltage domain is less than the threshold voltage of the input MOS transistor in the first-level logic unit. This avoids the possibility of a large static leakage current after the first power domain is powered on, enabling the circuit to maintain a low static power consumption state and solving the problems of uncertain output signals and excessive static power consumption in related technologies.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a power control circuit and an input / output circuit system. Background Technology

[0002] Input / output (I / O) interface circuits in integrated circuits typically handle signal transmission between internal and external circuitry. Internal circuitry usually uses lower supply voltages (e.g., 1.8V or lower), while external circuitry typically uses higher supply voltages (e.g., 3.3V or 5V). To achieve signal transmission at different voltages, the portion of the I / O circuitry connected to the internal chip uses the internal voltage; this area is typically the Core power domain. The portion of the I / O circuitry connected to the external chip uses the external circuitry voltage; this area is typically called the I / O power domain. Since I / O circuitry exists in both power domains, it requires two independent power supplies: the I / O power supply and the Core power supply. In practical applications, the circuit may encounter situations where the I / O power supply is powered on while the Core power supply is not powered on (or is floating).

[0003] For the output circuit of the I / O circuit, the circuit located in the Core power domain generates logic signals based on the signals inside the chip and transmits them to the I / O power domain, thereby sending the correct signals to the external circuitry. Under this power condition, because the Core power domain cannot generate the correct logic control signals, it may cause incorrect I / O output states, leading to malfunctions in externally connected devices; or it may result in intermediate signals (undefined states) between high and low levels within the I / O power domain, which can cause significant static leakage current in subsequent circuits. Therefore, a solution is needed to address these issues. Summary of the Invention

[0004] The purpose of this application is to provide a power control circuit and an input / output circuit system to solve the problems of uncertain output signals and excessive static power consumption of IO circuits in related technologies.

[0005] According to a first aspect of this application, embodiments of this application provide a power control circuit for an integrated circuit having a first power domain and a second power domain, wherein the voltage of the second power domain is higher than the voltage of the first power domain, the power control circuit comprising: A bias current generation module, coupled between the second power domain and ground, is used to generate a reference current based on the voltage of the second power domain and to suppress power voltage fluctuations. The voltage divider generation module is coupled to the bias current generation module to form a current mirror relationship. The voltage divider generation module is used to replicate the reference current proportionally and convert the replicated current into multiple intermediate voltages. A multi-level logic conversion module includes multiple cascaded logic units. The power supply terminals of the multiple logic units are respectively coupled to multiple intermediate voltage terminals of the voltage divider generation module to receive multiple intermediate voltages output by the voltage divider generation module. The power supply terminal of the first-level logic unit of the multi-level logic conversion module is coupled to the intermediate voltage terminal corresponding to the minimum intermediate voltage, and the voltage difference between the intermediate voltage terminal corresponding to the minimum intermediate voltage and the first power supply domain is less than the threshold voltage of the input MOS transistor in the first-level logic unit.

[0006] In some possible implementations, the bias current generating module includes a MOS transistor unit connected in a common-source, common-gate configuration and a first resistor; the MOS transistor unit includes a first branch and a second branch coupled to each other; the first resistor is connected in series between the second branch and ground for feedback regulation of the current in the second branch.

[0007] In some possible implementations, the first branch includes a second resistor and a plurality of first MOSFETs connected in series, the second resistor being connected in series between two adjacent first MOSFETs; the second branch includes a third resistor and a plurality of second MOSFETs connected in series, the second MOSFETs being connected in series between two adjacent second MOSFETs; the second resistor and the third resistor are used to adjust the bias voltage of the connection node between the MOSFETs.

[0008] In some possible implementations, the voltage divider generation module includes: a replica transistor unit and a voltage divider resistor unit; the replica transistor unit and the bias current generation module form a current mirror for generating a mirrored current; the voltage divider resistor unit is connected in series between the replica transistor unit and ground, and the mirrored current flows through the voltage divider resistor unit, generating multiple intermediate voltages with different voltage values ​​at different nodes of the voltage divider resistor unit.

[0009] In some possible implementations, the replica transistor unit includes a first replica transistor and a second replica transistor connected in series; the first replica transistor and the second replica transistor form a common source and common gate structure with the corresponding MOS transistor in the bias current generation module.

[0010] In some possible implementations, the power control circuit further includes: a startup control module coupled to the bias current generation module, used to provide a startup current to the bias current generation module during the circuit power-on initialization phase; the startup control module includes a capacitor detection unit and a startup logic unit, the capacitor detection unit is used to detect the power-on transient of the second power domain; the startup logic unit is coupled to the output terminal of the capacitor detection unit and the first power domain respectively, used to control the on / off state of the startup current according to the output of the capacitor detection unit and the voltage state of the first power domain.

[0011] In some possible implementations, the startup logic unit includes: a first MOSFET and a second MOSFET; the first MOSFET is connected in series between the second power domain and a common node, and the gate of the first MOSFET is coupled to the capacitor detection unit; the second MOSFET is connected in series between the common node and ground, and the gate of the second MOSFET is coupled to the first power domain; wherein, during the power-on process of the first power domain, when the first capacitor of the capacitor detection unit is charged, the current driving capability of the first MOSFET decreases, and when the current driving capability of the first MOSFET is weaker than the current driving capability of the second MOSFET, the voltage of the common node is pulled down to ground potential.

[0012] In some possible implementations, the multi-stage logic conversion module includes: a first-stage inverter to an Nth-stage inverter cascaded sequentially, where N is an integer greater than or equal to 2; the power supply terminal of the first-stage inverter is coupled to a first intermediate voltage terminal with the lowest voltage value, and the power supply terminals of the remaining inverters in the multi-stage logic conversion module are respectively coupled to intermediate voltage terminals with sequentially increasing voltage values ​​or to the voltage terminals of the second power supply domain.

[0013] In some possible implementations, the power control circuit further includes a Schmitt trigger module coupled to the multi-level logic conversion module, used to filter signal noise during the power-on process of the first power domain and output a power status control signal.

[0014] According to a second aspect of this application, embodiments of this application provide an input / output circuit system, comprising: The output drive circuit has a control input terminal and an output signal terminal; As described in any embodiment of this application, the output terminal of the power control circuit is coupled to the control input terminal of the output drive circuit. When the second power domain is powered on and the first power domain is not powered on, the power control circuit outputs a power status control signal to control the output drive circuit to lock the output signal terminal in a certain state.

[0015] This application provides a power control circuit and an input / output circuit system. Through the coordinated operation of a bias current generation module and a voltage divider generation module, intermediate voltages with different voltage values ​​are generated. The power supply terminal of the first-stage logic unit of the multi-stage logic conversion module is coupled to the intermediate voltage terminal corresponding to the minimum intermediate voltage. This ensures that the voltage difference between the intermediate voltage terminal and the first voltage domain is less than the threshold voltage of the input MOS transistor in the first-stage logic unit. This avoids the possibility of a large static leakage current after the first power domain is powered on, enabling the circuit to maintain a low static power consumption state and solving the problems of uncertain output signals and excessive static power consumption in related technologies. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a circuit diagram of a power control circuit for a related technology.

[0018] Figure 2 for Figure 1 A schematic diagram showing the specific connection of the series PMOS transistors.

[0019] Figure 3 This is a circuit diagram of the power control circuit in one embodiment of this application.

[0020] Figure 4 This is a partial circuit diagram of the power control circuit in one embodiment of this application.

[0021] Figure 5 This is a schematic diagram of an input / output circuit system in one embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] In integrated circuit design, input / output (I / O) circuits typically have an internal power domain (Core power domain) and an external power domain (I / O power domain). The voltage of the Core power domain (VDD, e.g., 1.8V) is usually lower than the voltage of the I / O power domain (VDDPST, e.g., 3.3V or 5V). When the I / O circuit operates in output mode, its control logic is generated by the Core power domain, and the output signal state is controlled by the output driver circuitry of the I / O power domain.

[0024] However, during system power-up, it often happens that the I / O power domain is powered on while the Core power domain is not. In this case, the Core power domain cannot provide effective control signals, causing the following problems: on the one hand, the output signal terminal (PAD) of the I / O circuit may be in an uncertain state, causing abnormal function of downstream circuits; on the other hand, the MOSFET device driving the PAD may be in a subthreshold conducting state, generating leakage current and increasing power consumption.

[0025] To solve the above problems, the conventional solution uses a power control circuit 1' (POC), which includes an inverter 10' and a Schmitt trigger 30' (see...). Figure 1 When the Core power domain is not powered on (VDD=0, where 0 represents a logic low level), the POC output is high (POC=1), and the I / O circuit output is locked to a defined state (e.g., high impedance). When the Core power domain is powered on (VDD=1, where 1 represents a logic high level), the POC output is low (POC=0), and the I / O circuit outputs a signal normally. It should be noted that the PMOS transistor in inverter 10'... Figure 1 The detailed structure is not shown in the diagram, but is symbolically represented by boxes. However, this scheme has the following problem: the voltage difference between the Core power domain and the IO power domain is large (e.g., VDD=1.8V, VDDPST=5V), and the PMOS transistor in inverter 10' cannot be completely turned off. When VDD is high (1.8V here), the gate of the PMOS transistor is connected to VDD (1.8V), and the source of the PMOS transistor is connected to VDDPST (5V), therefore the gate-source voltage V... GS =1.8V - 5V = -3.2V; because V GS =3.2V is still less than the threshold voltage -0.7V, so the PMOS transistor cannot be completely turned off and is still conducting. At this time, the NMOS transistor is also conducting because its gate voltage (1.8V) is greater than its threshold voltage, thus forming a leakage path from VDDPST to ground and generating leakage current.

[0026] To address the aforementioned leakage current issue, related technologies have proposed a solution involving connecting a large number of PMOS transistors in series, such as... Figure 1 As shown in module 11'. Figure 2The diagram illustrates the specific structure of multiple PMOS transistors connected in series in module 11'. Label G represents the common gate of the series-connected PMOS transistors, label D represents the drain of the first PMOS transistor, label S represents the source of the last PMOS transistor, and label B represents the common substrate of the series-connected PMOS transistors. Leakage current is reduced by increasing the equivalent resistance; exemplarily, 100 PMOS transistors are connected in series. However, this approach presents the following problems: a large number of series-connected PMOS transistors occupy a large chip area, and the dense layout makes signal routing very complex; a large number of series-connected PMOS transistors introduce large parasitic capacitances and resistances, reducing circuit response speed; furthermore, manufacturing deviations can easily cause uneven threshold voltage distribution among the series-connected PMOS transistors.

[0027] Another related technology uses a scheme that employs multiple diodes connected in series to divide the voltage, thereby raising the gate voltage by generating an intermediate voltage to reduce the gate-source voltage difference. Although this scheme can save a significant amount of area compared to connecting a large number of PMOS transistors in series, it introduces new technical problems: because the node voltages of each diode are different, isolation areas need to be reserved in the layout design to prevent leakage between diodes, making it difficult to further reduce the circuit area.

[0028] Another related technology uses MOSFETs instead of diodes and performs series voltage division. However, this approach also has limitations: the intermediate voltage it generates depends on the conduction characteristics of the MOSFET (i.e., the threshold voltage), meaning its voltage regulation is fixed and can only vary in integer multiples of the threshold voltage (approximately 0.7V). In actual systems, the voltage value of the internal power domain (Core VDD) is often set to specific values ​​(such as 1.2V, 1.1V, or 0.9V) according to requirements, and these values ​​are rarely exactly integer multiples of the threshold voltage. Therefore, the intermediate voltage generated in this approach is difficult to precisely match with the actual voltage of the internal power domain, resulting in a large voltage difference across the gate and source of the input MOSFET, preventing it from being in an ideal turn-off state, thus generating leakage current and failing to meet the requirements for ultra-low static power consumption.

[0029] Based on the above situations, this application proposes a power control circuit that generates an intermediate voltage with a precisely configurable potential through bias current and voltage divider resistors. This not only solves the leakage problem caused by insufficient voltage matching accuracy in related technologies, but also avoids complex layout isolation requirements, thereby achieving ultra-low static power consumption and high-precision power control in a smaller area.

[0030] The power control circuit of this application will be described in detail below with reference to the accompanying drawings.

[0031] See Figure 3 and Figure 4This application provides a power control circuit in one embodiment, applicable to integrated circuits having a first power domain and a second power domain, wherein the voltage of the second power domain is higher than the voltage of the first power domain. In this embodiment, the first power domain is an internal power domain (Core power domain), and the second power domain is an external power domain (IO power domain). The voltage of the Core power domain is denoted as VDD, for example, 1.8V, and the voltage of the IO power domain is denoted as VDDPST, for example, 5V.

[0032] like Figure 3 and Figure 4 As shown in the embodiments of this application, the power control circuit may include: a bias current generation module 10, a voltage divider generation module 20, and a multi-level logic conversion module 40.

[0033] Specifically, the bias current generation module 10 is coupled between the IO power supply domain and ground. The bias current generation module 10 employs a self-biasing circuit, which is used to generate a reference current based on the voltage of the IO power supply domain and also to suppress power supply voltage fluctuations.

[0034] In this embodiment, the bias current generation module 10 may include a MOS transistor unit connected by a common source and a common gate and a first resistor R1. The MOS transistor unit (not shown in the figure) may include a first branch 11 and a second branch 12 coupled to each other. By setting these two symmetrical branches, the MOS transistor devices on each branch can restrain each other during operation, thereby ensuring the stability of the circuit bias point.

[0035] Specifically, in this embodiment, the first branch 11 may include multiple MOSFETs M21, M22, M25 and M26 connected in series. The second branch 12 may include multiple MOSFETs M23, M24, M27 and M28 connected in series.

[0036] Specifically, the source of MOSFET M21 is coupled to the I / O power supply voltage VDDPST, the drain of MOSFET M21 is coupled to the source of MOSFET M22, and the gate of MOSFET M21 is coupled to the gate of MOSFET M23. The drain of MOSFET M22 is coupled to the drain of MOSFET M25, and the gate of MOSFET M22 is coupled to the gate of MOSFET M24. The source of MOSFET M25 is coupled to the drain of MOSFET M26, and the gate of MOSFET M25 is coupled to the gate of MOSFET M27. The source of MOSFET M26 is coupled to ground potential VSS, and the gate of MOSFET M26 is coupled to the gate of MOSFET M28.

[0037] Similarly, the source of MOSFET M23 is coupled to the I / O power supply voltage VDDPST, and the drain of MOSFET M23 is coupled to the source of MOSFET M24. The drain of MOSFET M24 is coupled to the drain of MOSFET M27. The source of MOSFET M27 is coupled to the drain of MOSFET M28. The source of MOSFET M28 is coupled to ground potential VSS.

[0038] It should be noted that the bias current generation module 10 of this application uses multiple sets of MOSFET devices connected in series (e.g., MOSFET M21 and MOSFET M22, MOSFET M25 and MOSFET M26, etc.) and applies different gate bias voltages to facilitate layout matching and reduce device mismatch caused by process errors.

[0039] In this embodiment, the first resistor R1 of the bias current generation module 10 is connected in series between the second branch 12 and ground. When the voltage of the IO power supply domain fluctuates, the voltage of each connection node inside the circuit (the connection node between MOSFETs M21 and M23, M22 and M24, M25 and M27, and M26 and M28) will change accordingly, which may cause the current flowing through each branch to change. Therefore, by using the first resistor R1 to provide feedback regulation of the current in the second branch 12, the amplitude of the branch current change can be reduced, thereby enhancing the stability of the circuit under power fluctuation conditions.

[0040] In some embodiments, the first branch 11 of the bias current generating module 10 may further include a second resistor R2, and the second branch 12 may include a third resistor R3.

[0041] The second resistor R2 is connected in series between two adjacent first MOSFETs (e.g., MOSFET M22 and MOSFET M25). The third resistor R3 is connected in series between two adjacent second MOSFETs (e.g., MOSFET M24 and MOSFET M27).

[0042] Specifically, one end of the second resistor R2 is coupled to the drain of MOSFET M22, the gate of MOSFET M25, and the gate of MOSFET M27, and the other end is coupled to the drain of MOSFET M25, the gate of MOSFET M26, and the gate of MOSFET M28. One end of the third resistor R3 is coupled to the drain of MOSFET M24, the gate of MOSFET M21, and the gate of MOSFET M23, and the other end of the third resistor R3 is coupled to the drain of MOSFET M27, the gate of MOSFET M22, and the gate of MOSFET M24.

[0043] In this embodiment, by configuring the resistance values ​​of the second resistor R2 and the third resistor R3 in the bias current generation module 10, a suitable bias voltage can be generated inside the bias current generation module 10 to adjust the voltage (i.e., gate voltage) of the connection nodes between MOSFETs M21 and M23, M22 and M24, M25 and M27, and M26 and M28. Based on these set connection node voltages, the aforementioned MOSFETs can operate stably in the saturation region, thereby increasing the output impedance of the circuit and improving the stability of the circuit. Furthermore, by reasonably configuring the resistance values ​​of the second resistor R2 and the third resistor R3, the magnitude of the bias current output by the bias current generation module 10 is set, thereby providing a reference current for the circuit that meets the design requirements.

[0044] Continue reading Figure 4 In this embodiment, the voltage divider generation module 20 is coupled to the bias current generation module 10 to form a current mirror relationship, which is used to replicate the reference current proportionally, and convert the replicated reference current into multiple intermediate voltages with different voltage values ​​through the voltage divider resistor unit 22.

[0045] In this embodiment, the voltage divider generation module 20 may include a replica transistor unit 21 and a voltage divider resistor unit 22. The replica transistor unit 21 and the aforementioned bias current generation module 10 form a current mirror to generate a mirrored current.

[0046] Specifically, the replication unit 21 may include a first replication transistor M29 and a second replication transistor M30 connected in series. The first replication transistor M29 and the second replication transistor M30 form a common-source, common-gate mirror mapping relationship with the corresponding MOS transistors in the bias current generation module 10. The source of the first replication transistor M29 is coupled to the IO power domain voltage terminal VDDPST, and the gate of the first replication transistor M29 is coupled to the gate of MOS transistor M21, the gate of MOS transistor M23, one end of the third resistor R3, and the drain of MOS transistor M24. The drain of the first replication transistor M29 is coupled to the source of the second replication transistor M30. The gate of the second replication transistor M30 is coupled to the drain of MOS transistor M24, one end of the third resistor R3, the gate of MOS transistor M21, and the gate of MOS transistor M23. The drain of the second replication transistor M30 is coupled to the voltage divider resistor unit 22. Based on the above connection relationship, the first replication transistor M29 and the second replication transistor M30 replicate the gate voltage of the corresponding MOS transistors in the bias current generation module 10 and share the same power supply voltage. Therefore, their gate-source voltages are exactly the same, ensuring that both the first replica transistor M29 and the second replica transistor M30 operate stably in the saturation region. Based on this, the reference current (e.g., 50nA) generated by the bias current generation module 10 can be replicated and amplified as needed (e.g., outputting 100nA) and transmitted to the subsequent voltage divider resistor unit 22.

[0047] In this embodiment, the voltage divider resistor unit 22 of the voltage divider generation module 20 is connected in series between the replica tube unit 21 and ground. The mirror current flows through the voltage divider resistor unit 22, generating multiple intermediate voltages with different voltage values ​​at different nodes of the voltage divider resistor unit 22.

[0048] Specifically, the voltage divider resistor unit 22 may include a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7 connected in series.

[0049] One end of the fourth resistor R4 is coupled to the drain of the second replica transistor M30. One end of the seventh resistor R7 is coupled to ground potential VSS. The voltage divider resistor unit 22 includes three output nodes: the first output node, the second output node, and the third output node. The first output node (corresponding to...) Figure 4 The labeled V2 is coupled to the coupling point of the sixth resistor R6 and the fifth resistor R5. The second output node (corresponding to...) Figure 4 The labeled V3 is coupled to the coupling point of the fifth resistor R5 and the fourth resistor R4. The third output node (corresponding to...) Figure 4 The junction (shown as V4) is coupled to the drain of the fourth resistor R4 and the second replica transistor M30, and this junction has the highest potential.

[0050] Therefore, in this embodiment, by reasonably setting the resistance values ​​of each resistor in the voltage divider resistor unit 22, the voltage difference between each output node of the voltage divider resistor unit 22 can be accurately controlled. For example, if the series resistor is set to a specific value (e.g., 10MΩ) and a mirror current of 100nA is applied, according to Ohm's law, a fixed voltage drop (e.g., 1V) will be generated across each resistor. Based on the voltage divider relationship (a 2V potential is generated to ground through the sixth resistor R6 and the seventh resistor R7, and each is boosted by 1V through the fifth resistor R5 and the fourth resistor R4), intermediate voltages of 4V, 3V, and 2V can be obtained at the three output nodes (V4, V3, V2), respectively, thereby providing the required power supply for the subsequent multi-stage logic conversion module 40.

[0051] Continue reading Figure 4 In this embodiment, the power control circuit may further include a startup control module 30. The startup control module 30 is coupled to the bias current generation module 10 and is used to provide a startup current to the bias current generation module 10 during the power-on initialization phase of the circuit.

[0052] In this embodiment, the startup control module 30 may include a capacitor detection unit 31 and a startup logic unit 32. The capacitor detection unit 31 is used to detect the power-on transient of the second power domain (i.e., the IO power domain). The startup logic unit 32 is coupled to the output terminal of the capacitor detection unit 31 and the first power domain (i.e., the Core power domain), and is used to control the on / off state of the startup current according to the output of the capacitor detection unit 31 and the voltage state of the first power domain.

[0053] Specifically, the capacitance detection unit 31 may include a series-connected MOSFET M15 and a first capacitor C0. The source of the MOSFET M15 is coupled to the IO power supply voltage terminal VDDPST, and the gate of the MOSFET M15 is coupled to the drain of the MOSFET M15. The drain of the MOSFET M15 is coupled to one end of the first capacitor C0, and the other end of the first capacitor C0 is coupled to ground potential VSS.

[0054] In this embodiment, the startup logic unit 32 of the startup control module 30 may include a first MOS transistor M16, a second MOS transistor M18, a third MOS transistor M17, a fourth MOS transistor M19, and a fifth MOS transistor M20.

[0055] In this configuration, the first MOSFET M16 is connected in series between the IO power supply domain (VDDPST) and a common node P (the coupling point between the first MOSFET M16 and the second MOSFET M18). The gate of the first MOSFET M16 is coupled to the drain of the MOSFET M15 in the capacitor detection unit 31. The second MOSFET M18 is connected in series between the aforementioned common node P and ground. The gate of the second MOSFET M18 is coupled to the core power supply domain (VDD). The source of the third MOSFET M17 is coupled to the IO power supply voltage terminal VDDPST. The gate of the third MOSFET M17 is coupled to the gate of the fourth MOSFET M19 and to the coupling point between the first MOSFET M16 and the second MOSFET M18. The drain of the third MOSFET M17 is coupled to the source of the fourth MOSFET M19. The drain of the fourth MOSFET M19 is coupled to ground potential VSS. The source of the fifth MOSFET M20 is coupled to the IO power supply voltage terminal VDDPST, the gate of the fifth MOSFET M20 is coupled to the coupling point of the third MOSFET M17 and the fourth MOSFET M19, and the drain of the fifth MOSFET M20 is coupled to one end of the second resistor R2 in the bias current generation module 10.

[0056] In this embodiment, during the power-on process of the first power domain, when the first capacitor C0 of the capacitor detection unit 31 is charged, the current driving capability of the first MOS transistor M16 is reduced. When the current driving capability of the first MOS transistor M16 is weaker than the current driving capability of the second MOS transistor M18, the voltage of the common node P is pulled down to ground potential.

[0057] In this embodiment, based on the above configuration, the operating logic of the start control module 30 under different power states is as follows: Scenario 1: The IO power domain is powered on, but the Core power domain is not powered on (i.e., VDDPST=1, VDD=0).

[0058] When the IO power domain is first powered on (VDDPST goes high) and the Core power domain is not yet powered (VDD remains low), due to the presence of the first capacitor C0, the voltage at the detection node Q (i.e., the coupling point between MOSFET M15 and the first capacitor C0) is initially at ground potential (0V), causing the first MOSFET M16 to be in the on state; while since VDD is low, the second MOSFET M18 is in the off state. Therefore, the potential of the common node P (i.e., the coupling point between the first MOSFET M16 and the second MOSFET M18) is pulled high. This high-level signal is processed by an inverter composed of the third MOSFET M17 and the fourth MOSFET M19, converted into a low-level signal, and applied to the gate of the fifth MOSFET M20, causing the fifth MOSFET M20 to be turned on. At this time, the fifth MOSFET M20 injects startup current into the bias current generation module 10, enabling the bias current generation module 10 to avoid a zero-current condition and complete the startup. As power-on time progresses, the IO power domain continuously charges the first capacitor C0 through MOSFET M15, causing the potential of the detection node Q to gradually rise. When the potential of the detection node Q rises to a certain level, the first MOSFET M16 will turn off. At this time, since both the first MOSFET M16 and the second MOSFET M18 are in the off state, the common node P may be in a floating state (i.e., an indeterminate state), but this will not cause the bias current generation module 10 to re-enter the zero operating point. It should be noted that the overall potential of the output voltage can be raised by adjusting the device size (width-to-length ratio). Even if the input signal of the Core power domain itself is zero at this time, this potential will not affect the normal logic function of the circuit; since the input of the multi-stage logic conversion module 40 is zero at this time, there is no additional quiescent current.

[0059] Scenario 2: The process and steady state of both the IO power domain and the core power domain being powered on (i.e., VDDPST=1, VDD=1).

[0060] In the initial stage of circuit operation, the first capacitor C0 has not yet completed charging, resulting in a very small gate voltage (i.e., an extremely negative gate-source voltage) for the first MOSFET M16, thus exhibiting a strong conduction (pull-up) tendency. At this time, the Core power domain is high, and the second MOSFET M18 is in the conducting state (pull-down). During this transient process, the pull-up capability of the first MOSFET M16 is stronger than the pull-down capability of the second MOSFET M18, so the potential of the common node P is pulled high. This high-level signal causes the subsequent circuit to control the fifth MOSFET M20 to be in the conducting state, thereby breaking the zero-current (degeneracy) state that the bias current generation module 10 may have, and realizing circuit startup. Subsequently, as the first capacitor C0 continues to charge, the potential at point Q gradually increases, causing the gate voltage of the first MOSFET M16 to be raised to close to the power supply voltage, and its pull-up capability weakens accordingly. When the pull-up capability of the first MOSFET M16 is weaker than the pull-down capability of the second MOSFET M18, the potential of the common node P is flipped and pulled low to ground potential. The low-level signal is processed by an inverter composed of the third MOSFET M17 and the fourth MOSFET M19, and converted into a high-level signal, which is then output to the gate of the fifth MOSFET M20, causing the fifth MOSFET M20 to be in the off state. This indicates that after the circuit enters a stable operating mode, the start control module 30 automatically stops and no longer injects any current into the bias current generation module 10, thus allowing the circuit to operate stably relying on the bias current generation module 10.

[0061] Return to reference Figure 3 In this embodiment, the multi-level logic conversion module 40 may include multiple cascaded logic units 41. The power supply terminals of the multiple logic units 41 are respectively coupled to multiple intermediate voltage terminals of the voltage divider generation module 20 to receive multiple intermediate voltages output by the voltage divider generation module 20. The power supply terminal of the first-level logic unit 41 of the multi-level logic conversion module 40 is coupled to the intermediate voltage terminal corresponding to the minimum intermediate voltage (i.e., the first intermediate voltage terminal with the lowest voltage value), and the voltage difference between the intermediate voltage terminal corresponding to the minimum intermediate voltage and the first power supply domain is less than the threshold voltage of the input MOS transistor in the first-level logic unit 41. It should be noted that the input MOS transistor refers to the MOS transistor in the logic unit whose source is coupled to the power supply terminal (i.e., the intermediate voltage terminal) (e.g., [insert example MOS transistor]). Figure 3 (PMOS transistor M1 in the circuit). Logic unit 41 can be an inverter, a buffer, or a NAND gate.

[0062] In this embodiment, the multi-stage logic conversion module 40 may include inverters cascaded sequentially from the first stage 411 to the Nth stage, where N is an integer greater than or equal to 2. The power supply terminal of the first stage inverter 411 is coupled to a first intermediate voltage terminal with the lowest voltage value. The power supply terminals of the remaining stages of inverters in the multi-stage logic conversion module 40 are respectively coupled to intermediate voltage terminals with successively increasing voltage values ​​or to voltage terminals of the second power supply domain. It should be noted that when N is an integer multiple of 2, an inverting Schmitt trigger is required; otherwise, a forward Schmitt trigger is used.

[0063] Specifically, in this embodiment, the multi-level logic conversion module 40 may include a first-level inverter 411, a second-level inverter 412, a third-level inverter 413, a fourth-level inverter 414, and a fifth-level inverter 415 cascaded in sequence.

[0064] The first-stage inverter 411 may include MOSFETs M1 and M2 connected in series. The source of MOSFET M1 is coupled to a first intermediate voltage terminal (i.e., coupled to the first output node V2). The gates of MOSFET M1 and M2 are coupled to the core power domain voltage terminal VDD. The drain of MOSFET M1 is coupled to the drain of MOSFET M2. The source of MOSFET M2 is coupled to ground potential VSS.

[0065] In this embodiment, the second-stage inverter 412 may include MOSFETs M3 and M4 connected in series. The source of MOSFET M3 is coupled to the second intermediate voltage terminal (i.e., coupled to the second output node V3), the gate of MOSFET M3 is coupled to the gate of MOSFET M4, and coupled to the coupling point of MOSFETs M1 and M2, and the drain of MOSFET M3 is coupled to the drain of MOSFET M4. The source of MOSFET M4 is coupled to ground potential VSS.

[0066] In this embodiment, the third-stage inverter 413 may include MOSFETs M5 and M6 connected in series. The source of MOSFET M5 is coupled to the third intermediate voltage terminal (i.e., coupled to the third output node V4), the gate of MOSFET M5 is coupled to the gate of MOSFET M6, and coupled to the coupling point of MOSFETs M3 and M4, and the drain of MOSFET M5 is coupled to the drain of MOSFET M6. The source of MOSFET M6 is coupled to ground potential VSS.

[0067] In this embodiment, the fourth-stage inverter 414 may include MOSFETs M7 and M8 connected in series. The source of MOSFET M7 is coupled to the third intermediate voltage terminal (i.e., coupled to the third output node V4). The gate of MOSFET M7 is coupled to the gate of MOSFET M8 and to the coupling point of MOSFETs M5 and M6. The drain of MOSFET M7 is coupled to the drain of MOSFET M8. The source of MOSFET M8 is coupled to ground potential VSS.

[0068] In this embodiment, the fifth-stage inverter 415 may include MOSFETs M9 and M10 connected in series. The source of MOSFET M9 is coupled to the IO power supply voltage terminal VDDPST. The gate of MOSFET M9 is coupled to the gate of MOSFET M10 and to the coupling point of MOSFETs M7 and M8. The drain of MOSFET M9 is coupled to the drain of MOSFET M10. The source of MOSFET M10 is coupled to ground potential VSS.

[0069] Therefore, in this embodiment, the power supply terminals of the first-stage inverter 411 to the fourth-stage inverter 414 of the multi-stage logic conversion module 40 are coupled to the corresponding intermediate voltage terminals, and the power supply terminal of the fifth-stage inverter 415 (i.e., the final-stage inverter) is coupled to the second power domain voltage terminal (i.e., the IO power domain voltage terminal). Accordingly, this application utilizes multiple intermediate voltages to progressively raise the low-voltage signal of the Core power domain to the high-voltage signal of the IO power domain, thereby solving the leakage current problem caused by excessive voltage difference.

[0070] Continue reading Figure 3 In this embodiment, the power control circuit of this application may further include a Schmitt trigger module 50, which is coupled to a multi-level logic conversion module 40 to filter signal noise during the power-on process of the first power domain (i.e., the Core power domain) and output a power status control signal.

[0071] Specifically, the Schmitt trigger module 50 may include MOSFETs M11, M12, M13, M14, M31, and M32.

[0072] Specifically, the source of MOSFET M11 is coupled to the I / O power supply voltage VDDPST, and the drain of MOSFET M11 is coupled to the source of MOSFET M12. The drain of MOSFET M12 is coupled to the drain of MOSFET M13, the source of MOSFET M13 is coupled to the drain of MOSFET M14, and the source of MOSFET M14 is coupled to ground VSS. The gates of MOSFETs M11, M12, M13, and M14 are coupled to each other and to the coupling point of MOSFETs M9 and M10. The source of MOSFET M31 is coupled to the coupling point of MOSFETs M11 and M12, and the drain of MOSFET M31 is coupled to ground VSS. The drain of MOSFET M32 is coupled to the I / O power supply voltage terminal VDDPST, and the source of MOSFET M32 is coupled to the coupling point of MOSFETs M13 and M14. The gate of MOSFET M31 is coupled to the gate of MOSFET M32, and is also coupled to the coupling point of MOSFETs M12 and M13.

[0073] In some embodiments, the Schmitt trigger module 50 may further include MOSFETs M33 and M34 connected in series, such as Figure 3 As shown, MOSFETs M33 and M34 work together as an output buffer unit to enhance the driving capability of the output signal.

[0074] Specifically, the source of MOSFET M33 is coupled to the IO power supply voltage VDDPST, the drain of MOSFET M33 is coupled to the drain of MOSFET M34, and the source of MOSFET M34 is coupled to ground potential VSS. The gate of MOSFET M33 is coupled to the gate of MOSFET M34, and also coupled to the coupling point of MOSFETs M31 and M32. The coupling point of MOSFETs M33 and M34 can serve as the output terminal O1 of the Schmitt trigger module 50, used to output the power state control signal (i.e., POC).

[0075] In some embodiments, the power control circuit of this application may further include a protection module 60, such as... Figure 3 As shown. The protection module 60 may include at least one resistor. In this embodiment, the protection module 60 includes multiple resistors (R8, R9, R10), which are connected in parallel. Of course, in other embodiments, they may be connected in series. The input terminal of the protection module 60 is coupled to the Core power domain voltage terminal VDD, and the output terminal of the protection module 60 is coupled to the input terminal of the multi-stage logic conversion module 40 (here, the connection node between the gates of MOSFET M1 and MOSFET M2). The protection module 60 is used to prevent voltage transient surges and to prevent damage to the MOSFETs.

[0076] See Figure 5This application also provides an input / output circuit system 1000 (hereinafter referred to as the system). The system may include an output drive circuit 200 and a power control circuit 100. The output drive circuit 200 has a control input terminal 210 and an output signal terminal 220. The specific structure of the power control circuit 100 is as described above and will not be repeated here.

[0077] In this embodiment, the output terminal O1 (i.e., the output POC signal) of the Schmitt trigger module 50 of the power control circuit 100 is coupled to the control input terminal 210 of the output drive circuit 200. When the power state control signal (POC signal) of the power control circuit 100 is not powered on in the Core power domain and the IO power domain is powered on, it controls the output drive circuit 200 to lock the output signal terminal 220 to a determined state.

[0078] Specifically, the output drive circuit 200 is an interface circuit located between the IO power domain and the Core power domain, including an output stage circuit for driving high and low level signals at the PAD terminal. When the input / output circuit system 1000 is in the power-on process, if the IO power domain powers on before the Core power domain, the power control circuit 100 generates a power state control signal (i.e., a POC signal) through the coordinated operation of the bias current generation module 10, the voltage divider generation module 20, the multi-level logic conversion module 40, and the Schmitt trigger module 50. This signal is transmitted to the control input terminal 210 of the output drive circuit 200, locking the output signal terminal 220 (i.e., the PAD terminal) to a defined state.

[0079] In this embodiment, the input / output circuit system 1000 generates intermediate voltages with different voltage values ​​through the coordinated operation of the bias current generation module 10 and the voltage divider generation module 20 in the power control circuit 100. The power supply terminal of the first-level logic unit 41 of the multi-level logic conversion module 40 is coupled to the intermediate voltage terminal corresponding to the minimum intermediate voltage. This makes the voltage difference between the intermediate voltage terminal and the first voltage domain less than the threshold voltage of the input MOS transistor in the first-level logic unit 41. This avoids the possibility of a large static leakage current after the first power domain is powered on, enabling the circuit to maintain a low static power consumption state and solving the problems of uncertain output signals and excessive static power consumption of IO circuits in related technologies.

[0080] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.

[0081] It is understood that those skilled in the art, guided by the above embodiments, can combine various implementation methods in the above embodiments to obtain technical solutions with multiple implementation methods. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A power supply control circuit, characterized in that, For an integrated circuit having a first power domain and a second power domain, wherein the voltage of the second power domain is higher than the voltage of the first power domain, the power control circuit includes: A bias current generation module, coupled between the second power domain and ground, is used to generate a reference current based on the voltage of the second power domain and to suppress power voltage fluctuations. The voltage divider generation module is coupled to the bias current generation module to form a current mirror relationship. The voltage divider generation module is used to replicate the reference current proportionally and convert the replicated current into multiple intermediate voltages. A multi-level logic conversion module includes multiple cascaded logic units. The power supply terminals of the multiple logic units are respectively coupled to multiple intermediate voltage terminals of the voltage divider generation module to receive multiple intermediate voltages output by the voltage divider generation module. The power supply terminal of the first-level logic unit of the multi-level logic conversion module is coupled to the intermediate voltage terminal corresponding to the minimum intermediate voltage, and the voltage difference between the intermediate voltage terminal corresponding to the minimum intermediate voltage and the first power supply domain is less than the threshold voltage of the input MOS transistor in the first-level logic unit.

2. The power control circuit as described in claim 1, characterized in that, The bias current generation module includes a MOS transistor unit with common source and common gate connection and a first resistor; The MOS transistor unit includes a first branch and a second branch that are coupled to each other; the first resistor is connected in series between the second branch and ground, and is used to provide feedback regulation of the current in the second branch.

3. The power control circuit as described in claim 2, characterized in that, The first branch includes a second resistor and a plurality of first MOSFETs connected in series, wherein the second resistor is connected in series between two adjacent first MOSFETs; The second branch includes a third resistor and multiple second MOSFETs connected in series, with the second MOSFETs connected in series between two adjacent second MOSFETs; The second resistor and the third resistor are used to adjust the bias voltage of the connection node between the MOS transistors.

4. The power control circuit as described in claim 1, characterized in that, The voltage divider generation module includes: a replica transistor unit and a voltage divider resistor unit; The replica tube unit and the bias current generation module constitute a current mirror for generating a mirror current. The voltage divider resistor unit is connected in series between the replica tube unit and ground. The mirror current flows through the voltage divider resistor unit, generating multiple intermediate voltages with different voltage values ​​at different nodes of the voltage divider resistor unit.

5. The power control circuit as described in claim 4, characterized in that, The replication unit includes a first replication transistor and a second replication transistor connected in series; the first replication transistor and the second replication transistor form a common source and common gate structure with the corresponding MOS transistor in the bias current generation module.

6. The power control circuit as described in claim 1, characterized in that, Also includes: A startup control module is coupled to the bias current generation module and is used to provide startup current to the bias current generation module during the circuit power-on initialization phase. The startup control module includes a capacitor detection unit and a startup logic unit. The capacitor detection unit is used to detect the power-on transient of the second power domain. The startup logic unit is coupled to the output terminal of the capacitor detection unit and the first power domain, respectively, and is used to control the on / off of the startup current according to the output of the capacitor detection unit and the voltage state of the first power domain.

7. The power control circuit as described in claim 6, characterized in that, The startup logic unit includes: a first MOS transistor and a second MOS transistor; The first MOSFET is connected in series between the second power domain and a common node, and the gate of the first MOSFET is coupled to the capacitor detection unit; the second MOSFET is connected in series between the common node and ground, and the gate of the second MOSFET is coupled to the first power domain. During the power-on process of the first power domain, when the first capacitor of the capacitor detection unit is charged, the current driving capability of the first MOS transistor decreases. When the current driving capability of the first MOS transistor is weaker than that of the second MOS transistor, the voltage of the common node is pulled down to ground potential.

8. The power control circuit as described in claim 1, characterized in that, The multi-level logic conversion module includes: a first-stage inverter to an Nth-stage inverter cascaded sequentially, where N is an integer greater than or equal to 2; The power supply terminal of the first-stage inverter is coupled to the first intermediate voltage terminal with the lowest voltage value. The power supply terminals of the other stages of the multi-stage logic conversion module are respectively coupled to intermediate voltage terminals with successively increasing voltage values ​​or to the voltage terminals of the second power domain.

9. The power control circuit as described in claim 1, characterized in that, Also includes: A Schmitt trigger module, coupled to the multi-level logic conversion module, is used to filter signal noise during the power-on process of the first power domain and output a power status control signal.

10. An input / output circuit system, characterized in that, include: The output drive circuit has a control input terminal and an output signal terminal; The power control circuit as described in any one of claims 1 to 9, wherein the output terminal of the power control circuit is coupled to the control input terminal of the output drive circuit; When the second power domain is powered on and the first power domain is not powered on, the power control circuit outputs a power status control signal to control the output drive circuit to lock the output signal terminal in a certain state.

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