GATE DRIVER FOR CONTROLLING CURRENT THROUGH A TRANSISTOR TO A CAPACITOR OR A CAPACITIVE LOAD

Abstract

A device includes a current source circuit with a first control input, a second control input, and an output. The current source circuit is designed to generate a current at the output with a first current level based on a first signal at the first control input being at a first logic level, and with a second current level based on the first signal at the first control input being at a second logic level. The current source circuit is also designed to generate a current at the output with a third current level based on a second signal at the second control input. A capacitor has a first terminal coupled to the output of the current source circuit and a second terminal coupled to a power supply terminal. A buffer has a buffer input coupled to the first terminal and a buffer output.

Description

BACKGROUND In many systems, power is supplied to a load by a solid-state switch (e.g., a transistor). A control circuit turns the transistor on to allow current to flow from a power source to the load, thus supplying power to the load. Some loads are capacitive or have a capacitor connected in parallel with the load. When the transistor is turned on, the capacitor charges. The charged capacitor allows the load to continue operating during a temporary loss of power from the power source. SUMMARY In one example, a device includes a current source circuit with a first control input, a second control input, and an output. The current source circuit is designed to generate a current at the output with a first current level based on a first signal at the first control input being at a first logic level, and with a second current level based on the first signal at the first control input being at a second logic level. The current source circuit is also designed to generate a current at the output with a third current level based on a second signal at the second control input. A capacitor has a first terminal connected to the output of the current source circuit and a second terminal connected to a power supply terminal.A buffer has a buffer input coupled to the first connection and a buffer output. In another example, a device includes a transistor with a control terminal. The device also includes a driver, which incorporates a configurable current source circuit. The configurable current source circuit has control inputs. The driver has a driver output coupled to the control terminal. The driver is designed to generate a voltage at the control terminal that changes at several rates based on control signals at the control inputs of the configurable current source circuit. In yet another example, a driver includes a current source circuit with a first control input, a second control input, and an output. A capacitor has a first terminal coupled to the output of the current source circuit and a second terminal coupled to a power supply terminal. A buffer has a buffer input coupled to its first terminal and a buffer output. A first comparator has a first and a second comparator input and an output. The first comparator input is coupled to a first terminal of the driver. The second comparator input is configured to receive a first reference signal. The output of the first comparator is coupled to the first control input of the current source circuit. A second comparator has a third and a fourth comparator input and an output.The third comparator input is connected to a second terminal of the driver. The fourth comparator input is designed to receive a second reference signal. The output of the second comparator is connected to the second control input of the current source circuit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a system that includes a gate driver and a transistor, in an example. Fig. 2 includes waveforms illustrating the operation of the gate driver of Fig. 1. Fig. 3 is a circuit diagram that provides an example of additional details for the gate driver of Fig. 1. Fig. 4 is a circuit diagram of a buffer included in the gate driver of Figs. 1 and 2, in an example. Fig. 5 is a circuit diagram that provides further details for the gate driver of Figs. 1 and 2, in an example. DETAILED DESCRIPTION The same reference numerals or other reference symbols are used in the drawings to denote the same or similar features (with regard to function and / or structure). The examples described here involve a capacitor connected in parallel with a load. However, the principles described here also apply to a capacitive load. In some examples, the power source for the load is a battery, such as the battery in a motor vehicle. In other examples, the power source for the load is a power converter. When the aforementioned transistor is switched on, the capacitor begins to charge. Until the voltage across the capacitor reaches or exceeds the minimum rated supply voltage for the load, the load remains in an off state. The current across the capacitor is proportional to the product of the capacitor's capacitance and the rate of change of the voltage across the capacitor, i.e., I = C*dv / dt, where I is the current across the capacitor, C is the capacitance, and dv / dt is the rate of change of the voltage across the capacitor. In the example of a motor vehicle, the power source for the load is the vehicle's battery, which could be a 12V battery. Accordingly, the rate of change of the voltage across the load is 12V. Given the relatively short time a transistor requires to switch on, the value of dv / dt is significantly large.Furthermore, the capacitance C can also be significantly large, for example, on the order of millifarads. Due to large values ​​of C and dv / dt, the current flowing through the transistor to charge the capacitor can be significantly high. The current flowing through the transistor passes through the transistor's drain-source resistance, causing the transistor to dissipate power. Dissipated power in a transistor causes an increase in the transistor's temperature. The level of the current I through the transistor while the capacitor is charging can be high enough to cause the transistor to overheat, potentially damaging it. Some control circuits that switch the transistor on and off can respond to a thermal problem with the transistor by switching it off.However, switching off the transistor can prevent the capacitor from fully charging and can prevent the load from rotating and operating. The examples described here involve a gate driver circuit that controls the turn-on of the transistor to ensure that the capacitor of a load is charged sufficiently to prevent the current through the transistor from becoming so high as to cause a thermal shutdown. The described gate driver allows the current through the transistor to be high enough to enable relatively rapid turn-on. In some examples, the gate driver implements a multi-phase turn-on process for the transistor, where the gate voltage is controlled by the gate driver to change at different rates as the capacitor charges. Fig. 1 is a circuit diagram of a system 100 comprising a gate driver 110, a transistor M1, a capacitor CLOAD, and a load 105. The capacitor CLOAD is connected in parallel with the load 105 between the transistor M1 (e.g., between a terminal, such as a source) and a power supply terminal (e.g., ground) 102. The voltage across the capacitor CLOAD is the voltage VOUT. The system 100 can include multiple loads 105, and each such load 105 can be connected in parallel with a capacitor CLOAD. In other examples (as indicated by the dashed lines), the system 100 includes a capacitive load 106 instead of a load 105, which is separated from but in parallel with the capacitor CLOAD. In still other examples, the system 100 includes a combination of a capacitor CLOAD / load 105 and a capacitive load 106. The gate driver 110 switches transistor M1 on and off. In response to transistor M1 being switched on, current IOUT flows from a supply voltage terminal 101 (VIN) through transistor M1 and to capacitor CLOAD and load 105. In some applications, system 100 is part of a motor vehicle, and voltage VIN is the voltage from the vehicle's battery (e.g., 12 V). In motor vehicle applications, load 105 is a subsystem within the motor vehicle. Examples of loads 105 in a motor vehicle include an infotainment system, an anti-lock braking system, etc. In the example shown in Fig. 1, the gate driver 110 has a driver output 110a, which is coupled to the gate of transistor M1. The driver 110 also has terminals 110b, 110c, and 110d. The gate driver 110 includes a current source circuit 112, a capacitor C1, comparators 114, 116, and 118, a buffer 120, a reference current circuit 115, and a reference voltage circuit 117. The current source circuit 112 has control inputs 112a, 112b, and 112c and an output 112d. The buffer 120 has a buffer input 120a and a buffer output 120b. The capacitor C1 has terminals C1a and C1b. The terminal C1a of capacitor C1 is connected to output 112d of current source circuit 112 and to buffer input 120a. The terminal C1b of capacitor C1 is connected to the power supply terminal 102. Buffer output 120b is connected to driver output 110a and, consequently, to the gate of transistor M1.Buffer 120 generates an output voltage VGATE at its output 120b. The current ICHARGE from the current source circuit 112 charges capacitor C1 to a voltage VREF1, which is the input voltage of the buffer 120. The buffer 120 implements a gain of "n" (e.g., n is greater than 1), such that the output voltage VGATE of the buffer is n times greater than its input voltage VREF1. In one example, n is 9, but in other examples, n has a value other than 9. The rate of change of the voltage VREF1 (dVREF1 / dt) is proportional to the magnitude of the current ICHARGE from the current source circuit 112 and the capacitance of capacitor C1, for example, dVREF1 / dt = ICHARGE / C1. Accordingly, the current source circuit 112 controls the rate of change of the voltage VREF1 by controlling the magnitude of the current ICHARGE. The buffer 120 generates the gate voltage VGATE for transistor M1, which is n times greater than the voltage VREF1. The rate of change of the gate voltage VGATE is proportional to the rate of change of the voltage VREF1.For example, dVGATE / dt is n times larger than dVREF1 / dt. Accordingly, the current source circuit 112 generates a current ICHARGE that controls the rate of change of the gate voltage VGATE for transistor M1. The current source circuit 112 generates the current ICHARGE at any one of several current levels. The current level of the ICHARGE is based on the signals provided at the control inputs 112a, 112b, and 112c. The comparator 114 has a positive (+) input, a negative (-) input, and an output 114a. The positive input of the comparator 114 is coupled to the driver terminal 110b. A current sensing circuit 135 is coupled to the transistor M1, for example, to the source of transistor M1. The current sensing circuit 135 may include a sensing resistor (e.g., 20 milliohms) whose voltage is proportional to the current IOUT through the sensing resistor. In another example, the current sensing circuit 135 includes a transistor that is significantly smaller than transistor M1 and is connected in parallel with transistor M1.The current sensing circuit 135 generates a current sensing signal SNS that is proportional to the current IOUT through transistor M1. The output 135a of the current sensing circuit 135 is coupled to the driver terminal 110b and the positive input of comparator 114. The reference current circuit 115 is coupled to the negative input of comparator 114 and generates a current ISET. Comparator 114 is a current comparator that compares a current sensing signal from the output 135a of the current sensing circuit 135 with the reference current ISET. The current sensing circuit 135 has a sensing output 135a that is coupled to the positive input of comparator 114. The output 114a of comparator 114 is coupled to the control input 112a of current source circuit 112. In the example of Fig. 1, if the detection signal SNS is smaller than the reference current ISET, the comparator 114 generates its output signal as a logic low (“0”).Otherwise, if the detection signal SNS is greater than the reference current ISET, comparator 114 generates its output signal as a logic high ("1"). The comparator 116 has a positive and a negative input and an output 116a. The positive input of the comparator 116 is connected to a terminal 110d of the driver 110 and to the source of transistor M1. The negative input of the comparator 116 is connected to the reference voltage circuit 117 and receives a reference voltage VREF2 generated by the reference voltage circuit 117. The voltage VREF2 can correspond to a minimum voltage required for the correct operation of the load 105. In one example, the reference voltage VREF2 is 3 V. The output 116a of the comparator 116 is connected to the control input 112b of the current source circuit 112. The comparator 116 is a voltage comparator that compares VOUT with the reference voltage VREF2.If VOUT is less than VREF2, the comparator 116 generates an output signal to control input 112b at a logic low level; otherwise, if VOUT is greater than VREF2, the comparator 116 generates an output signal to control input 112b at a logic high level. The comparator 118 has a positive and a negative input and an output 118a. The positive input of the comparator 118 is coupled to a terminal 110c of the driver 110 and to the drain of transistor M1. The negative input of the comparator 118 is coupled to a terminal 110d of the driver 110 and to the source of transistor M1. The output 118a of the comparator 118 is coupled to the control input 112c of the current source circuit 112. The comparator 118 determines whether the input voltage VIN exceeds a threshold voltage implemented in the comparator 118, which is greater than the output voltage VOUT.If VIN is greater than the reference voltage of comparator 118, which is greater than VOUT, comparator 118 generates an output signal to control input 112c at a logic high level; otherwise, if VOUT is within the reference voltage of VIN, comparator 118 generates an output signal to control input 112b at a logic low level. In other words, comparator 118 determines when capacitor CLOAD has been charged to the point where VOUT is relatively close to VIN (e.g., within the threshold voltage of comparator 118). Fig. 2 includes waveforms of the voltages VREF1, VGATE, and VOUT, and the current sensing signal SNS (which is a proxy for the current IOUT) during several phases designated RAMP1, RAMP2, and RAMP3. Referring to Fig. 1 and Fig. 2, the current source circuit 112 initially generates the current ICHARGE during the RAMP1 phase to turn on transistor M1 and begin charging capacitor C1. This current is generated at a level that causes capacitor C1 to charge relatively quickly, as indicated by the slope of the voltage VREF1 during the RAMP1 phase. VGATE is n times greater than VREF1. At time 201, VGATE reaches the threshold voltage of transistor M1, and transistor M1 responds by turning on. With transistor M1, the current IOUT begins to flow through transistor M1, and capacitor CLOAD begins to charge.The voltage across capacitor CLOAD is VOUT, and consequently, the voltage VOUT begins to rise. As noted above, the voltage VOUT is the voltage at the source of transistor M1. During the remainder of phases RAMP1, RAMP2, and RAMP3, the current IOUT continues to flow to capacitor CLOAD, and consequently, the voltage VOUT continues to rise. Comparator 114 compares the detection signal SNS with ISET, as described above. Comparator 114 implements hysteresis, so its output 114a is forced to a logic high level when SNS is above ISET and back to a logic low level when SNS falls below level 202. The difference between ISET and level 202 is the hysteresis of comparator 114. In response to SNS reaching ISET at point 207, phase RAMP2 begins, comparator 114 generates a logic high signal at its output 114a, and current source circuit 112 responds by decreasing the level of the current ICHARGE. With a lower current level, the rate of change of voltage VREF1 decreases, and likewise, the rate of change of voltage VGATE also decreases, as illustrated in Figure 204.As the gate voltage for transistor M1 continues to rise, but at a lower rate, while the source voltage (VOUT) continues to rise, the gate-source voltage (Vgs) of the transistor decreases, which in turn causes IOUT and the detection signal SNS to decrease, as illustrated in Figure 205. In response to the detection signal SNS reaching the lower level 202 of the comparator 114's hysteresis, the current source circuit 212 increases the current ICHARGE to a level that may be lower than the level implemented during phase RAMP1 but higher than the level during 204. At the higher current ICHARGE level, the rate of change of voltage VREF1, and thus VGATE, increases, as shown in 205. The Vgs of transistor M1 increases in response, and consequently, the output current IOUT and the detection signal SNS also increase, as shown in 206. During phase RAMP2, the current source circuit 212 causes the current ICHARGE to oscillate between two relatively low levels based on the comparison between the detection signal SNS and ISET and the lower level 202 of the comparator's hysteresis.This process keeps the charging current IOUT to the capacitor CLOAD at a level low enough to avoid a thermal event as described above. Phase RAMP2 ends and phase RAMP3 begins when the voltage VOUT reaches the voltage VREF2, identified by point 208. The comparator 116 compares VOUT with the voltage VREF2 and generates a logic high signal to control input 112b of the current source circuit 112 when VOUT reaches VREF2. In response to the activation of a logic high at the control input 112b, the current source circuit 112 increases the level of the current ICHARGE to a level higher than the current ICHARGE levels during phase RAMP2. Due to the higher current ICHARGE level, the voltage VREF1 increases at an even higher rate during phase RAMP3 than it did during phase RAMP2. The voltage VGATE also increases at a higher rate during phase RAMP3 (reference 209) than during phase RAMP2.The gate voltage of transistor M1 can increase at a relatively rapid rate during the RAMP3 phase because the transistor's source voltage (VOUT) also increases. Consequently, the Vgs of transistor M1 during the RAMP3 phase is not so high that there is a risk of the current IOUT being high enough to cause transistor M1 to overheat. The reduced drain-source voltage (Vds) of transistor M1 during the RAMP3 phase is lower than during the RAMP1 and RAMP2 phases, thus also reducing the heat generated by transistor M1. Phase RAMP3 ends when the voltage VOUT is close to the input voltage VIN, meaning that the Vds of transistor M1 is relatively low and, consequently, the power dissipated in transistor M1 is low enough not to overheat the transistor. Comparator 118 determines when VOUT is within a threshold level of VIN. In one example, the threshold level is 2 V, meaning that comparator 118 generates a logic high at its output 118a when VOUT is within 2 V of VIN. In response to the activation of a logic high signal level at the control input 112c, the current source circuit 112 generates the current ICHARGE to an even higher level, thereby causing the voltages REF1 and VGATE to rise at even higher rates, as shown in Figure 210. Since the Vds of transistor M1 is relatively low (e.g.,2 V) and decreases while the capacitor CLOAD continues to charge, the current IOUT can increase without the risk of overheating the transistor M1, as shown in 211. Fig. 3 is a circuit diagram of system 100 in another example, in which the gate driver 110 includes transistors M2 and M3. Fig. 3 illustrates a technique for activating the gate driver 110 to initiate the turn-on process for transistor M1, as described above. Transistor M3 is an n-channel field-effect transistor (NFET) whose drain and source are coupled via capacitor C1. The gate of transistor M3 is coupled to a terminal 110e of the gate driver 110, through which an ON / OFF signal 301 is provided. In this example, when the ON / OFF signal is at a logic high level, transistor M3 is turned on, pulling the voltage VREF1 low to ground. When VREF1 is at or near ground, VGATE is below the threshold voltage for transistor M1, and accordingly, transistor M1 is turned off.If the ON / OFF signal is at a logic low level, transistor M3 is switched off, and gate driver 110 can operate as described above. Transistor M2 is connected in series between the output 112d of the current source circuit 112 and terminal C1a of capacitor C1. The gate of transistor M2 is coupled to terminal 110f of the gate driver 110. A clock signal 302 is supplied to the gate of transistor M2 to turn the transistor on and off. When transistor M2 is on, the current ICHARGE flows through transistor M2 to charge capacitor C1. When transistor M2 is off, the current ICHARGE does not flow to capacitor C1. Accordingly, the average charging current for capacitor C1 in the example of Fig. 3 is ICHARGE*D, where D is the duty cycle of the clock signal 302. For example, if D is 0.5, the average charging current for capacitor C1 is ICHARGE / 2. Therefore, the different levels of the charging current to capacitor C1, as described above, are ICHARGE*D.By sweeping the duty cycle of transistor M2, the current source circuit 112 can generate the current ICHARGE at higher levels, thus enabling fine control of the current by the current source circuit 112. Fig. 4 is a circuit diagram of an example buffer 120. The buffer 120 includes transistors M31, M32, M33, M34, M35, and M36, and resistors R1 and R2. Transistors M31, M35, and M36 are NFETs, and transistors M32–M34 are p-channel field-effect transistors (PFETs). The sources of transistors M32–M34 are coupled to each other and to a supply voltage terminal 401 (e.g., an internally generated supply voltage). The gates of transistors M32–M34 are coupled to each other and to the drain of transistor M32. The drains of transistors M32 and M31 are coupled to each other. One terminal of resistor R1 is coupled to the source of transistor M31, and the other terminal of resistor R1 is coupled to the supply voltage terminal 102. The gate of transistor M31 is coupled to the buffer input 120a and receives the voltage VREF1.The drain of transistor M33 is coupled to the drain of transistor M35 and to the gates of transistors M35 and M36. The drains of transistors M34 and M36 are coupled to each other. One terminal of resistor R2 is coupled to the source of transistor M35, and the other terminal of resistor R2 is coupled to the supply voltage terminal 102. The source of transistor M36 is coupled to the buffer output 120b and provides the voltage VGATE. Current I31 is the current through transistors M31 and M32. Current I35 is the current through transistors M35 and M33. Current I36 is the current through transistors M36 and M34 and at the gate of transistor M1 (Fig. 1 and Fig. 2). The combination of transistors M32 and M33 forms a current mirror. The current mirror ratio is 1:n, which means that current I35 is n times greater than current I31. In one example, n is 3. Resistor R2 can have a resistance value that is m times greater than the resistance value of resistor R1. In one example, m is 3, which means that the resistance value of resistor R2 is 3 times greater than the resistance value of resistor R1. The voltage V_R1 at the source of transistor M31 is the voltage VREF1 at its gate minus the threshold voltage of transistor M31. The current I31 is the voltage V_R1 / R1. In the example where the current mirroring ratio between transistors M32 and M33 is 1:3, the current I35 is 3*I31. The current I35, which is 3 times the current I31, flows through resistor R2, whose resistance is 3 times that of resistor R1. Accordingly, with an example current mirroring ratio of 1:3 and an R2 of 3*R1, the voltage V_R2 across resistor R2 is 9 times the voltage V_R1. The voltage at the gates of transistors M35 and M36 is the threshold voltage of transistor M35 above the voltage V_R2, and the voltage at the source of transistor M36 is a threshold voltage below the voltage at the gate of transistor M36. Accordingly, the voltage VGATE is approximately equal to the voltage V_R2.Since the voltage V_R2 is n*m*V_R1, and V_R1 is proportional to the voltage VREF1 (e.g., a threshold voltage smaller than VREF1), the voltage VGATE is also n*m*VREF1 and proportional to the voltage VREF1. In the example described above, where n and m are both 3, the voltage VGATE is approximately 9 times VREF1 (ignoring the threshold voltage of transistor M31). Accordingly, buffer 120 implements a gain of n*m, which is a gain of 9 when n=m=3. In some examples, the gain of buffer 120 is between 8 and 11. Transistor M34 supplies the current to the gate of transistor M1 needed to maintain the voltage VGATE at approximately n*m*VREF1. Fig. 5 is a circuit diagram of system 100, which provides exemplary implementations of the current source circuit 112 and the comparator 114. The comparator 114 includes transistors (e.g., NFETs) M114a and M114b, a Schmitt trigger 522, and an inverter 523. Transistors M114a and M114b are coupled to form a current mirror. The reference current circuit 115 is coupled to transistor M114a and supplies the current ISET through transistor M114a. The current ISET is mirrored through transistor M114b. In the example of Fig. 5, the sensing signal SNS is a current ISNS from the current sensing circuit 135. The input of the Schmitt trigger 522 is coupled to the drain of transistor M114b and to the output of the current sensing circuit 135. If the current ISNS is greater than the current through the transistor M114b, the Schmitt trigger 522 generates a logic high at its output to the input of the inverter 523.If, on the other hand, the current ISNS is smaller than the current through transistor M114b, the Schmitt trigger 522 generates a logic low at its output at the input of inverter 523. The output of inverter 523 is coupled to the gate of transistor M57 and the drain of transistor M58b, which are described below. The current source circuit 112 includes transistors M51, M52, M53, M54, M55, M56, M57, M58a, M58b, and M59, and current sources I51 and I52. In this example, transistors M55, M56, and M59 are PFETs, and transistors M51–M54 and M57, M58a, and M58b are NFETs. Transistors M52, M53, M54, and M55 are connected in series between an internal supply terminal 107 and ground. Transistors M55 and M56 are coupled to each other to form a current mirror. The drain of transistor M56 is coupled to output 112d of the current source circuit 112. The current through transistor M56 is the current ICHARGE, which charges capacitor C1 when transistor M3 is off. The drain of transistor M59 is coupled to current source I52, and the source of transistor M59 is coupled to current source I51 and to the drain of transistor M51. The gates of transistors M51, M52, M53, and M54 are coupled to each other and to the source of transistor M59 and the drain of transistor M51. The gates of transistors M58a and M58b are coupled to each other and to the output 116a of comparator 116. The sources of transistors M58a, M58b, M51, and M52 are coupled to each other and to ground. The drain of transistor M58a is coupled to the drain of transistor M52 and to the source of transistor M53. The drain of transistor M58b is coupled to the gate of transistor M57 and to the output of inverter 523. When the output signal from inverter 523 is logic high, transistor M57 is switched on. When the output signal from comparator 116 is logic high, transistors M58a and M58b are switched on.Furthermore, the output 118a of comparator 118 is coupled to the gate of transistor M59. Accordingly, when the output signal from comparator 118 is logic high, transistor M59 is switched on. Current from current source I51 flows through transistor M51. Similarly, when transistor M59 is switched on, current from current source I52 also flows through transistor M51. Accordingly, when transistor M59 is switched on, current from both current sources I51 and I52 flows through transistor M51. When transistor M1's switch-on process is initiated, transistors M58a, M58b, and M59 are switched off. When the current IOUT through its proxy ISNS is less than ISET, the output of Schmitt trigger 522 is logic low and the output of inverter 523 is logic high, thus switching on transistor M57. In this configuration, a current mirror is formed between transistor M51 and transistor M54, and accordingly, the current from current source I51 flowing through transistor M51 is mirrored through transistor M54 (e.g., a current mirror ratio of 1:1).The current ICHARGE is approximately equal to the current from the power source I51. In this configuration (transistor M57 switched on), the current ICHARGE represents the charging current for capacitor C1 in phase RAMP1 (Fig. 2). When the current IOUT reaches ISET via its proxy ISNS (during the RAMP2 phase), the output of the Schmitt trigger 522 switches to a logic high state, which the inverter 523 inverts to a logic low state, thus turning off transistor M57. With transistor M57 off, a current mirror is formed between transistor M51 and the series connection of transistors M52-M54. The current mirror ratio in this configuration is 3:1, since the series connection of transistors M52-M54 is equivalent to a transistor with a channel length L that is three times the channel length of transistor M51, assuming that all individual transistors in this example have the same channel width W and channel length L. Accordingly, the current ICHARGE decreases during the periods identified as 204 and 205 in Fig. 2.During the RAMP2 phase, the current ICHARGE alternates between two levels - one level equal to the current from the power source I51 and another level equal to one third of the size of the current from the power source I51. When the current IOUT falls to the lower level 202 in Fig. 2 via its proxy ISNS, the output of the Schmitt trigger 522 switches to a logic low state, which the inverter 523 inverts to a logic high state, thereby turning transistor M57 back on. As a result, the current ICHARGE rises during period 206, as described above. Comparator 116 determines when the output voltage VOUT reaches the reference voltage VREF2, thus marking the end of phase RAMP2 and the beginning of phase RAMP3. When VOUT reaches VREF2, comparator 116 forces its output 116a to a logic high state, causing transistors M58a and M58b to turn on. Turning on transistor M58b forces transistor M57 to remain off for the remainder of the turn-on process for transistor M1. Turning on transistor M58a reconfigures the current mirror to a current mirror between transistor M51 and the series connection of transistors M53 and M54 with a current mirror ratio of 2:1. In this configuration (transistor M58a turned on), the current ICHARGE is smaller than the current ICHARGE during phase RAMP1 and larger than the current ICHARGE during phase RAMP2 when transistor M57 was off. Finally, when comparator 118 determines that the voltage VOUT is within the threshold voltage of comparator 118 of the voltage VIN, comparator 118 forces its output 118a into a logic high state, thereby turning on transistor M59. With transistor M59 turned on, current from current source I52 is added to the current from current source I51 flowing through transistor M59, and the current ICHARGE rises to an even higher level, which occurs during period 210 in Fig. 2. In some examples, the rate of change of the voltage VGATE during phases RAMP1, RAMP2, and RAMP3 can be configured. For example, the gate driver 110 may contain one or more registers into which values ​​can be programmed, for example, via an interface (such as an integrated circuit bus, a serial peripheral interface bus, etc.). In some such examples, the rate of change of the voltage VGATE can be configured by configuring the magnitude of the currents generated by the current source circuit 112. In one specific example, a configuration value can be programmed into the gate driver 112 that proportionally adjusts the current ICHARGE generated by the current source circuit 112 during all phases RAMP1-RAMP3. In this description, the term "couple" can cover connections, communications, or signal paths that enable a functional relationship corresponding to this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intermediary component C, provided that the intermediary component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A. Furthermore, in this description, the use of "based on" means "at least partially based on". Therefore, if X is based on Y, then X can be a function of Y and any number of other factors. A device that is "configured" to perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at a point in time to perform that function, and / or can be configured (or reconfigured) by a user after manufacture to perform that function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnections of the device, or a combination thereof. As used herein, the terms "connector", "node", "connection", "pin", and "conduit" are used interchangeably. Unless otherwise specified, the use of these terms generally means a connection between, or termination of, a device element, circuit element, integrated circuit, appliance or other electronics, or a semiconductor component. A circuit or device that, according to the present description, includes certain components, may instead be designed to be coupled with these components to form the described circuit arrangement or device. For example, a structure that, according to the description, includes one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g., a circuit board, a power supply, or a power supply).a semiconductor die and / or an integrated circuit (IC) package) and may be designed to be coupled, either during or after manufacturing, for example by an end user and / or a third party, with at least some of the passive elements and / or sources to form the described structure. While the use of specific transistors is described here, other transistors (or equivalent devices) can be used instead with little or no change to the rest of the circuit design. For example, a field-effect transistor (“FET”) (such as an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT – e.g., an NPN or PNP transistor), an insulated-gate bipolar transistor (IGBT), and / or a junction field-effect transistor (JFET) can be used instead of, or in conjunction with, the devices described here. The transistors can be depletion-mode devices, drain-expanded devices, enhancement-mode devices, natural transistors, or other types of device-structure transistors.Furthermore, the devices can be implemented in / over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs). The claims may refer to the control input of a transistor and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and the source. In the context of a BJT, the control input is the base, and the current terminals are the collector and the emitter. References herein to a FET being "turned on" or "enabled" mean that the FET's conduction channel is present and drain current can flow through the FET. References herein to a FET being "turned off" or "disabled" mean that the conduction channel is not present, so no drain current flows through the FET. However, current can still flow through the transistor's body diode in a "turned-off" FET. The circuits described here are reconfigurable to include additional or different components to provide functionality at least partially similar to that available before the component exchange. Unless otherwise specified, components shown as resistors generally represent one or more elements connected in series and / or parallel to provide an impedance value represented by the resistor shown. For example, a resistor or capacitor shown and described here as a single component may instead be multiple resistors or capacitors connected in parallel between the same nodes.These are capacitors that are connected in series between the same two nodes as the single resistor or capacitor. While certain elements of the described examples are contained within an integrated circuit and other elements are located outside the integrated circuit, in other embodiments additional or fewer features may be integrated within the integrated circuit. Furthermore, some or all of the features shown to be external to the integrated circuit may be contained within the integrated circuit, and / or some features shown to be internal to the integrated circuit may be integrated outside the integrated circuit. The term "integrated circuit," as used herein, means one or more circuits that are: (i) integrated in / over a semiconductor substrate; (ii) integrated within a single semiconductor package; (iii) integrated within the same module; and / or (iv) integrated in / on the same printed circuit board. Uses of the term "ground" in the foregoing description include chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this description. Unless otherwise specified, in this description, "about," "approximately," or "essentially" preceding a parameter means a range within ±10% of that parameter or, if the parameter is zero, an acceptable range of values ​​around zero. Within the scope of protection of the claims, modifications of the described examples as well as other examples are possible.

Claims

A device comprising: a current source circuit with a first control input, a second control input, and an output, wherein the current source circuit is designed to generate a current at the output with a first current level based on a first signal at the first control input being at a first logic level, and with a second current level based on the first signal at the first control input being at a second logic level, and the current source circuit is designed to generate the current at the output with a third current level based on a second signal at the second control input; a capacitor with a first terminal coupled to the output of the current source circuit and with a second terminal coupled to a power supply terminal; and a buffer with a buffer input coupled to the first terminal and with a buffer output. Device according to claim 1, further comprising a transistor with a control terminal coupled to the buffer output. The device according to claim 2, further comprising: a current sensing circuit coupled to the transistor, wherein the current sensing circuit has a sensing output; and a current comparator with a first comparator input, a second comparator input and a comparator output, wherein the first comparator input is coupled to the sensing output, the second comparator input is coupled to a reference current circuit and the comparator output is coupled to the first control input. Device according to claim 2, wherein the transistor has a transistor terminal and the device further comprises a comparator with a first comparator input, a second comparator input and a comparator output, wherein the first comparator input is coupled to the transistor terminal, the second comparator input is coupled to a reference voltage circuit and the comparator output is coupled to the second control input. The device according to claim 2, wherein the transistor has a first transistor terminal and a second transistor terminal, and the current source circuit has a third control input, the current source circuit is designed to generate the current at the output with a fourth current level based on a third signal at the third control input, and the device further comprises: a comparator with a first comparator input, a second comparator input and a comparator output, wherein the first comparator input is coupled to the first transistor terminal, the second comparator input is coupled to the second transistor terminal and the comparator output is coupled to the third control input. Device according to claim 1, further comprising a transistor connected between the output of the current source circuit and the first terminal of the capacitor. A device comprising: a transistor with a control terminal; and a driver comprising a configurable current source circuit, wherein the configurable current source circuit has control inputs, the driver having a driver output coupled to the control terminal, the driver being designed to generate a voltage at the control terminal which changes at multiple rates based on control signals at the control inputs of the configurable current source circuit. The device according to claim 7, further comprising: a current sensing circuit coupled to the transistor, wherein the current sensing circuit has a sensing output; and a comparator with a first comparator input coupled to the sensing output, wherein the comparator has a comparator output coupled to a first control input of the control inputs of the configurable current source circuit, wherein the comparator is configured to compare a signal at the sensing output with a reference current;and wherein the driver is designed to generate the voltage at the control terminal at a first rate of several rates based on a signal at the comparator output being in a first logic state, and to generate the voltage at the control terminal at a second rate of several rates based on the signal at the comparator output being in a second logic state. The device according to claim 8, wherein the comparator is a first comparator, the transistor has a transistor terminal, and the device further comprises: a second comparator with a first comparator input coupled to the transistor terminal, wherein the second comparator has an output coupled to a second control input of the control inputs of the current source circuit, wherein the second comparator is configured to compare a voltage at the transistor terminal with a reference voltage; and wherein the driver is configured to generate the voltage at the control terminal at a third rate of the multiple rates based on a signal at the output of the second comparator. Device according to claim 9, wherein the first comparator is a current comparator and the second comparator is a voltage comparator. Device according to claim 7, wherein the driver includes a capacitor with a capacitor terminal coupled to an output of the configurable current source circuit. The device according to claim 11, further comprising a buffer with a buffer input coupled to the capacitor terminal and with a buffer output coupled to the driver output. Device according to claim 12, wherein the buffer has a gain and the gain is greater than 1. Device according to claim 13, wherein the reinforcement is between 8 and 11. Device according to claim 12, wherein the transistor is a first transistor, wherein the driver further comprises a second transistor which is connected between the output of the configurable current source circuit and the capacitor terminal. The device according to claim 7, wherein the transistor has a transistor terminal and wherein the driver is configured to: generate the voltage at the control terminal at a first rate and second rates of the multiple rates until a voltage at the transistor terminal reaches a threshold voltage; and generate the voltage at the control terminal at a third rate of the multiple rates when the voltage at the transistor terminal is above the threshold voltage. A driver comprising: a current source circuit with a first control input, a second control input, and an output; a capacitor with a first terminal coupled to the output of the current source circuit and a second terminal coupled to a power supply terminal; a buffer with a buffer input coupled to the first terminal and a buffer output; a first comparator with a first and a second comparator input and an output, wherein the first comparator input is coupled to a first terminal of the driver, the second comparator input is configured to receive a second reference signal, and the output of the first comparator is coupled to the first control input of the current source circuit;and a second comparator with a third and a fourth comparator input and an output, wherein the third comparator input is coupled to a second terminal of the driver, wherein the fourth comparator input is configured to receive a second reference signal, and wherein the output of the second comparator is coupled to the second control input of the current source circuit. Driver according to claim 17, wherein the current source circuit is designed to provide a current with a first, a second and a third current level based on signals from the outputs of the first and second comparator. Driver according to claim 17, wherein the first comparator is a current comparator and the second comparator is a voltage comparator. Driver according to claim 17, wherein the current source circuit has a third control input and the driver further comprises: a third comparator with a fifth and a sixth comparator input and an output, wherein the fifth comparator input is coupled to the second terminal of the driver, wherein the sixth comparator input is coupled to a fourth terminal of the driver, wherein the output of the third comparator is coupled to the third control input of the current source circuit.

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