METHOD, SYSTEMS AND DEVICES FOR COUPLING POWER AMPLIFIER INPUT SIGNALS

Abstract

Methods, systems, and a device for coupling a power amplifier input signal are disclosed. An exemplary system comprises a first amplifier (204) comprising a signal input (234a, 234b), a feedback input (246), and a differential output comprising a first output (236a) and a second output (236b); a first resistor (218a) comprising a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the first output (236a); a second resistor (218b) comprising a third resistor terminal and a fourth resistor terminal, wherein the third resistor terminal is coupled to the second resistor terminal at a common-mode output node (242), and the fourth resistor terminal is coupled to the second output (236b); and a second amplifier (208) comprising a first input (242) and a third output (240).wherein the first input (242) is coupled to the second resistor terminal and the third resistor terminal, and the third output (240) is coupled to the feedback input (246) of the first amplifier (204).

Description

[0001] This disclosure relates generally to power amplifier input signals and, in particular, to methods, systems and devices for coupling power amplifier input signals. BACKGROUND

[0002] Some electronic devices include one or more transceivers for communicating with other devices using radio frequency (FF) signals. Such transceivers include FF power amplifiers for converting low-power FF signals into higher-power signals. The higher-power signals drive an antenna in the transceiver to transmit data contained in the low-power FF signal to other devices. Some power amplifiers are coupled with other stages of a transceiver, such as an input stage and an output stage. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram of an example transmitter for sending an information signal. Fig. Figure 2 is a schematic representation of an exemplary preamplifier circuit arrangement made up of Fig. 1, comprising a common path for modulated signals and bias. Fig. Figure 3 is a schematic representation of an exemplary second preamplifier and power amplifier of the preamplifier circuit arrangement from Fig. 2. Fig. Figure 4 is a schematic representation of an exemplary envelope detection circuit arrangement made of Fig. 2 to trace the envelope of an output of an exemplary first pre- and power amplifier of the preamplifier circuit arrangement from Fig. 2 and generating a dynamic preload based on the envelope. Fig. Figure 5 is a block diagram of an exemplary processing platform, comprising a programmable circuit arrangement, structured to implement the signal processing circuit arrangement 102 of the transmitter. Fig. 1.

[0003] Generally, the same reference symbols are used throughout the drawing(s) and accompanying written description to refer to the same or similar parts. The drawings are not necessarily to scale. Rather, the thickness of the layers or areas in the drawings may be exaggerated. Although the figures show layers and areas with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be imperceptible, intersecting, and / or irregular.

[0004] As used herein, references to connections (e.g., attached, coupled, joined, and joined) may include intermediate elements between the elements referenced by the connection reference and / or relative movement between those elements, unless otherwise specified. Therefore, connection references do not necessarily imply that two elements are directly connected and / or in a fixed relationship to each other.

[0005] Unless expressly stated otherwise, descriptors such as "first," "second," "third," etc., are used here without implying or otherwise indicating any meaning of priority, physical order, arrangement in a list, and / or sequence in any way, but are used merely as labels and / or arbitrary names to distinguish elements for the sake of easier understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element in a claim may be referred to by a different descriptor, such as "second" or "third."In such cases, it is understood that such descriptors are used only to uniquely identify those elements within the context of the discussion (for example, within a claim), where the elements might otherwise share the same name.

[0006] As used herein, "approximately" and "about" modify their subjects / values ​​to account for the potential presence of variations that occur in real-world applications. For example, "approximately" and "about" may modify dimensions that may not be exact due to manufacturing tolerances and / or other genuine defects as understood by the average person skilled in the art. For example, "approximately" and "about" may indicate that these dimensions may be within a tolerance range of + / - 10% unless otherwise specified in the description below.

[0007] As used here, the phrase “in communication”, including variations thereof, encompasses direct communication and / or indirect communication through one or more intermediaries and does not require direct physical (e.g., wired) communication and / or constant communication, but instead additionally includes targeted communication at periodic intervals, planned intervals, aperiodic intervals and / or one-off events.

[0008] As used herein, an integrated circuit / circuit assembly is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more components consisting of an ASIC, an FPGA, a chip, a microchip, a programmable logic assembly, a semiconductor substrate coupling multiple circuit elements, a system-on-a-chip (SoC), etc. DETAILED DESCRIPTION OF EXAMPLES OF EXECUTION

[0009] The demand for smaller, lighter, and more portable electronic devices, such as smartphones, laptops, wearables, and IoT (Internet of Things) devices, is constantly growing. Reduced die sizes allow manufacturers to pack more functionality into more compact form factors on an integrated circuit (IC), making these devices easier for users to carry and use. Additionally, smaller die sizes contribute to lower manufacturing costs and improved energy efficiency for consumers. In the context of integrated circuits, a die is a small block of semiconducting material on which a given functional circuit is fabricated.

[0010] Transmitters are one of many types of integrated circuits (ICs) used in communication devices (e.g., smartphones, laptops, IoT devices, etc.). Transmitters communicate data from one device to another. In some examples, transmitters comprise multiple stages to perform various functions for efficient and accurate transmission. As used here, a stage can be referred to as a "device" and / or a "module." For example, the power amplifier in a transmitter can be referred to as a stage, a device, a module, etc., of the transmitter. In some examples, a challenge arises when transmitting a signal from one stage to the next.

[0011] There are various techniques for coupling one device (e.g., a power amplifier) ​​to another device (e.g., an input stage or an output stage). A coupling technique can be selected based on the transceiver application. For example, a transmitter operating in a relatively high frequency range (e.g., the GHz range, such as 2.4 GHz, 5–7 GHz, and 77–81 GHz) uses on-chip transformers or inductors to couple a radio frequency (FF) signal between different stages. For instance, transformers provide impedance matching between a source stage (e.g., a power amplifier) ​​and a receiving stage (e.g., an antenna). As used here, impedance matching is the process of matching the impedance of a source and a load to ensure efficient power transfer and minimize signal reflections.Impedance is a measure of the resistance to the flow of alternating current (AC) in a circuit. For example, impedance can be represented by the sum of the total resistance of a circuit (R) and the total reactance of the circuit (X) (e.g., Z = R + jX, where "j" denotes that the reactance "X" is an imaginary part of the impedance, Z). As resistance and / or reactance increase, so does impedance. Both resistance and reactance are typically measured in ohms. Circuits can exhibit inductive reactance (XL) and / or capacitive reactance (XC). Both inductive and capacitive reactance are measured based on frequency (f). For example, inductive reactance increases when frequency increases (e.g. XL = 2πfL, where L is the inductance in Henry), and capacitive reactance increases when frequency decreases (e.g. XC = 1 / 2πfC, where C is the capacitance in Farad).According to a maximum power transfer theorem, the maximum power is transferred from a source (e.g., a source stage) to a load (e.g., a receiving stage) when the source and load impedances are complex conjugates of each other. Impedance matching ensures that the load receives the maximum available power from the source.

[0012] Transformers and / or inductors can provide signal attenuation, amplification, and / or filtering to meet the requirements of the receiving stage. Additionally, transformers can provide DC blocking. For DC blocking, a transformer couples AC signals from the primary side of the transformer to the secondary side, thus blocking the DC component of a flip-flop signal and allowing the AC component of the FF signal to pass from the source stage to the receiving stage. DC blocking can be used when coupling FF signals between stages because the DC bias or offset voltage from one stage can interfere with the operation of the other. Inductors are also used in conjunction with capacitors to provide DC blocking.Although the inductors and / or transformers provide advantages for coupling a FF signal from a source stage to a receiver stage, they also occupy a larger part of the total transmitter area (e.g. 30-40% of the total transmitter area).

[0013] A transmitter operating in a lower frequency range (e.g., lower than the GHz range, such as 170 MHz–950 MHz) can implement coupling capacitors, as opposed to inductors, to couple a radio frequency (FF) signal between different stages, such as a pre-amplifier / power amplifier (PPA) and a power amplifier (PA). Lower-frequency transmitters are less likely to use on-chip transformers or inductors for coupling the FF signal because such transformers or inductors would be large at lower frequencies. For example, the lower the frequency, the larger the size of the inductor, since the reactance of an inductor (XL) is directly proportional to the frequency (e.g., XL = 2πLf). Therefore, there is a trade-off for lower-frequency transmitters: larger area versus impedance matching with inductors.To maintain an acceptable impedance (Z) at a lower frequency, for example, the inductor can be significantly larger than the inductor of a transmitter operating at a higher frequency. Therefore, lower-frequency transmitters can use capacitors to couple FF signals between stages (e.g., between a PPA and a PA) as a trade-off for impedance matching and reduced footprint, since large transformers and / or inductors can present design challenges and occupy too much space in a transmitter.

[0014] In some examples, capacitors can be used in lower-frequency transmitters because capacitive reactance (XC) is inversely proportional to frequency. For example, capacitors can be used between a PPA and a PA to couple the output signal from the PPA to the input of the PA. Capacitors can be used because a capacitor can be smaller than an inductor and still provide adequate impedance. For example, capacitive reactance (XC) is measured as the reciprocal of 2πCf, where C is the value of the capacitor in farads. However, the coupling capacitors can still be large to efficiently couple the flip-flop signal from the PPA to the PA. In some examples, the coupling capacitors are chosen to be larger (e.g., 8 to 10 times larger) than the input capacitance of the amplifier into which the flip-flop signal is coupled (e.g., coupled to the PA).

[0015] In some examples, a problem encountered when coupling capacitors involves biasing a stage input. For instance, the input devices of the power amplifier (PA) may be biased with a DC voltage. In some examples, the input devices of a PA are transistors. The gate terminals of the transistors must be biased with a certain gate voltage to ensure intended operation. In some examples, the bias voltage can be drawn from the DC component (Vdc) of a power amplifier (PPA) output signal. In some examples, particularly with higher-frequency transmitters, the DC component can be provided by a center tap of a transformer's secondary coil.

[0016] Alternatively, the bias can be generated using a fixed bias scheme or a dynamic bias scheme. In fixed bias schemes for lower-frequency transmitters, the bias is provided via a high-impedance resistor directly coupled to the gate terminals of the input transistors, and the flip-flop signal is provided by coupling capacitors connected between the PPA output and the PA output. The resistor must be a high-impedance resistor because the output of the PPA (e.g., the communication signal, the flip-flop signal, etc.) has a different path than the path through which the bias signal is provided (e.g., the output of a driver bias circuit). For example, the impedance of the bias resistors is in parallel with the input impedance of the PA.Therefore, a split signal current can occur if the bias resistors are not sufficiently high. For example, part of the communication signal might enter the power amplifier (PA), and another part might enter the bias resistors and return to the bias circuit. In some cases, this split signal current can be prevented if the input resistors provide an impedance that is sufficiently high or higher than the PA's input impedance. In some cases, the required bias resistor value can be determined based on the coupling capacitor values, the gate capacitance of the input transistors, and the transmitter's operating frequency.

[0017] A problem arises when using coupling capacitors if a dynamic bias scheme is implemented in a lower-frequency transmitter. In some examples, dynamic bias schemes involve tracking a signal level of the input to the power amplifier (e.g., tracking an envelope of the power amplifier output signal) and generating a bias that is a function of the signal amplitude. In some examples, the high values ​​of the coupling capacitors and bias resistors make it impractical to implement dynamic biasing due to the RC-based biasing (e.g., bias resistors implemented in parallel with the coupling capacitors in lower-frequency transmitters).

[0018] For example, high values ​​of the coupling capacitors and bias resistors increase the RC delay of the bias path, causing a memory effect and introducing non-idealities into the transmitter output. This memory effect worsens the transmitter's error vector magnitude (EVM). As used here, "memory effect" refers to the phenomenon where the transmitter's output signal is affected by its previous states or inputs. In some examples, the memory effect can arise from various factors. These factors can introduce a time-dependent response in the transmitter, causing the output signal to be affected by past inputs. For instance, if there are large resistances in the dynamic bias path and large coupling capacitors at the PA input, the bias will take longer to respond to a change in the level of the PPA output signal.For example, if the PPA output suddenly increases, the dynamic bias scheme ideally outputs a bias voltage that faithfully follows the increase in the envelope of the PPA output signal. However, the large resistance in the bias path, in conjunction with the large coupling capacitor, introduces a delay in tracking the increase in the PPA output envelope, thus creating a delay that causes the memory effect. The resistance value cannot be decreased because without a high resistance value, there is a split current signal, which causes a decrease in the PPA voltage gain, requiring higher current consumption in the PPA to recover the lost gain.

[0019] Examples revealed here reduce and / or eliminate the problem of the memory effect and decrease the amount of semiconductor die area required when implementing a dynamic bias.

[0020] Fig. Figure 1 is a block diagram of an exemplary transmitter 100 for transmitting an information signal. The exemplary transmitter 100 comprises an exemplary signal processing circuit arrangement 102, exemplary digital-to-analog converters (DACs) 104A, 104B, exemplary filters 106A, 106B, an exemplary mixer 108, an exemplary preamplifier circuit arrangement 110, an exemplary power amplifier (PA) 112, an exemplary balun 114, and an exemplary antenna 116.

[0021] In Fig. 1 includes the exemplary signal processing circuit arrangement 102 first connections 118a, 118b. The exemplary DACs 104A, 104B include second connections 120a, 120b. The exemplary filters 106A, 106B include third connections 122a, 122b. The exemplary mixer 108 includes a fourth connection 124. The exemplary preamplifier circuit arrangement 110 includes a fifth connection 126. The exemplary PA 112 includes a sixth connection 128. The exemplary balun 114 includes a seventh connection 130. In some examples, the connections (e.g., the first connections 118a, 118b, the second connections 120a, 120b, the third connections 122a, 122b, the fourth connection 124, the fifth connection 126, the sixth connection 128, and the seventh connection 130) represent communication channels, such as wires, copper traces, cables, etc.The exemplary connections 118a, 118b, 120a, 120b, 122a, 122b, 124, 126, 128, 130 can be any type of channel that can communicate data (e.g., analog signals, digital signals, waveforms, etc.) from one stage to another.

[0022] The exemplary signal processing circuit arrangement 102 is coupled to the exemplary DACs 104A and 104B via the exemplary first connections 118a and 118b. In this example, the first connections 118a and 118b are representative of the outputs of the signal processing circuit arrangement 102, with the first connection 118a and the first connection 118b providing differential outputs. The exemplary DACs 104A and 104B are coupled to the exemplary filters 106A and 106B via the exemplary second connections 120a and 120b, respectively. In this example, the second connections 120a and 120b are representative of the outputs of the DACs 104A and 104B, with the second connection 120a and the second connection 120b providing differential outputs. The exemplary filters 106A, 106B are coupled to the exemplary mixer 108 via the exemplary third connections 122a, 122b.In this example, the third connections 122a and 122b are representative of the outputs of filters 106A and 106B, with third connections 122a and 122b providing differential outputs. The exemplary mixer 108 is coupled to the exemplary preamplifier circuit arrangement 110 via the exemplary fourth connection 124. The exemplary fourth connection 124 provides a differential output. The exemplary preamplifier circuit arrangement 110 is coupled to the exemplary PA 112 via the exemplary fifth connection 126. The exemplary fifth connection 126 provides a differential output. The exemplary PA 112 is coupled to the exemplary balun 114 via the exemplary sixth connection 128. The exemplary sixth connection 128 provides a differential output.The exemplary balun 114 is coupled to the exemplary antenna 116 via the exemplary seventh connection 130.

[0023] In Fig. Figure 1 is the exemplary signal processing circuit arrangement 102, hardware that processes digital signals. In some examples, the signal processing circuit arrangement 102 is a baseband processor and / or a modem. For example, the signal processing circuit arrangement 102 converts digital data into analog signals suitable for transmission over a communication channel. In some examples, the signal processing circuit arrangement 102 receives the digital information from a programmable circuit arrangement (e.g., a central processing unit (CPU), a microprocessor, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), which may be in the form of binary bits, and prepares it for modulation. For example, the signal processing circuit arrangement 102 generates in-phase (I) data and quadrature (Q) data from the digital information.In some examples, the I-data is a data signal representing an in-phase sine wave, and the Q-data is a data signal representing a quadrature-phase sine wave, where the in-phase and quadrature-phase sine waves have the same frequency and are 90 degrees out of phase with each other. In other examples, the I-data is binary bits represented by a modulated cosine waveform, and the Q-data is binary bits represented by a modulated sine waveform (where, for example, the sine wave is shifted 90 degrees relative to the cosine wave). Of course, any signal processing circuit arrangement and any modulation scheme can be used.In this example, the I-data is provided via a first of the first connections 118a for a first DAC 104A, and the Q-data is provided via a second of the first connections 118 for the second DAC 104B.

[0024] In Fig. 1. The exemplary DACs 104A and 104B convert the output of the signal processing circuit arrangement 102 (e.g., I-data and Q-data) into an analog signal. For example, the DACs 104A and 104B convert the digital data, which is in a discrete binary form consisting of 0s and 1s, into a continuous analog waveform. In some examples, the first DAC 104A converts the I-data into an analog signal, and the second DAC 104B converts the Q-data into an analog signal. The exemplary DACs 104A and 104B convert the output of the signal processing circuit arrangement 102 to transmit information contained in the output of the signal processing circuit arrangement 102. In some examples, the DACs 104A, 104B generate the modulating signal that is to be mixed by the exemplary mixer 108.

[0025] In Fig. In this example, the exemplary filters 106A and 106B receive the output of the exemplary DACs 104A and 104B via the exemplary second connections 120a and 120b to filter out unwanted frequencies. For example, the outputs of the DACs 104A and 104B at the second connections 120a and 120b are continuous analog waveforms that contain not only the original data from the digital information but also additional frequencies introduced during the digital-to-analog conversion. Therefore, the exemplary filters 106A and 106B eliminate noise and irrelevant components from the transmitted signal. In some examples, a first filter 106A receives the output of the DAC 104A via the first of the second connections 120a, and the second filter 106B receives the output of the second DAC 104B via the second of the second connections 120b.The bandpass filters can have any suitable frequency profile, and in some examples, filters 106A and 106B are bandpass filters. Additionally or alternatively, the example filters 106A and 106B are any type of analog signal filter.

[0026] In Fig. In Figure 1, the exemplary mixer 108 mixes the output of the exemplary filters 106A and 106B with a carrier signal to convert the modulated signals (e.g., the filtered analog signals) to a higher frequency that can be transmitted. Such a conversion is called "up-conversion." Although only one stage of frequency up-conversion is shown, there may be multiple stages of frequency up-conversion utilized by the exemplary transmitter 100. In some examples, the carrier signal is a local oscillator (LO) signal with a high frequency capable of traveling long distances with minimal interference. In other examples, the mixer 108 combines the carrier signal (e.g., the LO signal) with the filtered analog signals, resulting in output signals. For example, mixer 108 combines the carrier signal with the output of the first filter 106A and the output of the second filter 106B to produce output signals (e.g.to generate differential output signals. The exemplary mixer 108 can be implemented by any type of mixing circuit arrangement. Depending on the application of the exemplary transmitter 100, the modulated signal can utilize any type of modulation technique (e.g., amplitude modulation, frequency modulation, phase modulation). In this example, the differential output signals are provided via the fourth connection 124 for the preamplifier circuit arrangement 110.

[0027] In Fig. 1. The exemplary preamplifier circuit arrangement 110 prepares the output signals that are to be amplified by the exemplary PA 112. As described in detail, for example, in conjunction with Fig. As described in Figure 2, the preamplifier circuit arrangement 110 generates the initial gain signals, which are amplified sufficiently to be noise-tolerant and determinable by the PA 112. The exemplary preamplifier circuit arrangement 110 receives the output signals via the fourth connection 124 and first and second coupling capacitors 132a, 132b. In some examples, the first coupling capacitor 132a and the second coupling capacitor 132b couple the output signals from the mixer 108 to the preamplifier circuit arrangement 110. In some examples, the first and second coupling capacitors 132a, 132b prevent the output signals from interfering with the bias voltage applied to the input devices of the preamplifier circuit arrangement 110 by blocking all DC components in the output signals. The exemplary initial amplification signals are provided for further processing by the exemplary PA 112.In this example, the first amplified signals are provided via the fifth connection 126 for the PA 112. An example of the preamplifier circuit arrangement 110 is shown in conjunction with... Fig. 2 described in more detail.

[0028] In Fig. 1. The exemplary PA 112 generates second amplification signals that include a power level (e.g., an amplitude) large enough to transmit the information. For example, the PA 112 increases the power level of the first amplification signals until they meet the specification of the transmitter 100. In some examples, the second amplification signals drive the antenna 116. For example, the purpose of the transmitter 100 is to deliver a signal with required characteristics and a specified power level to the antenna 116, and the PA 112 provides the amplification of this signal to the expected level at an antenna terminal (e.g., the balun 114). In this example, the second amplified signals are provided to the balun 114 via the sixth connection 128.

[0029] In Fig. 1. The exemplary balun 114 matches the impedance of the antenna 116 to the channels (e.g., transmission lines) carrying the second gain signals from the PA 112. In some examples, the balun 114 is a device used to convert a balanced (e.g., differential) AC signal (e.g., second gain signals) into an unbalanced (e.g., single-channel) AC signal. By using the exemplary balun 114, the balanced signal (e.g., second gain signals) from the transmission line is converted into an unbalanced signal suitable for the antenna 116. This helps ensure efficient power transmission and minimizes signal loss due to impedance mismatch. Alternatively, the exemplary balun 114 converts a balanced signal into an unbalanced signal.The output of the example balun 114 depends on the configuration of the example PA 112 and the example antenna 116. In this example, the output of the balun 114 is provided to the antenna 116 via the seventh connection 130.

[0030] In Fig. In this example, the antenna 116 serves to receive the second amplification signals and transmit them as a wireless FF signal. The antenna 116 is coupled to the output of the balun 114 via the seventh connection 130 and receives an unbalanced (or single-channel) version of the second amplification signals. In some examples, the antenna 116 is implemented by any type of antenna suitable for transmitting FF signals.

[0031] Fig. Figure 2 is a schematic representation of an exemplary preamplifier circuit arrangement 210 for implementing the preamplifier circuit arrangement 110 from Fig. 1. The exemplary preamplifier circuit arrangement 210 comprises an exemplary first pre- and power amplifier (PPA) 202, an exemplary second PPA 204, an exemplary envelope detection circuit arrangement 206, an exemplary common-mode feedback or CMFB amplifier 208, and exemplary averaging resistors 218a, 218b. The exemplary representation in Fig. 2 includes an exemplary PA 212, an exemplary balun 214 and an exemplary antenna 216 to illustrate the connections 226, 228 and 230 within the schematic representation of the exemplary preamplifier circuit arrangement 210.

[0032] In Fig. 2 The exemplary first PPA 202 comprises a first PPA input 220a and a second PPA input 220b, designed to receive the output signals (e.g., up-converted modulated signals) from the mixer (not shown). For example, the first PPA input 220a and the second PPA input 220b of the first PPA 202 are connected to the outputs of the mixer 108 via the exemplary fourth connection 224 and the exemplary coupling capacitors 132a, 132b. Fig. 1 coupled. The exemplary first PPA 202 serves to provide first amplified signals for both the exemplary second PPA 204 and the exemplary envelope detection circuit arrangement 206. For example, a first signal path that couples the first PPA 202 with the second PPA 204 and the envelope detection circuit arrangement 206 are arranged electrically in parallel to each other. The first signal path couples a first PPA output 222a and a second PPA output 222b to the exemplary second PPA 204. In some examples, the first PPA 202 serves to increase the gain of the output signals by an initial amount to 1) prepare the output signals for amplification by the PA 112 and 2) provide a signal level high enough for the envelope detection circuit arrangement 206 to detect (e.g., track, detect, identify, etc.) the envelope of the amplified output signals.In some examples, the signal at the first PPA output 222a has the same gain and frequency as the signal at the second PPA output 222b, but is phase-shifted by 180 degrees relative to the signal at the second PPA output 222b. Additionally and / or alternatively, the signal at the first PPA output 222a is phase-shifted by an arbitrary number of degrees relative to the signal at the second PPA output 222b.

[0033] In Fig. In Figure 2, the exemplary second PPA 204 comprises a third PPA input 234a and a fourth PPA input 234b. The third PPA input 234a is coupled to the exemplary first PPA output 222a via an exemplary first coupling capacitor 232a. The fourth PPA input 234b is coupled to the exemplary second PPA output 222b via an exemplary second coupling capacitor 232b. The exemplary second PPA 204 comprises a third PPA output 236a and a fourth PPA output 236b. The exemplary third and fourth PPA outputs 236a and 236b are coupled to the third connection 226.

[0034] In this example, the second PPA 204 provides a second gain for the first amplified output signals at the third and fourth PPA inputs 234a and 234b, and outputs second amplified signals at the third and fourth PPA outputs 236a and 236b. For example, the second PPA 204 increases the gain of the first amplified signals by a second amount to prepare the output signals for further amplification by the PA 112. In this example, the second PPA 204 increases the gain of the signals at the first PPA output 222a and the second PPA output 222b.

[0035] In Fig. In this example, the second PPA 204 serves to output a PA bias voltage on the same path (e.g., on the third connection 226) as the second amplified signals. In this example, the third PPA output 236a includes the second amplified signal and the PA bias voltage for biasing input devices of the exemplary PA 112. In this example, the fourth PPA output 236b includes the second amplified signal and the PA bias voltage for biasing the input device of the PA 112. In some examples, the bias voltage is generated based on the envelope detection circuit arrangement 206, the CMFB amplifier 208, and the averaging resistors 218a and 218b.

[0036] For example, includes, in Fig. 2, the preamplifier circuit arrangement 110, the envelope detection circuit arrangement 206 for tracking an envelope of an output of the first PPA 202. Examples of the envelope detection circuit arrangement 206 are described in U.S. Patent No. 11,303,248, which is hereby incorporated in its entirety by reference. The exemplary envelope detection circuit arrangement 206 comprises a first envelope input and a second envelope input, wherein the first envelope input is coupled to the first PPA output 222a and the second envelope input is coupled to the second PPA output 222b. In some examples, the envelope detection circuit arrangement 206 detects (e.g., tracks, monitors, identifies, records) the output of the first PPA 202 based on the signals at the first PPA output 222a and the second PPA output 222b.The exemplary envelope detection circuit arrangement 206 generates a rectified bias voltage of the detected output. For example, the envelope detection circuit arrangement 206 monitors a level of the first amplified signal (e.g., the signals at the first and second PPA outputs 222a, 222b) and outputs a full-wave rectified signal whose mean follows a amplitude or voltage fluctuation level of the first amplified signal. In other words, the exemplary envelope detection circuit arrangement 206 takes a high-frequency signal as an input and produces an output that is the full-wave rectified version, the mean level of which follows the envelope of the high-frequency input signal. In some examples, the envelope detection circuit arrangement 206 then adds a fixed bias voltage to the full-wave rectified signal.For example, if the detected output of the first PPA 202 is low, the fixed bias ensures that the output of the envelope detection circuit arrangement 206 is at a level high enough to drive an input to the CMFB amplifier 208. Ultimately, the envelope detection circuit arrangement 206 generates a dynamic bias at an eighth connection 238. The exemplary envelope detection circuit arrangement 206 is coupled to the CMFB amplifier 208 via the eighth connection. In some examples, the dynamic bias is provided as an input to the CMFB amplifier 208. The exemplary envelope detection circuit arrangement 206 is described in more detail below in conjunction with... Fig. 4 described.

[0037] In Fig. The exemplary CMFB amplifier 208 comprises a first amplifier input, a second amplifier input, and a feedback output 240. The first amplifier input is coupled via the eighth connection 238 to the exemplary envelope detection circuit arrangement 206 to obtain the dynamic bias. The second amplifier input is coupled to a common-mode output node 242 of the exemplary averaging resistors 218a and 218b. The feedback output 240 is coupled to a fifth PPA input 246 of the second PPA 204 to feed a correction signal back to the second PPA 204. In some examples, the feedback output 240 is a feedback input to the second PPA 204.

[0038] In Fig. Figure 2 comprises the exemplary averaging resistors 218a and 218b: a first averaging resistor 218a with a first and a second resistor terminal, and a second averaging resistor 218b with a third and a fourth resistor terminal. The first resistor terminal of the first averaging resistor 218a is coupled to the third PPA output 236a, and the second resistor terminal of the first averaging resistor 218a is coupled to the third resistor terminal of the second averaging resistor 218b at the common-mode output node 242. The fourth resistor terminal of the second averaging resistor 218b is coupled to the fourth PPA output 236b. In this example, the first and second averaging resistors 218a and 218b provide an average amplitude of the second amplified signals.For example, the output common-mode node 242, which connects the second resistor terminal of the first averaging resistor 218a to the third resistor terminal of the second averaging resistor 218b, is an output common-mode voltage of the second PPA 204.

[0039] In an exemplary first operation of the exemplary preamplifier circuit arrangement 110, the exemplary first PPA 202 receives first output signals from a mixer (e.g., the mixer 108). Fig. 1) The exemplary first PPA 202 amplifies the first output signals by an initial amount. The exemplary envelope detection circuit arrangement 206 receives the first amplified signals at the first PPA output 222a and the second PPA output 222b. The exemplary envelope detection circuit arrangement 206 rectifies the output of the exemplary first PPA 202 and generates a dynamic bias. In some examples, the dynamic bias is an instantaneous bias whose value depends on the amplitude of the signals at outputs 222a and 222b of the first PPA 202. In some examples, an instantaneous bias is a dynamic bias that instantaneously (e.g., approximately in real time) follows the change in the amplitude of the signals at output 222a of the first PPA 202. In some examples, the input devices of the PA 212 are biased at this dynamic bias.

[0040] In the exemplary first operation of the preamplifier circuit arrangement 110, the dynamic bias voltage is provided via the eighth connection 238 for the first amplifier input of the CMFB amplifier 208. The exemplary CMFB amplifier 208 ensures that the exemplary common-mode node 242 of the exemplary second PPA 204 is set equal to the exemplary dynamic bias voltage. For example, the CMFB amplifier 208 compares the dynamic bias voltage with the output common-mode voltage of the second PPA 204. The exemplary CMFB amplifier 208 feeds a correction signal back to the feedback output 240 at the fifth PPA input 246. The correction signal at the feedback output 240 changes until the two amplifier inputs of the CMFB amplifier 208 are equal.For example, the correction signal at feedback output 240 is applied to the gate terminals of two PMOS transistors, which operate to increase or decrease the bias voltage at the third and fourth PPA outputs 236a and 236b. An exemplary operation of the two PMOS transistors is described below in conjunction with... Fig. 3 is described in more detail. In some examples, the output common-mode voltage refers to an average of two sinusoidal signals (e.g., the second amplified signals at the third PPA output 236a and the fourth PPA output 236b). Therefore, the bias voltage of the PA 212 is adjusted based on the correction signal. The exemplary third PPA output 236a and the exemplary fourth PPA output 236b both carry this adjusted bias voltage and the actual modulated signal. For example, the actual modulated signal (e.g., the second amplified signals) is "on top" of the bias voltage. As used here, "on top" means that the AC signal is combined with the DC signal (e.g., superimposed, added to, modulated with, mixed with, etc.) and that the resulting waveform carries both the characteristics of the DC signal and the variations introduced by the AC signal.

[0041] In an exemplary second operation of the exemplary preamplifier circuit arrangement 110, the exemplary first PPA 202 receives second output signals from a mixer (e.g., the mixer 108). Fig. 1) In this example, the second output signals have a higher gain than the first output signals in the exemplary first operation. Therefore, the output of the exemplary first PPA 202 increases relative to the output during the exemplary first operation. The exemplary envelope detection circuit arrangement 206 rectifies the output of the exemplary first PPA 202 and generates a dynamic bias voltage, the value of which has increased due to the increase in the amplitude of the second modulated signals.

[0042] In the exemplary second operation of the preamplifier circuit arrangement 110, the increased dynamic bias voltage is provided via the eighth connection 238 for the first amplifier input of the CMFB amplifier 208. The CMFB amplifier 208 compares the dynamic bias voltage with the common-mode output voltage of the second PPA 204. In some examples, the common-mode output voltage of the second PPA 204 may initially be lower than the dynamic bias voltage. The exemplary CMFB amplifier 208 feeds a correction signal back into the exemplary second PPA 204, which causes the second PPA 204 to increase its common-mode output voltage. The correction signal at the feedback output 240 changes until the two amplifier inputs of the CMFB amplifier 208 are equal. Therefore, the bias voltage of the PA 212 is adjusted based on the correction signal and faithfully follows the signals at the output of the first PPA 202.

[0043] In this example, a dynamic bias loop provided by the CMFB amplifier 208 is fast enough to ensure that the memory effect does not affect an output of the transmitter (e.g., transmitter 100 from). Fig. 1) not damaged. For example, the correction signal provided by the CMFB amplifier 208 changes at a rate fast enough to ensure that the PA bias faithfully follows the output of the first PPA 202. Additionally, if the PA bias is on the same signal path as the actual signal, the area of ​​the power amplifier on a die is reduced. For example, combining the bias signal path and the actual signal path at the third PPA output 236a and the fourth PPA output 236b eliminates the need for coupling capacitors between the PPA (e.g., the second PPA 204) and the PA 212.

[0044] Fig. Figure 3 is a schematic representation of the exemplary second PPA 304. The exemplary second PPA 304 can replace the exemplary second PPA 204. Fig. 2 implement. The exemplary second PPA 204 comprises an exemplary first transistor 302a, an exemplary second transistor 302b, an exemplary third transistor 306, an exemplary fourth transistor 308, an exemplary fifth transistor 310, an exemplary current source 312, the exemplary first averaging resistor 318a, the exemplary second averaging resistor 318b, the exemplary first coupling capacitor 332a and the exemplary second coupling capacitor 332b.

[0045] In Fig. Figure 3 represents the exemplary first transistor 302a, the exemplary second transistor 302b, and the exemplary fifth transistor 310, representing structures and characteristics of n-channel metal-oxide-semiconductor (NMOS) transistors that can be used to implement the second PPA 304, the first PPA 202, the PA 112 / 212, and / or any type of amplifier. Although the following description refers only to the first transistor 302a, the description applies to each of the exemplary first transistor 302a, the exemplary second transistor 302b, the exemplary fifth transistor 310, and / or any other NMOS transistor. The exemplary first transistor 302a includes a gate terminal 314, a drain terminal 316, and a source terminal 317. In some examples, the gate terminal 314 is a control terminal. In some examples, the drain terminal 316 and the source terminal 317 are power terminals.The exemplary first transistor 302a operates at a specific threshold voltage (VTH). The value of VTH depends on intrinsic device characteristics of the transistor (e.g., doping concentration, channel length, oxide thickness, etc.) and the operating temperature. When a voltage level applied to the gate terminal 314 meets the VTH of the first transistor 302a (e.g., is greater than it) (e.g., VGS > VTH), the first transistor 302a is said to be in an "on" state and establishes a closed circuit between the drain terminal 316 and the source terminal 317, causing an electrical drain-to-source current (Ids) to flow between the drain terminal 316 and the source terminal 317 of the first transistor 302a (e.g., Ids = ION). If the voltage level applied to the exemplary gate terminal 314 does not meet the VTH of the first transistor 302a (e.g., is smaller than it) (e.g.,VGS<VTH), wird der erste Transistor 302a als in einem „Aus“-Zustand befindlich bezeichnet und errichtet einen offenen Stromkreis zwischen dem Drain-Anschluss 316 und dem Source-Anschluss 317, bewirkend, dass der elektrische Drain-zu-Source-Strom (Ids) versiegt (z. B. Ids = IOFF).

[0046] In Fig. Figure 3 represents the exemplary third transistor 306 and the exemplary fourth transistor 308, representing a different type of transistor. For example, the third transistor 306 and the fourth transistor 308 represent structures and characteristics of p-channel metal-oxide-semiconductor and PMOS transistors, respectively, which can be used to implement the second PPA 204 / 304, the first PPA 202, the PA 112 / 212, and / or any type of amplifier. In the examples disclosed here, PMOS transistors are represented with an arrow at the source terminal pointing toward the gate terminals, while NMOS transistors are represented with an arrow at the source terminal pointing away from the gate terminal. The "on" and "off" states of a PMOS transistor are activated based on opposing inputs at its terminal relative to the NMOS transistor.For example, if a voltage level applied to the gate terminal of a PMOS transistor relative to the supply voltage (VCC) equals the VTH of the PMOS transistor (e.g., is greater than it) (e.g., VGS > VTH), the PMOS transistor is said to be in an "off" state, and if a voltage level applied to the gate terminal of the PMOS transistor relative to the supply voltage (VCC) does not equal the VTH of the PMOS transistor (e.g., is less than it) (e.g., VGS > VTH), the PMOS transistor is said to be in an "off" state. <VTH), wird der PMOS-Transistor als in einem „Ein“-Zustand befindlich bezeichnet.

[0047] In Fig. In the second example transistor 302b, the second example transistor comprises a gate terminal, a drain terminal, and a source terminal. The third example transistor 306 comprises a gate terminal, a drain terminal, and a source terminal. The fourth example transistor 308 comprises a gate terminal, a drain terminal, and a source terminal. The fifth example transistor 310 comprises a gate terminal, a drain terminal, and a source terminal. As described above, the first example averaging resistor 318a comprises the first resistor terminal and the second resistor terminal, and the second example averaging resistor 318b comprises the third resistor terminal and the fourth resistor terminal.

[0048] In Fig. The gate terminal of 314 is coupled to the first coupling capacitor 332a. The drain terminal of 316 is coupled to the drain terminal of the exemplary third transistor 306. The source terminal of 317 is coupled to ground. The gate terminal of the exemplary second transistor 302b is coupled to the second coupling capacitor 332b. The drain terminal of the exemplary second transistor 302b is coupled to the drain terminal of the exemplary fourth transistor 308. The source terminal of the exemplary second transistor 302b is coupled to ground.

[0049] In Fig. 3 is the gate terminal of the exemplary third transistor 306 coupled to the gate terminal of the exemplary fourth transistor 308. The gate terminals of the exemplary third and fourth transistors 306 and 308 are connected to the exemplary feedback output 340 of the exemplary CMFB amplifier 208. Fig. 2 coupled. For example, the gate terminals of the exemplary third and fourth transistors 306, 308 receive (e.g., are provided with, etc.) the correction signal from the CMFB amplifier 208. The source terminals of the exemplary third and fourth transistors 306, 308 are coupled to a voltage supply rail (VDDA).

[0050] In Fig. 3. The exemplary first transistor 302a and the exemplary second transistor 302b are biased by the exemplary fifth transistor 310, and the exemplary fifth transistor 310 is biased at Iref. In some examples, Iref is a current generated by the exemplary current source 312. The exemplary second PPA 304 from Fig. 3 includes an exemplary third resistor 320 and an exemplary fourth resistor 322. The exemplary third resistor 320 includes a fifth resistor terminal and a sixth resistor terminal. The exemplary fourth resistor 322 includes a seventh resistor terminal and an eighth resistor terminal.

[0051] In Fig. The drain terminal of the exemplary fifth transistor 310 is coupled to an output of the exemplary current source 312. The gate terminal of the exemplary fifth transistor 310 is connected to the drain terminal of the exemplary fifth transistor 310 and the output of the exemplary current source 312. The gate terminal of the exemplary fifth transistor 310 is coupled to the fifth resistor terminal of the exemplary third resistor 320 at a bias node 324. The sixth resistor terminal of the exemplary third resistor 320 is coupled to the gate terminal 314 of the exemplary first transistor 302a. The seventh resistor terminal of the exemplary fourth resistor 322 is coupled to the gate terminal of the exemplary fifth transistor 310 at the bias node 324.The eighth resistor terminal of the exemplary fourth resistor 322 is coupled to the gate terminal of the exemplary second transistor 302b. In this way, the exemplary fifth transistor 310 biases the gate voltages of the exemplary first transistor 302a and the second transistor 302b through the exemplary third resistor 320 and the exemplary fourth resistor 322. For example, the voltage Vref at the bias node 324 is applied to the gate terminals of the exemplary first transistor 302a and the exemplary second transistor 302b, where Vref is a level that satisfies (e.g., is greater than) the VTH of the first and second transistors 302a and 302b, causing the first and second transistors 302a and 302b to be in an "on" state.

[0052] In Fig. In section 3, the exemplary first transistor 302a and the exemplary second transistor 302b are referred to as the gain transistors. For example, the first transistor 302a and the second transistor 302b provide the second amount of gain for the input signals vin_p, vin_m (e.g., the first amplified signals at the first and second PPA outputs 222a, 222b). The exemplary first transistor 302a outputs a first output signal (vout_m) whose gain has been increased by a second amount. The exemplary second transistor 302b outputs a second output signal (vout_p) whose gain has been increased by a second amount. The exemplary first and second transistors 302a, 302b invert the input signal (vin_p and vin_m, respectively) from gate to drain. In some examples, the common-mode output voltage (vout_avg) is obtained by averaging the first output signal (vout_m) and the second output signal (vout_p).For example, the averaging resistors 318a and 318b generate the common-mode output voltage of the first output signal (vout_m) and the second output signal (vout_p), where the common-mode output voltage is at a common-mode output node 342. The common-mode output voltage of the first output signal (vout_m) and the second output signal (vout_p) is provided for the second amplifier input of the exemplary CMFB amplifier 208.

[0053] In Fig. In this section, the exemplary third transistor 306 and the exemplary fourth transistor 308 ensure that the output nodes 336a and 336b are held at the required bias. For example, the third transistor 306 and the fourth transistor 308 are biased by the correction signal at the feedback output 340 provided by the CMFB amplifier. Using this correction signal, the third transistor 306 and the fourth transistor 308 maintain the output nodes 336a and 336b at the required bias. The CMFB amplifier controls the gate terminals of the exemplary third transistor 306 and the exemplary fourth transistor 308 via a dynamic correction signal. For example, the CMFB amplifier ensures that the output common-mode voltage (vout_avg) is set equal to the dynamic bias by adjusting the value of the correction signal.

[0054] In one example operation, the example CMFB amplifier determines that the dynamic bias is increased. In this example, the CMFB amplifier outputs a reduced correction signal at feedback output 340 to ensure that the output common-mode voltage (vout_avg) also increases. In some examples, when the voltage at the gate terminals of the third transistor 306 and the fourth transistor 308 drops to a low level (e.g., decreases), the current at the drain terminals increases. In another example operation, the example CMFB amplifier determines that the dynamic bias is decreased. In this example, the CMFB amplifier outputs an increased correction signal at feedback output 340 to ensure that the output common-mode voltage (vout_avg) also decreases.In some examples, when the voltage at the gate terminals of the third transistor 306 and the fourth transistor 308 rises to a high level (e.g., increases), the current at the drain terminals decreases.

[0055] In some examples, the values ​​of the averaging resistors 318a and 318b are chosen to be high enough not to reduce the gain of the second PPA 304, but low enough not to slow down the dynamic bias path. For example, if the resistance of the averaging resistors 318a and 318b is too low, some of the signal current generated by the first and second transistors 302a and 302b, in response to the first amplified signals, flows into the averaging resistors 318a and 318b, thereby reducing the voltage gain of the second PPA 304. In this scenario, the current consumption of the second PPA 304 must be increased to recover the lost gain. Alternatively, if the resistance of the averaging resistors 318a, 318b is too high, the averaging resistors 318a, 318b cause the output common-mode voltage (vout_avg) to take longer to follow the dynamic bias (e.g.to adjust to this), and therefore cause a memory effect. Therefore, the resistance values ​​of the averaging resistors 318a and 318b are selected so that there is neither a memory effect nor increased current consumption.

[0056] Fig. Figure 4 is a schematic representation of the exemplary envelope detection circuit arrangement 406 for tracking the envelope of the first PPA outputs at the first and second PPA outputs 422a, 422b and generating a dynamic bias at an eighth junction 438 based on the envelope. The exemplary envelope detection circuit arrangement 406 comprises an exemplary level detector 402 based on a full-wave rectifier and an exemplary filter 404. The exemplary level detector 402 monitors a level of the first amplified signals at the first PPA outputs 422a, 422b and outputs a full-wave rectified signal whose mean follows a amplitude or voltage fluctuation level of the first amplified signals at the first PPA outputs 422a, 422b.In one example, the level detector 402, based on a full-wave rectifier, is an envelope detector that takes a high-frequency signal as an input and produces an output that is the full-wave rectified version, the mid-level of which follows the envelope of the high-frequency input signal. The exemplary filter 404 includes a capacitor that stores charge on a rising edge of the high-frequency signal and slowly releases it through a resistor as the high-frequency signal falls.

[0057] In Fig. Figure 4 comprises the exemplary level detector 402 based on a full-wave rectifier, comprising first and second NMOS transistors T1 and T2, which are coupled together. The drain terminals of the first and second NMOS transistors T1 and T2 are biased to a suitable voltage level, VDDA_ENV_DET, in the exemplary envelope detection circuit arrangement 406, and the source terminals of the first and second NMOS transistors T1 and T2 are coupled together and, via an exemplary resistor R3, to an input node of the exemplary filter 404. In some examples, the voltage level VDDA_ENV_DET is approximately 1.2 volts. A full-wave rectified node 408 is located at a point in the exemplary envelope detection circuit arrangement 406 where the source terminals of the NMOS transistors T1 and T2 are coupled together.In some examples, this full-wave rectified node 408 sums the voltages from the rectified half-cycles from the source terminals of T1 and T2.

[0058] In Fig. In Figure 4, the exemplary resistors R1 and R2 and the exemplary capacitors C3 and C4 are coupled to the gate terminals of the first and second NMOS transistors T1 and T2, respectively. The sides of the exemplary capacitors C3 and C4 opposite the gate terminals of the first and second NMOS transistors T1 and T2 are connected to the outputs 422a and 422b of the exemplary first PPA1 (e.g., the first PPA 202 from...). Fig. 2) coupled to receive the differential first amplified signals, shown as V1+ and V1. A gate voltage signal VG_ENV_DET is applied across the exemplary resistors R1 and R2, opposite the side of resistors R1 and R2 that are coupled to the gate terminals of T1 and T2. In one example, the gate voltage signal VG_ENV_DET is a fixed DC bias signal (F_bias).

[0059] In Fig. 4. The exemplary filter 404 provides a filtered level signal (e.g., dynamic bias) at a node in the exemplary envelope detection circuit arrangement 406, where the exemplary capacitor C8 and the exemplary resistor R6 are coupled together. The exemplary dynamic bias is fed via the eighth connection 438 to an input of the exemplary CMFB amplifier to drive the exemplary PA (e.g., PA 112 from Fig. 1 and / or the PA 212 from Fig. 2) to pre-tension, as revealed herein.

[0060] In Fig. Figure 4 includes the exemplary envelope detection circuit arrangement 406 with a third NMOS transistor T3. The side of the exemplary resistor R3 opposite the full-wave rectifier node 408 is coupled to T3. The drain terminal of the NMOS transistor T3 is coupled to the exemplary resistor R3, opposite one side of the exemplary resistor R3 that is coupled to the full-wave rectifier node 408. The exemplary resistor R3 is a level-shifting resistor that controls a DC component of the dynamic bias signal, providing a small signal voltage gain of the PA (e.g., PA 112 from Fig. 1 and / or PA 212 from Fig. 2) adapts. The source terminal of T3 is coupled to one side of the exemplary capacitors C5-C8, opposite a side coupled to the exemplary resistors R4-R6. A control signal with a defined voltage level is applied to the gate terminal of T3 to control the application of the dynamic bias signal to the side of capacitors C5-C8 opposite a side coupled to the exemplary resistors R4-R6, thereby switching the exemplary envelope detection circuit arrangement 406 on (or off). As an example, the control voltage is generated by pumping a defined reference current into the drain terminal of another transistor device whose drain and gate terminals are electrically short-circuited and whose gate terminal is coupled to the gate terminal of T3.Therefore, the exemplary NMOS transistors T3 can be selectively activated to turn on the dynamic bias, or deactivated to turn off the dynamic bias.

[0061] In Fig. Example Filter 404 is a resistor-capacitor, or RC, filter circuit. Example Filter 404 includes several (e.g., four in this example) capacitors C5-C8, with one end of each of the capacitors C5-C8 coupled together. The purpose of the RC filter is to remove high-frequency components from the dynamic bias without adding excessive RC delay, which can lead to a memory effect and degrade the EVM of the transmitted signal. The opposite end of the example capacitors C5-C7 is coupled to an adjacent capacitor via appropriate resistors R4-R6. Thus, the example resistors R4-R6 and the example capacitors C5-C8 form an RC filter circuit adapted to implement a low-pass filter transfer function. A voltage VSSA_ENV_DET (e.g.,(an electrical ground reference) is connected to the side of the exemplary capacitors C5-C8 that is opposite the side that is coupled to the exemplary resistors R4-R6.

[0062] “Containing” and “comprising” (and all forms and tenses thereof) are used here as open terms. Thus, if a claim uses any form of “containing” or “comprising” (e.g., encompasses, includes, encompassing, containing, exhibiting, etc.) as a preamble or within a claim recitation of any kind, it is understood that additional elements, expressions, etc., may be present without being outside the scope of protection of the claim or recitation in question. As used here, the expression “at least,” when used as the transitional term, for example, in a preamble of a claim, is open in the same way as the terms “comprising” and “exhibiting” are open.The term "and / or," when used, for example, in a form such as A, B and / or C, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used here in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to implementations comprising any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used here in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to implementations comprising any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.As used here in the context of describing the execution or performance of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A and B" is intended to refer to implementations comprising any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used here in the context of describing the execution or performance of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A or B" is intended to refer to implementations comprising any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0063] Singular references (e.g., "a," "a," "first," "second," etc.), as used here, do not preclude a plurality. The term "a" object, as used here, refers to one or more of that object. The terms "a," "one or more," and "at least one" are used interchangeably here. Furthermore, several means, elements, or processes, although listed individually, may be implemented, for example, by the same entity or object. In addition, although individual features may be included in different examples or claims, these may potentially be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0064] Fig. Figure 5 is a block diagram of an exemplary programmable circuit arrangement platform 500, structured for implementing sections and / or parts of the transmitter 100. Fig. 1. The Programmable Circuit Assembly Platform 500 can be, for example, a server, a personal computer, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smartphone, a tablet, such as an iPadTM), or any other type of computing and / or electronic device.

[0065] The programmable circuit assembly platform 500 of the illustrated example also includes a programmable circuit assembly 512. The programmable circuit assembly 512 of the illustrated example is hardware. For example, the programmable circuit assembly 512 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers of any desired family or manufacturer. The programmable circuit assembly 512 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit assembly 512 implements the signal processing circuit assembly 102.

[0066] The programmable circuit arrangement 512 of the illustrated example includes a local memory 513 (e.g., a buffer, register, etc.). The programmable circuit arrangement 512 of the illustrated example communicates via a bus 518 with a main memory 514, 516, which includes a volatile memory 514 and a non-volatile memory 516. The volatile memory 514 can be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and / or any other type of RAM. The non-volatile memory 516 can be implemented by flash memory and / or any other desired type of storage device. Access to the main memory 514, 516 of the illustrated example is controlled by a memory controller 517.In some examples, the memory control 517 can be implemented by one or more integrated circuits, logic circuits, microcontrollers of any desired family or manufacturer, or any other type of circuit arrangement for managing the flow of data to and from the main memory 514, 516.

[0067] The programmable circuit arrangement platform 500 of the illustrated example also includes an interface circuit arrangement 520. The interface circuit arrangement 520 can be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a USB (Universal Serial Bus) interface, a Bluetooth® interface, an NFC (Near Field Communication) interface, a PCI (Peripheral Component Interconnect) interface and / or a PCIe (Peripheral Component Interconnect Express) interface.

[0068] In the illustrated example, one or more input devices 522 are connected to the interface circuit arrangement 520. The input device(s) 522 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuit arrangement 512. The one or more input devices 522 can be implemented, for example, by an audio sensor, a microphone, a keyboard, a button, a mouse, a touchscreen, a keypad, a trackball, an isopoint device, and / or a speech recognition system.

[0069] One or more output devices 524 are also connected to the interface circuit arrangement 520 of the illustrated example. The output device(s) 524 can be implemented, for example, by display devices (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), an in-plane switching display (IPS), a touchscreen, etc.), a tactile output device, and / or a loudspeaker. The interface circuit arrangement 520 of the illustrated example therefore typically includes a graphics driver card, a graphics driver chip, and / or a graphics processing unit (GPU) circuit arrangement.

[0070] The interface circuit arrangement 520 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a home gateway, a wireless access point, and / or a network interface to facilitate data exchange with external machines (e.g., computing devices of any kind) through a network 526. Communication can be effected, for example, by an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight (BLS) wireless system, a line-of-sight (LLS) wireless system, a mobile phone system, an optical link, etc.

[0071] The programmable circuit arrangement platform 500 of the illustrated example also includes one or more mass storage discs or devices 528 for storing firmware, software, and / or data. Examples of such mass storage discs or devices 528 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage discs or devices such as flash memory devices and / or SSDs.

[0072] The machine-readable instructions 532 may be stored in the mass storage device 528, in volatile memory 514, in non-volatile memory 516 and / or on at least one non-volatile computer-readable storage medium, such as a CD or DVD, which may be removable.

[0073] It is understood from the foregoing that exemplary systems, devices, manufactured articles, and methods have been disclosed that implement a single signal path to couple a signal output by an amplifier of a transmitter to another amplifier of the transmitter. The single signal path disclosed herein provides both a signal to be amplified and a bias for biasing the subsequent amplifier. Disclosed systems, devices, manufactured articles, and methods improve the efficiency of using a computing device by eliminating and / or reducing a delay in the output of a signal, such as is typically caused by a memory effect. Accordingly, disclosed systems, devices, manufactured articles, and methods relate to one or more improvements to the operation of a machine such as a computer or other electronic and / or mechanical device.

[0074] The following claims are hereby incorporated into this Detailed Description by reference. Although certain exemplary systems, devices, manufactured articles, and processes have been disclosed herein, the scope of protection of the invention of this patent is not limited thereto. Rather, this patent covers all systems, devices, manufactured articles, and processes that reasonably fall within the scope of protection of the claims of this patent. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 11,303,248

[0036]

Claims

[1] System comprising the following: a first amplifier comprising a signal input, a feedback input and a differential output comprising a first output and a second output; a first resistor comprising a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the first output; a second resistor comprising a third resistor terminal and a fourth resistor terminal, wherein the third resistor terminal is coupled to the second resistor terminal at a common-mode output node and the fourth resistor terminal is coupled to the second output; and a second amplifier comprising a first input and a third output, wherein the first input is coupled to the second resistor terminal and the third resistor terminal, and the third output is coupled to the feedback input of the first amplifier. [2] System according to claim 1, wherein the feedback input is coupled to receive a correction signal from the third output, wherein the correction signal is intended to cause the first amplifier to adjust a common-mode voltage at the output common-mode node. [3] System according to claim 1, wherein the second amplifier comprises a second input and the system further comprises an envelope detection circuit arrangement to provide a dynamic bias for the second input. [4] System according to claim 1, further comprising an envelope detection circuit arrangement comprising: a level detector based on a full-wave rectifier, comprising a second input, a third input and a fourth output, wherein the second input and the third input are coupled to receive differential first amplified signals; and a filter comprising a fourth input and a dynamic bias output, wherein the fourth input is coupled to the fourth output of the level detector based on a full-wave rectifier and the dynamic bias output is coupled to the fifth input of the second amplifier. [5] System according to claim 1, further comprising a third amplifier comprising a second input and a third input, wherein the second input is coupled to the first output and the third input is coupled to the second output. [6] System according to claim 1, further comprising: an envelope detection circuit arrangement comprising a second input, a third input and a dynamic bias output, wherein the dynamic bias output is coupled to a fourth input of the second amplifier; and a third amplifier comprising a fourth output and a fifth output, wherein the fourth output is coupled to the second input and is coupled to the signal input, wherein the fifth output is coupled to the third input and is coupled to the signal input. [7] System according to claim 1, further comprising a third amplifier, comprising a fourth output and a fifth output, wherein the fourth output is coupled to the signal input of the first amplifier and the fifth output is coupled to the signal input. [8] System according to claim 1, further comprising: a third amplifier; a first capacitor comprising a first capacitor terminal and a second capacitor terminal, wherein the first capacitor terminal is coupled to a fourth output of the third amplifier and the second capacitor terminal is coupled to the signal input of the first amplifier; and a second capacitor comprising a third capacitor terminal and a fourth capacitor terminal, wherein the third capacitor terminal is coupled to a fifth output of the third amplifier and the fourth capacitor terminal is coupled to the signal input. [9] System according to claim 1, wherein the first amplifier is a preamplifier. [10] System according to claim 1, wherein the second amplifier is a common-mode feedback or CMFB amplifier. [11] Circuit, comprising: a first transistor comprising a first gate terminal, a first drain terminal and a first source terminal; a first resistor comprising a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the first drain terminal; a second transistor, comprising a second gate terminal, a second drain terminal and a second source terminal; a second resistor comprising a third resistor terminal and a fourth resistor terminal, wherein the third resistor terminal is coupled to the second drain terminal and the fourth resistor terminal is coupled to the second resistor terminal at a common-mode output node; a third transistor comprising a third gate terminal, a third drain terminal and a third source terminal, wherein the third drain terminal is coupled to the first resistor terminal and to the first drain terminal; and a fourth transistor comprising a fourth gate terminal, a fourth drain terminal and a fourth source terminal, wherein the fourth drain terminal is coupled to the third resistor terminal and the second drain terminal, and wherein the fourth gate terminal is coupled to the third gate terminal. [12] Circuit according to claim 11, further comprising: a first capacitor, coupled to the first gate terminal; and a second capacitor, coupled to the second gate terminal. [13] Circuit according to claim 11, further comprising: a third resistor, coupled to the first gate terminal; and a fourth resistor, coupled to the second gate terminal. [14] Circuit according to claim 11, further comprising: a power source a fifth transistor comprising a fifth gate terminal, a fifth drain terminal and a fifth source terminal, wherein the fifth drain terminal is coupled to the current source and to the fifth gate terminal; and a third resistor comprising a fifth resistor terminal and a sixth resistor terminal, wherein the fifth resistor terminal is coupled to the fifth gate terminal and the sixth resistor terminal is coupled to the first gate terminal. [15] Circuit according to claim 11, wherein the first transistor and the second transistor are n-channel metal oxide semiconductor and NMOS transistors, respectively. [16] Circuit according to claim 11, wherein the third transistor and the fourth transistor are p-channel metal oxide semiconductor and PMOS transistors, respectively. [17] Circuit according to claim 11, wherein the third gate terminal and the fourth gate terminal are coupled to receive a correction signal, wherein the correction signal is intended to cause the first transistor and the second transistor to adjust a common-mode voltage at the output common-mode node. [18] Circuit according to claim 17, wherein the first resistor and the second resistor are averaging resistors, wherein the averaging resistors are intended to generate the common-mode voltage of a first voltage at the first drain terminal and a second voltage at the second drain terminal. [19] Institution, comprehensive: a signal processing circuit arrangement comprising a first data output and a second data output; a preamplifier circuit arrangement, comprising: a first amplifier comprising a first input, a second input, a first output and a second output, wherein the first input is coupled to receive the first data output and the second input is coupled to receive the second data output; a second amplifier comprising a third input, a fourth input, a feedback input, a differential output comprising a third output and a fourth output, wherein the third input (234a) is coupled to the first output and the fourth input is coupled to the second output; a third amplifier comprising a fifth input, a sixth input and a feedback output, wherein the feedback output is coupled to the feedback input; and Averaging resistors coupled to the third and fourth outputs and coupled to the fifth input; a power amplifier comprising a seventh input and an eighth input, wherein the seventh input is coupled to the third output and the eighth input is coupled to the fourth output; and an antenna coupled to an output of the power amplifier. [20] Device according to claim 19, further comprising a mixer for: Receiving the first data output and the second data output; Generating a first modulated signal based on the first data output and a second modulated signal based on the second data output; Outputting the first modulated signal to the first input; and Outputting the second modulated signal to the second input. [21] Device according to claim 19, wherein the seventh input is coupled to receive a bias and an amplified first modulated signal on a path and the eighth input is coupled to receive the bias and an amplified second modulated signal on a path.

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