GATE CONNECTOR STRUCTURES FOR THE CONSTRUCTION OF AN ADVANCED INTEGRATED CIRCUIT STRUCTURE
DE602018091685T2Active Publication Date: 2026-06-03INTEL CORP
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Patent Information
- Application Number
- DE602018091685
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2017-12-30
- Filing Date
- 2018-10-30
- Publication Date
- 2026-06-03
- Estimated Expiration
- 2038-10-30
AI Technical Summary
Technical Problem
Conventional fabrication processes face challenges in scaling integrated circuits to the 10 nanometer node or smaller, limiting further advancements due to variability and the need for new methodologies to optimize device performance.
Method used
Implementing pitch quartering and merged fin approaches in semiconductor fabrication, combined with selective doping and trench isolation techniques, to enhance the integration of semiconductor fins and transistors, allowing for tighter pitch and reduced leakage pathways.
Benefits of technology
Enables the fabrication of advanced integrated circuits with increased density and improved performance by reducing variability and controlling sub-fin leakage, facilitating the integration of multi-gate transistors on bulk silicon substrates.
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