Integrated inductor with conductive polymer separator layer

Abstract

The conductive polymer layer between the seed layer and the magnetic material in the integrated inductor acts as a separator between the magnetic material and the seed layer, improving the inductor performance. [Solution] The integrated inductor structure includes a conductive polymer isolation layer. Within the integrated inductor, the conductive polymer layer between the seed layer and the magnetic material functions as an isolation layer between the magnetic material and the seed layer, improving inductor performance by mitigating the decrease in inductor efficiency induced, for example, by eddy currents. In one example, a microelectronic assembly 100 includes a glass layer 110 having a first surface and a second surface and an inductor 117 within the layer, where the inductor includes a continuous portion of conductive material 216 between the first surface and the second surface, a magnetic material 214 at least partially surrounding the conductive material, and a conductive polymer 222 at least partially surrounding the magnetic material.

Description

Background Art

[0001] When generally fabricated on a wafer of a semiconductor material such as silicon, an electronic circuit is called an integrated circuit (IC). A wafer having such ICs is usually cut into a number of individual dies. A die can be packaged into an IC package containing one or more dies together with other electronic components such as resistors, capacitors, and inductors. The IC package can be integrated into an electronic system such as a home electronic system or onto a server such as a mainframe.

Brief Description of the Drawings

[0002] In the following detailed description, embodiments will be readily understood by combining with the accompanying drawings. For the ease of this description, like structural elements will be denoted with like reference numerals. Embodiments are shown by way of example and not as a limitation in the figures of the accompanying drawings.

[0003] [Figure 1] FIG. 1 is a schematic cross-sectional view of one exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0004] [Figure 2] FIGS. 2A and 2B are diagrams showing different cross-sectional views of an example of an integrated inductor having a conductive polymer separation layer according to some embodiments of the present disclosure. [Figure 3] FIGS. 3A and 3B are diagrams showing different cross-sectional views of an example of an integrated inductor having a conductive polymer separation layer according to some embodiments of the present disclosure. [Figure 4] FIGS. 4A and 4B are diagrams showing different cross-sectional views of an example of an integrated inductor having a conductive polymer separation layer according to some embodiments of the present disclosure. [Figure 5] FIGS. 5A and 5B are diagrams showing different cross-sectional views of an example of an integrated inductor having a conductive polymer separation layer according to some embodiments of the present disclosure. [Figure 6] Figures 6A and 6B show different cross-sectional views of examples of integrated inductors having a conductive polymer separator layer according to some embodiments of the present disclosure.

[0005] [Figure 7] This is a flowchart illustrating an exemplary method for fabricating a microelectronic assembly including an inductor having a conductive polymer separator layer, according to several embodiments.

[0006] [Figure 8-1] Figures 8A and 8B provide side cross-sectional views of various stages in the fabrication of exemplary microelectronic assemblies according to the method of Figure 7, according to several embodiments. [Figure 8-2] Figures 8C and 8D provide side cross-sectional views of various stages in the fabrication of exemplary microelectronic assemblies according to the method of Figure 7, according to several embodiments. [Figure 8-3] Figures 8E and 8F provide side cross-sectional views of various stages in the fabrication of exemplary microelectronic assemblies by the method of Figure 7, according to several embodiments. [Figure 8-4] Figure 8G provides side cross-sectional views of various stages in the fabrication of exemplary microelectronic assemblies by the method of Figure 7, according to several embodiments.

[0007] [Figure 9] This is a top view of a wafer and die that may include any of the IC structures disclosed herein, according to any of the embodiments disclosed herein.

[0008] [Figure 10] This is a side cross-sectional view of an IC package, which may include any of the assemblies or IC structures disclosed herein, according to various embodiments.

[0009] [Figure 11]This is a side cross-sectional view of an IC device assembly, which may include one of the assemblies or IC structures disclosed herein, according to any embodiment disclosed herein.

[0010] [Figure 12] This is a block diagram of an exemplary electrical device which may include one of the assemblies or IC structures disclosed herein, according to one of the embodiments disclosed herein. [Modes for carrying out the invention]

[0011] This specification discloses integrated circuit (IC) structures and assemblies including an integrated inductor having a conductive polymer isolation layer. Each of the systems, methods, and devices of this disclosure has several innovative aspects, and no single one alone possesses all the desirable attributes disclosed herein. Details of the implementation of one or more of the subjects described herein are described below in the accompanying drawings.

[0012] Inductors play a crucial role in modern microelectronic assemblies, particularly in voltage regulators. In some cases, inductors for such circuits can be integrated into the package substrate (e.g., the core of the package substrate).

[0013] One type of inductor that can be integrated within a package substrate is a coaxial inductor, such as a coaxial magnetic integrated inductor (MIL). A coaxial inductor can be formed within the substrate by creating an opening (e.g., a through-hole or plated through-hole (PTH) in the package core) and coating this opening with a magnetic material. The trend towards using glass substrates allows for the integration of inductors with smaller dimensions and therefore smaller pitches than previously possible with conventional package substrates. The smaller via widths achievable with glass substrates further enable the use of high-permeability materials in a smaller footprint, thereby improving inductance density and design flexibility.

[0014] According to some examples, such integrated coaxial inductors can be fabricated by depositing magnetic material into through-holes in a glass substrate using an electroplating process (also known as electroplating). Typically, a seed layer is first deposited on the sidewalls of the opening to enable the electroplating of the magnetic material. Thus, one or more seed layers are deposited using processes other than electroplating, such as electroless plating or sputtering. Seed layers, such as copper seeds or other copper-like seeds, may have high conductivity and low sheet resistance (e.g., about 1 ohm per square). Electroplating magnetic material onto seed layers with low sheet resistance can be detrimental to the operation of the inductor. For example, the seed layer may adversely affect the impedance of eddy current loops within the magnetic material, significantly reducing the efficiency of the inductor.

[0015] As illustrated in the examples described herein, a conductive polymer layer between a seed layer and a magnetic material in an integrated inductor can function as a separator between the magnetic material and the seed layer to improve inductor performance (for example, by mitigating the decrease in inductor efficiency induced by eddy currents). In one example, a microelectronic assembly includes a glass layer having a first surface and a second surface, and an inductor within the layer, where the inductor includes a continuous portion of conductive material between the first and second surfaces, a magnetic material at least partially surrounding the conductive material, and a conductive polymer at least partially surrounding the magnetic material.

[0016] The IC structures and microelectronic assemblies, including integrated inductors having conductive polymer isolation layers as described herein, may be implemented within or / or between various such components associated with the IC. In various embodiments, components associated with the IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, and antennas. Components associated with the IC may include those mounted on the IC or connected to the IC. The IC may be either analog or digital and, depending on the components associated with the IC, may be used in multiple applications such as microprocessors, optoelectronics, logic blocks, and audio amplifiers. In some embodiments, the IC structures described herein may be included in radio frequency ICs (RFICs), which may be included in any component associated with an IC such as an RF receiver, RF transmitter, or RF transceiver, used, for example, in telecommunications within base stations (BS) or user equipment (UE). Such components may include, but are not limited to, power amplifiers, low-noise amplifiers, RF filters (including arrays or banks of RF filters), switches, upconverters, downconverters, and duplexers. In some embodiments, the IC structures described herein may be included in a memory device or circuit. In some embodiments, the IC structures described herein may be employed as part of a chipset for performing one or more related functions within a computer.

[0017] For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the exemplary implementations. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details, and / or that the present disclosure may be practiced with only some of the aspects described. In other instances, well-known functions are omitted or simplified so as not to obscure the exemplary implementations. The terms "substantially," "close," "approximately," "near," and "about" generally refer to within + / - 10% of a target value, e.g., within + / - 5% of a target value, based on the context of a particular value described herein or known in the art. Similarly, terms indicating the orientation of various elements, such as "in the same plane," "perpendicular," "orthogonal," "parallel," or any other angle between elements generally refer to within + / - 10% of a target value, e.g., within + / - 5% of a target value, based on the context of a particular value described herein or known in the art.

[0018] In the following description, reference is made to the accompanying drawings that form a part hereof, in which exemplary embodiments that can be practiced are shown by way of illustration. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description is not to be taken in a limiting sense.

[0019] In the drawings, some schematic diagrams of exemplary structures of the various devices and assemblies described herein may be shown with precise right angles and straight lines, but this is merely for illustrative purposes, and embodiments of these assemblies may be curved, rounded, or otherwise irregular in shape, as indicated by and sometimes inevitably resulting from the fabrication process used to manufacture the semiconductor device assemblies. Therefore, it should be understood that such schematic diagrams may not reflect the limitations of the actual process, which may cause features to appear less "ideal" when examining any of the structures described herein using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images. Such images of actual structures may also show possible fabrication defects, such as non-linear edges of material, tapered vias or other openings, unintended rounding of corners or variations in the thickness of different material layers, occasionally occurring helical dislocations, edge dislocations, or combination dislocations within crystalline regions, and / or occasionally occurring single-atom or cluster of atomic dislocation defects. Other defects common in the field of device fabrication, not listed herein, may exist. For example, inspection of some of the device's layout and mask data for reconstructing the circuit using optical microscopy, TEM, or SEM, and inspection of the device's cross-section for detecting the shape and position of various device elements described herein using reverse engineering and / or physical failure analysis (PFA), for example, would enable the determination of the presence of an integrated inductor having a conductive polymer separator layer as described herein.

[0020] Various operations may be described sequentially as a plurality of distinct actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of the description should not be construed as suggesting that these operations necessarily depend on order. These operations may not be performed in the order presented. The operations described may be performed in an order different from the described embodiments. Various additional operations may be performed, and / or the operations described may be omitted in additional embodiments.

[0021] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between" when used in reference to a measurement range includes the endpoints of the measurement range.

[0022] The description uses the phrases "in an embodiment" or "in embodiments," each of which may refer to one or more of the same or different embodiments. The terms "comprising," "including," "having," and the like used with respect to embodiments of the present disclosure are synonymous. The present disclosure may use descriptions based on perspectives such as "above," "below," "upper," "bottom," and "side," but such descriptions are used to facilitate the discussion and are not intended to limit the application of the disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" to describe a common object merely indicates that different instances of the same object are being referred to, and is not intended to suggest that the objects so described must be in a given order in any temporal, spatial, sequential, or any other manner. Some materials may be described in the singular, but such materials may include a plurality of materials; for example, a semiconductor material may include two or more different semiconductor materials.

[0023] Multiple elements referenced in the descriptions of Figures 1, 2A-2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, and 8A-8G using reference numbers are shown in different patterns within these drawings, and a legend showing the correspondence between reference numbers and patterns is provided at the bottom of each drawing page, including Figures 1, 2A-2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, and 8A-8G. For example, the legend shows that Figure 1 shows the glass core 110, conductive material 216, and similar elements using different patterns.

[0024] Figure 1 is a schematic side cross-sectional view of one exemplary microelectronic assembly 100, which may contain a glass core with one or more integrated inductors having conductive polymer isolation layers as described herein, according to some embodiments of the present disclosure. The microelectronic assembly 100 may include a substrate 107 with a double-sided bridge die 114-1 in a cavity 119 within the substrate 107, the die 114-1 may be electrically coupled to a conductive path, for example, a conductive trace 108A or a conductive via 108B, in a metal layer of the substrate 107 located below the bottom of the cavity 119. As used herein, the terms “die,” “microelectronic component,” and similar variations may be used without distinction. As used herein, the terms “interconnection component,” “bridge die,” and similar variations may be used without distinction. The bridge die 114-1 may be electrically coupled to dies 114-2, 114-3 by a die-to-die (DTD) interconnect 130 on a second surface 120-2. Specifically, a conductive contact 124 on the upper surface of die 114-1 may be coupled to a conductive contact 122 on the bottom surface of dies 114-2 and 114-3 by conductive vias 108B passing through a second dielectric material layer 112B. The substrate 107 may include a dielectric material 112 (e.g., a first dielectric material layer 112A and a second dielectric material layer 112B, both referred to as “one or more layers of dielectric material 112” as shown), and a conductive material 108 disposed within one or more layers of dielectric material 112 to provide conductive paths (e.g., conductive traces 108A and conductive vias 108B) passing through the substrate 107, and providing conductive pads and contacts. The substrate 107 may include a first surface 120-1 and a second surface 120-2 on the opposite side.

[0025] As used herein, “conductive contact” may refer to a portion of a conductive material (e.g., metal) that functions as an electrical interface between different components (e.g., a portion of a conductive interconnect); the conductive contact may be recessed into the surface of a component, coplanar with it, or extend away from it (e.g., having a columnar shape), and may take any suitable form (e.g., a conductive pad or socket, or a portion of a conductive line or via). In a general sense, “interconnection” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnection provides electrical connectivity between two electrical components to facilitate the communication of electrical signals between them; an optical interconnection provides optical connectivity between two optical components to facilitate the communication of optical signals between them. As used herein, both electrical interconnections and optical interconnections are included in the term “interconnection.” The properties of the interconnection described shall be understood herein in relation to the signaling medium associated therewith. Therefore, when used in relation to electronic devices such as ICs that operate using electrical signals, the term “interconnection” can also describe any element formed of a conductive material that provides electrical connectivity to one or more elements associated with the IC, or / or to various such elements. In such cases, the term “interconnection” can refer to both conductive traces (sometimes also called “metal traces,” “lines,” “metal lines,” “wiring,” “metal wiring,” “trench,” or “metal trench”) and conductive vias (sometimes also called “vias” or “metal vias”). At times, conductive traces and vias are referred to as “metal traces” and “metal vias,” respectively, to emphasize the fact that these elements contain conductive materials such as metal. Similarly, when used in relation to devices that also operate using optical signals, such as photonic ICs (PICs), “interconnection” can also describe any element formed of a photoconductive material that provides optical connectivity to one or more elements associated with the PIC.In such cases, the term "interconnection" may refer to an optical waveguide (e.g., a structure that guides and confines optical waves) including optical fibers, optical splitters, optical couplers, optical couplers, and optical vias.

[0026] The dies 114-1, 114-2, and 114-3 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the die (e.g., of dies 114-1, 114-2, and 114-3) may include dielectric materials such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photosensitive dielectrics, and / or benzocyclobutene-based polymers). In some embodiments, the insulating material of dies 114-1, 114-2, and 114-3 may include semiconductor materials such as silicon, germanium, or Group III-V materials (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths within dies 114-1, 114-2, and 114-3 may include conductive traces and / or conductive vias and can connect any of the conductive contacts within dies 114-1, 114-2, and 114-3 in any suitable manner (e.g., connecting multiple conductive contacts on the same or different surfaces of dies 114-1, 114-2, and 114-3). Exemplary structures that may be included within dies 114-1, 114-2, and 114-3 disclosed herein are discussed below with reference to IC device 1800. The conductive paths within dies 114-1, 114-2, and 114-3 may be bounded by liner materials such as adhesive liners and / or barrier liners, where appropriate. In some embodiments, one or more of dies 114-1, 114-2, and 114-3 are wafers. In some embodiments, one or more of the dies 114-1, 114-2, and 114-3 are monolithic silicon, fan-out or fan-in package dies, or die stacks (e.g., stacked wafers, stacked dies, or stacked multilayer dies).

[0027] In some embodiments, dies 114-1, 114-2, and 114-3 may include conductive paths for routing power, ground, and / or signals to and from other dies 114-1, 114-2, and 114-3 contained within the microelectronic assembly 100. For example, die 114-1 may include a TSV 125 containing conductive vias such as metal vias isolated from the surrounding silicon or other semiconductor material by a barrier oxide, or other conductive paths through which power, ground, and / or signals can be transmitted between the package substrate 102 and one or more dies "on" die 114-1 (e.g., dies 114-2 and / or 114-3 in the embodiment of Figure 1). In some embodiments, die 114-1 does not need to route power and / or ground to dies 114-2 and 114-3; instead, dies 114-2 and 114-3 may be directly coupled to power and / or ground lines in the package substrate 102 via a substrate-to-package substrate (STPS) interconnect 150, conductive paths provided by conductive material 108 in the substrate 107, and a die-to-substrate (DTS) interconnect 140. In some embodiments, die 114-1 may be thicker than dies 114-2 and 114-3. In some embodiments, die 114-1 may be a memory device or a high-frequency serializer and deserializer (SerDes) such as a Peripheral Component Interconnect (PCI) express. In some embodiments, die 114-1 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encoder. In some embodiments, die 114-2 and / or die 114-3 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encoder. In some embodiments, dies 114-1, 114-2, and 114-3 may be as described below with reference to die 1502 in Figure 9.

[0028] The dielectric material 112 of the substrate 107 may be formed in layers (e.g., at least a first dielectric material layer 112A and a second dielectric material layer 112B). In some embodiments, the dielectric material 112 may include an organic material such as an organic build-up film. In some embodiments, the dielectric material 112 may include, for example, ceramics, epoxy films having filler particles inside, glass, inorganic materials, or a combination of organic and inorganic materials. In some embodiments, the conductive material 108 may include a metal (e.g., copper). In some embodiments, the substrate 107 may include layers of dielectric material 112 / conductive material 108, where lines / traces / pads / contacts of conductive material 108 in one layer (e.g., conductive trace 108A) are electrically coupled to lines / traces / pads / contacts of conductive material 108 in an adjacent layer (e.g., conductive trace 108A) by vias of conductive material 108 extending through the dielectric material 112 (e.g., 108B). The conductive traces 108A may be referred to herein as “conductive lines,” “conductive elements,” “conductive pads,” or “conductive contacts.” A substrate 107 containing such layers may be formed, for example, using printed circuit board (PCB) fabrication techniques.

[0029] The substrate 107 may contain N layers of conductive material 108, where N is an integer greater than or equal to 1. In Figure 1, the layers are labeled in descending order from the second surface 120-2 (e.g., top surface) of the substrate 107 (e.g., layer N, layer N-1, layer N-2, etc.). Specifically, as shown in Figure 1, the substrate 107 may contain four metal layers (e.g., N, N-1, N-2, and N-3). The N metal layer may contain conductive contacts 121 on the second surface 120-2 of the substrate 107, which are coupled by the DTS interconnect 140 to conductive contacts 122 on the bottom surfaces of dies 114-2, 114-3. The N-2 metal layer may include a conductive trace 108A having an upper surface (for example, a surface facing the second surface 120-2 of the substrate 107), an opposite bottom surface (for example, a surface facing the first surface 120-1 of the substrate 107), and a lateral surface extending between the upper and bottom surfaces of the conductive trace 108A. The substrate 107 may further include an N-1 metal layer above the N-2 metal layer and below the N metal layer.

[0030] In various attached figures, specific numbers and arrangements of dielectric material 112 / conductive material 108 layers are shown, but these specific numbers and arrangements are merely illustrative, and any desired number and arrangement of dielectric material 112 / conductive material 108 may be used. Furthermore, while a specific number of layers (e.g., four layers) within the substrate 107 are shown, these layers may represent only a portion of the substrate 107, and further layers may exist (e.g., layers N-4, N-5, N-6, etc.).

[0031] As shown in Figure 1, the substrate 107 may further include a glass core 110. The glass core 110 may also be called a glass layer or glass substrate. A further layer 111 may be present beneath the glass core 110 and bonded to the package substrate 102 by an interconnect 150. As used herein, the term “glass core” refers to a layer (e.g., a glass layer) or structure (e.g., a portion of a glass layer) of any glass material such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, aluminoborosilicate), soda-lime glass, soda-lime silica, boroflote glass, lead borate glass, photosensitive glass, non-photosensitive glass, or ceramic glass. Specifically, the glass core 110 may be a solid volume / layer of bulk glass or glass, as opposed to a material that may contain glass particles (e.g., a substrate / plate constructed of glass fibers and an epoxy binder), such as a glass fiber reinforced polymer. Such glass materials are typically amorphous and often transparent amorphous solids. In some embodiments, the glass core 110 may be an amorphous solid glass layer. In some embodiments, the glass core 110 may comprise a material comprising silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass core 110 may comprise a material having a weight percentage of silicon of at least about 0.5%, for example, between about 0.5% and 50%, between about 1% and 48%, or at least about 23%, which is, for example, one of the materials described above. For example, if the glass core 110 is fused silica, the weight percentage of silicon may be about 47%. In some embodiments, the glass core 110 may comprise a material having at least 23% silicon and / or at least 26% oxygen by weight, and in some further embodiments, the glass core 110 may further comprise at least 5% aluminum by weight.In some embodiments, the glass core 110 may contain any of the materials described above, and may further contain one or more additives such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the glass core 110 may be a glass layer that does not contain organic adhesives or organic materials. The glass core 110 may be distinguished from the “prepreg” or “FR4” core of a PCB substrate, for example, which contains glass fibers embedded in a resin organic material such as epoxy. In such conventional cores / substrates containing glass fibers and epoxy, the diameter of the glass fibers is generally in the range of 5 to 200 microns. In contrast, the glass core 110 may be a glass layer with sides ranging from about 10 millimeters to about 250 millimeters (e.g., 10 mm × 10 mm to 250 mm × 250 mm).

[0032] In some embodiments, the cross-section of the glass core 110 in the xz, yz, and / or xy planes of the exemplary coordinate system shown in Figure 1 may be substantially rectangular (the axes shown in subsequent figures refer to the axes of the coordinate system shown in Figure 1), but in some further embodiments, the glass core 110 may have rounded or beveled edges / sides / sidewalls. In some embodiments, in a top view of the glass core 110 (e.g., in the xy plane of the coordinate system shown in Figure 1), the glass core 110 may have a first length ranging from 10 to 250 millimeters and a second length ranging from 10 to 250 millimeters, with the first length being perpendicular to the second length. The thickness of the glass core 110 (e.g., a dimension measured along the z axis of the coordinate system in Figure 1) may range from about 50 microns to 1.4 millimeters. In some embodiments, the glass core 110 may be a glass core substrate, where the glass core substrate has a thickness ranging from about 50 microns to 1.4 millimeters. In some embodiments, the glass core 110 may be a glass layer having a rectangular volume, optionally having rounded or beveled edges / sides / sidewalls. In some such embodiments, the rectangular volume may have a first side and a second side perpendicular to the first side, the first side having a length ranging from 10 to 250 mm, and the second side having a length ranging from 10 to 250 mm. In some embodiments, the glass core 110 may be a rectangular volume having some (e.g., vias) removed and filled with another material (e.g., metal), e.g., TGV115. In some embodiments, the glass core 110 may be a glass layer having a thickness ranging from 50 microns to 1.4 mm, a first length ranging from 10 to 250 mm, and a second length ranging from 10 to 250 mm, the first length being perpendicular to the second length.

[0033] In some implementations, the substrate 107 containing the glass core 110, and the dies 114-1, 114-2, and 114-3 may together be referred to as the "multilayer die subassembly 104". The glass core 110 can provide mechanical stability to the multilayer die subassembly 104, the substrate 107, and / or the microelectronic assembly 100. The glass core 110 can reduce warping and provide a more robust surface for mounting the multilayer die subassembly 104 to the package substrate 102 or other substrates (e.g., interposer or circuit board).

[0034] In some implementations, the dielectric material 112 of the substrate 107 and the glass core 110 may together be referred to as a “multilayer glass substrate.” In some such embodiments, the glass core 110 may be a glass layer having a thickness ranging from about 25 to 50 microns. In some embodiments, a further layer 111 may also be part of the multilayer glass substrate. In some such embodiments, the substrate may be a coreless substrate.

[0035] In the example of Figure 1, the glass core 110 includes glass through-vias (TGVs) 115 and 117. In the example shown, some of the TGVs are or may include conductive vias containing a conductive material to form conductive interconnects, and some of the TGVs may include inductor structures. For example, TGV 115 is a conductive via that may contain any suitable conductive material, such as a metal, e.g., copper, silver, nickel, gold, aluminum, or other metals or alloys. TGV 117 is or includes an integrated inductor having a conductive polymer isolation layer, as illustrated in the examples described herein. TGVs 115 and 117 may be vias extending between the first and second sides of the glass core 110 (e.g., between the bottom and top surfaces of the glass core 110). Thus, in some examples, the assembly may include both conductive vias and vias containing inductor structures within the same plane or layer, both of which may extend through the glass core 110 between the first and second surfaces of the glass core 110. The openings for TGV115 and 117 can be formed using any suitable process, including, for example, direct laser drilling or a laser-induced etching process (which may also be called laser patterning or selective laser activation). In some embodiments, the TGV115 and 117 disclosed herein may have a pitch between 50 microns and 500 microns, measured, for example, from the center of one TGV115, 117 to the center of an adjacent TGV115, 117. The TGV115 and 117 may have any suitable size and shape. In some embodiments, the TGV115 and 117 may have a rounded (e.g., circular or elliptical), rectangular, or other shaped cross-section. In some embodiments, at least some of the TGV115 and 117 may have an hourglass shape (for example, the TGV115 and 117 may be tapered from both sides such that the TGV has a narrower width between two larger widths). In some embodiments, at least some of the TGV115 and 117 may taper downward from one surface of the glass core 110 to another, for example from the top surface of the glass core 110 to the bottom surface of the glass core 110.

[0036] A substrate 107 (e.g., an additional layer 111) may be coupled to a package substrate 102 by an STPS interconnect 150. Specifically, the top surface of the package substrate 102 may include a pair of conductive contacts 146. Conductive contacts 144 on the bottom surface of the substrate 107 may be electrically and mechanically coupled to conductive contacts 146 on the top surface of the package substrate 102 by the STPS interconnect 150. The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and one or more conductive paths to route power, ground, and signals through the dielectric material (e.g., conductive traces and / or conductive vias as shown). In some embodiments, the insulating material of the package substrate 102 may be an organic dielectric material, a flame-retardant grade 4 material (FR-4), a bismaleimide triazine (BT) resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric including an inorganic filler, or a dielectric material such as a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). Specifically, if the package substrate 102 is formed using a standard PCB process, the package substrate 102 may contain FR-4, and the conductive paths within the package substrate 102 may be formed by patterned copper sheets separated by a build-up layer of FR-4. The conductive paths within the package substrate 102 may be bounded, where appropriate, by liner materials such as adhesive liners and / or barrier liners. In some embodiments, the package substrate 102 may be formed using a via packaging process defined by lithography. In some embodiments, the package substrate 102 may be manufactured using a standard organic package manufacturing process, and thus the package substrate 102 may take the form of an organic package. In some embodiments, the package substrate 102 may be a set of redistribution layers formed on a panel carrier by laminating or spin-on dielectric materials and creating conductive vias and lines by laser drilling and plating.In some embodiments, the package substrate 102 may be formed on a removable carrier using any suitable technique, such as a redistribution layer technique. Any method known in the art for fabricating the package substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.

[0037] In some embodiments, the package substrate 102 may be a lower-density medium, and the dies 114-1, 114-2, and 114-3 may be a higher-density medium or have areas containing a higher-density medium. As used herein, the terms “lower-density” and “higher-density” are relative terms indicating that conductive paths (including, e.g., conductive interconnects, conductive lines, and conductive vias) in a lower-density medium have a larger and / or larger pitch than conductive paths in a higher-density medium. In some embodiments, a higher-density medium may be manufactured using an advanced lithography modified semi-additive process or semi-additive build-up process (using small longitudinal interconnect features formed by an advanced laser or lithography process), while a lower-density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using a standard laser process to remove areas of unwanted copper using an etching chemical reaction). In other embodiments, higher density media may be manufactured using semiconductor fabrication processes such as single damascene processes or dual damascene processes. In some embodiments, additional dies may be disposed on the top surfaces of dies 114-2, 114-3. In some embodiments, additional components may be disposed on the top surfaces of dies 114-2, 114-3. Additional passive components such as surface-mount resistors, capacitors, and / or inductors may be disposed on the top or bottom surface of the package substrate 102 or embedded within the package substrate 102.

[0038] The microelectronic assembly 100 in Figure 1 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the substrate 107 and the package substrate 102 around the associated STPS interconnect 150. In some embodiments, the underfill material 127 may extend between the upper level dies 114-2, 114-3 and the upper surface of the substrate 107 around the associated DTS interconnect 140, and between the bridge die 114-1 and the upper level dies 114-2, 114-3 around the DTD interconnect 130. The underfill material 127 may be an insulating material such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that assists in soldering the multilayer die subassembly 104 to the package substrate 102 when forming the STPS interconnect 150, and then polymerizes and encapsulates the STPS interconnect 150. The underfill material 127 may be selected to have a CTE that can mitigate or minimize stress between the substrate 107 and the package substrate 102 resulting from non-uniform thermal expansion within the microelectronic assembly 100. In some embodiments, the CTE of the underfill material 127 may have a value intermediate to the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the dielectric material 112 of the dies 114-1, 114-2, 114-3 and / or the substrate 107.

[0039] The STPS interconnect 150 disclosed herein can take any suitable form. In some embodiments, a pair of STPS interconnects 150 may include solder (e.g., solder bumps or balls that are subjected to thermal reflow to form the STPS interconnect 150) as shown in Figure 1, and the STPS interconnect 150 may include solder between conductive contacts 144 on the bottom surface of the substrate 107 and conductive contacts 146 on the top surface of the package substrate 102. In some embodiments, a pair of STPS interconnects 150 may include an anisotropic conductive material, such as an anisotropic conductive film or anisotropic conductive paste. The anisotropic conductive material may include a conductive material dispersed in a non-conductive material.

[0040] The DTD interconnect 130 disclosed herein may take any suitable form. The DTD interconnect 130 may have a finer pitch than the STPS interconnect 150 in the microelectronic assembly. In some embodiments, the dies 114-1, 114-2, 114-3 on both sides of a pair of DTD interconnects 130 may be unpackaged dies, and / or the DTD interconnect 130 may include small conductive bumps (e.g., copper bumps). The DTD interconnect 130 may have a pitch that is too fine to bond directly to the package substrate 102 (e.g., too fine to function as a DTS interconnect 140 or STPS interconnect 150). In some embodiments, a pair of DTD interconnects 130 may include solder. In some embodiments, a pair of DTD interconnects 130 may include an anisotropic conductive material such as one of the materials discussed above. In some embodiments, the DTD interconnect 130 may be used as a data transfer lane, while the STPS interconnect 150 may be used, in particular, for power and ground lines. In some embodiments, some or all of the DTD interconnects 130 in the microelectronic assembly 100 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, the DTD interconnects 130 may be bonded to each other (e.g., under high pressure and / or high temperature) without the use of intervening solder or anisotropic conductive material. Any of the conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146) may include bonding pads, solder bumps, conductive posts, or any other suitable conductive contacts. In some embodiments, some or all of the DTD interconnects 130 and / or DTS interconnects 140 within the microelectronic assembly 100 may be solder interconnects containing solder having a higher melting point than the solder contained in some or all of the STPS interconnects 150.For example, if the DTD interconnect 130 and DTS interconnect 140 in the microelectronic assembly 100 are formed before the STPS interconnect 150 is formed, the solder-based DTD interconnect 130 and DTS interconnect 140 may use a higher temperature solder (e.g., having a melting point above 200 degrees Celsius), while the STPS interconnect 150 may use a lower temperature solder (e.g., having a melting point below 200 degrees Celsius). In some embodiments, the higher temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (e.g., eutectic tin-bismuth), or tin, silver, and bismuth. In some embodiments, the lower temperature solder may include indium, indium, and tin, or gallium.

[0041] In the microelectronic assembly 100 disclosed herein, some or all of the DTS interconnects 140 and STPS interconnects 150 may have a larger pitch than some or all of the DTD interconnects 130. The DTD interconnects 130 may have a smaller pitch than the STPS interconnects 150 due to the greater material similarity between the substrates 107 and upper-level dies 114-2, 114-3 on both sides of a pair of DTS interconnects 140, and between the substrates 107 and package substrates 102 on both sides of a pair of STPS interconnects 150. Specifically, differences in the material composition of the substrate 107 and the die (e.g., one or more of dies 114-1, 114-2, 114-3) or the package substrate 102 may result in differences in expansion and contraction due to the heat generated during operation (and the heat applied during various manufacturing operations). To mitigate damage (e.g., cracking, solder bridging) caused by these differences in expansion and contraction, the DTS interconnect 140 and STPS interconnect 150 may be formed larger and further apart than the DTD interconnect 130, which may experience less thermal stress due to the greater material similarity of the pair of dies on either side of the DTD interconnect. In some embodiments, the DTS interconnect 140 disclosed herein may have a pitch between 25 and 250 microns. In some embodiments, the STPS interconnect 150 disclosed herein may have a pitch between 55 and 1000 microns, while the DTD interconnect 130 disclosed herein may have a pitch between 25 and 100 microns.

[0042] The microelectronic assembly 100 in Figure 1 may also include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board by a second-level interconnect on the bottom surface of the package substrate 102. The second-level interconnect may be any suitable second-level interconnect, including solder balls for a ball grid array configuration, pins in a pin grid array configuration, or lands in a land grid array configuration. The circuit board may be, for example, a motherboard and may have other components mounted thereon. The circuit board may include conductive paths and other conductive contacts for routing power, ground, and signals through the circuit board, as is known in the art. In some embodiments, the second-level interconnect may not couple the package substrate 102 to the circuit board, instead coupling the package substrate 102 to another IC package, interposer, or any other suitable component. In some embodiments, the substrate 107 may not be coupled to the package substrate 102, instead being coupled to a circuit board such as a PCB.

[0043] Figure 1 shows a microelectronic assembly 100 having a substrate containing conductive paths provided by a specific number of dies and conductive material 108 coupled to other dies, but this number and configuration is merely illustrative, and the microelectronic assembly 100 may contain any desired number and configuration of dies. Figure 1 shows die 114-1 as a double-sided die and dies 114-2, 114-3 as single-sided dies, but dies 114-2, 114-3 may be double-sided dies, and die 114-1 may be a single-pitch die or a mixed-pitch die. In some embodiments, additional components may be disposed on the upper surfaces of dies 114-2 and / or 114-3. In this context, a double-sided die refers to a die having connections on both surfaces. In some embodiments, a double-sided die may include through-TSVs for forming connections on both surfaces. The active surface of a double-sided die, which is the surface containing one or more active devices and most of the interconnects, may face either direction depending on the design and electrical requirements.

[0044] Furthermore, although various elements are shown in Figure 1 as being included within the microelectronic assembly 100, some of these elements may be omitted in various embodiments. For example, in various embodiments, the additional layer 111, underfill material 127, and package substrate 102 may not be present within the microelectronic assembly 100. In some embodiments, each of the microelectronic assemblies 100 disclosed herein may function as a system-in-package (SiP) containing multiple dies 114-1, 114-2, 114-3 having different functions. In such embodiments, the microelectronic assembly 100 may be referred to as a SiP.

[0045] Figures 2A–2B, 3A–3B, 4A–4B, 5A–5B, and 6A–6B show different cross-sectional views of examples of integrated inductors having a conductive polymer separator layer. The inductors shown in Figures 2A–2B, 3A–3B, 4A–4B, 5A–5B, and 6A–6B are examples of coaxial inductors integrated within glass or other substrates. Thus, the inductors described herein may be called inductor structures, integrated inductors, coaxial inductors, or coaxial magnetic integrated inductors. The figures labeled with the letter A in Figures 2A–2B, 3A–3B, 4A–4B, 5A–5B, and 6A–6B (e.g., Figure 2A) show a cross-section in the yz plane of the exemplary coordinate system shown in Figure 1, along plane AA shown in the corresponding figure labeled with the letter B (e.g., along plane AA shown in Figure 2B). Figures 2A-2B, 3A-3B, 4A-4B, 5A-5B, and 6A-6B labeled with the letter B (e.g., Figure 2B) show a cross-section in the xy-plane of the exemplary coordinate system shown in Figure 1, along plane BB shown in the corresponding figure labeled with the letter A (e.g., along plane BB shown in Figure 2A). The dashed boxes in the corresponding figures labeled with the letter A indicate regions of the IC structure shown in the figures labeled with the letter B. For example, the dashed box in Figure 2A indicates region 211 shown in the cross-section of Figure 2B. The dashed box in Figure 3A indicates region 311 shown in the cross-section of Figure 3B. The dashed box in Figure 4A indicates region 411 shown in the cross-section of Figure 4B. The dashed box in Figure 5A indicates region 511 shown in the cross-section of Figure 5B. Similarly, the dashed box in Figure 6A indicates region 611 shown in the cross-section of Figure 6B.

[0046] First, looking at Figures 2A and 2B, the IC structure 200 includes a glass layer 210 with a first side or surface 213-1 and a second side or surface 213-2. The glass layer 210 may be, for example, a glass core. In other examples, different core materials may be present in the assembly (e.g., ceramic, epoxy, or another core material). The IC structure 200 includes two inductors 202-1 and 202-2 within the glass layer 210. As can be seen in Figures 2A and 2B, the inductors 202-1 and 202-2 extend through the glass layer 210 such that portions of the inductors 202-1 and 202-2 are coplanar with the first surface 213-1 and the second surface 213-2 opposite the first surface 213-1. In the example shown in Figures 2A and 2B, the insulating material 212 is present between the glass 210 and the inductors 202-1 and 202-2 (e.g., between the glass 210 and the sidewalls of the inductors 202-1 and 202-2), and also on the first surface 213-1 and the second surface 213-2. In such an example, the insulating material 212 may include a nonconductive polymer or other suitable insulating material. In the example shown in Figures 2A and 2B, the insulating material 232 is present in layers above and below the glass layer 210, where the insulating material 232 has a different material composition from the core material (e.g., different from the glass layer 210). The insulating material 232 may be or include a build-up material (also known as a build-up layer), an interlayer dielectric (ILD) material, or any other suitable insulating material. In some examples, the insulating material 232 may include an organic dielectric material (e.g., polyimide or other suitable dielectric material) and / or a build-up film.

[0047] Inductors 202-1 and 202-2 include a conductive material 216 that can fill the internal regions of inductors 202-1 and 202-2 (e.g., regions 236-1 and 236-2, respectively), as shown in Figures 2A and 2B. Therefore, the portion of the conductive material 216 filling the inductors 202-1 and 202-2 may be called a conductive plug. In other examples, as will be discussed below, the interior of the inductor may contain a void or another material such as a dielectric material. As can be seen in Figures 2A and 2B, a continuous portion of the conductive material 216 exists between the first surface 213-1 and the second surface 213-2. In one example, the conductive material 216 may be any suitable electrically conductive material, such as a material containing metal. In one example, the conductive material 216 may be copper or contain copper.

[0048] In the examples shown in Figures 2A and 2B, portions of the conductive material 216 may form conductive contact structures coupled to each of the inductors 202-1 and 202-2. For example, conductive contact structure 234-1 may include a portion of the conductive material 216 that covers and is coupled to (e.g., in contact with, e.g., directly in contact with) the conductive material 216 within the internal region 236-1 of inductor 202-1. Similarly, conductive contact structure 234-2 may include a portion of the conductive material 216 that covers and is coupled to the conductive material 216 within the internal region 236-2 of inductor 202-2. In some examples, the conductive material 216 of conductive contact structures 234-1 and 234-2 may be the same as or different from the conductive material 216 within the internal regions 236-1 and 236-2 of inductors 202-1 and 202-2. In some examples, the conductive material 216 in the internal regions 236-1, 236-2 of inductors 202-1, 202-2, and the conductive material 216 of the contact structures 234-1, 234-1, can be deposited in the same process or using different processes. The conductive interconnects 238-1, 238-2 extend through the insulating material 232 above the inductors 202-1, 202-2 and couple with the respective conductive contact structures 234-1, 234-2.

[0049] The inductor further includes a magnetic material 214 that at least partially surrounds the conductive material 216. As can be seen in Figure 2B, the magnetic material 214 of the inductor 202-1 completely surrounds the continuous portion of the conductive material 216 present in the intermediate or central region of the inductor 202-1 between the first surface 213-1 and the second surface 213-2. The magnetic material 214 may include ferromagnetic elements. The magnetic material 214 may include, for example, cobalt nickel iron, cobalt iron, or another ferromagnetic material (e.g., a ferromagnetic rare earth metal). In some examples, the magnetic material 214 may be substantially pure, and the magnetic region may contain at least 80%, at least 90%, at least 95%, or at least 99% of ferroelectric elements by weight or cross-sectional area. In some embodiments, the magnetic material 214 includes a mixture of several ferroelectric elements, where the combined ferroelectric elements constitute at least 80%, at least 90%, etc., of the magnetic region by weight or cross-sectional area. In some examples, the magnetic material 214 may contain dopants such as one or more of boron, sulfur, phosphorus, and oxygen. In some examples, the magnetic material 214 is deposited using an electroplating process.

[0050] Inductors 202-1 and 202-2 also include an insulating material 212 between the magnetic material 214 and the conductive material 216. In Figures 2A and 2B, the insulating material 212 between the magnetic material 214 and the conductive material 216 is shown as being the same material as the insulating material 212 between the glass 210 and inductors 202-1 and 202-2, but the insulating material 212 between the magnetic material 214 and the conductive material 216 may be substantially the same as or different from the insulating material between the glass 210 and inductors 202-1 and 202-2. In the example shown in Figures 2A and 2B, inductors 202-1 and 202-2 also include a seed layer 226-2 of a seed material 226 (to enable the deposition of the conductive material 216 using, for example, an electroplating process) between the insulating material 212 on the conductive material 216 and the magnetic material 214. In one example, the seed layer 226-2 includes a metal such as copper or another suitable seed material (e.g., a copper-like seed material) that allows the conductive material 216 to be deposited on the seed layer 226-2 (e.g., using an electroplating process).

[0051] Inductors 202-1 and 202-2 also include a conductive polymer 222 (e.g., a conductive polymer separation layer) that at least partially surrounds the magnetic material 214. Thus, rather than directly electroplating the magnetic material 214 onto the seed layer 226-1 on the sidewall of the opening, a layer of conductive polymer 222 may be deposited (e.g., directly) onto the seed layer 226-1, and then the magnetic material 214 may be electroplated onto the conductive polymer 222 on the sidewall of the opening. In some examples, the seed layer 226-1 on the sidewall of the opening (e.g., on the glass 210, or on the insulating material 212 on the glass 210) may have the same or different material composition as the seed layer 226-2 between the magnetic material 214 and the conductive material 216. In some examples, the conductive polymer includes one or more of polythiophene and polypyrrole, or other suitable conductive polymers. Conductive or conductive polymers, also known as “conjugated polymers,” are multimolecular compounds having a conjugated bonding system in their main chain. In some examples, electron conduction occurs along the polymer backbone and is made possible by the presence of conjugated bonds. In such examples, the mechanism of conductivity is related to the presence of a high-energy conduction band resulting from the delocalization of electrons at double bonds. Electrons can be released from one of the conjugated double bonds present in the chain. Polythiophenes and polypyrroles belong to the group of electrically conductive polymers. The conductivity of these polymers can be improved using dopants such as molecular organic dopants and inorganic dopants. In some examples, the conductive polymer 222 may contain alkali metals or DMBI-H (e.g., doped with them). In some examples, the conductive polymer has a thickness on the sidewalls of the opening in the range of about 1 to 10 microns, where the thickness is the dimension of the conductive polymer 222 in a plane substantially parallel to the glass layer 210 (e.g., the glass substrate).

[0052] For example, the conductive polymer 222 may be electroplated onto a seed layer 226-1 (e.g., on the glass 210, or on the sidewall of an insulating material 212 on the glass 210) and can function as an intralayer isolation material. In such an example, the conductive polymer 222 is sufficiently conductive, and therefore the magnetic material 214 can be plated onto the conductive polymer 222 on the sidewall. In one example, the conductive polymer 222 may have conductivity in the range of about 100 S / m to 1000 S / m, or in the range of about 500 S / m to 1000 S / m. The conductive polymer 222 may also have relatively high thermal stability (e.g., higher than about 250°C), thereby making it a suitable material for use in inductors 202-1 and 202-2 that can be formed in a treated panel that can withstand thermal stress from subsequent processing. Therefore, the IC structure 200 in Figures 2A and 2B includes inductors 202-1 and 202-2 having a layer of conductive polymer between the glass 210 and the magnetic material 214.

[0053] Figures 3A and 3B show different cross-sectional views of another example of an IC structure 300 comprising integrated inductors 302-1 and 302-2 having a conductive polymer isolation layer. As can be seen in Figures 3A and 3B, inductors 302-1 and 302-2 are substantially identical to inductors 202-1 and 202-2. However, in the IC structure 300 of Figures 3A and 3B, there is no insulating / buffer material between the seed layer 226 on the surfaces 213-1 and 213-2 of the glass 210 and on the sidewalls of the opening through the glass 210. Thus, in the example shown in Figures 3A and 3B, the seed layer 226 is on the glass 210 and in direct contact with it, whereas in the example shown in Figures 2A and 2B, an insulating material 212 is present on the sidewalls of the opening within the glass 210, and the seed layer is on the insulating material 212. Additionally, in Figure 3A, the insulating material 212 layer is located between the magnetic material and the seed layer 226-2, as well as on surfaces 213-1 and 213-2 of the glass 210.

[0054] Figures 4A to 4B show different cross-sectional views of another example of an IC structure 400 comprising integrated inductors 402-1 and 402-2 having a conductive polymer separator layer. Inductors 402-1 and 402-2 are similar to inductors 302-1 and 302-2 of Figures 3A to 3B discussed above, in that inductors 402-1 and 402-2 include a conductive material 216 in a via opening, a seed layer 226-1 on the sidewall of the via between the glass 210 and the conductive material 216, a conductive polymer 222 on the sidewall between the seed layer 226-1 and the conductive material 216, a magnetic material 214 on the sidewall between the conductive polymer 222 and the conductive material 216, and an insulating material 212 between the magnetic material 214 and the conductive material 216. However, inductors 402-1 and 402-2 differ from inductors 202-1 and 202-2 in that inductors 402-1 and 402-2 include dielectric material 513 (e.g., dielectric plug) within the central regions 436-1 and 436-2 of inductors 402-1 and 402-2. Thus, as can be seen in Figures 4A and 4B, inductors 402-1 and 402-2 each include a continuous portion of insulating material 513 between the surfaces 213-1 and 213-2 of the glass layer 210, and the conductive material 216 surrounds the insulating material 513. In the example shown in Figure 4A, the dielectric plug is taller than the thickness of the glass 210, and therefore the continuous portion of the insulating material 513 extends beyond planes 213-1 and 213-2 (where the height of the dielectric plug and the thickness of the glass are dimensions of such a structure in a plane substantially perpendicular to the glass layer 210, along the z-axis, as shown, for example, in Figure 4A). Thus, in the example shown in Figure 4A, portion 513-2 of the insulating material 513 lies coplanar with portion 216 of the conductive material 216 on the glass 210 (e.g., portion 213-1 of the conductive material 216 extending beyond plane 213-1), and portion 513-1 of the insulating material 513 lies coplanar with portion 216 of the conductive material 216 below the glass 210 (e.g., portion 213-2 of the conductive material 216 extending beyond plane 213-2). In such an example, the insulating material 513 may include a polymer material (e.g., a polymer plug containing a non-conductive polymer material), or any other suitable insulating material.The exemplary IC structure 400 shown in Figure 4A includes another seed layer 226-3 on top of the insulating material 513 (for example, to allow the deposition of a conductive material 216 on top of the insulating material 513 to form a conductive contact 427). In such an example, the seed layer 226-3 is provided on top of a dielectric plug, and a portion of the dielectric plug (for example, the upper portion 513-2 of the insulating material 513 shown in Figure 4A) is in contact with the seed layer 226-3. Similar structures including seed layers and pads may be present on both sides of the IC structure 400. For example, a seed layer similar to the seed layer 226-3 may be deposited on the bottom portion 513-1 of the insulating material 513, and a conductive contact similar to the conductive contact 427 may be provided on the seed layer.

[0055] Figures 5A and 5B show different cross-sectional views of another example of an IC structure 500 comprising integrated inductors 502-1 and 502-2 having conductive polymer isolation layers. Inductors 502-1 and 502-2 are similar to inductors 302-1 and 302-2 in Figures 3A and 3B discussed above, in that they include a layer of conductive polymer 222 and a layer of magnetic material 214 on the conductive polymer 222. However, inductors 502-1 and 502-2 in Figures 5A and 5B include multiple alternating layers of conductive polymer 222 and magnetic material 214. As can be seen in Figures 5A and 5B, the inductor 502-1 includes a first magnetic layer 214-1, a first conductive polymer layer 222-1 that at least partially surrounds the first magnetic layer 214-1, a second magnetic layer 214-2 that at least partially surrounds the first conductive polymer layer 222-1, and a second conductive polymer layer 222-2 that at least partially surrounds the second magnetic layer 214-2. The thickness (e.g., width) of the sidewalls of the conductive polymer 222 and magnetic material 214 layers may be approximately the same or different in consecutive layers. For example, the width of the first conductive polymer layer 222-1 may be approximately the same as or different from the width of the second conductive polymer layer 222-2. Similarly, the width of the first magnetic layer 214-1 may be approximately the same as or different from the width of the second magnetic layer 214-2. Therefore, in the example shown in Figures 5A and 5B, the inductor 502-1 includes multiple layers of magnetic material 214 and conductive polymer 222 on the sidewall of the opening through the glass 210. In such an example, this series of depositions of conductive polymer and magnetic material can be used to achieve better isolation and better inductor efficiency.

[0056] Figures 6A and 6B show different cross-sectional views of another example of an IC structure 600 comprising integrated inductors 602-1 and 602-2 having a conductive polymer isolation layer. Inductors 602-1 and 602-2 are similar to inductors 202-1 and 202-2 in Figures 2A and 2B discussed above, in that they include a layer of conductive polymer 222 and a layer of magnetic material 214 on the conductive polymer 222. However, IC structure 600 differs from IC structure 200 in that a buffer layer (e.g., a thicker layer 615 of insulating material 212, as shown on the sidewall of the inductor opening in Figure 6A) is not present on the glass surfaces 613-1 and 613-2. In such an example, the buffer material may be polished from the top and bottom surfaces of the glass 210 before depositing a thin layer of insulating material 212 which is deposited on top of the magnetic material 214. As mentioned above, the insulating material deposited on the magnetic material 214 may have the same or a different material composition as the buffer material (e.g., the insulating material layer 615).

[0057] Accordingly, Figures 2A-2B, 3A-3B, 4A-4B, 5A-5B, and 6A-6B show different cross-sectional views of examples of integrated inductors having conductive polymer separators. Integrated inductors having one or more conductive polymer separators may include additional or different features from those specifically shown in the examples shown in Figures 2A-2B, 3A-3B, 4A-4B, 5A-5B, and 6A-6B. For example, although the inductors in Figures 2A-2B, 3A-3B, 4A-4B, 5A-5B, and 6A-6B are shown to have substantially circular cross-sectional shapes, inductors may have other cross-sectional shapes (e.g., elliptical, rectangular, or other rounded or non-rounded cross-sectional shapes). Furthermore, the material layers shown in Figures 2A-2B, 3A-3B, 4A-4B, 5A-5B, and 6A-6B may have different relative thicknesses than those shown in Figures 2A-2B, 3A-3B, 4A-4B, 5A-5B, and 6A-6B. For example, the magnetic material 214 is shown to be thicker than the conductive polymer 222 in Figures 2A-2B; in other examples, the magnetic material 214 and the conductive polymer 222 may have substantially the same thickness, or the conductive polymer 222 may be thicker than the magnetic material 214. Other examples may have additional or different intervening layers than those shown in Figures 2A-2B, 3A-3B, 4A-4B, 5A-5B, and 6A-6B. Additionally, while the integrated inductors in Figures 2A-2B, 3A-3B, 4A-4B, 5A-5B, and 6A-6B are shown as being disposed within an opening in the glass layer, in other examples, integrated inductors having a conductive polymer isolation layer may be formed in a layer, substrate, or core containing a material other than glass.

[0058] Figure 7 is a flowchart of an exemplary method 700 for fabricating an IC structure or microelectronic assembly including an integrated inductor having a conductive polymer separator layer. Figures 8A–8G provide cross-sectional views along the yz axis (e.g., the yz axis shown in Figures 1, 2A–2B, 3A–3B, 4A–4B, 5A–5B, and 6A–6B) at various stages of fabricating an exemplary microelectronic assembly by the method of Figure 7, according to several embodiments. The operations of the method of Figure 7 are shown once each and in a specific order, but the operations may be performed in any suitable order and may be repeated if desired. For example, one or more operations may be performed substantially simultaneously with the fabrication of the integrated inductor having the conductive polymer separator layer. In another example, the operations may be performed in a different order that reflects the structure in which the integrated inductor having the conductive polymer separator layer is mounted.

[0059] Furthermore, the exemplary fabrication method in Figure 7 may include other operations not specifically shown in Figure 7, such as various cleaning or planarization operations known in the art. For example, in some embodiments, the support and various other layers of material subsequently deposited thereon may be cleaned before, after, or between any of the processes of the methods described herein to remove, for example, oxides, organic and metallic contaminants bonded to the surface, and subsurface contamination. In some embodiments, cleaning may be performed, for example, by using a chemical solution (such as a peroxide) and / or by using ultraviolet (UV) radiation combined with ozone and / or by oxidizing the surface (for example, by using thermal oxidation) and then removing the oxide (for example, by using hydrofluoric acid (HF)). In another example, the intermediate IC structure described herein may be planarized before, after, or between any of the processes of the methods in Figure 7 described herein to remove, for example, a coating or excess material. In some embodiments, planarization may be performed using either a wet or dry planarization process, for example, chemical mechanical planarization (CMP), which can be understood as a process that uses an abrasive surface, an abrasive, and a slurry to remove a coating and planarize the surface.

[0060] Turning to Figure 7, Method 700 begins with a process 702 in which an opening is formed within a glass layer (e.g., a glass substrate or a glass core). The IC structure 800A in Figure 8A is an exemplary resulting structure of process 702. The IC structure 800A shows an opening 802 within a glass layer 210. The opening 802 may be called a TGV opening, a through-hole, or PTH (e.g., referring to electroplating in a subsequent process). The opening 802 extends between a first surface 813-1 and a second surface 813-2 of the glass layer 210. Although a single opening 802 is shown in Figure 8A, the microelectronic assemblies described herein may include any number of such openings. Multiple openings, such as opening 802, may be formed within the glass, some of which can be filled with a conductive material to form conductive vias, and some of which can be filled with the materials described herein to form an embedded inductor having a conductive polymer separator layer. The aperture 802 may be formed within the glass layer 210 using any suitable subtractive technique, such as direct laser drilling or a laser-induced etching process, which may be combined with any suitable patterning technique, such as photolithography or electron beam (e-beam) patterning, depending on the case. In other embodiments, for example, when molten glass is filled into a mold having space for a future aperture, the aperture 802 may be formed during the fabrication of the glass layer 210 itself. Although Figure 8A and subsequent figures show the aperture 802 as having a substantially linear profile, the aperture 802 may have a cross-sectional shape that tapers from one or both sides. In the example where the aperture 802 tapers from both sides, the aperture 802 may have widths at both ends (e.g., a first width coplanar with face 813-1 and a second width coplanar with face 813-2) that are greater than the width between the two ends (e.g., a third width between the first and second widths may be smaller than the first and second widths). In the example shown in Figure 8A, the insulating material 212 is provided covering the side wall 803 of the opening 802, as well as surfaces 813-1 and 813-2.In one such example, the insulating material 212 may function as a buffer layer between the glass 210 and the material to be deposited later; however, in other examples, the buffer layer may not be deposited on the side wall 803 of the opening 802.

[0061] Referring again to method 700 in Figure 7, method 700 follows process 704, which provides a conductive material as a seed layer on the sidewall of the opening. IC structure 800B in Figure 8B is an exemplary, resulting IC structure of process 704. IC structure 800B includes a layer of conductive material 826 on the sidewall 803 of the opening. In the example shown in Figure 8B, the conductive material 826 is deposited on the insulating material 212 on the sidewall 803 of the opening 802. The conductive material 826 may be deposited using any suitable technique such as a physical vapor deposition process (e.g., sputtering), and may be any suitable seed material such as copper or another suitable conductive seed material.

[0062] Referring again to method 700 in Figure 7, method 700 is followed by process 706, which provides a conductive polymer by covering the conductive material on the sidewall. IC structure 800C in Figure 8C is an exemplary, resulting IC structure of process 706. IC structure 800C includes a layer of conductive polymer 222 covering the conductive material 826 of the seed layer on the sidewall 803 of the opening 802. The conductive polymer 222 may comprise one or more conductive polymer materials, such as polythiophene and polypyrrole, and / or other suitable polymer materials, and may be deposited using any suitable deposition technique. For example, the thickness (e.g., width) of the conductive polymer 222 deposited on the sidewall 803 may depend on the dopant concentration to achieve the desired conductivity. In some examples, the thickness of the conductive polymer 222 deposited on the sidewall may range from about 1 to 10 micrometers, or about 2 to 6 micrometers.

[0063] Referring again to method 700 in Figure 7, method 700 follows process 708, which provides magnetic material by covering the conductive polymer on the sidewall. IC structure 800D in Figure 8D is an exemplary, resulting IC structure of process 708. As can be seen in Figure 8D, IC structure 800D includes a layer of magnetic material 214 on the sidewall 803 of the opening, covering the conductive polymer 222. The magnetic material 214 may be provided directly on the conductive polymer 222 using an electroplating process. In some examples, the thickness (e.g., width) of the magnetic material deposited on the sidewall 803 is in the range of about 1 to 5 micrometers. As mentioned above with respect to Figures 5A to 5B, in some examples, multiple alternating layers of conductive polymer 222 and magnetic material 214 may be deposited on the sidewall.

[0064] The method may then involve one or more polishing and / or etching processes to remove the magnetic material 214, conductive polymer 222, and conductive material 826 from the top and bottom (e.g., from the first surface 813-1 and the second surface 813-2). The IC structure 800E in Figure 8E is an exemplary, resulting IC structure from the process of removing the magnetic material 214 and conductive material from the top and bottom of the structure. As can be seen in Figure 8E, after polishing, the insulating material 212 is exposed on the top and bottom of the structure. In another example where the insulating material 212 is not present covering the first surface 813-1 and the second surface 813-2, the glass 210 may be exposed on surfaces 813-1 and 813-2 after such polishing / etching processes. For example, Figures 6A and 6B show exemplary IC structures 600 in which the glass is exposed after polishing to remove material from the glass surface.

[0065] Referring again to method 700 in Figure 7, method 700 is followed by process 710, which provides an insulating material by covering the magnetic material on the sidewall. IC structure 800F in Figure 8F is an exemplary, resulting IC structure of process 710. IC structure 800F includes layers of insulating material 812 on the sidewall 803 covering the magnetic material 214, as well as covering the upper and lower sides (e.g., covering surfaces 813-1 and 813-2). The insulating material 812 may be any suitable insulating material, such as an insulating polymer material or any other suitable insulating material, and may be deposited on the sidewall 803 according to any suitable deposition process. The insulating material 812 may have substantially the same material composition as the insulating material 212 or a different material composition.

[0066] Referring again to method 700 in Figure 7, method 700 is followed by process 712, which provides conductive material into the opening. IC structure 800G in Figure 8G is an exemplary, resulting IC structure of process 712. Providing the conductive material may involve filling the opening 802 with conductive material 216. For example, conductive material 216 may be deposited using an electroplating process. In such an example, the method involves depositing another conductive material 826 as a seed layer covering the insulating material 812 and electroplating conductive material 216 onto conductive material 826. As can be seen in Figure 8G, IC structure 800G includes a continuous portion of conductive material 216 within the opening 802 between the first surface 813-1 and the second surface 813-2. In other examples, the opening 802 does not have to be completely filled with conductive material 216, or an opening may be formed within the conductive material 216 to provide further material within the opening on the conductive material 216, as shown in Figures 4A-4B.

[0067] Thus, Figure 7 illustrates a method 700 for fabricating an IC structure or microelectronic assembly containing an integrated inductor having a conductive polymer isolation layer. By carrying out method 700, several features in the final IC structure may be produced, which are characteristic of using method 700. For example, one such feature is shown in IC structure 800G of Figure 8G, where a glass layer 210 (or other core or core material in the substrate) extends through the core (e.g., through the glass layer) between a first surface 813-1 and a second surface 813-2 via 850, a conductive material 216 within the via, a seed layer (e.g., conductive material 216) on the sidewall 803 of the via 850 between the core and the conductive material 216, where the seed layer includes a metal, a conductive polymer 222 on the sidewall 803 between the seed layer and the conductive material 216, a magnetic material 214 on the sidewall 803 between the conductive polymer 222 and the conductive material 216, and an insulating material 812 on the sidewall 803 between the magnetic material 214 and the conductive material 216. In another example, the implementation of method 700 may involve performing processes 706 and 708 multiple times to deposit multiple alternating layers of conductive polymer 222 and magnetic material 214. Such an example is shown in Figures 5A and 5B, where the IC structure 500 includes two layers of conductive polymer 222 and magnetic material 214 on the sidewall of an opening in which an inductor structure is disposed. An integrated inductor having conductive polymer layers according to the example described herein may allow for high-density and uniform plating of magnetic material on a panel scale (e.g., on a scale of about 500 mm). Additionally, the conductive polymer layers according to the example described herein can mitigate the adverse effects of eddy currents on the performance of the inductor.

[0068] IC structures and microelectronic assemblies including integrated inductors having conductive polymer isolation layers by the techniques described herein may be incorporated into any suitable electronic component or electronic device. Figures 9 to 12 show various examples of devices that may include one or more IC structures or assemblies comprising integrated inductors having conductive polymer isolation layers disclosed herein.

[0069] Figure 9 is a top view of a wafer 1500 and a die 1502 which may include one or more IC structures according to any embodiment disclosed herein. The wafer 1500 may be made of a semiconductor material and may include one or more dies 1502 having IC structures formed on the surface of the wafer 1500. Each die 1502 may be a repeating unit of a semiconductor product containing any suitable IC. After the semiconductor product has been manufactured, the wafer 1500 may undergo a flaking process in which the dies 1502 are separated from each other to provide separate “chips” of the semiconductor product. In some embodiments, the wafer 1500 or die 1502 may include memory devices (random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, and conductive-bridging RAM (CBRAM) devices), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 in Figure 12) or as other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0070] Figure 10 is a side cross-sectional view of an exemplary IC package 1650 which may include an assembly or one or more IC structures comprising an integrated inductor having a polymer isolation layer according to any of the embodiments disclosed herein. In some embodiments, the IC package 1650 may be a system-in-package (SiP).

[0071] The package substrate 1652 may be formed of a dielectric material (e.g., ceramic, build-up film, epoxy film with filler particles inside, glass, organic material, inorganic material, combination of organic and inorganic materials, embedded portion formed of different materials, etc.) and may have conductive paths extending through the dielectric material between surface 1672 and surface 1674, or between different positions on surface 1672 and / or between different positions on surface 1674.

[0072] The package substrate 1652 may include conductive contacts 1663 that are coupled through the package substrate 1652 to a conductive path (not shown), thereby enabling the circuits in the die 1656 and / or interposer 1657 to be electrically coupled to various conductive contacts 1664 (or to devices (not shown) included in the package substrate 1652).

[0073] The IC package 1650 may include an interposer 1657 coupled to the package substrate 1652 via conductive contacts 1661 of the interposer 1657, a first-level interconnect 1665, and conductive contacts 1663 of the package substrate 1652. The first-level interconnect 1665 shown in Figure 10 is a solder bump, but any suitable first-level interconnect 1665 may be used. In some embodiments, the interposer 1657 may not be included in the IC package 1650; instead, the die 1656 may be directly coupled to the conductive contact 1663 at face 1672 by the first-level interconnect 1665. More generally, one or more dies 1656 may be coupled to the package substrate 1652 via any suitable structure (e.g., silicon bridge, organic bridge, one or more waveguides, one or more interposers, wire bond, etc.).

[0074] The IC package 1650 may include one or more dies 1656 coupled to the interposer 1657 via conductive contacts 1654 of the die 1656, a first-level interconnect 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660 may be coupled to a conductive path (not shown) through the interposer 1657, thereby allowing circuits within the die 1656 to be electrically coupled to various conductive contacts 1661 (or to other devices (not shown) included in the interposer 1657). The first-level interconnect 1658 shown in Figure 10 is a solder bump, but any suitable first-level interconnect 1658 may be used. As used herein, “conductive contact” may refer to a portion of a conductive material (e.g., metal) that functions as an interface between different components; the conductive contact may be recessed into the surface of a component, coplanar with that surface, or extend away from that surface, and may take any suitable form (e.g., a conductive pad or socket).

[0075] In some embodiments, an underfill material 1666 may be disposed between the package substrate 1652 and the interposer 1657 around the first level interconnect 1665, and a mold compound 1668 may be disposed around the die 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the mold compound 1668. An exemplary material that may be used for the underfill material 1666 and the mold compound 1668 is, where appropriate, an epoxy mold material. A second level interconnect 1670 may be coupled to a conductive contact 1664. The second level interconnect 1670 shown in Figure 10 is a solder ball (for example, for a ball grid array configuration), but any suitable second level interconnect 1670 may be used (for example, a pin in a pin grid array configuration or a land in a land grid array configuration). As is known in the art and as will be discussed below with reference to Figure 11, the second level interconnect 1670 may be used to connect the IC package 1650 to another component such as a circuit board (e.g., a motherboard), an interposer, or another IC package.

[0076] Die 1656 may take any of the embodiments of die 1502 discussed herein. In embodiments in which IC package 1650 includes multiple dies 1656, IC package 1650 may be called a multi-chip package (MCP). Die 1656 may include circuitry for performing any desired function. For example, one or more of the dies 1656 may be logic dies (e.g., silicon-based dies), and one or more of the dies 1656 may be memory dies (e.g., high-bandwidth memory).

[0077] The IC package 1650 shown in Figure 10 is a flip-chip package, but other package architectures may be used. For example, the IC package 1650 could be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 1650 may be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although the IC package 1650 in Figure 10 shows two dies 1656, the IC package 1650 may contain any desired number of dies 1656. The IC package 1650 may include additional passive components such as surface-mount resistors, capacitors, and inductors disposed on the first or second surface 1672 of the package substrate 1652, or on either surface of the interposer 1657. More generally, the IC package 1650 may include any other active or passive components known in the art.

[0078] Figure 11 is a side cross-sectional view of an IC device assembly 1700, which may include an assembly comprising an integrated inductor with a polymer isolation layer according to any embodiment disclosed herein, or one or more IC packages or other electronic components (e.g., dies) comprising one or more IC structures. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first surface 1740 of the circuit board 1702 and a second surface 1742 opposite to the circuit board 1702; generally, components may be disposed on one or both of surfaces 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may take any form of an embodiment of the IC package 1650 discussed above with reference to Figure 10 (for example, which may include one or more IC structures according to the embodiments described herein).

[0079] In some embodiments, the circuit board 1702 may be a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed with a desired circuit pattern to route electrical signals between components coupled to the circuit board 1702 (optionally in conjunction with other metal layers). In other embodiments, the circuit board 1702 may be a non-PCB substrate.

[0080] The IC device assembly 1700 shown in Figure 11 includes a package-on-interposer structure 1736 coupled to a first surface 1740 of a circuit board 1702 by a coupling component 1716. The coupling component 1716 can electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (shown in Figure 11), male and female sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0081] The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as the form discussed above with reference to the coupling component 1716. Although a single IC package 1720 is shown in Figure 11, multiple IC packages may be coupled to the package interposer 1704; in fact, additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be, for example, a die (die 1502 in Figure 9), an IC device, or any other suitable component, or may include such a component. Generally, the package interposer 1704 may spread connections to a wider pitch or reroute some connections to different connections. For example, the package interposer 1704 may couple an IC package 1720 (e.g., a die) to a pair of BGA conductive contacts of a coupling component 1716 for coupling to a circuit board 1702. In the embodiment shown in Figure 11, the IC package 1720 and the circuit board 1702 are mounted on opposing sides of the package interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be mounted on the same side of the package interposer 1704. In some embodiments, three or more components may be interconnected by the package interposer 1704.

[0082] In some embodiments, the package interposer 1704 may be formed as a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer 1704 may be formed of polymer materials such as epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or polyimide. In some embodiments, the package interposer 1704 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to through-silicon vias (TSVs) 1706. The package interposer 1704 may further include embedded devices 1714, which include both passive and active devices. These devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take any form of package-on-interposer structure known in the art.

[0083] The IC device assembly 1700 may include an IC package 1724 which is coupled to a first surface 1740 of a circuit board 1702 by a coupling component 1722. The coupling component 1722 may take any form of the embodiments discussed above with reference to coupling component 1716, and the IC package 1724 may take any form of the embodiments discussed above with reference to IC package 1720.

[0084] The IC device assembly 1700 shown in Figure 11 includes a package-on-package structure 1734 coupled to a second surface 1742 of a circuit board 1702 by a coupling component 1728. The package-on-package structure 1734 may include IC packages 1726 and 1732 coupled to each other by a coupling component 1730 such that an IC package 1726 is positioned between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 may take any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured according to any of the package-on-package structures known in the art.

[0085] Figure 12 is a block diagram of an exemplary electrical device 1800, which may include an assembly or one or more IC structures comprising an integrated inductor having a polymer isolation layer according to any of the embodiments disclosed herein. For example, any suitable component of the electrical device 1800 may include one or more of the IC device assemblies 1700, IC packages 1650, or dies 1502 disclosed herein. Although several components are shown in Figure 12 as being included in the electrical device 1800, any one or more of these components may be omitted or duplicated if appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1800 may be mounted on one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-chip (SoC) die.

[0086] Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components shown in Figure 12, but may include interface circuits for coupling to such one or more components. For example, the electrical device 1800 may not include the display device 1806, but may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1806 can be coupled. In another set of examples, the electrical device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1824 or the audio output device 1808 can be coupled.

[0087] The electrical device 1800 may include processing devices 1802 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts such electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include memory 1804 which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory: DRAM), non-volatile memory (e.g., read-only memory: ROM), flash memory, solid-state memory, and / or hard drives. In some embodiments, the memory 1804 may include a memory that shares a die with the processing device 1802. This memory may be used as a cache memory and may include embedded DRAM (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0088] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communication for data transfer to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. This term does not imply that the associated device does not include any wiring, although this may not be the case in some embodiments.

[0089] The 1812 communication chip may implement any of several wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi® (IEEE 802.11 family), the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), and the Long-Term Evolution (LTE) project with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP® 2")). IEEE 802.16-compatible broadband radio access (BWA) networks are commonly referred to as WiMAX® networks, an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 compliance and interoperability testing. The communication chip 1812 may operate in accordance with Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Advanced HSPA (E-HSPA), or LTE networks. The communication chip 1812 may operate in accordance with GSM® Advanced High-Speed ​​Data Transmission (EDGE), GSM® EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Advanced UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and their derivatives, as well as any other radio protocols designated as 3G, 4G, 5G and later. In other embodiments, the communication chip 1812 may operate in accordance with other radio protocols. The electrical device 1800 may include an antenna 1822 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM wireless transmission).

[0090] In some embodiments, the communication chip 1812 may manage wired communications such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet®). As described above, the communication chip 1812 may comprise multiple communication chips. For example, the first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi® or Bluetooth®, and the second communication chip 1812 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX®, LTE, EV-DO, or others. In some embodiments, the first communication chip 1812 may be dedicated to wireless communications, and the second communication chip 1812 may be dedicated to wired communications.

[0091] The electrical device 1800 may include a battery / power supply circuit 1814. The battery / power supply circuit 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).

[0092] The electrical device 1800 may include a display device 1806 (or the corresponding interface circuit discussed above). The display device 1806 may include any visual indicator such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0093] The electrical device 1800 may include an audio output device 1808 (or the corresponding interface circuit discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, headset, or earphone.

[0094] The electrical device 1800 may include an audio input device 1824 (or the corresponding interface circuit discussed above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output).

[0095] The electrical device 1800 may include a GPS device 1818 (or the corresponding interface circuit discussed above). As is known in the art, the GPS device 1818 can communicate with a satellite-based system and receive the position of the electrical device 1800.

[0096] The electrical device 1800 may include another output device 1810 (or the corresponding interface circuit discussed above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0097] The electrical device 1800 may include another input device 1820 (or the corresponding interface circuit discussed above). Examples of other input devices 1820 may include an accelerometer, gyroscope, compass, image capture device, keyboard, cursor control device such as a mouse, stylus, touchpad, barcode reader, quick response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

[0098] The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA®), ultramobile personal computer, etc.), a desktop electrical device, a server device or other network computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.

[0099] The following paragraphs provide various examples of embodiments disclosed herein.

[0100] Example 1 provides a microelectronic assembly comprising: a glass layer having a first surface and a second surface; and an inductor within the layer, wherein the inductor has a continuous portion of a conductive material between the first surface and the second surface, a magnetic material at least partially surrounding the conductive material, and a conductive polymer at least partially surrounding the magnetic material.

[0101] Example 2 provides the microelectronic assembly described in Example 1, wherein the conductive polymer comprises one or more of polythiophene and polypyrrole.

[0102] Example 3 provides the microelectronic assembly described in Example 2, wherein the conductive polymer further comprises an alkali metal or DMBI-H.

[0103] Example 4 provides a microelectronic assembly according to any one of Examples 1 to 3, wherein the conductive polymer has conductivity in the range of about 100 to 1000 S / m.

[0104] Example 5 provides a microelectronic assembly according to any one of Examples 1 to 4, wherein the conductive polymer has a thickness in the range of about 1 to 10 microns, and the thickness is the dimension of the conductive polymer in a plane substantially parallel to the layer.

[0105] Example 6 provides a microelectronic assembly according to any one of Examples 1 to 5, wherein the magnetic material comprises one or more of iron, cobalt, and nickel.

[0106] Example 7 provides the microelectronic assembly described in Example 6, wherein the magnetic material further comprises one or more of boron, sulfur, phosphorus, and oxygen.

[0107] Example 8 provides a microelectronic assembly according to any one of Examples 1 to 7, wherein the conductive polymer is a first conductive polymer layer, the magnetic material is a first magnetic material layer, and the inductor further comprises a second magnetic material layer at least partially surrounding the first conductive polymer layer, and a second conductive polymer layer at least partially surrounding the second magnetic material layer.

[0108] Example 9 provides a microelectronic assembly according to any one of Examples 1 to 8, wherein the inductor has an insulating material between the conductive material and the magnetic material.

[0109] Example 10 provides the microelectronic assembly described in Example 9, wherein the inductor has a seed layer between the insulating material and the conductive material, and the seed layer contains a metal.

[0110] Example 11 provides the microelectronic assembly according to Example 10, wherein the seed layer is a first seed layer, and the microelectronic assembly further comprises a second seed layer between the glass and the conductive polymer.

[0111] Example 12 provides a microelectronic assembly according to any one of Examples 1 to 11, further comprising an insulating material between the glass and the conductive polymer.

[0112] Example 13 provides a microelectronic assembly according to any one of Examples 1 to 12, wherein the inductor has an insulating material and the conductive material surrounds the insulating material.

[0113] Example 14 provides a microelectronic assembly comprising a substrate having a core, wherein the core includes a first surface and a second surface opposite to the first surface; vias extending through the core and between the first surface and the second surface; a conductive material within the vias; a seed layer on the sidewall of the vias between the core and the conductive material, wherein the seed layer includes a metal; a conductive polymer material on the sidewall between the seed layer and the conductive material; a magnetic material on the sidewall between the conductive polymer and the conductive material; and an insulating material on the sidewall between the magnetic material and the conductive material.

[0114] Example 15 provides the microelectronic assembly described in Example 14, wherein the conductive polymer material is a conjugated polymer material comprising one or more inorganic dopants and organic molecular dopants.

[0115] Example 16 provides a microelectronic assembly according to any one of Examples 14 to 15, wherein the conductive polymer material is a first conductive polymer layer, the magnetic material is a first magnetic layer, and the microelectronic assembly further comprises a second conductive polymer layer having the conductive polymer material between the first magnetic layer and the insulating material, and a second magnetic layer having the magnetic material between the second conductive polymer layer and the insulating material.

[0116] Example 17 provides a microelectronic assembly according to any one of Examples 1 to 16, wherein the microelectronic assembly includes or is part of a central processing unit.

[0117] Example 18 provides a microelectronic assembly according to any one of Examples 1 to 17, wherein the microelectronic assembly includes or is part of a memory device.

[0118] Example 19 provides a microelectronic assembly according to any one of Examples 1 to 18, wherein the microelectronic assembly includes or is part of a logic circuit.

[0119] Example 20 provides a microelectronic assembly according to any one of Examples 1 to 19, wherein the microelectronic assembly includes or is part of an input / output circuit.

[0120] Example 21 provides a microelectronic assembly according to any one of Examples 1 to 20, wherein the microelectronic assembly includes or is part of a field-programmable gate array transceiver.

[0121] Example 22 provides a microelectronic assembly described in any one of Examples 1 to 21, wherein the microelectronic assembly includes or is part of a field-programmable gate array logic.

[0122] Example 23 provides a microelectronic assembly according to any one of Examples 1 to 22, wherein the microelectronic assembly includes or is part of a power supply circuit.

[0123] Example 24 provides an IC package comprising the microelectronic assembly described in any one of Examples 1 to 23.

[0124] Example 25 provides the IC package described in Example 24, further comprising additional IC components coupled to a microelectronic assembly.

[0125] Example 26 provides the IC package described in Example 25, wherein further IC components have a package substrate.

[0126] Example 27 provides the IC package described in Example 25, wherein a further IC component has an interposer.

[0127] Example 28 provides the IC package described in Example 25, wherein further IC components have further assemblies or dies.

[0128] Example 29 provides a computing device comprising a carrier substrate and an assembly coupled to the carrier substrate, wherein the assembly is either the assembly described in any one of Examples 1 to 16, or the assembly is contained within the IC package described in any one of Examples 17 to 28.

[0129] Example 30 provides the computing device described in Example 29, wherein the computing device is a wearable or handheld computing device.

[0130] Example 31 provides a computing device according to Example 29 or 30, wherein the computing device further comprises one or more communication chips.

[0131] Example 32 provides a computing device according to any one of Examples 29-31, wherein the computing device further comprises an antenna.

[0132] Example 33 provides a computing device according to any one of Examples 29-32, wherein the carrier board is a motherboard.

[0133] Example 34 provides an IC structure comprising an inductor in an opening within a material layer (e.g., a substrate core material such as glass or another substrate core), wherein the inductor has a continuous portion of conductive material, a magnetic material around the conductive material, and a conductive polymer layer around the magnetic material within the opening.

[0134] Example 35 provides a method for fabricating a microelectronic assembly, the method comprising the steps of: forming an opening in a core material (such as a glass layer); providing a first conductive material on the sidewall of the opening, wherein the first conductive material includes a metal; providing a conductive polymer on the first conductive material; providing a magnetic material on the conductive polymer; providing an insulating material on the magnetic material; and filling the opening with a second conductive material on the insulating material.

[0135] Example 36 provides the method of Example 35, wherein the step of providing the conductive polymer includes the step of electroplating the conductive polymer onto the first conductive material.

[0136] Example 37 provides a method according to any one of Examples 35 to 36, wherein the step of providing the magnetic material includes the step of electroplating the magnetic material onto the conductive polymer.

[0137] Example 38 provides a method according to any one of Examples 35 to 37, wherein the insulating material is a first insulating material, and the method further comprises the step of depositing a second insulating material on the sidewall of the opening before providing the first conductive material.

[0138] Example 39 provides a method according to any one of Examples 35 to 38, further comprising the steps of: providing a further layer of the conductive polymer on the magnetic material; and providing a further layer of the magnetic material on the further layer of the conductive polymer.

[0139] Example 40 provides a method according to any one of Examples 35 to 39, wherein the opening is a first opening, and the method further comprises the steps of forming a second opening in the glass layer and filling the second opening with a conductive material.

[0140] Example 41 provides a method according to any one of Examples 35-40, wherein the microelectronic assembly is the microelectronic assembly described in any one of the preceding examples.

[0141] Example 42 provides a process for creating a microelectronic assembly by the method described in any one of Examples 35-40.

[0142] The above description of the provided implementation of the Disclosure, including matters described in the Abstract, is not intended to be exhaustive or to limit the Disclosure to the exact form disclosed. While specific implementations and examples of the Disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the Disclosure, as will be apparent to those skilled in the art. These modifications may be added to the Disclosure in light of the above detailed description. [Other possible items] [Item 1] A glass layer having a first surface and a second surface; and The inductor in the aforementioned layer, where the inductor is The continuous portion of the conductive material between the first surface and the second surface, A magnetic material that at least partially surrounds the conductive material, and A conductive polymer that at least partially surrounds the magnetic material. has A microelectronic assembly comprising: [Item 2] The microelectronic assembly according to item 1, wherein the conductive polymer comprises one or more of polythiophene and polypyrrole. [Item 3] The conductive polymer further comprises an alkali metal or DMBI-H. The microelectronic assembly described in item 2. [Item 4] The conductive polymer has conductivity in the range of about 100 to 1000 S / m. The microelectronic assembly described in item 1. [Item 5] The conductive polymer has a thickness in the range of about 1 to 10 microns, and the thickness is the dimension of the conductive polymer in a plane substantially parallel to the layer. The microelectronic assembly described in item 1. [Item 6] The magnetic material includes one or more of iron, cobalt, and nickel. The microelectronic assembly described in item 1. [Item 7] The microelectronic assembly according to item 6, wherein the magnetic material further comprises one or more of boron, sulfur, phosphorus, and oxygen. [Item 8] The conductive polymer is a first conductive polymer layer, the magnetic material is a first magnetic material layer, and the inductor is A second magnetic material layer that at least partially surrounds the first conductive polymer layer, and A second conductive polymer layer that at least partially surrounds the second magnetic material layer. The microelectronic assembly described in item 1, further comprising: [Item 9] The inductor has an insulating material between the conductive material and the magnetic material. The microelectronic assembly described in item 1. [Item 10] The inductor has a seed layer between the insulating material and the conductive material, and the seed layer contains a metal. The microelectronic assembly described in item 9. [Item 11] The seed layer is a first seed layer, and the microelectronic assembly is The second seed layer between the glass and the conductive polymer The microelectronic assembly described in item 10 further includes the features described therein. [Item 12] Insulating material between the glass and the conductive polymer The microelectronic assembly described in item 1 further includes the features described in item 1. [Item 13] The inductor has an insulating material, and the conductive material surrounds the insulating material. The microelectronic assembly described in item 1. [Item 14] A substrate having a core, wherein the core includes a first surface and a second surface opposite to the first surface; vias extending through the core and between the first and second surfaces; Conductive material within the via; A seed layer on the side wall of the via between the core and the conductive material, wherein the seed layer contains metal; A conductive polymer material on the side wall between the seed layer and the conductive material; The magnetic material on the side wall between the conductive polymer material and the conductive material; and The insulating material on the side wall between the magnetic material and the conductive material A microelectronic assembly comprising: [Item 15] The conductive polymer material comprises a conjugated polymer material containing one or more inorganic dopants and organic molecular dopants. The microelectronic assembly described in item 14. [Item 16] The conductive polymer material is a first conductive polymer layer, the magnetic material is a first magnetic layer, and the microelectronic assembly is A second conductive polymer layer having the conductive polymer material between the first magnetic layer and the insulating material, and A second magnetic layer having the magnetic material between the second conductive polymer layer and the insulating material. The microelectronic assembly described in item 14 further comprises the following: [Item 17] A method for fabricating a microelectronic assembly, wherein the method is The step of forming an opening within the core material; The step of providing a first conductive material on the side wall of the opening, wherein the first conductive material includes a metal; A step of providing a conductive polymer on the first conductive material; A step of providing a magnetic material on the conductive polymer; The step of providing an insulating material on the magnetic material; and The step of covering the insulating material and filling the opening with the second conductive material. A method that includes [a certain feature]. [Item 18] The step of providing the conductive polymer includes the step of electroplating the conductive polymer onto the first conductive material. The method described in item 17. [Item 19] The step of providing the magnetic material includes the step of electroplating the magnetic material onto the conductive polymer. The method described in item 17. [Item 20] The insulating material is a first insulating material, and the method is The step of depositing a second insulating material on the side wall of the opening before providing the first conductive material. The method described in item 17, further comprising:

Claims

1. A glass layer having a first surface and a second surface; and The inductor within the glass layer, where the inductor is The continuous portion of the conductive material between the first surface and the second surface, A magnetic material that at least partially surrounds the conductive material, and A conductive polymer that at least partially surrounds the magnetic material. has A microelectronic assembly comprising:

2. The conductive polymer comprises one or more of polythiophene and polypyrrole. The microelectronic assembly according to claim 1.

3. The conductive polymer further comprises an alkali metal or DMBI-H. The microelectronic assembly according to claim 2.

4. The conductive polymer has conductivity in the range of about 100 to 1000 S / m. The microelectronic assembly according to claim 1.

5. The conductive polymer has a thickness in the range of about 1 to 10 microns, and the thickness is the dimension of the conductive polymer in a plane substantially parallel to the glass layer. The microelectronic assembly according to claim 1.

6. The magnetic material includes one or more of iron, cobalt, and nickel. The microelectronic assembly according to claim 1.

7. The magnetic material further comprises one or more of boron, sulfur, phosphorus, and oxygen. The microelectronic assembly according to claim 6.

8. The conductive polymer is a first conductive polymer layer, and the magnetic material is a first magnetic material layer. The aforementioned inductor is A second magnetic material layer that at least partially surrounds the first conductive polymer layer, and A second conductive polymer layer that at least partially surrounds the second magnetic material layer. It further possesses, The microelectronic assembly according to claim 1.

9. The inductor has an insulating material between the conductive material and the magnetic material. The microelectronic assembly according to claim 1.

10. The inductor has a seed layer between the insulating material and the conductive material, and the seed layer contains a metal. The microelectronic assembly according to claim 9.

11. The seed layer is a first seed layer, and the microelectronic assembly is Second seed layer between the glass layer and the conductive polymer The microelectronic assembly according to claim 10, further comprising:

12. Insulating material between the glass layer and the conductive polymer The microelectronic assembly according to claim 1, further comprising:

13. The inductor has an insulating material, and the conductive material surrounds the insulating material. The microelectronic assembly according to any one of claims 1 to 12.

14. A substrate having a core, wherein the core includes a first surface and a second surface opposite to the first surface; vias passing through the core and extending between the first and second surfaces; Conductive material within the via; A seed layer on the side wall of the via between the core and the conductive material, wherein the seed layer contains metal; Conductive polymer material on the side wall between the seed layer and the conductive material; The magnetic material on the side wall between the conductive polymer material and the conductive material; and The insulating material on the side wall between the magnetic material and the conductive material A microelectronic assembly comprising:

15. The conductive polymer material comprises a conjugated polymer material containing one or more inorganic dopants and organic molecular dopants. The microelectronic assembly according to claim 14.

16. The conductive polymer material is a first conductive polymer layer, the magnetic material is a first magnetic layer, and the microelectronic assembly is A second conductive polymer layer having the conductive polymer material between the first magnetic layer and the insulating material, and A second magnetic layer having the magnetic material between the second conductive polymer layer and the insulating material. The microelectronic assembly according to claim 14 or 15, further comprising:

17. A method for fabricating a microelectronic assembly, wherein the method is The step of forming an opening within the glass layer; The step of providing a first conductive material on the side wall of the opening, wherein the first conductive material includes a metal; Steps include providing a conductive polymer on the first conductive material; A step of providing a magnetic material on the conductive polymer; The step of providing an insulating material on the magnetic material; and The step of covering the insulating material and filling the opening with the second conductive material. A method that includes [a certain feature].

18. The step of providing a conductive polymer includes the step of electroplating the conductive polymer onto the first conductive material. The method according to claim 17.

19. The step of providing the magnetic material includes the step of electroplating the magnetic material onto the conductive polymer. The method according to claim 17.

20. The insulating material is a first insulating material, and the method is The step of depositing a second insulating material on the side wall of the opening before providing the first conductive material. The method according to claim 17, further comprising:

21. The aforementioned method, The step of providing a further layer of the conductive polymer on the magnetic material; and The step of providing a further layer of the magnetic material on the further layer of the conductive polymer. The method according to claim 17, further comprising:

22. The opening is a first opening, and the method is The step of forming a second opening within the glass layer; and Step of filling the second opening with a conductive material. The method according to claim 17, further comprising:

23. The method according to claim 17, wherein the conductive polymer comprises one or more of polythiophene and polypyrrole.

24. The conductive polymer further comprises an alkali metal or DMBI-H. The method according to claim 23.

25. The conductive polymer has conductivity in the range of about 100 to 1000 S / m. The method according to any one of claims 17 to 24.

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