Recording medium, recording device, recording method, playback device, and playback method

Abstract

The present technology relates to a recording medium, a recording device, a recording method, a reproduction device, and a reproduction method that make it possible to correctly reproduce multi-level code that has been recorded at high density. According to the present invention, a recording medium stores: M-ary multi-level code produced by coding user data into an M-ary (d,k) RLL code for which M is at least 3; and an M-ary specific pattern that repeats a run that is longer than the longest run k of the multi-level code. Reproduction from the recording medium is performed, and the multi-level code is decoded in accordance with the specific pattern. The present technology can be applied, for example, to recording media and recording / reproduction devices that perform recording / reproduction to / from a recording medium.

Description

[Technical Field]

[0001] The present technology relates to a recording medium, a recording device, a recording method, a reproducing device, and a reproducing method, and in particular to a recording medium, a recording device, a recording method, a reproducing device, and a reproducing method that enable correct reproduction of, for example, a multi-level code recorded at high density. [Background technology]

[0002] The present applicant has previously proposed recording and reproduction of a multi-level code that can take three or more ML values ​​and is suitable for high-density recording (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 090457 Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Document 1 does not disclose a specific method for correctly reproducing a multi-level code recorded at high density.

[0005] The present technology has been made in view of such circumstances, and makes it possible to correctly reproduce multi-level codes recorded at high density. [Means for solving the problem]

[0006] The recording medium of the present technology is a recording medium on which a multi-level code of ML values, in which user data is encoded into a (d, k) RLL code of 3 or more ML values, and a specific pattern of the ML values ​​that repeats runs greater than the maximum run k of the multi-level code, are recorded.

[0007] In the recording medium of the present technology, a multi-level code of ML values, in which user data is encoded into a (d, k) RLL code of 3 or more ML values, and a specific pattern of the ML values ​​that repeats runs greater than the maximum run k of the multi-level code, are recorded.

[0008] The recording device of the present technology is a recording device that includes an encoding unit that encodes user data into a multi-level code that is a (d, k) RLL code with ternary or greater ML values, and a recording unit that records a specific pattern of the ML values ​​that repeats runs greater than a maximum run length k of the multi-level code, and the multi-level code, on a recording medium.

[0009] The recording method of the present technology is a recording method that includes encoding user data into a multi-level code that is a (d, k) RLL code with ternary or greater ML values, and recording a specific pattern of the ML values ​​that repeats a run greater than a maximum run k of the multi-level code and the multi-level code on a recording medium.

[0010] In the recording device and recording method of the present technology, user data is encoded into a multi-level code, which is a (d, k) RLL code with ternary or greater ML values, and a specific pattern of the ML values ​​that repeats runs greater than a maximum run length k of the multi-level code and the multi-level code are recorded on a recording medium.

[0011] The playback device of the present technology is a playback device that includes a playback unit that plays back a recording medium on which a multi-level code of ML values, which is obtained by encoding user data into a (d, k) RLL code of 3 or more ML values, and a specific pattern of the ML values ​​that repeats a run greater than a maximum run k of the multi-level code, are recorded, and a decoding unit that decodes the multi-level code in accordance with the specific pattern.

[0012] A playback method of the present technology is a playback method including: playing a recording medium on which a multi-level code of ML values, in which user data is encoded into a (d, k) RLL code of 3 or more ML values, and a specific pattern of the ML values ​​that repeats a run greater than a maximum run k of the multi-level code, are recorded; and decoding the multi-level code in accordance with the specific pattern.

[0013] In the playback device and playback method of the present technology, a recording medium is played back on which a multi-level code of ML values, which is obtained by encoding user data into a (d, k) RLL code of ternary or greater ML values, and a specific pattern of the ML values ​​that repeats a run greater than a maximum run k of the multi-level code, are recorded, and the multi-level code is decoded according to the specific pattern.

[0014] The recording device and the playback device may be independent devices, or may be internal blocks that make up a single device.

[0015] The recording device and playback device can be realized by causing a computer to execute a program. The program can be distributed by recording it on a recording medium or transmitting it via a transmission medium. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a block diagram showing an example of the configuration of an embodiment of a recording and reproducing device to which the present technology is applied. [Figure 2] 10 is a flowchart illustrating an example of a recording process in which the recording / reproducing device records user data on the optical disc 16. [Figure 3] 10 is a flowchart illustrating an example of a reproduction process in which the recording / reproducing device reproduces user data recorded on the optical disc 16. [Figure 4] FIG. 2 is a block diagram showing an example of the configuration of a channel encoding unit 12. [Figure 5] FIG. 2 is a block diagram showing an example of the configuration of a signal processing unit 17. [Figure 6] FIG. 1 is a diagram illustrating a method for expressing a multi-level code. [Figure 7] FIG. 1 is a diagram showing a code generation model for generating an edge code (a multilevel code expressed by the edge code). [Figure 8] FIG. 10 is a diagram showing an example of a code LUT in which 512 block codes are registered as 9-bit / 4-cell codes with k=4 and ML=5. [Figure 9]FIG. 10 is a diagram showing an example of a code LUT in which 512 block codes are registered as 9-bit / 4-cell codes with k=4 and ML=5. [Figure 10] FIG. 10 is a diagram showing an example of a code LUT in which 512 block codes are registered as 9-bit / 4-cell codes with k=4 and ML=5. [Figure 11] FIG. 10 is a diagram showing an example of a code LUT in which 512 block codes are registered as 9-bit / 4-cell codes with k=4 and ML=5. [Figure 12] FIG. 10 is a diagram showing an example of a code LUT in which 512 block codes are registered as 9-bit / 4-cell codes with k=4 and ML=5. [Figure 13] FIG. 10 is a diagram showing an example of a code LUT in which 512 block codes are registered as 9-bit / 4-cell codes with k=4 and ML=5. [Figure 14] 1 is a diagram illustrating an example of an ECC cluster configured by an ECC processing unit 11. FIG. [Figure 15] 10 is a diagram illustrating an example of a frame configured by frame configuration section 13. FIG. [Figure 16] FIG. 10 is a diagram illustrating an example of an FS. [Figure 17] 1 is a diagram illustrating an example of a RUB configured by a RUB configuration unit 14. FIG. [Figure 18] FIG. 10 is a diagram illustrating an example of the configuration of Run-in. [Figure 19] FIG. 1 is a diagram showing an example of the configuration of a G-100CELL constituting GAptn and GBptn, and an L-100CELL constituting LAptn and LBptn. [Figure 20] FIG. 10 is a diagram illustrating an example of the configuration of SY0. [Figure 21] FIG. 10 is a diagram illustrating an example of the configuration of NC0. [Figure 22] 10A and 10B are diagrams illustrating configuration examples of a 4-cell pattern and a 2-2 cell pattern. [Figure 23] FIG. 10 is a diagram illustrating an example of the configuration of APC SYNC. [Figure 24] FIG. 2 is a diagram illustrating an example of the configuration of NC1 and NC2. [Figure 25]FIG. 10 is a diagram illustrating an example of the configuration of Run-out. [Figure 26] 10A and 10B are diagrams illustrating a specific example of frame configuration and DC control performed by frame configuration section 13. [Figure 27] 10A and 10B are diagrams illustrating an example of detection of a specific pattern by the sync detection unit 18. FIG. [Figure 28] 10 is a flowchart illustrating an example of a detection process for detecting a specific pattern. [Figure 29] FIG. 10 is a diagram illustrating an example of dissimilarity calculated by a simulation. [Figure 30] FIG. 10 is a diagram showing another first example of dissimilarity calculated by simulation. [Figure 31] FIG. 10 is a diagram showing another second example of dissimilarity calculated by simulation. [Figure 32] FIG. 10 is a diagram showing another third example of dissimilarity calculated by simulation. [Figure 33] 10A and 10B are diagrams illustrating the effect of DC control of multilevel codes. [Figure 34] 10A and 10B are diagrams illustrating the effect of DC control of multilevel codes. [Figure 35] 10A and 10B are diagrams illustrating the effect of DC control of multilevel codes. [Figure 36] FIG. 10 is a diagram illustrating an example of a required SNR as a decoding performance of a multilevel code. [Figure 37] FIG. 1 is a block diagram illustrating an example of the configuration of an embodiment of a computer. DETAILED DESCRIPTION OF THE INVENTION

[0017] <One embodiment of a recording / playback device to which the present technology is applied>

[0018] FIG. 1 is a block diagram showing an example of the configuration of an embodiment of a recording / playback device to which the present technology is applied.

[0019] In FIG. 1, the recording and playback device includes an ECC (Error Correction Coding) processing unit 11, a channel encoding unit 12, a frame construction unit 13, a RUB (Recording Unit Block) construction unit 14, a recording and playback system 15, an optical disk 16, a signal processing unit 17, a sync detection unit 18, a frame detection unit 19, a DCC deletion unit 20, a channel decoding unit 21, an ECC processing unit 22, and a control unit 23.

[0020] The ECC processing unit 11 is supplied with user data to be recorded on the optical disc 16 (content such as images and sounds, computer programs, and various other data).

[0021] The ECC processing unit 11 constructs ECC target data including a predetermined unit of user data. The ECC target data is data that is the target of ECC processing. The ECC processing unit 11 performs ECC processing to add parity to the ECC target data, thereby constructing an ECC cluster, which is a sequence of binary data. The ECC processing unit 11 supplies the ECC cluster to the channel encoding unit 12.

[0022] The channel encoding unit 12 encodes the ECC cluster from the ECC processing unit 11 into a predetermined channel code.

[0023] Here, as the channel code, for example, a multi-level code of ML values ​​of three or more values ​​can be adopted. As the multi-level code of ML values, for example, a multi-level code generated by state transition of a code generation model described later can be adopted.

[0024] The channel encoding unit 12 encodes the ECC cluster into a multi-level code with ML values. Hereinafter, the (sequence of) multi-level codes obtained by encoding the ECC cluster will also be referred to as cluster multi-level codes. The cluster multi-level codes are supplied from the channel encoding unit 12 to the frame configuration unit 13.

[0025] The frame constructor 13 constructs a frame including the sequence of the cluster multi-level code from the channel encoder 12 and supplies the frame to the RUB constructor 14 .

[0026] That is, the frame configuration unit 13 divides the sequence of cluster multi-level codes from the channel coding unit 12 into DC control units, which are units for performing DC (Direct Current) control, and performs DC control for each (sequence of) cluster multi-level codes in the DC control unit.

[0027] Furthermore, the frame constructing unit 13 constructs a frame by adding a frame sync (FS) indicating the beginning (or end) of a frame to the cluster multi-level codes of a plurality of DC control units after DC control.

[0028] DC control is performed by adding a DCC (Direct Current Control) cell to the cluster multilevel code of the DC control unit. The DCC cell is a multilevel cell that takes the same ML value as the multilevel code, which is the channel code, and can be regarded as a single multilevel code.

[0029] As described above, the frame configuration unit 13 not only configures frames but also performs DC control, and therefore also serves as a DC control unit that performs DC control.

[0030] The RUB construction unit 14 constructs a RUB as a recording block, which is the unit of recording on the optical disc 16, by adding Run-in and Run-out to the beginning and end of multiple frames from the frame construction unit 13, and supplies it to the recording / playback system 15.

[0031] Run-in and Run-out are multilevel patterns that take the same ML values ​​as the multilevel code, which is the channel code, and can be considered as a multilevel code sequence. Run-in and Run-out represent the beginning and end of a RUB, respectively.

[0032] When constructing a RUB, an APC (Automatic Power Control) SYNC can be added to a necessary frame among the multiple frames that make up the RUB.

[0033] APC SYNC is a multi-level pattern that takes on ML values ​​similar to the multi-level code, which is a channel code, and can be considered as a multi-level code sequence. APC SYNC is a pattern used for timing recovery of the channel clock of a recording / playback device and power control.

[0034] The recording / reproducing system 15 is composed of a pickup (not shown) and the like. The recording / reproducing system 15 functions as a recording unit that records data (multilevel code) on the optical disc 16 by irradiating the optical disc 16 with light such as laser light to form marks. The recording / reproducing system 15 also functions as a reproducing unit that reproduces data recorded on the optical disc 16 by irradiating the optical disc 16 with laser light, receiving light reflected from the optical disc 16 in response to the laser light, and outputting a reproduction signal corresponding to the reflected light.

[0035] The recording and reproducing system 15 irradiates the optical disc 16 with a laser beam in accordance with the RUB from the RUB constructing unit 14, and records the RUB on the optical disc 16. The recording and reproducing system 15 also irradiates the optical disc 16 with a laser beam to reproduce a reproduction signal (RF (Radio Frequency) signal) corresponding to the RUB etc. recorded on the optical disc 16, and supplies the reproduction signal to the signal processing unit 17.

[0036] The optical disc 16 is a type of disc-shaped recording medium, and has tracks formed by lands (tracks) and grooves (tracks) adjacent to each other.

[0037] A groove is a track that is grooved and wobbles, for example, for addressing purposes, and a land is a track sandwiched between two (adjacent) grooves.

[0038] In the optical disc 16, in order to record data at a high linear density, data is recorded (marks are formed) on both the lands and grooves.

[0039] As the optical disk 16, other types of recording media can be used, such as a disk-shaped recording medium that does not have grooves for recording data (only grooves for applying servo are formed), that is, a recording medium that performs so-called grooveless mirror surface recording.

[0040] The signal processing unit 17 processes the reproduced signal from the recording and reproducing system 15 to restore a sequence of multi-level codes, and supplies the restored sequence to the sync detection unit 18 and the frame detection unit 19. The sequence of multi-level codes restored by the signal processing unit 17 includes a multi-level code obtained by encoding an ECC cluster including user data, Run-in and Run-out (as multi-levels), FS (as multi-levels), and APC SYNC (as multi-levels).

[0041] Here, the multilevel code as the channel code is a (d, k) RLL code of ML values. Run-in, FS, and APC SYNC are all specific patterns of ML values ​​that repeat a run greater than the maximum run k of the multilevel code as the channel code.

[0042] The sync detector 18 detects Run-in, FS, and APC SYNC as specific patterns from the multilevel code sequence from the signal processor 17, and supplies them to a frame detector 19 and other necessary blocks.

[0043] The frame detection unit 19 detects frames from the sequence of multilevel codes from the signal processing unit 17 in accordance with the specific pattern (for example, FS) from the sync detection unit 18 and supplies the detected frames to the DCC deletion unit 20.

[0044] The DCC removal unit 20 removes the DCC cells from the frames received from the frame detection unit 19, and supplies the resulting multilevel code (cluster multilevel code) obtained by encoding the ECC cluster to the channel decoding unit 21.

[0045] The channel decoding unit 21 decodes (channel decodes) the cluster multi-level code from the DCC removing unit 20, and supplies the ECC cluster obtained by the decoding to the ECC processing unit 22.

[0046] As described above, the channel decoding unit 21 decodes the cluster multi-level code included in the detected frame according to the specific pattern, and therefore it can be said that the channel decoding unit 21 decodes the cluster multi-level code according to the specific pattern.

[0047] The ECC processing unit 22 performs ECC processing on the ECC cluster from the channel decoding unit 21 to correct errors that have occurred in the ECC target data included in the ECC cluster, and outputs the user data included in the ECC target data after the error correction.

[0048] The control unit 23 controls each block that constitutes the recording / reproducing device. That is, the control unit 23 has a built-in register group 23A. Commands and other various information are stored (set) in the register group 23A in response to, for example, operations on an operation unit (not shown). The control unit 23 controls each block that constitutes the recording / reproducing device in response to the stored values ​​(set values) in the register group 23A.

[0049] In FIG. 1, the recording / reproducing device can be configured as a device that performs both reproduction and recording, or as a reproduction-only device that performs reproduction only, or as a recording-only device that performs recording only.

[0050] In addition, in FIG. 1, the recording / playback device can be configured to have the optical disk 16 built in beforehand, or can be configured to have the optical disk 16 detachably mounted.

[0051] Furthermore, the ECC processing unit 11 through the RUB configuration unit 14 and the signal processing unit 17 through the control unit 23 that constitute the recording and reproducing device of FIG. 1 can be configured on a single chip.

[0052] Furthermore, as the recording medium on which the multi-level code is recorded, in addition to a disk-shaped recording medium such as the optical disk 16, a tape-shaped or card-shaped recording medium, or a recording medium using semiconductors such as a memory card can be used.

[0053] <Recording Processing>

[0054] FIG. 2 is a flowchart illustrating an example of a recording process in which the recording / reproducing apparatus of FIG. 1 records user data on the optical disc 16. In FIG.

[0055] In step S11, the ECC processing unit 11 constructs ECC target data including a predetermined unit of user data from the user data supplied thereto. Furthermore, the ECC processing unit 11 performs ECC processing on the ECC target data to construct an ECC cluster by adding parity to the ECC target data, and supplies the ECC cluster to the channel encoding unit 12, and the process proceeds from step S11 to step S12.

[0056] In step S12, the channel encoding unit 12 encodes the ECC cluster from the ECC processing unit 11 into a multi-level code (cluster multi-level code) of ML values, and supplies it to the frame configuration unit 13, and the process proceeds to step S13.

[0057] In step S13, the frame constructing unit 13 constructs a frame including the sequence of the cluster multi-level code from the channel encoding unit 12, and supplies the frame to the RUB constructing unit 14, and the process proceeds to step S14.

[0058] The frame configuration unit 13 divides the sequence of the cluster multi-level code from the channel encoding unit 12 into DC control units, and performs DC control by adding a DCC cell to (the sequence of) the cluster multi-level code in the DC control unit.

[0059] Then, the frame constructing unit 13 constructs a frame by adding an FS to the cluster multi-level codes of a plurality of DC control units after the DC control.

[0060] In step S14, the RUB constructor 14 receives frames from the frame constructor 13 and adds an APC SYNC to the necessary frames. Furthermore, the RUB constructor 14 collects the necessary frames and constructs a RUB by adding a Run-in and a Run-out to the collection of frames. The RUB constructor 14 supplies the RUB to the recording / playback system 15, and the process proceeds from step S14 to step S15.

[0061] In step S15, the recording / reproducing system 15 records the RUB on the optical disc 16 by irradiating the optical disc 16 with laser light in accordance with the RUB from the RUB constructing unit 14.

[0062] Similar processing is performed thereafter, so that user data is recorded in units of RUB onto the optical disc 16. That is, recording onto the optical disc 16 is performed using RUBs as recording units.

[0063] <Recycling process>

[0064] FIG. 3 is a flowchart illustrating an example of a playback process in which the recording / playback device of FIG. 1 plays back user data recorded on the optical disc 16. In FIG.

[0065] In step S21, the recording / reproducing system 15 irradiates the optical disc 16 with a laser beam to reproduce a reproduction signal corresponding to the RUB recorded on the optical disc 16, and supplies the reproduction signal to the signal processing unit 17, and the process proceeds to step S22.

[0066] In step S22, the signal processing unit 17 processes the reproduced signal from the recording / reproducing system 15.

[0067] In the signal processing of the reproduced signal, equalization of the reproduced signal and restoration of the sequence of multilevel codes as RUB are performed.

[0068] The sequence of multilevel codes obtained by signal processing of the reproduced signal is supplied from the signal processing unit 17 to the sync detection unit 18 and frame detection unit 19, and the process proceeds from step S22 to step S23.

[0069] In step S23, the sync detection unit 18 detects Run-in, FS, and APC SYNC as specific patterns from the sequence of multilevel codes from the signal processing unit 17, and supplies them to the frame detection unit 19, and the process proceeds to step S24.

[0070] In step S24, the frame detection unit 19 detects frames from the sequence of multi-level codes from the signal processing unit 17 in accordance with the specific pattern from the sync detection unit 18, and supplies them to the DCC removal unit 20, and the process proceeds to step S25.

[0071] In step S25, the DCC deletion unit 20 deletes the DCC cell from the frame from the frame detection unit 19. The DCC deletion unit 20 supplies the cluster multi-level code obtained by deleting the DCC cell from the frame to the channel decoding unit 21, and the process proceeds from step S25 to step S26.

[0072] In step S26, the channel decoding unit 21 decodes (channel decodes) the cluster multi-level code from the DCC removing unit 20 into an ECC cluster, which is a sequence of binary data, and supplies it to the ECC processing unit 22, and the process proceeds to step S27.

[0073] In step S27, the ECC processing unit 22 performs ECC processing on the ECC target data included in the ECC cluster from the channel decoding unit 21. The ECC processing unit 22 outputs the user data included in the ECC target data after the ECC processing.

[0074] Thereafter, the same process is carried out to reproduce user data from the optical disc 16 in units of RUB.

[0075] <Configuration example of the channel encoding unit 12>

[0076] FIG. 4 is a block diagram showing an example of the configuration of the channel encoding unit 12 in FIG.

[0077] 4, the channel coding unit 12 includes an LUT (Look Up Table) storage unit 51 and a code generation unit 52.

[0078] The LUT storage unit 51 stores a code LUT in which a block code composed of a series of multi-value edge codes generated by a code generation model described later is registered in association with binary data to be encoded into the multi-value edge code.

[0079] The code generation unit 52 receives an ECC cluster of binary data from the ECC processing unit 11. The code generation unit 52 refers to the code LUT stored in the LUT storage unit 51 and encodes the ECC cluster from the frame configuration unit 13.

[0080] That is, the code generation unit 52 encodes the ECC cluster of binary data by converting it into a block code consisting of a series of multi-value edge codes associated with the binary data of a predetermined number of bits in the code LUT.

[0081] The code generator 52 then supplies the block code obtained by the encoding, that is, the sequence of multi-level edge codes, to the frame constructor 13.

[0082] <Configuration example of signal processing unit 17>

[0083] FIG. 5 is a block diagram showing an example of the configuration of the signal processing unit 17 in FIG.

[0084] In FIG. 5, the signal processing unit 17 includes an ADC (Analog to Digital Converter) 31, a PLL (Phase Locked Loop) 32, a memory 33, an adaptive equalization unit 34, a restoration unit 35, a convolution unit 36, an error calculation unit 37, an HPF (High Pass Filter) 41, and an AGC (Auto Gain Controller) 42.

[0085] A playback signal is supplied to the ADC 31 from the recording and playback system 15. The ADC 31 performs AD conversion of the analog playback signal from the recording and playback system 15 in synchronization with a channel clock supplied from the PLL 32, and outputs a digital playback signal obtained as a result. The playback signal output by the ADC 31 is supplied to the PLL 32 and memory 33 via the HPF 41 and AGC 42.

[0086] The PLL 32 generates a channel clock that is synchronized with the playback signal supplied from the ADC 31 via the HPF 41 and AGC 42, and supplies it to the ADC 31 and other necessary blocks that make up the recording and playback device.

[0087] The memory 33 temporarily stores the playback signal supplied from the ADC 31 via the HPF 41 and AGC 42 .

[0088] The adaptive equalization unit 34 adaptively equalizes the reproduction signal stored in the memory 33, and supplies an equalized signal y obtained by equalizing the reproduction signal, such as a PR signal obtained from a desired PR (Partial Response) channel, to the restoration unit 35 and the error calculation unit 37.

[0089] Here, the error e of the equalized signal y is supplied to the adaptive equalizer 34 from the error calculator 37. The equalization of the reproduced signal in the adaptive equalizer 34 is adaptively performed so as to reduce the error e from the error calculator 37.

[0090] The restoration unit 35 performs maximum likelihood decoding such as Viterbi decoding on the equalized signal y from the adaptive equalization unit 34 to restore a multilevel code sequence, which is a channel code, from the equalized signal y, and supplies the restored sequence to the sync detection unit 18 and frame detection unit 19, as well as to the convolution unit 36.

[0091] The restoration of the multilevel code in the restoration unit 35 can be performed by a method other than maximum likelihood decoding, that is, for example, threshold processing.

[0092] The convolution unit 36 generates a target signal for the equalization signal y, which is the equalization result of the adaptive equalization unit 34, by convolving the sequence of multi-valued codes from the restoration unit 35 with the impulse response of a desired PR channel, and supplies it to the error calculation unit 37.

[0093] The error calculation unit 37 calculates an error e of the equalization signal y from the adaptive equalization unit 34 with respect to the target signal from the convolution unit 36, and supplies it to the adaptive equalization unit 34.

[0094] Here, for example, the Run-in etc. included in the RUB recorded on the optical disk 16 are known patterns. The target signal of the equalization signal y obtained by equalizing the reproduction signal of such a known pattern can be obtained, for example, by convolution of the restoration result restored from the equalization signal y and the impulse response of a desired PR channel. Also, the target signal of the equalization signal y obtained by equalizing the reproduction signal of a known pattern can be obtained, for example, by convolution of the known pattern and the impulse response of a desired PR channel.

[0095] The HPF 41 cuts the DC (Direct Current) component of the reproduction signal output by the ADC 31 by filtering the reproduction signal, and supplies it to the AGC 42.

[0096] The AGC 42 performs AGC (Auto Gain Control) processing to adjust the gain of the reproduction signal from the HPF 41, and supplies it to the PLL 32 and the memory 33.

[0097] <Method of expressing multi-valued codes>

[0098] FIG. 6 is a diagram for explaining a method of expressing multi-valued codes.

[0099] Here, let 3 = one (value) of the multi-valued codes of the <ML value> be called a cell. n cells are n arrangements of multi-valued codes. The code length of the multi-valued code is represented by cells.

[0100] The ML multilevel code can be expressed by an ML multilevel code, a multilevel edge code, or an NRZ (non-return-to-zero) code.

[0101] A multilevel code is a code that expresses a multilevel code by a value (level), and is hereinafter also referred to as a level code. An ML-level multilevel code takes values ​​0, 1, 2, ..., ML-1.

[0102] Here, inversion (level inversion) of the ML multilevel code means converting the level code to a value that is symmetrical with respect to the intermediate value between 0 and ML-1. Therefore, the level code L'(t) after inversion of the level code L(t) at time t (tth) is expressed by the formula L'(t) = ML-1 - L(t).

[0103] A multi-level edge code is a code that expresses a multi-level code using edges, and is hereinafter also referred to as an edge code.

[0104] An edge represents the amount of change from the previous value of the multi-level code, and is counted so as to rotate between 0 and ML-1, which the multi-level code of the ML value takes.

[0105] For example, if two consecutive cells in a multilevel code with ML=5 are 00, the change from the 0 in the first cell to the 0 in the second cell is 0, so the edge between the two cells is 0.

[0106] For example, if two consecutive cells in a multilevel code with ML=5 are 01, the change from 0 in the first cell to 1 in the second cell is 1, so the edge between the two cells is 1.

[0107] For example, if two consecutive cells in a multilevel code with ML=5 are 13, the change from 1 in the first cell to 3 in the second cell is 2, so the edge between the two cells is 2.

[0108] For example, if the value of two consecutive cells in a multilevel code with ML=5 is 32, the change from 3 in the first cell to 2 in the second cell is 4 when counted by rotating from 0 to 4=ML-1, so the edge between the two cells is 4.

[0109] Therefore, for example, the edge code expressing the level code 00113322... for ML=5 is *0102040.... * is a value determined by the value immediately before the leading 0 in the level code 00113322....

[0110] The level code L(t) at time t and the edge code c(t) at time t satisfy the equation L(t) = (L(t-1) + c(t)) ML, where % represents the modulo operator, and A B represents the remainder when A is divided by B.

[0111] The channel encoding unit 12 (FIG. 1) encodes the ECC cluster (including user data) from the ECC processing unit 11 into an edge code that expresses a multilevel code as described above, and supplies the edge code to the frame configuration unit 13.

[0112] The frame constructor 13 constructs a frame by adding DCC cells while converting the edge code from the channel encoder 12 into a level code. The conversion from the edge code c(t) to the level code L(t) is performed according to the above-mentioned formula L(t) = (L(t-1) + c(t)) % ML.

[0113] NRZ codes are codes that express multi-level codes (level codes) with values ​​centered around 0. The NRZ code N(t) at time t is expressed using the level code L(t) as the equation N(t) = L(t) * 2 - (ML-1). The NRZ codes for ML = 5 level codes 0, 1, 2, 3, and 4 are -4, -2, 0, +2, and +4, respectively.

[0114] <Code generation model>

[0115] FIG. 7 is a diagram showing a code generation model for generating edge codes (multilevel codes expressed by edge codes) to be registered in the code LUT of the LUT storage unit 51 (FIG. 4).

[0116] The code generation model has states that represent the number of consecutive zeros, equal to the number of consecutive zeros on the 0 edge. Therefore, if the maximum number of consecutive zeros is represented by k, the code generation model has a total of k+1 states, including state s0, state s1, ..., state s#k. State s#i is the state that represents the number of consecutive zeros being i.

[0117] In the code generation model, when 0 is output as the edge code, the state transitions to state s#k', which represents the number of consecutive zeros k' (<=k) including the 0, where the edge is 0. In addition, in the code generation model, when either 1 or ML-1 is output as the edge code, the state transitions to state s0, which represents the number of consecutive zeros being 0. In state s#k, which represents the maximum number of consecutive zeros being k, only one of 1 or ML-1 other than 0 can be output as the edge code, and after either edge code 1 or ML-1 is output, the state transitions to state s0.

[0118] The edge code registered in the code LUT can be generated by the state transition of the code generation model described above.

[0119] Generally, for a channel code (recording modulation code), it is necessary to ensure the frequency of obtaining information for detecting phase errors in a PLL that generates a channel clock. In other words, it is necessary to ensure the frequency of transitions (changes) in the value of the channel code. For this reason, the maximum number of consecutive occurrences of the same value is limited, which is called k-limitation.

[0120] For example, a code generation model in which the maximum number of consecutive zeros k is limited to 1 is composed of a state s0 representing that the number of consecutive zeros is 0 and a state s1 representing that the number of consecutive zeros is 1.

[0121] When in state s0, any of 0 to ML-1 can be output as the edge code. When 0 is output as the edge code in state s0, a state transition occurs from state s0 to state s1, and when either 1 or ML-1 is output as the edge code, a state transition occurs from state s0 to state s0.

[0122] When in state s1, the edge code cannot be 0, but can be any of 1 to ML-1 other than 0. In state s1, any of 1 to ML-1 is output as the edge code, and a state transition occurs from state s1 to state s0.

[0123] Hereinafter, a multi-level code (edge ​​code) generated by a code generation model will be described using a multi-level code with ML=5 as an example.

[0124] The details of the generation of the multi-level code using the code generation model are described in Patent Document 1.

[0125] In encoding to a multi-level code (multi-level encoding), for example, binary data of a certain number of bits is converted into a (series of) multi-level code, which is a sequence of cells with values ​​greater than or equal to 1. Therefore, the coding rate for encoding to a multi-level code is expressed in units of bits / cell.

[0126] The coding efficiency of a multilevel code is defined as the ratio of the coding rate to the theoretical limit coding rate of the multilevel code when the maximum number of consecutive occurrences k=∞.

[0127] The theoretical limit coding rate of a multilevel code is the theoretical limit coding rate of the multilevel code, i.e., the maximum number of binary data bits that can theoretically be assigned to one cell of the multilevel code. For a multilevel code with ML=5 when the maximum number of consecutive occurrences is k=1, the theoretical limit coding rate can be calculated as (approximately) 2.271553 = log24.828427 bits by taking log2 of the Shannon capacity of the multilevel code with ML=5, 4.828427.

[0128] According to the present inventors, it has been confirmed that for a multilevel code with ML=5, when the maximum number of consecutive occurrences k is 2 or more, the coding rate rapidly approaches the theoretical limit coding rate, and the coding efficiency becomes 99% or more.

[0129] Now, as the encoding method for multi-level encoding in the channel encoding unit 12, for example, a method is adopted in which m-bit binary data is converted into a fixed-length (n-cell) block code (a sequence of edge codes representing) consisting of a sequence of n-cell multi-level codes.

[0130] Among fixed-length block codes formed by a sequence of n-cell multilevel codes, a block code formed by (an edge code representing) a multilevel code with k=4 and ML=5 will be described below. The multilevel code with k=4 and ML=5 is a multilevel code (represented by an edge code) with ML=5 when the maximum number of consecutive occurrences is k=4.

[0131] According to the inventors of the present invention, among block codes consisting of (edge ​​codes representing) multilevel codes with k=4 and ML=5, a block code with a code length n of 4 cells has been confirmed to be a highly efficient block code with a coding efficiency of 97%.

[0132] In a block code consisting of a multi-level code with a code length n of 4 cells, k=4, and ML=5, 9-bit binary data is encoded into a block code consisting of a multi-level code with 4 cells. Here, the block code consisting of a multi-level code with a code length n of 4 cells, k=4, and ML=5, into which 9-bit binary data is encoded as described above, is also referred to as a 9-bit / 4-cell code with k=4 and ML=5.

[0133] The edge code (sequence) (representing a multilevel code) constituting the 9-bit / 4-cell code with k=4 and ML=5 can be generated by starting from a certain state as the initial state and performing four state transitions in the code generation model with k=4 and ML=5.

[0134] In optical recording, the read gain in the high frequency range is low, so the RMTR (Repeated Minimum Transition Run) is limited. By limiting the RMTR, the high frequency components of the read signal can be suppressed. For example, in the 17PP code and PCWA110 code, which are binary channel codes (two-valued codes), the RMTR is limited to 6 and 2, respectively.

[0135] RMTR refers to the number of repetitions of a minimum transition pattern, which is a pattern with a minimum period when the same value (level) change is repeated at the minimum period. For example, in an edge code (or a block code composed of) ML=5, if 41 is repeated, the minimum transition pattern is 41 or 14, and if 23 is repeated, the minimum transition pattern is 23 or 32.

[0136] For an edge code c(t), the run length for which the equation c(t) + c(t+1) = ML is satisfied is the RMTR. For a level code L(t), the run length for which the equations L(t) != L(t+1) and L(t) = L(t+2) are satisfied is the RMTR. A != B means that A and B are not equal.

[0137] 8, 9, 10, 11, 12, and 13 are diagrams showing examples of code LUTs in which 512 block codes are registered as 9-bit / 4-cell codes with k=4 and ML=5.

[0138] In the code LUT, block codes (edge ​​codes of four cells constituting the block codes) and binary data are registered in association with each other. In Figs. 8 to 13, 9-bit binary data is shown in decimal notation. According to the code LUTs in Figs. 8 to 13, for example, binary data 0 (here, zero expressed in 9 bits) is coded as 1111 (edge ​​codes of four cells constituting the block codes).

[0139] The RMTR of the block codes registered in the code LUTs shown in Figures 8 to 13 is limited to 3 (or less). Also, the sequence of multilevel codes (edge ​​codes) obtained by channel coding according to the code LUTs shown in Figures 8 to 13 is a (0, 4) RLL code with ML=5 values.

[0140] Note that the (d, k) RLL code of the ML value is an edge code, which is a multi-level code of the ML value with a minimum run of d and a maximum run of k. Therefore, in the level code, the (d, k) RLL code of the ML value is a multi-level code of the ML value with a minimum run of d+1 and a maximum run of k+1. For example, the (0, 4) RLL code of the ML value = 5 is a 5-level code with a minimum run of 1 and a maximum run of 5.

[0141] It should be noted that the multi-level code (or the block code configured therewith) used in the recording and reproducing device is not limited to the multi-level code shown in Figures 8 to 13. That is, the recording and reproducing device can use a 5-level multi-level code generated using a code generation model other than the multi-level codes shown in Figures 8 to 13. Furthermore, the recording and reproducing device can use a 3-level multi-level code, a 4-level multi-level code, or a 6-level or higher multi-level code generated using a code generation model.

[0142] <ECCクラスタ>

[0143] FIG. 14 is a diagram illustrating an example of an ECC cluster configured by the ECC processing unit 11 of FIG.

[0144] The ECC processing unit 11 constructs ECC target data including, for example, 256 kB (kilo Byte) of user data, and constructs an ECC cluster including the ECC target data.

[0145] The ECC processing unit 11 scrambles 256 kB of user data, including an EDC (Error Detection Code), and adds control data including the RUB address and padding to the scrambled result, thereby constructing 262,740 B (Byte) of data as ECC target data.

[0146] Here, the ECC processing unit 11 configures 128 (=256kB / 2kB) sectors from 256kB of user data, with 2048B (=2kB) of user data as one sector.

[0147] The ECC target data consists of one 80B (byte) control data placed at the beginning, 128 2048B sectors placed after the control data, 4B EDC placed immediately after each sector, and 4B padding placed at the end.

[0148] 14, numbers in parentheses indicate the number of bytes, and numbers without parentheses indicate the number of symbols. Here, in ECC processing, one symbol is 10 bits.

[0149] The ECC processing unit 11 generates ECC target data of 232 symbols horizontally and 906 symbols vertically. As described above, the 232 symbols ECC target data is 262,740 B = 232 symbols × 10 bits × 906 rows / 8 bits of data.

[0150] The ECC processing unit 11, for example, adds 4-symbol parity (PI (Parity Inner)) to each row of the 232 x 906 symbol ECC target data, and adds 88-symbol parity (PO (Parity Outer)) to each column, thereby forming an ECC cluster of 236 x 994 symbols. The ECC cluster formed by the ECC processing unit 11 is a product code of PO[994,906] x PI[236,232] of 10-bit symbols (Galois field of 2^10).

[0151] The symbol sequence of one row of an ECC cluster is 2,360 dbits (data bits) = 236 symbols × 10 bits of data. If we call this 2,360 dbits of data in one row row data, the ECC cluster is divided into rows of data. Furthermore, a data sequence in which each row data is arranged horizontally constitutes a frame, and a RUB containing the frame is constructed. The RUB is then recorded in the track direction on the optical disc 16.

[0152] An ECC cluster can be constructed by adding 4 symbols of parity (PI) to each row of the 232 x 906 symbols of ECC target data and 76 symbols of parity (PO) to each column, resulting in an ECC cluster of 236 x 982 symbols.

[0153] Whether to configure an ECC cluster of 236×994 symbols or an ECC cluster of 236×982 symbols can be selected (set) according to the stored values ​​of the register group 23A.

[0154] <frame>

[0155] FIG. 15 is a diagram illustrating an example of a frame configured by the frame configuration unit 13 in FIG.

[0156] The frame configuration unit 13 is supplied with a cluster multi-level code (series) obtained by channel encoding (multi-level encoding) the ECC cluster according to, for example, the code LUTs shown in Figures 8 to 13 from the channel encoding unit 12.

[0157] That is, in the channel encoding unit 12, a data sequence in which row data of an ECC cluster is arranged horizontally (in one row) is encoded into a block code as a 9-bit / 4-cell code with k=4 and ML=5 in accordance with the code LUT shown in Figures 8 to 13. This block code sequence is supplied from the channel encoding unit 12 to the frame configuration unit 13 as a cluster multi-level code sequence.

[0158] The cluster multi-level code supplied from the channel coding unit 12 to the frame configuration unit 13 is an edge code. The frame configuration unit 13 converts the edge code as the cluster multi-level code into a level code, and configures a frame including the level code while performing DC control.

[0159] The frame configuration unit 13 arranges the sequence of level codes as cluster multi-level codes in a frame for each DC control unit for performing DC control, for example, 240 cells. The sequence of level codes of 240 cells as the DC control unit is also called a code sequence, and the i-th code sequence from the beginning of the frame is also referred to as a code sequence Code#i.

[0160] The frame constructing section 13 places a 20-cell FS at the beginning of the frame, and then places 16 code sequences, Code#1, Code#2, ..., Code#16, after the FS.

[0161] When arranging each code sequence Code#i, DC control is performed by adding a multilevel code (ML=5) to the beginning of the code sequence Code#i as a DCC cell of one cell that minimizes the absolute value of the DSV (Digital Sum Value) from the beginning of the frame to the end of the code sequence Code#i. This DC control reduces the DC component of the frame.

[0162] The DSV is an integrated value of the NRZ code taken for a multilevel code sequence, and serves as an index of the DC component contained in the multilevel code sequence from which the integrated value is taken.

[0163] If the DSV of the multilevel codes from the beginning of the sequence to the kth (cell) multilevel code is represented as DSV(K) and the NRZ code of the i-th multilevel code is represented as N(i), then DSV(K) can be calculated, for example, according to the formula DSV(K)=ΣN(i), where Σ represents the summation obtained by changing i from 1 to K.

[0164] The frame configuration section 13 adds a DCC cell that minimizes the absolute value of the DSV from the beginning of the frame to the end of the code sequence Code#1, which is placed immediately after the FS.

[0165] Then, immediately after the FS, the frame constructor 13 places a code sequence Code#1, to the beginning of which is added a DCC cell that minimizes the DSV.

[0166] Thereafter, the frame configuration section 13 adds to the beginning of the code sequence Code#2 a DCC cell that minimizes the absolute value of the DSV from the beginning of the frame to the end of the code sequence Code#2.

[0167] Then, the frame configuration section 13 places the code sequence Code#2, to which a DCC cell that minimizes the DSV is added at the beginning, immediately after the code sequence Code#1.

[0168] Similarly, the frame constructing unit 13 arranges code sequences Code#3 to Code#16, each with a DCC cell added at the beginning, to construct a frame.

[0169] Therefore, a frame is composed of one FS, 16 code sequences Code#1 through Code#16, and 16 DCC cells. The FS, code sequence Code#i, and DCC cells are composed of 20 cells, 240 cells, and 1 cell, respectively, so the frame is composed of 3876 (=20+16×240+16×1) cells. The portion of the frame excluding the FS is composed of 3856 (=3876−20) cells.

[0170] The DSV of the FS is 0. Therefore, the DSV from the beginning of the frame to the end of the code sequence Code#i can be calculated by calculating the DSV from immediately after the FS to the end of the code sequence Code#i.

[0171] <fs>

[0172] FIG. 16 is a diagram showing an example of the FS in FIG.

[0173] FIG. 16 shows an example of level codes as FS of 20 cells when the 9-bit / 4-cell code with k=4 and ML=5 shown in FIGS. 8 to 13 is used for channel coding.

[0174] FS has a + pattern and a - pattern. The + pattern and the - pattern are in a level inversion relationship.

[0175] The FS has a pattern in which level codes 0 and 4 each have eight consecutive cells. Therefore, the FS is a 9-bit / 4-cell code with k=4 and ML=5 shown in Figures 8 to 13 used for channel coding of user data, i.e., a specific pattern of ML=5 values ​​that repeats runs greater than 5, which is the maximum run in the level code of a (0,4) RLL code with ML=5. This makes it easier to distinguish and detect the FS from user data, and enables correct reproduction of multilevel codes recorded at high density.

[0176] In the 9-bit / 4-cell code with k=4 and ML=5 shown in FIGS. 8 to 13, TR (Transition Run) is 1 or less.

[0177] TR indicates the length of a sequence of same level codes sandwiched between different level codes.

[0178] For example, in the level code sequence ...2311030, at the end 030, there is only one occurrence of another level code 3 being sandwiched between the same level code 0. Therefore, TR=1.

[0179] For example, in the level code sequence ...23410303, at the end 0303, there is a sequence of the same level code 0 followed by another level code 3, and there is also a sequence of the same level code 3 followed by another level code 0. Therefore, TR=2.

[0180] As the FS that constitutes the frame, a pattern that reduces the TR is selected from the + pattern and the - pattern.

[0181] For example, in a frame placed after a sequence of multilevel codes with TR=1, . . . 030, at the end, a -pattern FS with a smaller TR is selected as follows:

[0182] That is, when a + pattern FS is placed after a multilevel code sequence ...030, the multilevel code sequence of the concatenated portion becomes ...030 34444..., the concatenated portion becomes 0303, and TR=2.

[0183] On the other hand, when a minus pattern FS is placed after the multilevel code sequence ...030, the multilevel code sequence of the concatenated portion becomes ...030 10000..., the concatenated portion becomes 030, and TR=1.

[0184] Therefore, since the FS of the - pattern reduces the TR more than the FS of the + pattern, the FS of the - pattern is selected.

[0185] The 9-bit / 4-cell code (edge ​​code) with k=4 and ML=5 shown in FIGS. 8 to 13 is a multilevel code sequence with a TR of 1 or less in level code.

[0186] In addition, in the multilevel code sequence as a frame configured by arranging the FSs in Figure 16, the RMTR limit (RMTR = 3) is observed, just like the 9-bit / 4-cell code with k = 4 and ML = 5 shown in Figures 8 to 13.

[0187] <rub>

[0188] FIG. 17 is a diagram illustrating an example of a RUB configured by the RUB configuration unit 14 in FIG.

[0189] The RUB construction unit 14 constructs a frame cluster from a plurality of frames supplied from the frame construction unit 13 and an APC SYNC, and constructs a RUB by adding Run-in and Run-out to the beginning and end of the frame cluster, respectively.

[0190] The RUB constructor 14 acquires from the frame constructor 13 272 frames to be included in one RUB as frames that constitute a frame cluster.

[0191] Of the 272 frames included in the RUB, the first to 271st frames are made up of 3876 cells as shown in FIG. 15, but the last frame, the 272nd frame, is made up of 1985 cells.

[0192] In the first to 271st frames, as shown in FIG. 15, a 20-cell FS is placed at the beginning, followed by 16 sets of one DCC cell and 240 code sequences.

[0193] On the other hand, in the 272nd frame, a 20-cell FS is placed at the beginning, followed by eight sets of one DCC cell and a 240-cell code sequence, and then one set of one DCC cell and a 36-cell code sequence.

[0194] As described above, the 272nd frame is composed of one 20-cell FS, nine 1-cell DCC cells, eight 240-cell code sequences, and one 36-cell code sequence, for a total of 1985 (=20+8×1+8×240+1×1+1×36) cells. The portion of the 272nd frame excluding the FS is composed of 1965 (=1985-20) cells.

[0195] The frame constructor 13 constructs 272 frames to be included in one RUB, namely, 271 frames of 3876 cells and one frame of 1985 cells.

[0196] The RUB constructing unit 14 constructs a frame cluster by adding three APC SYNCs of 520 cells to a collection of 272 frames included in one RUB.

[0197] Three APC SYNCs are added to a group of 272 frames included in one RUB so that they are spaced at approximately equal intervals.

[0198] For example, three APC SYNCs are added to the end of the 68th, 136th, and 204th frames (the beginning of the 69th, 137th, and 205th frames) of the 272 frames included in one RUB.

[0199] By arranging the APC SYNCs at approximately equal intervals, the timing for timing recovery and the like can be made uniform in the frame cluster.

[0200] The RUB constructing unit 14 constructs a RUB by adding a Run-in of 4360 cells to the beginning of the frame cluster and adding a Run-out of 259 cells to the end of the frame cluster.

[0201] <run-in>

[0202] FIG. 18 is a diagram illustrating an example of the configuration of the Run-in in FIG.

[0203] That is, FIG. 18 shows an example of Run-in recorded on two adjacent tracks on the optical disc 16.

[0204] FIG. 18 shows a Run-in recorded in a land L and a Run-in recorded in a groove G on either the inner or outer circumferential side of the land L.

[0205] In the optical disc 16, a land L is paired with at least one groove G on the inner or outer circumferential side of the land L. Run-ins (and hence RUBs) are recorded in the paired land L and groove G, aligned at the same position in the track direction. Figure 18 shows the run-ins of the paired land L and groove G.

[0206] As described in Figure 17, Run-in is a pattern of 4360 cells, and is composed of, from the beginning, PLL / LMS training, which is a 4000-cell ML=5 value pattern, and RUB SYNC, which is a 360-cell ML=5 value pattern.

[0207] PLL / LMS training is used, for example, for XTC (Cross Talk Cancel) learning, gain recovery (gain adjustment in AGC 42 (FIG. 5)), PLL 32 (FIG. 5) pull-in, and timing recovery (channel clock adjustment in PLL 32).

[0208] XTC is a process for canceling crosstalk components in a reproduced signal by adaptive equalization of the reproduced signal performed by the adaptive equalizer 34 (FIG. 5).

[0209] XTC is performed, for example, by filtering the playback signal with an FIR (Finite Impulse Response) filter. XTC learning refers to learning of the tap coefficients of the FIR filter used in XTC, and the tap coefficients are adaptively adjusted so as to reduce the error e of the equalized signal y output by the error calculation unit 37.

[0210] In XTC learning, the tap coefficients are adjusted so as to reduce the squared error of the equalized signal y relative to the target signal. Therefore, XTC learning is LMS (Least Mean Square) learning.

[0211] The PLL / LMS training for the group G is configured by arranging, from the beginning, GAptn, a 2000 cell ML=5 value pattern, and GBptn, a 2000 cell ML=5 value pattern. The PLL / LMS training for the land L is configured by arranging, from the beginning, LAptn, a 2000 cell ML=5 value pattern, and LBptn, a 2000 cell ML=5 value pattern.

[0212] GAptn can be configured by arranging, for example, 20 G-100CELLs, which are 100-cell ML=5 value patterns. GBptn can be configured by arranging, for example, 20 G-100CELLs, similar to GAptn. In this case, GAptn and GBptn have the same pattern.

[0213] It should be noted that different patterns can be adopted for GAptn and GBptn.

[0214] LAptn can be configured by arranging, for example, 20 L-100CELLs, which are 100-cell ML=5 value patterns. LBptn can be configured by arranging, for example, 20 L-100CELLs, just like LAptn. In this case, LAptn and LBptn have the same pattern.

[0215] It should be noted that different patterns can be adopted for LAptn and LBptn.

[0216] For the G-100CELL that constitutes GAptn and GBptn, and the L-100CELL that constitutes LAptn and LBptn, a pattern can be adopted in which the magnitude of the cross-correlation value calculated using NRZ code is a value below a threshold, for example, 0.

[0217] The cross-correlation value XC(K) of the sequences A and B of the multilevel codes of two ML values ​​represents the correlation between the sequences A and B of the multilevel codes.

[0218] The i-th NRZ codes of multilevel code sequences A and B, each with a length (number of cells) of K, are represented as NA(i) and NB(i), respectively. The cross-correlation value XC(K) of multilevel code sequences A and B can be calculated, for example, according to the formula XC(K) = Σ(NA(i) × NB(i)). Σ represents the summation obtained by changing i from 1 to K.

[0219] By adopting a pattern in which the magnitude of the cross-correlation value is 0 as the G-100CELL and L-100CELL, the magnitude of the cross-correlation value between the entire PLL / LMS training of the adjacent groove G and land L also becomes 0.

[0220] This makes it possible to detect PLL / LMS training while suppressing the effects of crosstalk.

[0221] For G-100CELL and L-100CELL, it is also possible to adopt a pattern in which the magnitude of each DSV is equal to or less than a threshold value, for example, 0.

[0222] By adopting a pattern in which the magnitude of each DSV becomes 0 for G-100CELL and L-100CELL, the magnitude of the DSV for the entire PLL / LMS training also becomes 0.

[0223] This allows the DC component to be suppressed and the PLL / LMS training to be detected.

[0224] In addition, for the first 200 cells of GAptn, which are surrounded by a dotted line in Fig. 18, an APC pattern for APC can be placed instead of a G-100 CELL. Whether to place a G-100 CELL or an APC pattern in the first 200 cells of GAptn can be selected, for example, for each RUB. Similarly, for the first 200 cells of LAptn, an APC pattern can be selectively placed instead of an L-100 CELL.

[0225] The RUB SYNC is used to detect the FS of the frame in the RUB containing the RUB SYNC.

[0226] The RUB SYNC of groove G is composed of, from the beginning, SY0 of 40 cells, NC0 of 40 cells, SY0, a 4-cell pattern of 4 cells, NC0, a 2-2 cell pattern of 4 cells, SY0, a 4-cell pattern, a 2-2 cell pattern, NC0, a 4-cell pattern, a 2-2 cell pattern, SY0, a 4-cell pattern, a 2-2 cell pattern, a 4-cell pattern, NC0, and a 4-cell pattern.

[0227] SY0, NC0, the 4-cell pattern, and the 2-2-cell pattern are all patterns with ML=5 values.

[0228] The RUB SYNC of land L is composed of, from the beginning, NC0, SY0, NC0, 2-2 cell pattern, SY0, 4 cell pattern, NC0, 2-2 pattern, 4 cell pattern, SY0, 2-2 cell pattern, 4 cell pattern, NC0, 2-2 cell pattern, 4 cell pattern, 2-2 cell pattern, SY0, and 2-2 cell pattern.

[0229] SY0, NC0, the 4-cell pattern, and the 2-2-cell pattern have a + pattern and a - pattern, similar to the FS described with reference to FIG.

[0230] In Figure 18, SY0, NC0, 4-cell pattern, and 2-2 cell pattern with + at the top are + patterns. SY0, NC0, 4-cell pattern, and 2-2 cell pattern with - at the top are - patterns. SY0 and NC0 without either + or - at the top are + patterns.

[0231] As the RUB SYNC for the groove G and the land L, a pattern in which the magnitude of the cross-correlation value is equal to or less than a threshold value, for example, 0, can be adopted.

[0232] This makes it possible to suppress the influence of crosstalk and detect RUB SYNC (SY0 and the like that constitute it).

[0233] Furthermore, as the RUB SYNC for the groove G and the land L, a pattern in which the magnitude of the DSV is a value equal to or less than a threshold value, for example, 0, can be adopted.

[0234] This makes it possible to suppress the DC component and detect RUB SYNC (SY0 and the like that constitute it).

[0235] Since the DSVs for PLL / LMS training and RUB SYNC are 0, the DSV for the entire Run-in is also 0.

[0236] FIG. 19 is a diagram showing an example of the configuration of a G-100CELL constituting GAptn and GBptn, and an L-100CELL constituting LAptn and LBptn in FIG.

[0237] A in Fig. 19 shows an example of a level code for 100 cells as G-100CELL, and B in Fig. 19 shows an example of a level code for 100 cells as L-100CELL.

[0238] As explained in Fig. 18, G-100CELL and L-100CELL have patterns in which the cross-correlation value is 0. Furthermore, G-100CELL and L-100CELL each have a pattern in which the magnitude of the DSV is 0.

[0239] FIG. 20 is a diagram illustrating an example of the configuration of SY0 in FIG.

[0240] FIG. 20 shows an example of a level code as SY0 of 40 cells.

[0241] As explained in FIG. 18, SY0 has a + pattern and a - pattern.

[0242] SY0 has a pattern of eight consecutive cells each of level codes 0 and 4. Therefore, SY0 is a 9-bit / 4-cell code with k=4 and ML=5 shown in Figures 8 to 13 used for channel coding of user data, that is, a pattern of ML=5 values ​​that repeats a run greater than 5, which is the maximum run in the level code of the (0,4) RLL code with ML=5 value.

[0243] The RUB SYNC including SY0, and ultimately the Run-in, also have a specific pattern of ML=5 values ​​that repeats runs greater than 5, which is the maximum run in the level code of the (0,4) RLL code of ML=5 values ​​used for channel coding of user data. This makes it easier to distinguish and detect the RUB SYNC (SY0 that constitutes it) from user data, and enables correct reproduction of multilevel codes recorded at high density.

[0244] FIG. 21 is a diagram illustrating an example of the configuration of NC0 in FIG.

[0245] FIG. 21 shows an example of a level code as NC0 of 40 cells.

[0246] As explained in FIG. 18, NC0 has a + pattern and a - pattern.

[0247] The cross-correlation value (magnitude) between SY0 shown in FIG. 20 and NC0 shown in FIG.

[0248] 18, SY0 and NC0 are arranged at opposing positions (adjacent positions) in the run-ins of the groove G and land L. Therefore, the cross-correlation value is 0 in the SY0 section and the NC0 section of the groove G and land L.

[0249] FIG. 22 is a diagram showing configuration examples of the 4-cell pattern and the 2-2 cell pattern of FIG.

[0250] Figure 22A shows an example of a level code as a 4-cell 4-cell pattern, and Figure 22B shows an example of a level code as a 2-2 pattern of 4 cells.

[0251] As explained in FIG. 18, the 4-cell pattern and the 2-2-cell pattern include a + pattern and a − pattern.

[0252] A 4-cell pattern is a pattern in which four cells contain the same value. A 2-2 cell pattern is a pattern in which two cells contain one value followed by two cells containing a second value that is different from the first value.

[0253] The cross-correlation value between the 4-cell pattern and the 2-2 cell pattern is zero.

[0254] 18, the 4-cell pattern and the 2-2 cell pattern are arranged in opposing positions in the run-ins of the groove G and the land L. Therefore, in the 4-cell pattern section and the 2-2 cell pattern section of the groove G and the land L, the cross-correlation value is 0.

[0255] As described above, the cross-correlation value is 0 in the SY0 and NC0 sections of the groove G and land L, and also in the 4-cell pattern section and the 2-2 cell pattern section.

[0256] As a result, as explained in FIG. 18, the cross-correlation value between the RUB SYNCs of the groove G and the land L becomes zero.

[0257] <APC SYNC>

[0258] FIG. 23 is a diagram showing an example of the configuration of the APC SYNC in FIG.

[0259] That is, FIG. 23 shows an example of APC SYNC recorded in a groove G and a land L as two adjacent tracks on the optical disc 16.

[0260] The APC SYNC of the groove G is composed of eight 40-cell patterns, from the beginning: NC1, SY0, a 4-cell pattern, a 2-2 cell pattern, a 4-cell pattern, NC0, a 4-cell pattern, a 2-2 cell pattern, a 4-cell pattern, SY0, a 4-cell pattern, a 2-2 cell pattern, a 4-cell pattern, a 2-2 cell pattern, and NC0.

[0261] The APC SYNC of land L is composed of eight 40-cell blocks, starting from the beginning: NC2, NC0, 2-2 cell pattern, 4 cell pattern, 2-2 cell pattern, SY0, 2-2 cell pattern, 4 cell pattern, 2-2 cell pattern, NC0, 2-2 cell pattern, 4 cell pattern, 2-2 cell pattern, 4 cell pattern, and SY0.

[0262] Both NC1 and NC2 are patterns with ML=5 values.

[0263] APC SYNC is a pattern that causes DSV to become 0.

[0264] As explained in FIG. 20, SY0 is a pattern of ML=5 values ​​that repeats runs greater than 5, which is the maximum run in the level code of the ML=5 (0,4) RLL code used for channel coding of user data.

[0265] The APC SYNC including such SY0 also has a specific pattern of ML=5 values ​​that repeats runs greater than 5, which is the maximum run in the level code of the (0,4) RLL code of ML=5 values ​​used for channel coding of user data. This makes it easier to distinguish and detect the APC SYNC (SY0 constituting it) from user data, and enables correct reproduction of multilevel codes recorded at high density.

[0266] 23, an APC pattern for APC can be placed instead of NC1 in 200 cells that are part of the first eight NC1s of the APC SYNC of the groove G. Whether to place NC1 or an APC pattern can be selected, for example, for each APC SYNC or RUB. Similarly, an APC pattern can be selectively placed in 200 cells that are part of the first eight NC2s of the APC SYNC of the land L.

[0267] In addition, in the APC SYNC of the groove G and the land L, SY0 and NC0, whose cross-correlation value is 0, are arranged at opposite positions. Similarly, the 4-cell pattern and the 2-2 cell pattern, whose cross-correlation value is 0, are also arranged at opposite positions.

[0268] Therefore, the cross-correlation value in the section from immediately after the eight NC1s of the APC SYNC of the groove G to the end of the APC SYNC is 0. Similarly, the cross-correlation value in the section from immediately after the eight NC2s of the APC SYNC of the land L to the end of the APC SYNC is 0.

[0269] FIG. 24 is a diagram showing an example of the configuration of NC1 and NC2 in FIG.

[0270] Figure 24A shows an example of a level code as NC1 of 40 cells, and Figure 24B shows an example of a level code as NC2 of 40 cells.

[0271] The cross-correlation value of NC1 and NC2 is 0. In addition, both NC1 and NC2 have a pattern with a DSV of 0.

[0272] As explained in Figure 23, the cross-correlation value of the section from immediately after the eight NC1s of the APC SYNC of the groove G to the end of the APC SYNC, and the cross-correlation value of the section from immediately after the eight NC2s of the APC SYNC of the land L to the end of the APC SYNC, are both 0.

[0273] Since the cross-correlation value between NC1 and NC2 is also 0, the cross-correlation value between the APC SYNC of the groove G and the land L is also 0.

[0274] <run-out>

[0275] FIG. 25 is a diagram illustrating an example of the configuration of Run-out in FIG.

[0276] That is, FIG. 25 shows an example of Run-out recorded in a groove G and a land L as two adjacent tracks on the optical disc 16.

[0277] The Run-out of the groove G and land L is configured by arranging, from the beginning, 60 SY1 cells and 199 PoA cells.

[0278] SY1 is composed of three 20-cell FSs (Fig. 16) arranged side by side.

[0279] The PoA of group G is composed of a 199-cell level code sequence, which is obtained by excluding only the last cell from the 200-cell level code sequence formed by arranging two G-100CELLs, each of which has 100 cells, that make up the GAptn of group G (Figure 18).

[0280] The PoA of Land L is composed of a 199-cell level code sequence, which is obtained by excluding only the last cell from the 200-cell level code sequence, which is formed by arranging two L-100CELLs, each of which has 100 cells, that make up Land L's LAptn (Figure 18).

[0281] The cross-correlation value between the PoA of the groove G and the PoA of the land L is zero.

[0282] If the magnitude of the cross-correlation value between two SY1s is set as a threshold, the magnitude of the cross-correlation value between the run-outs of the groove G and land L is equal to or less than the threshold.

[0283] As described above, by setting the magnitude of the cross-correlation value between the run-outs of the groove G and the land L to a threshold value or less, the influence of crosstalk can be suppressed as much as possible and the run-outs can be detected.

[0284] <Specific examples of frame configuration and DC control of frame configuration unit 13>

[0285] FIG. 26 is a diagram showing a specific example of frame configuration and DC control performed by frame configuration section 13.

[0286] For example, assume that the sequence of row data of an ECC cluster supplied from the ECC processing unit 11 to the channel encoding unit 12 is 0x006 0x199 0x1c5 .... 0x indicates that the value that follows is a hexadecimal number.

[0287] In this embodiment, one symbol is 10 bits, and when the row data sequence 0x006 0x199 0x1c5 . . . is expressed in symbol units, i.e., in 10-bit units, the row data bit sequence becomes 0000000110 0110011001 0111000101 . . .

[0288] The row data is channel-coded in 9-bit units in the channel coding unit 12 according to the code LUT shown in FIGS. 8 to 13 into a 9-bit / 4-cell code with k=4 and ML=5.

[0289] Therefore, when the bit sequence of row data 0000000110 0110011001 0111000101 ... is expressed in 9-bit units, it becomes 000000011 001100110 010111000 ....

[0290] The bit sequence of 9-bit row data, 000000011 001100110 010111000 ..., is expressed in decimal as 3 102 184 ...

[0291] A 9-bit row data sequence 3 102 184 ... is channel-encoded into a 9-bit / 4-cell code with k=4 and ML=5 according to the code LUT shown in Figures 8 to 13. According to the channel encoding, the row data sequence 3 102 184 ... is encoded into an edge code sequence 1211 1343 0134 ... as a cluster multi-level code.

[0292] The channel encoding unit 12 supplies the frame configuration unit 13 with the edge code sequence 1211 1343 0134 . . . as the cluster multi-level code described above.

[0293] The frame configuration unit 13 places a 20-cell FS at the beginning of the frame. The frame configuration unit 13 also converts the edge code as the cluster multi-level code into a level code.

[0294] Then, the frame configuration unit 13 places level codes as cluster multi-level codes, which are 16 code sequences of 240 cells, Code#1, Code#2, . . . , Code#16, after the FS while performing DC control.

[0295] In DC control, when arranging each code sequence Code#i, a multilevel code with ML=5 is added to the beginning of the code sequence Code#i as a DCC cell that minimizes the absolute value of the DSV from the beginning of the frame to the end of the code sequence Code#i.

[0296] The frame configuration unit 13 performs DC control using an internal memory (not shown) of the frame configuration unit 13.

[0297] FIG. 26 shows an example of the contents stored in the built-in memory of the frame configuration unit 13 used for DC control.

[0298] 26, the address ADDR indicates the position in terms of the number of cells, with the address ADDR of the beginning of the frame being 0. The address ADDR of the (i+1)th position (cell) from the beginning of the frame is i.

[0299] Since a 20-cell FS is placed at the beginning of the frame, the DCC cell added to the beginning of the first code sequence Code#1 is placed at address ADDR=20. Then, the code sequence Code#1 is placed in 240 cells starting from address ADDR=21, i.e., addresses ADDR=21 to 260.

[0300] Level LVL#j represents the level code when the DCC cell (value) is j. For example, in the column with address ADDR=21, level LVL0 is 1340. This 1340 indicates that when the DCC cell is 0, the level code of the four cells starting from the cell with address ADDR=21 is 1340.

[0301] The address ADDR indicates the position of the first level code in the sequence of level codes for level LVL#j written in the column of that address ADDR. For example, in the column of address ADDR=257, the level LVL0 is 2220, but the address ADDR=257 indicates the position of 2 in the first cell of 2220. Therefore, the address ADDR of the 0 in the last cell of 2220 is 260.

[0302] DCC#p indicates the p-th DCC cell from the beginning of the frame. In the DCC#p column, level LVL#j indicates the value (level code) j of DCC cell #p.

[0303] The DSV immediately below level LVL#j represents the DSV when the DCC cell is j.

[0304] In DC control, the frame configuration unit 13 writes the five values ​​0, 1, 2, 3, and 4, which are candidates for the DCC cell to be added to the beginning of the first code sequence Code#1, into the rows of levels LVL0, LVL1, LVL2, LVL3, and LVL4 in the column with address ADDR=20 immediately after FS.

[0305] Then, the frame construction unit 13 assumes that the DCC cell added to the beginning of the code sequence Code#1 is j, and converts the 240 cells from the 1st to the 240th cells of the edge code sequence as the cluster multi-level code into level codes as candidates for the code sequence Code#1.

[0306] As a result, for each of the DCC cell candidates 0 to 4 added to the beginning of the code sequence Code#1, a sequence of level codes of 240 cells is obtained as candidates for the code sequence Code#1.

[0307] The frame configuration unit 13 writes the level code sequences of 240 cells as candidates for the code sequence Code#1 for each of the DCC cell candidates 0 to 4 into addresses ADDR=21 to 260 of the rows of levels LVL0 to LVL4, respectively.

[0308] For example, the edge code sequence 1211 1343 0134 ... as the cluster multi-level code described above is converted into a level code sequence 1340 1431 1204 ... for DCC cell candidate 0 (LVL0) and written to addresses ADDR=21 to 260 of the row of level LVL0.

[0309] Specifically, for example, the edge code 1 of the first cell in the edge code sequence 1211 is converted to level code 1, which is counted by rotating by 1 from the previous level code 0, since the previous level code is DCC cell candidate 0.

[0310] The edge code 2 of the second cell in the edge code sequence 1211 is converted to level code 3, which is counted by rotating by 2 from level code 1 obtained in the previous conversion, since the previous level code is level code 1 obtained in the previous conversion.

[0311] The edge code 1 of the third cell in the edge code sequence 1211 is converted to level code 4, which is counted by rotating by 1 from level code 3, since the previous level code is level code 3 obtained in the previous conversion.

[0312] The edge code 1 of the fourth cell of the edge code sequence 1211 is converted to level code 0, which is counted by rotating by 1 from level code 4, because the previous level code is level code 4 obtained in the previous conversion.

[0313] Similarly, for DCC cell candidates 1 to 4 (LVL1 to LVL4) as well as DCC cell candidate 0, the edge code sequence 1211 1343 0134 ... as the cluster multi-level code is converted into a level code sequence as a candidate for the code sequence Code#1. Then, the level codes as candidates for the code sequence Code#1 for each of DCC cell candidates 1 to 4 (LVL1 to LVL4) are written to addresses ADDR=21 to 260 of the rows of levels LVL1 to LVL4, respectively.

[0314] The frame configuration unit 13 calculates the DSV for each level LVL#j from the beginning of the frame to the level code written at address ADDR=260.

[0315] Here, the DSV of FS is 0 as explained in Figure 15. Therefore, at each of levels LVL0 to LVL4, the DSVs of DCC cell candidates 0 to 4 written at address ADDR=20 immediately after FS (from the beginning of the frame) are equal to the NRZ codes -4, -2, 0, +2, and +4 of DCC cell candidates 0 to 4, respectively.

[0316] The frame constructor 13 detects the level (hereinafter also referred to as the minimum DSV level) LVL#j, which is the minimum absolute value of the DSV up to the level code written at address ADDR=260.

[0317] The frame constructor 13 determines the DCC cell candidate j of the minimum DSV level LVL#j as the DCC cell to be added to the beginning of the code sequence Code#1. Furthermore, the frame constructor 13 determines the level code as the candidate for the code sequence Code#1 written at addresses ADDR=21 to 260 of the minimum DSV level LVL#j as the code sequence Code#1.

[0318] Then, the frame configuration section 13 adds the determined DCC cell to the beginning of the determined code sequence Code#1, and places it after the FS.

[0319] 26, the DSVs up to the level code written at address ADDR=260 for levels LVL0 to LVL4 are -76, -4, 58, 30, and -8. Therefore, the DSV with the smallest absolute value is -4 for level LVL1, and so level LVL1 is detected as the minimum DSV level.

[0320] Then, candidate 1 of the DCC cell of the minimum DSV level LVL1 is determined as the DCC cell to be added to the beginning of the code sequence Code#1. Furthermore, the level code as a candidate of the code sequence Code#1 written at addresses ADDR=21 to 260 of the minimum DSV level LVL1 is determined as the code sequence Code#1.

[0321] Next, the frame configuration unit 13 writes the quintuple values ​​0 to 4, which are candidates for the DCC cell to be added to the beginning of the second code sequence Code#2, into the rows of levels LVL0 to LVL4 in the column of address ADDR=261 immediately after code sequence #1.

[0322] The frame construction unit 13 assumes that the DCC cell added to the beginning of the code sequence Code#2 is j, and converts 240 cells from the 241st to the 480th cells of the edge code sequence as the cluster multi-level code into level codes as candidates for the code sequence Code#2.

[0323] As a result, for each of the DCC cell candidates 0 to 4 added to the beginning of the code sequence Code#2, a sequence of level codes of 240 cells is obtained as candidates for the code sequence Code#2.

[0324] The frame configuration unit 13 writes the level code sequences of 240 cells as candidates for the code sequence Code#2 for each of the DCC cell candidates 0 to 4 into addresses ADDR=262 to 501 of the rows of levels LVL0 to LVL4, respectively.

[0325] The frame configuration unit 13 calculates the DSV for each level LVL#j from the beginning of the frame to the level code written at address ADDR=501.

[0326] The DSV is calculated based on the last cell of the previously determined code sequence Code#1, that is, DSV=-4 up to the level code written at address ADDR=260.

[0327] Therefore, at each of levels LVL0 to LVL4, the DSVs of DCC cell candidates 0 to 4 written at address ADDR=261 immediately after the most recently determined code sequence Code#1 are -8, -6, -4, -2, 0, which are the sum of the NRZ codes of DCC cell candidates 0 to 4, -4, -2, 0, +2, +4, respectively, to the reference DSV=-4.

[0328] The frame constructor 13 detects the minimum DSV level LVL#j, which is the smallest absolute value of the DSV up to the level code written at address ADDR=501.

[0329] The frame constructor 13 determines the DCC cell candidate j of the minimum DSV level LVL#j as the DCC cell to be added to the beginning of the code sequence Code#2. Furthermore, the frame constructor 13 determines the level code as the candidate for the code sequence Code#2 written at addresses ADDR=262 to 501 of the minimum DSV level LVL#j as the code sequence Code#2.

[0330] Then, the frame configuration section 13 adds the determined DCC cell to the beginning of the determined code sequence Code#2, and places it after the code sequence Code#1.

[0331] 26, the DSVs up to the level code written at address ADDR=501 for levels LVL0 to LVL4 are -10, -38, 84, -24, and -32. Therefore, the DSV with the smallest absolute value is -10 for level LVL0, and therefore level LVL0 is detected as the minimum DSV level.

[0332] Then, candidate 0 of the DCC cell with the minimum DSV level LVL0 is determined as the DCC cell to be added to the beginning of the code sequence Code#2. Furthermore, the level code as a candidate of the code sequence Code#2 written at addresses ADDR=262 to 501 with the minimum DSV level LVL0 is determined as the code sequence Code#2.

[0333] The frame constructing unit 13 similarly arranges the code sequences Code#3 to Code#16 while adding DCC cells as DC control, thereby constructing a frame.

[0334] <Detecting specific patterns>

[0335] FIG. 27 is a diagram for explaining an example of detection of a specific pattern by the sync detection unit 18. In FIG.

[0336] The sync detection unit 18 is supplied with, for example, a series of level codes of multi-level codes as a result of Viterbi decoding of a playback signal from the signal processing unit 17. From the series of level codes from the signal processing unit 17, the sync detection unit 18 detects RUB SYNC, FS, and APC SYNC from Run-in as a specific pattern.

[0337] The sync detection unit 18 has a register group shown in Fig. 27. The register group is configured by sequentially connecting a plurality of registers D that store level codes of ML=5 values.

[0338] The register group is made up of registers D whose number is equal to or greater than the number of cells of the longest specific pattern detected by the sync detection unit 18. In Fig. 27, the register group is made up of registers D whose number is the same as 360 cells, which is the number of cells in RUB SYNC.

[0339] In the register group, a level code (hereinafter also referred to as a reproduction level code) from the signal processing unit 17 is supplied to the first-stage register D (the rightmost register D in FIG. 27).

[0340] The register D in the first stage latches the latest reproduction level code from the signal processing unit 17, and each of the other registers D latches the stored value of the previous register D (the register D on the right in FIG. 27). As a result, the sequence of reproduction level codes supplied from the signal processing unit 17 to the register group shifts from the rightmost register D to the leftmost register D. As a result, the registers D constituting the register group store the sequence of reproduction level codes from the signal processing unit 17 in chronological order, from the leftmost register D to the rightmost register D.

[0341] When the latest playback level code is stored in the rightmost register D, the sync detection unit 18 calculates the dissimilarity between the sequence of playback level codes C(t-(L-1)), C(t-(L-2)), ..., C(t) stored in the registers of number L equal to the number of cells L of the specific pattern from the rightmost register D and the sequence of level codes S(0), S(1), ..., S(L-1) as the specific pattern.

[0342] C(t) represents the latest reproduction level code stored in the rightmost register D, that is, the reproduction level code at the latest time t.

[0343] Dissimilarity represents the degree of dissimilarity between two sequences of multilevel codes. When the two sequences are identical, dissimilarity takes a minimum predetermined value, such as 0, and the greater the degree of dissimilarity, the greater the value.

[0344] The dissimilarity IXC(t) between the sequence of playback level codes C(t-(L-1)) to C(t) and the sequence of level codes S(0) to S(L-1) as specific patterns can be calculated, for example, according to the formula IXC(t) = Σabs(ZC(ti) - ZS(i)).

[0345] In the formula IXC(t) = Σabs(ZC(ti) - ZS(i)), Σ represents the summation obtained by changing i from 0 to L-1. Furthermore, abs() represents the absolute value in the parentheses. ZC(ti) and ZS(i) represent the NRZ code of the reproduction level code C(ti) and the level code S(i) as a specific pattern, respectively.

[0346] According to the formula IXC(t)=Σabs(ZC(ti)-ZS(i)), the dissimilarity is calculated as the sum of absolute values ​​of the difference ZC(ti)-ZS(i) of the NRZ code between the reproduction level code C(ti) and the level code S(i) that constitutes the specific pattern. As the dissimilarity, in addition to the sum of absolute values ​​of the difference ZC(ti)-ZS(i), a value corresponding to the magnitude of the difference ZC(ti)-ZS(i), such as the sum of squares of the difference ZC(ti)-ZS(i), can be used.

[0347] The sync detection unit 18 detects a specific pattern according to the dissimilarity IXC(t) between the sequence of playback level codes C(t-(L-1)) to C(t) and the sequence of level codes S(0) to S(L-1) as the specific pattern.

[0348] That is, when the sync detection unit 18 detects a dissimilarity IXC(t) below the threshold, it determines the position of the playback level code C(t) at which the dissimilarity IXC(t) is detected as the end position of the specific pattern, and detects the sequence of playback level codes C(t-(L-1)) to C(t) of L cells as the sequence of level codes S(0) to S(L-1) as the specific pattern.

[0349] In addition, when the sync detection unit 18 detects a dissimilarity v that is equal to or less than a threshold, if no dissimilarity lower than that dissimilarity v is detected within a judgment interval (predetermined interval) that is a time corresponding to a predetermined number of cells, the sync detection unit 18 can detect a specific pattern by regarding the position of the playback level code where the dissimilarity v was detected as the end position of the specific pattern.

[0350] The position of register D that is away from the rightmost register D by the judgment interval (the number of cells corresponding to it) is referred to as the data extraction position. When a dissimilarity smaller than a dissimilarity v that is equal to or smaller than the threshold is not detected within the judgment interval, the position of the reproduction level code where the dissimilarity v is detected is detected as the position of the specific pattern (end). When the minimum value of the dissimilarity is equal to or smaller than the threshold in an interval twice the judgment interval centered on the data extraction position, the position of the reproduction level code where the minimum dissimilarity is detected is detected as the position of the specific pattern.

[0351] In this case, when a dissimilarity v2 that is below the threshold but greater than the dissimilarity v1 is obtained near the dissimilarity v1 that is below the threshold, it is possible to prevent the position of the reproduction level code where the dissimilarity v2 is detected from being mistakenly detected as the position of a specific pattern.

[0352] FIG. 28 is a flowchart illustrating an example of a detection process for detecting a specific pattern.

[0353] In step S111, the sync detection unit 18 resets the detection pointer that points to the position of register D in the built-in register group (FIG. 27). When the detection pointer is reset, the detection pointer is set to point to register D at the beginning (right end) of the register group.

[0354] Furthermore, in step S111, the sync detection unit 18 resets the minimum dissimilarity, which indicates the minimum value of the dissimilarity, and the process proceeds to step S112. In resetting the minimum dissimilarity, the minimum dissimilarity is set to a predetermined value that exceeds a threshold (similarity threshold).

[0355] In step S112, the sync detection unit 18 calculates the dissimilarity IXC(t) between the sequence C(t-(L-1)) to C(t) of L playback level codes stored in L registers D starting from the first register D in the register group and the sequence S(0) to S(L-1) of level codes as a specific pattern with L cells, and the process proceeds to step S113.

[0356] In step S113, the sync detection unit 18 determines whether a dissimilarity equal to or less than the threshold has already been detected (calculated) in the currently executed detection process, and whether the detection pointer points to register D, which is the data extraction position.

[0357] If it is determined in step S113 that a dissimilarity equal to or less than the threshold has not been detected, or if it is determined that the detection pointer does not point to register D, which is the data extraction position, the process proceeds to step S114.

[0358] In step S114, the sync detection unit 18 determines whether the latest dissimilarity IXC(t) is equal to or less than the threshold and smaller than the minimum dissimilarity.

[0359] In step S114, if it is determined that the latest dissimilarity IXC(t) is equal to or less than the threshold and less than the minimum dissimilarity, i.e., if a dissimilarity IXC(t) is calculated that is equal to or less than the threshold and less than the minimum dissimilarity, processing proceeds to step S115.

[0360] In step S115, the sync detection unit 18 resets the detection pointer, as in step S111. Furthermore, in step S115, the sync detection unit 18 updates the minimum dissimilarity to the latest dissimilarity IXC(t), and the process proceeds to step S117.

[0361] If it is determined in step S114 that the latest dissimilarity IXC(t) is not equal to or less than the threshold value or is not smaller than the minimum dissimilarity, the process proceeds to step S116.

[0362] That is, for example, if the dissimilarity IXC(t) is not equal to or less than the threshold value, or if it is equal to or less than the threshold value but is not smaller than the minimum dissimilarity, the process proceeds from step S114 to step S116.

[0363] In step S116, the sync detection unit 18 increments the detection pointer, and the process proceeds to step S117. In incrementing the detection pointer, the detection pointer is set to point to the register D next to the current register D (the register D on the left).

[0364] In step S117, a new reproduction level code is supplied to the first register D of the register group, and after the stored values ​​(reproduction level codes) of each register D are shifted, the process returns to step S112, and the same processes are repeated thereafter.

[0365] Then, in step S113, if it is determined that a dissimilarity equal to or less than the threshold value has been detected and the detection pointer is pointing to register D, which is the data extraction position, the process proceeds to step S118.

[0366] That is, if the determination interval has elapsed since a dissimilarity equal to or less than the threshold was detected, the process proceeds from step S113 to step S118.

[0367] In step S118, the sync detection unit 18 detects the specific pattern by determining the position of the reproduction level code stored in the data extraction position register D as the position of the specific pattern (the end of the specific pattern), and ends the specific pattern detection process. After the end of the specific pattern detection process, the specific pattern detection process is executed again.

[0368] According to the detection process of Figure 28, when a dissimilarity v below a threshold is detected, if there is no dissimilarity smaller than the dissimilarity v within the judgment section centered on the position (time) of the reproduction level code where the dissimilarity v was obtained, the position of the reproduction level code where the dissimilarity v was obtained is detected as the position of the specific pattern.

[0369] Therefore, when a dissimilarity equal to or less than the threshold is detected at a position other than the position of a specific pattern, it is possible to prevent that position from being erroneously detected as the position of a specific pattern.

[0370] In this embodiment, a value corresponding to the magnitude of the difference in the NRZ code between the reproduction level code sequence and the specific pattern is used as the dissimilarity indicating the degree of dissimilarity between two sequences of multi-level codes, and the specific pattern is detected according to this dissimilarity.

[0371] The specific pattern can also be detected according to, for example, the similarity that indicates the degree of similarity between the sequence of the reproduction level code and the specific pattern.

[0372] As the similarity between the sequence of reproduction level codes and the specific pattern, for example, the cross-correlation value XC(K)=Σ(NA(i)×NB(i)) of the sequences A and B of the multi-level codes described in FIG. 18 can be used.

[0373] The cross-correlation value XC(K) increases as the sequence of playback level codes and the specific pattern become more similar. Therefore, when the cross-correlation value XC(K) is used as the similarity, the position of the level code with a similarity equal to or greater than a threshold value can be detected as the position of the specific pattern.

[0374] However, the maximum value that the cross-correlation value XC(K) between the sequence of reproduction level codes and the specific pattern can take varies depending on the specific pattern and its length (number of cells). Therefore, when using such a cross-correlation value XC(K) as the similarity, it is not easy to set an appropriate threshold value.

[0375] On the other hand, as explained in FIG. 27, the dissimilarity IXC(t) calculated by the formula IXC(t)=Σabs(ZC(ti)-ZS(i)) takes a minimum value of 0 when the sequence of reproduction level codes C(t-(L-1)) through C(t) matches the sequence of level codes S(0) through S(L-1) as a specific pattern, and takes a larger value as the degree of dissimilarity between the sequence of reproduction level codes C(t-(L-1)) through C(t) and the sequence of level codes S(0) through S(L-1) as a specific pattern increases.

[0376] Therefore, the threshold value of the dissimilarity for detecting a specific pattern can be easily set based on the minimum value of 0.

[0377] FIG. 29 is a diagram showing an example of dissimilarity calculated by simulation.

[0378] In FIG. 29, the horizontal axis represents time (the number of cells of the reproduction level code) t, and the vertical axis represents the dissimilarity IXC(t).

[0379] In the simulation, a detection process was performed to detect RUB SYNC as a specific pattern from a sequence of reproduction level codes obtained by Viterbi decoding of the reproduction signal of the groove G.

[0380] FIG. 29 shows the dissimilarity when the cER (cell error rate) of the playback level code is 0.

[0381] In the simulation, the position of (the end of) RUB SYNC in the sequence of the playback level code is at time t=759.

[0382] In FIG. 29, the dissimilarity IXC(759) reaches the minimum value of 0 at time t=759, which is the position of RUB SYNC.

[0383] Near time t=759, negative peaks (downward peaks) of dissimilarity IXC(t) exist not only at time t=759 but also before and after time t=759. However, at the negative peaks before and after time t=759, dissimilarity IXC(t) is about 350. Therefore, by setting the threshold value of dissimilarity IXC(t) to, for example, about 200, RUB SYNC at the position of time t=759 can be correctly detected.

[0384] In addition, in Figure 29, if the threshold is set to, for example, 400, not only the dissimilarity IXC(759) at time t = 759, but also the dissimilarity IXC(t) of approximately 350 before and after time t = 759 will be below the threshold.

[0385] However, dissimilarity IXC(t) of approximately 350 before and after time t=759 exists within the determination interval from time t=759, where minimum dissimilarity IXC(759) occurs. In this case, according to the detection process in Fig. 28, time t=759, where minimum dissimilarity IXC(759) occurs, is correctly detected as the position of the specific pattern, rather than the position of dissimilarity IXC(t) of approximately 350 before and after time t=759.

[0386] Fig. 30 is a diagram showing another first example of dissimilarity calculated by simulation, Fig. 31 is a diagram showing another second example of dissimilarity calculated by simulation, and Fig. 32 is a diagram showing another third example of dissimilarity calculated by simulation.

[0387] In the simulation, similar to the case of Fig. 29, a detection process was executed to detect RUB SYNC as a specific pattern from a sequence of reproduction level codes obtained by Viterbi decoding of the reproduction signal of groove G. In the sequence of reproduction level codes, the position of RUB SYNC is at time t=759, similar to the case of Fig. 29.

[0388] 30 to 32, similarly to FIG. 29, the horizontal axis represents time t, and the vertical axis represents dissimilarity IXC(t).

[0389] FIG. 30 shows the dissimilarity when the cER of the reproduction level code is about 0.018. FIG. 31 shows the dissimilarity when the cER of the reproduction level code is about 0.100. FIG. 32 shows the dissimilarity when the cER of the reproduction level code is about 0.599.

[0390] According to FIGS. 30 to 32, when the cER is about 0.1 or less (FIGS. 30 and 31), it can be confirmed that by setting the threshold to about 200, RUB SYNC as a specific pattern can be detected with sufficient accuracy.

[0391] Also, even when the cER is quite poor at about 0.5 (FIG. 32), it can be confirmed that by setting the threshold to about 300, RUB SYNC as a specific pattern can be detected with sufficient accuracy.

[0392] <Effect of DC control>

[0393] FIGS. 33, FIG. 34, and FIG. 35 are diagrams for explaining the effect of DC control of a multilevel code.

[0394] FIG. 33 shows the power spectral density (PSD) of a series of ML = 5-level multilevel codes obtained by not performing DC control of the multilevel code, that is, as a fixed level code as a DCC cell, for example, by adding 0 to form a frame.

[0395] In FIG. 33, the horizontal axis represents the normalized frequency, and the vertical axis represents the PSD. The same applies to FIGS. 34 and 35.

[0396] According to FIG. 33, when DC control of the multilevel code is not performed, it can be confirmed that even when the normalized frequency is about 1e - 4 (= 0.0001), the PSD is about 0 dB and the low-frequency component is not suppressed.

[0397] FIG. 34 shows the PSD of a series of ML = 5-level multilevel codes when DC control of the multilevel code is performed.

[0398] According to FIG. 34, when DC control of the multilevel code is performed, the PSD is about −23 dB when the normalized frequency is about 1e−4, and it can be confirmed that the low frequency components are suppressed.

[0399] FIG. 35 shows the PSD of a binary PCWA (Parity-Complementary Word Assignment) 100 code sequence, which is used as a channel code in AD (Archival Disc) 2.

[0400] AD2 is an optical disc standard that enables high-density data recording, and details thereof are described, for example, in "White Paper: Archival Disc Technology 2nd Edition," July 2018.

[0401] AD2 employs PCWA110 code, which is a binary code with a coding rate of 2 / 3, as a channel code. The PCWA110 code is described in, for example, Japanese Patent No. 4998472.

[0402] In AD2, DC control is performed by adding one DCC bit to every 59 bits of user data. Therefore, in the PCWA110 code sequence obtained by channel coding user data into PCWA110 code with a coding rate of 2 / 3, DC control is performed in units of 90T (90 bits) PCWA110 code sequence, where T represents the period of the channel clock.

[0403] 34 and 35, it can be seen that the DC control of the multilevel code (FIG. 34) has the same effect of suppressing low-frequency components as AD2 (FIG. 35).

[0404] In this technique, DC control of the multi-level code is performed in units of a sequence of 240 cells (240T) of multi-level code, as described with reference to FIGS.

[0405] Therefore, DC control of the multilevel code of the present technology can be performed more efficiently than in the case of AD2.

[0406] In other words, the DC control of the multi-level code of this technology can achieve the same performance in suppressing low-frequency components as the DC control of the binary PCWA110 code, with DC control that has a longer period (less frequent) than the DC control of the binary PCWA110 code.

[0407] <Required SNR>

[0408] FIG. 36 is a diagram showing an example of the required SNR as the decoding performance of a multi-level code.

[0409] 36, the horizontal axis represents the linear density of recording on the optical disc 16 as a percentage of the linear density of AD2, and the vertical axis represents the required SNR (Signal to Noise Ratio), which is the SNR required to obtain a cER of 1e-4 (=0.0001).

[0410] The smaller the required SNR, the more likely it is that a desired cER can be obtained even with a noisy reproduced signal. Therefore, a small required SNR indicates good code (information) decoding performance.

[0411] FIG. 36 plots the required SNR obtained by simulations performed by the inventors of the present invention for a binary PCWA110 code and a multilevel code (a 5-level code) with ML=5 levels.

[0412] In FIG. 36, binary-ISI=11 represents the required SNR of the PCWA110 code when the ISI (Inter-Symbol Interference) length, which is the length at which inter-symbol interference occurs, is 11T. binary-ISI=13 represents the required SNR of the PCWA110 code when the ISI length is 13T. 5-ary-ISI=2 represents the required SNR of the 5-ary code when the ISI length is 2T (2 cells). 5-ary-ISI=3 represents the required SNR of the 5-ary code when the ISI length is 3T.

[0413] In addition, in FIG. 5, the required SNR of AD2 is indicated by a dotted line.

[0414] According to FIG. 36, it can be confirmed that a 5-ary code with an ISI length of 3T (5-ary-ISI=3) can achieve decoding performance equivalent to that of AD2 at a linear density 120% that of AD2.

[0415] Therefore, with a 5-ary code with an ISI length of 3T (5-ary-ISI=3), it is possible to improve the linear density by 20% while achieving decoding performance equivalent to that of AD2.

[0416] Here, the ratio of the amount of user data included in a RUB to the amount of data in the RUB is referred to as format efficiency.

[0417] The format efficiency of the AD2 RUB is approximately 87.9%, while the format efficiency of the RUB in Fig. 17, which is composed of 5-level codes, is approximately 88.051%. Therefore, the format efficiency of the 5-level code RUB is improved by approximately 0.2% compared to AD2.

[0418] Therefore, compared to AD2, the 5-level code can improve the linear density by 20% without reducing the format efficiency.

[0419] The above describes the case where a 9-bit / 4-cell code with k=4 and ML=5 is used as a block code composed of a multi-level code with 3<=ML values ​​for channel coding. However, the block code used for channel coding is not limited to a 9-bit / 4-cell code with k=4 and ML=5.

[0420] That is, the block code used for channel coding can be a block code consisting of a one-cell multilevel code or a multilevel code of two or more cells generated by a code generation model of any k and ML, such as a 9-bit / 5-cell code with k=5 and ML=4.

[0421] <Description of the computer to which this technology is applied>

[0422] Next, the series of processes of the above-mentioned ECC processing unit 11 to RUB configuration unit 14 and part or all of the signal processing unit 17 to ECC processing unit 22 can be performed by hardware or software. When the series of processes are performed by software, the programs constituting the software are installed in a general-purpose computer or the like.

[0423] FIG. 37 is a block diagram showing an example of the configuration of an embodiment of a computer in which a program for executing the above-described series of processes is installed.

[0424] The program can be recorded in advance on the hard disk 905 or ROM 903 as a recording medium built into the computer.

[0425] Alternatively, the program can be stored (recorded) on a removable recording medium 911 driven by the drive 909. Such a removable recording medium 911 can be provided as a so-called package software. Here, examples of the removable recording medium 911 include a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, and a semiconductor memory.

[0426] The program can be installed into the computer from the removable recording medium 911 as described above, or can be downloaded to the computer via a communication network or a broadcasting network and installed on the built-in hard disk 905. That is, the program can be transferred to the computer wirelessly from a download site via an artificial satellite for digital satellite broadcasting, or transferred to the computer by wire via a network such as a LAN (Local Area Network) or the Internet.

[0427] The computer includes a CPU (Central Processing Unit) 902 , to which an input / output interface 910 is connected via a bus 901 .

[0428] When a user inputs a command via an input / output interface 910 by operating an input unit 907, the CPU 902 executes a program stored in a read-only memory (ROM) 903 in accordance with the command. Alternatively, the CPU 902 loads a program stored on a hard disk 905 into a random access memory (RAM) 904 and executes the program.

[0429] As a result, the CPU 902 performs processing according to the flowchart described above or processing performed by the configuration of the block diagram described above. Then, the CPU 902 outputs the processing results from the output unit 906 via the input / output interface 910, or transmits them from the communication unit 908, or further records them on the hard disk 905, as necessary.

[0430] The input unit 907 is made up of a keyboard, a mouse, a microphone, etc. The output unit 906 is made up of an LCD (Liquid Crystal Display), a speaker, etc.

[0431] In this specification, the processing performed by a computer according to a program does not necessarily have to be performed in chronological order according to the order described in the flowchart. In other words, the processing performed by a computer according to a program also includes processing that is executed in parallel or individually (for example, parallel processing or processing by objects).

[0432] The program may be processed by a single computer (processor), or may be distributed among multiple computers. Furthermore, the program may be transferred to and executed on a remote computer.

[0433] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology.

[0434] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0435] The present technology can have the following configurations.

[0436] <1> a multilevel code of ML values ​​obtained by encoding user data into a (d, k) RLL code of 3 or more ML values; a specific pattern of the ML values ​​that repeats a run larger than the maximum run k of the multilevel code; was recorded Recording medium. <2> The multi-level code is recorded by encoding a binary ECC cluster including the user data and parity used in ECC (Error Correction Coding) processing. <1> The recording medium described in <3> The multilevel code is recorded by performing DC (Direct Current) control to minimize the absolute value of DSV (Digital Sum Value), which is the cumulative value of NRZ (Non Return to Zero) code that expresses the multilevel code with the ML value centered around 0. <1> or <2> The recording medium described in <4> The DC control is performed by adding a DCC (Direct Current Control) cell of the ML value to the multilevel code sequence. <3> The recording medium described in <5> It is a disk-shaped recording medium <1> Or <4> 10. The recording medium according to claim 1, wherein <6> A pattern of the ML values, the magnitude of which is calculated using an NRZ (Non Return to Zero) code that expresses the multilevel code with the ML values ​​centered around 0, is equal to or less than a threshold, is recorded on an adjacent track. <5> The recording medium described in <7> The pattern of ML values ​​in which the cross-correlation value is 0 is recorded on an adjacent track. <6> The recording medium described in <8> Recording on the recording medium is performed using RUB (Recording Unit Block) as a recording unit, The RUB is Run-in is a pattern that indicates the beginning of the RUB. a plurality of frames including the multi-level code obtained by encoding a binary ECC cluster including the user data and a parity used in ECC (Error Correction Coding) processing; Run-out is a pattern that indicates the end of the RUB. Including, The specific pattern is the Run-in <1> Or <7> 10. The recording medium according to claim 1, wherein <9> The RUB includes an FS (Frame Sync) that is a pattern indicating the beginning of the frame, The specific pattern is the FS. <8> The recording medium described in <10> The RUB includes an APC SYNC pattern for APC (Automatic Power Control), The specific pattern is the APC SYNC. <8> or <9> The recording medium described in <11> an encoding unit that encodes user data into a multilevel code that is a (d, k) RLL code with 3 or more ML values; a recording unit that records the specific pattern of the ML values ​​that repeats a run larger than the maximum run k of the multi-level code and the multi-level code on a recording medium; A recording device comprising: <12> The multilevel code is expressed by the ML value centered on 0. The multilevel code is further provided with a DC (Direct Current) control unit that performs DC (Direct Current) control to minimize the absolute value of a DSV (Digital Sum Value), which is an accumulated value of an NRZ (Non Return to Zero) code. <11> The recording device according to claim 1. <13> The DC control unit performs the DC control by adding a DCC (Direct Current Control) cell of the ML value to the sequence of the multilevel code. <12> The recording device according to claim 1. <14> Encoding user data into a multilevel code that is a (d, k) RLL code with 3 or more ML values; recording the specific pattern of the ML values ​​repeating a run larger than the maximum run k of the multi-level code and the multi-level code on a recording medium; A recording method including: <15> a reproducing unit for reproducing a recording medium on which a multilevel code of ML values, obtained by encoding user data into a (d, k) RLL code of ternary or more ML values, and a specific pattern of the ML values, which repeats a run greater than a maximum run k of the multilevel code, are recorded; a decoding unit that decodes the multi-level code according to the specific pattern; A playback device comprising: <16> a detection unit that detects the specific pattern from the sequence of the multi-level code reproduced from the recording medium, The decoding unit decodes the multi-level code obtained by encoding the user data according to the specific pattern. <15> The playback device described in <17> The detection unit detects the specific pattern according to a dissimilarity indicating a degree of dissimilarity between the sequence of the multi-level code reproduced from the recording medium and the specific pattern. <16> The playback device described in <18> The detection unit calculates, as the dissimilarity, a value corresponding to the magnitude of a difference in an NRZ (Non Return to Zero) code that expresses the multilevel code with the ML value centered at 0 between the sequence of the multilevel code reproduced from the recording medium and the specific pattern. <17> The playback device described in <19> When the minimum value of the dissimilarity in a predetermined section is equal to or less than a threshold value, the detection unit detects the position of the multi-level code where the minimum value of the dissimilarity is detected as the position of the specific pattern. <18> The playback device described in <20> Reproducing a recording medium on which a multilevel code of ML values, which is obtained by encoding user data into a (d, k) RLL code of 3 or more ML values, and a specific pattern of the ML values, which repeats a run greater than a maximum run k of the multilevel code, are recorded; decoding the multi-level code according to the specific pattern; A playback method including: [Explanation of symbols]

[0437] 11 ECC processing unit, 12 channel coding unit, 13 frame construction unit, 14 RUB construction unit, 15 recording / playback system, 16 optical disk, 17 signal processing unit, 18 sync detection unit, 19 frame detection unit, 20 DCC removal unit, 21 channel decoding unit, 22 ECC processing unit, 23 control unit, 23A register group, 51 LUT storage unit, 52 code generation unit, 31 ADC, 32 PLL, 33 memory, 34 adaptive equalization unit, 35 restoration unit, 36 convolution unit, 37 error calculation unit, 41 HPF, 42 AGC, 901 bus, 902 CPU, 903 ROM, 904 RAM, 905 hard disk, 906 output unit, 907 input unit, 908 communication unit, 909 Drive, 910 Input / Output Interface, 911 Removable Recording Media < / rub> < / fs>

Claims

1. a multi-level ML code obtained by encoding user data into a (d, k) RLL code with 3 or more ML values; a specific pattern of the ML value that repeats a run larger than the maximum run k of the multilevel code; is recorded, A pattern of ML values ​​in which the magnitude of a cross-correlation value calculated using an NRZ (Non Return to Zero) code that expresses the multilevel code with the ML value centered at 0 is equal to or less than a threshold value is recorded on an adjacent track. Recording medium.

2. The multi-level code is recorded by encoding a binary ECC cluster including the user data and parity used in ECC (Error Correction Coding) processing. The recording medium according to claim 1 .

3. (delete)

4. (delete)

5. It is a disk-shaped recording medium The recording medium according to claim 1 .

6. (delete)

7. The pattern of the ML values ​​in which the cross-correlation value is 0 is recorded on an adjacent track. The recording medium according to claim 1 .

8. Recording on the recording medium is performed using RUB (Recording Unit Block) as a recording unit, The RUB is Run-in is a pattern that indicates the beginning of the RUB; a plurality of frames including the multi-level code obtained by encoding a binary ECC cluster including the user data and a parity used in ECC (Error Correction Coding) processing; Run-out is a pattern that indicates the end of the RUB. Including, The specific pattern is the Run-in. The recording medium according to claim 1 .

9. The RUB includes an FS (Frame Sync) that is a pattern indicating the beginning of the frame, The specific pattern is the FS. The recording medium according to claim 8.

10. The RUB includes APC SYNC, which is a pattern for APC (Automatic Power Control), The specific pattern is the APC SYNC. The recording medium according to claim 8.

11. an encoding unit that encodes user data into a multi-level code that is a (d, k) RLL code with 3 or more ML values; a recording unit that records a specific pattern of the ML values ​​that repeats a run larger than the maximum run k of the multilevel code, and records the pattern of the ML values, in which the magnitude of a cross-correlation value calculated using an NRZ (Non Return to Zero) code that expresses the multilevel code with the ML values ​​centered at 0, is equal to or smaller than a threshold, on an adjacent track; A recording device comprising:

12. (delete)

13. (delete)

14. Encoding user data into a multi-level code that is a (d, k) RLL code with 3 or more ML values; a specific pattern of the ML values ​​repeating a run larger than the maximum run k of the multilevel code, and a pattern of the ML values ​​in which the magnitude of a cross-correlation value calculated using an NRZ (Non Return to Zero) code that expresses the multilevel code with the ML values ​​centered at 0 is equal to or smaller than a threshold value, is recorded on an adjacent track; A recording method including:

15. a reproducing unit for reproducing a recording medium on which a multilevel code of ML values, obtained by encoding user data into a (d, k) RLL code of ternary or more ML values, and a specific pattern of the ML values, which repeats a run greater than a maximum run k of the multilevel code, are recorded; a detection unit that detects the specific pattern from the sequence of the multi-level code reproduced from the recording medium; a decoding unit that decodes the multi-level code according to the specific pattern; Equipped with The detection unit detecting the specific pattern according to a dissimilarity indicating a degree of dissimilarity between the sequence of the multi-level code reproduced from the recording medium and the specific pattern; The dissimilarity is calculated as a value corresponding to the magnitude of the difference in NRZ (Non Return to Zero) code, which expresses the multilevel code with the ML value centered at 0, between the sequence of the multilevel code reproduced from the recording medium and the specific pattern. playback device.

16. The decoding unit decodes the multi-level code obtained by encoding the user data according to the specific pattern. The playback device according to claim 15.

17. (delete)

18. (delete)

19. When the minimum value of the dissimilarity in a predetermined section is equal to or less than a threshold value, the detection unit detects the position of the multi-level code where the minimum value of the dissimilarity is detected as the position of the specific pattern. The playback device according to claim 15.

20. Reproducing a recording medium on which a multilevel code of ML values, obtained by encoding user data into a (d, k) RLL code of ternary or more ML values, and a specific pattern of the ML values ​​that repeats a run greater than a maximum run k of the multilevel code, are recorded; detecting the specific pattern from the sequence of the multi-level code reproduced from the recording medium; decoding the multi-level code according to the specific pattern; Including, The detection detecting the specific pattern according to a dissimilarity indicating a degree of dissimilarity between the sequence of the multi-level code reproduced from the recording medium and the specific pattern; The dissimilarity is calculated as a value corresponding to the magnitude of the difference in NRZ (Non Return to Zero) code, which expresses the multilevel code with the ML value centered at 0, between the sequence of the multilevel code reproduced from the recording medium and the specific pattern. How to play.

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