Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device and a method for manufacturing the same that can easily improve the cooling effect and make the device thinner.SOLUTION: A semiconductor device has: a semiconductor chip having a first surface on which electrode terminals are formed and a second surface on the opposite side of the first surface; and a Peltier element provided on the second surface or on the first surface. The Peltier element has a thermoelectric semiconductor layer including a plurality of thermoelectric semiconductor elements, and the thermoelectric semiconductor element is a sintered body of a coating film of a composition including a thermoelectric semiconductor material.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In recent years, semiconductor devices have become increasingly high-frequency, high-density, and high-power, and conventional heat dissipation measures have become insufficient in terms of heat dissipation characteristics, resulting in a problem that the temperature of the semiconductor chip rises and the desired characteristics cannot be obtained. To address this problem, it has been proposed to provide semiconductor devices with Peltier elements that have heat absorption characteristics.

[0003] For example, Patent Document 1 describes that in a semiconductor package in which multiple face-down semiconductor chips are sealed with a sealing cap, a Peltier element is provided on the sealing cap on the back surface of the semiconductor chip or on the back surface of the circuit board. However, Patent Document 1 does not describe the detailed structure or material of the Peltier element, nor the method of forming it. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-198476 Summary of the Invention [Problem to be solved by the invention]

[0005] There is still room for improvement in order to further enhance the cooling effect of the Peltier element on the semiconductor chip. Furthermore, there is a demand for making the entire semiconductor device thinner while still incorporating a Peltier element. Furthermore, even in so-called three-dimensional packaging semiconductor devices in which multiple semiconductor chips are stacked, there is a demand for a configuration that can be made as thin as possible.

[0006] In view of the above problems, an object of the present invention is to provide a semiconductor device that can easily improve the cooling effect and can be easily made thinner, and a method for manufacturing the same. [Means for solving the problem]

[0007] As a result of extensive research into solving the above problems, the inventors discovered that the above problems can be solved by providing a Peltier element including a thermoelectric semiconductor element that is a sintered body of a coating film of a composition containing a thermoelectric semiconductor material on a predetermined surface of a semiconductor chip, and thus completed the present invention. That is, the present invention provides the following [1] to [6]. [1] A semiconductor chip having a first surface on which electrode terminals are formed and a second surface opposite to the first surface, and a Peltier element provided on the second surface or the first surface, the Peltier element has a thermoelectric semiconductor layer including a plurality of thermoelectric semiconductor elements; The thermoelectric semiconductor element is a sintered body of a coating film of a composition containing a thermoelectric semiconductor material. [2] further comprising a connection layer facing the first surface of the semiconductor chip and electrically connected to the semiconductor chip; The semiconductor chip is electrically connected to the connection layer via electrode terminals on the first surface, and the Peltier element is provided on the second surface. [3] The semiconductor device according to [1] or [2] above, wherein the adjacent thermoelectric semiconductor elements are spaced apart from each other, and the gaps between the adjacent thermoelectric semiconductor elements are filled with a reinforcing material. [4] The semiconductor device according to any one of the above [1] to [3], wherein the composition containing the thermoelectric semiconductor material contains a polymer component, an ionic compound, and thermoelectric semiconductor particles. [5] A method for manufacturing a semiconductor device, comprising: (i) a coating step of applying a composition containing a thermoelectric semiconductor material onto a first surface of the semiconductor chip on which electrode terminals are formed, or onto a second surface opposite to the first surface, to obtain a coating film; and (ii) an annealing step of annealing the coating film to obtain a thermoelectric semiconductor layer that constitutes the Peltier element. [6] The method for manufacturing a semiconductor device according to [5] above, wherein in the coating step, a composition containing the thermoelectric semiconductor material is coated onto a second surface of a semiconductor chip of a semiconductor device component comprising the semiconductor chip and a connection layer electrically connected by electrode terminals on a first surface of the semiconductor chip to obtain a coating film. [Effects of the Invention]

[0008] The semiconductor device according to the present invention can provide a semiconductor device that can easily improve the cooling effect and can be easily thinned, and a method for manufacturing the same. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view showing an example of a semiconductor device. [Figure 2] FIG. 10 is a schematic cross-sectional view showing another example of a semiconductor device. [Figure 3] FIG. 10 is a schematic cross-sectional view showing another example of a semiconductor device. [Figure 4] FIG. 10 is a schematic cross-sectional view showing another example of a semiconductor device. [Figure 5] 1 is a schematic cross-sectional view showing an example of a three-dimensional mounting type semiconductor device. [Figure 6] 1A to 1C are schematic process diagrams showing an example of a method for manufacturing a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention (hereinafter, sometimes referred to as "the present embodiment") will be described.

[0011] [Semiconductor Devices] The semiconductor device according to this embodiment comprises a semiconductor chip having a first surface on which electrode terminals are formed and a second surface opposite to the first surface, and a Peltier element provided on the second surface or on the first surface, wherein the Peltier element has a thermoelectric semiconductor layer including a plurality of thermoelectric semiconductor elements, and the thermoelectric semiconductor elements are a sintered body of a coating film of a composition including a thermoelectric semiconductor material. In the case of a face-up semiconductor chip, the circuit side is formed upward, and the substrate and semiconductor chip are usually electrically connected by wire bonding. Therefore, the encapsulant is formed thicker above the semiconductor chip to encase the wires, and the distance between the Peltier element and the semiconductor chip, which is the heating element, becomes larger. In contrast, in semiconductor chips such as face-down semiconductor chips that are electrically connected to a layer to be connected (such as the circuit surface of a substrate) by electrode terminals formed on the surface facing the layer to be connected, wire bonding is not performed, so it is possible to place a Peltier element in close proximity to the semiconductor chip. Also, as long as the thermoelectric semiconductor element formed from a coating film can be insulated from the semiconductor chip, it can be formed directly by coating on the back surface of a face-down semiconductor chip or the like (the surface opposite to the surface facing the layer to be connected) without an adhesive layer or support medium. Therefore, in the semiconductor device, the distance between the cooling surface of the Peltier element and the semiconductor chip is short, and the semiconductor chip can be cooled efficiently. Furthermore, by using a thermoelectric semiconductor element formed from a coating film, it is easy to thin the thermoelectric semiconductor layer, making it suitable for application to semiconductor devices where thinning is highly desired.

[0012] Hereinafter, the "surface on which the electrode terminals are formed" of the semiconductor chip may be referred to as the "first surface." Also, the "surface opposite to the surface on which the electrode terminals are formed" of the semiconductor chip may be referred to as the "second surface." In the case of a face-down type semiconductor chip, the first surface is the surface facing the layer to be connected, and the second surface is the surface opposite to the surface facing the layer to be connected.

[0013] The configuration of the semiconductor device may be, for example, as in semiconductor device 100A shown in Figure 1 described below, further including a connection layer facing a first surface of the semiconductor chip and electrically connected to the semiconductor chip, the semiconductor chip being electrically connected to the connection layer via electrode terminals on the first surface, and the Peltier element being provided on the second surface.

[0014] The Peltier element is provided on the second surface of the semiconductor chip directly or via an intervening layer, and examples of the intervening layer include an adhesive layer, an insulator layer, and a sealing material layer. Furthermore, when the Peltier element is provided on the first surface of the semiconductor chip via an intervening layer, the intervening layer may be a sealing material layer or a circuit board.

[0015] <Semiconductor chip> As the semiconductor chip, a conventionally known one used in integrated circuits such as a microprocessor, a memory, and a high frequency power amplifier can be used. The semiconductor device according to this embodiment may include one or more semiconductor chips, i.e., may be monolithic or may be configured as a multi-chip. When a semiconductor device includes a plurality of semiconductor chips, the plurality of semiconductor chips are preferably arranged in a predetermined array in the planar direction. Examples of semiconductor chips that are electrically connected to the connection layer using electrode terminals formed on the surface facing the connection layer include face-down semiconductor chips as well as so-called TSV (Through Silicon Via) chips that have through electrodes.

[0016] <Connected Layer> Examples of the layer to be connected include a layer including a circuit surface of a circuit board, and a layer including an electrode formation surface of the TSV chip. The connection layer includes terminals that serve as connection lands for electrically connecting with bumps provided on the first surface of the semiconductor chip, terminals for sending and receiving signals to and from external devices, and terminals for receiving power to be supplied to the semiconductor chip and Peltier element. When the connection layer is a layer including a circuit surface of a circuit board, the semiconductor device includes a circuit board including the connection layer. The circuit board may have a recess for accommodating a semiconductor chip, and terminals for connection to the semiconductor chip may be provided on the bottom surface of the recess. In this case, the semiconductor chip is accommodated in the recess of the circuit board, and the gap between the semiconductor chip and the circuit board is sealed with a sealant as necessary, thereby forming a substrate-embedded semiconductor device.

[0017] The layer to be connected may be provided on the semiconductor chip as a rewiring layer, in which case the semiconductor device becomes a fan-out type semiconductor device. Here, the fan-out type semiconductor device is a semiconductor device in which the side surfaces of the semiconductor chip as well as the second surface thereof are sealed with a sealing material, the rewiring layer to be the layer to be connected is formed to have an area larger than the size of the semiconductor chip in accordance with the shape of the sealing material layer made of this sealing material, and bumps (protruding electrodes) are formed on the surface of the rewiring layer opposite to the surface connected to the semiconductor chip.

[0018] <Peltier element> The Peltier element has a thermoelectric semiconductor layer including a plurality of P-type thermoelectric semiconductor elements and a plurality of N-type thermoelectric semiconductor elements arranged alternately. One end of the N-type thermoelectric semiconductor element and one end of the P-type thermoelectric semiconductor element adjacent to each other in a first set are electrically connected, the other end of the N-type thermoelectric semiconductor element of the first set are electrically connected to the other end of the P-type thermoelectric semiconductor element of a second set, one end of the P-type thermoelectric semiconductor element of the second set is electrically connected to one end of the N-type thermoelectric semiconductor element paired with the P-type thermoelectric semiconductor element of the second set and forming the second set, the other end of the N-type thermoelectric semiconductor element of the second set is electrically connected to the other end of the P-type thermoelectric semiconductor element of a third set, and so on. When electricity is applied to the leading thermoelectric semiconductor element and the last thermoelectric semiconductor element, heat absorption occurs at the electrical junction where current flows from N to P, and heat radiation occurs at the electrical junction where current flows from P to N. As a result, one side of the Peltier element absorbs heat and the other side generates heat, and the object to be cooled can be cooled by bringing the heat-absorbing side of the Peltier element close to or in contact with the object.

[0019] In the semiconductor device according to this embodiment, the Peltier element has a thermoelectric semiconductor layer, and the thermoelectric semiconductor layer is a fired body of a coating film of a composition containing a thermoelectric semiconductor material. In this case, the composition containing the thermoelectric semiconductor material may contain a polymer component, an ionic compound, and thermoelectric semiconductor particles. A coating film formed using such a composition is suitable for forming, by coating, a thermoelectric semiconductor layer having good thermoelectric conversion properties. The thermoelectric semiconductor layer formed from the coating film does not require the above-mentioned substrate, and therefore can be easily made thin, making it suitable for application to semiconductor packages for which thinning is strongly demanded. The coating film is formed by, for example, gravure printing, and may also be formed by inkjet printing or other means. The adjacent thermoelectric semiconductor elements may be spaced apart from each other, and the gaps between the adjacent thermoelectric semiconductor elements may be filled with a reinforcing material, such as various insulators described below. The materials for forming the thermoelectric semiconductor layer and the method of application will be described later.

[0020] The Peltier element may be provided with other layers as needed. For example, a coating layer consisting of one or more layers may be disposed to cover the thermoelectric semiconductor layer on at least one of the main surfaces to protect the thermoelectric semiconductor layer. The coating layer may also include a sealing layer. If the coating layer is a single layer, the coating layer itself may also function as a sealing layer, and if the coating layer is made up of multiple layers, any one of the layers may include a sealing layer. If the coating layer includes a sealing layer, permeation of water vapor in the atmosphere can be more effectively suppressed, making it easier to maintain the performance of the Peltier element for a long period of time. The covering layer may include an adhesive layer (adhesive layer). In this specification, "adhesive" includes both adhesiveness and pressure-sensitive adhesiveness that allows adhesion by pressure sensitivity at the initial stage of application. Examples of adhesiveness other than pressure-sensitive adhesiveness include moisture-sensitive adhesiveness and adhesiveness by heat melting.

[0021] (covering body) It is preferable to provide a cover that covers at least the side surfaces of the semiconductor chip. The cover is, for example, constituted by an encapsulant layer formed by encapsulating the semiconductor chip with an encapsulant. Furthermore, if the circuit board has a recess that accommodates the semiconductor chip, the cover can also be constituted by an edge that forms the wall surface of the recess and faces the side surface of the semiconductor chip. The provision of the cover not only makes it easier to seal the semiconductor chip, but also allows for electrical continuity between the Peltier element and the connected layer by providing through-holes in the cover and placing conductors inside the through-holes. By electrically connecting the Peltier element and the connected layer with conductors placed in the through-holes, the conductive path to the Peltier element can be made thicker and shorter, reducing the resistance of the conductive path. Furthermore, the size (package size) of the semiconductor device can be made smaller than with wire bonding using metal wires.

[0022] Instead of using a circuit board having a recess, a sealing material layer may be formed on the periphery of a circuit board that does not have a recess, and through holes may be provided in this sealing material layer.

[0023] <Three-dimensional packaging type semiconductor device> The semiconductor device may be a semiconductor device in which the single or multiple semiconductor chips are a first semiconductor chip, and further includes a second semiconductor chip, and the first semiconductor chip and the second semiconductor chip are stacked. Hereinafter, a semiconductor device having a configuration in which multiple units including semiconductor chips are stacked will be referred to as a "three-dimensional packaging type semiconductor device." For example, as shown in Figure 5 described below, a configuration can be used in which a first unit has a face-up first semiconductor chip such as a DRAM mounted on a circuit board on the backside of a face-down semiconductor chip, and a second unit including a face-down second semiconductor chip is mounted on the backside of the circuit board of this first unit, and a Peltier element is further mounted on the semiconductor chip of the first unit.

[0024] In the case of a three-dimensionally mounted semiconductor device, it is preferable that the stacking order of the unit including the first semiconductor chip and the unit including the second semiconductor chip is such that the unit including the first semiconductor chip is stacked on top of the unit including the second semiconductor chip, and the Peltier element is positioned above the first semiconductor chip.

[0025] Hereinafter, examples of the configuration of semiconductor devices according to embodiments of the present invention will be described with reference to the drawings. The drawings are all schematic and may be exaggerated to facilitate understanding.

[0026] <Embodiment 1> Fig. 1 is a cross-sectional view showing an example of a semiconductor device according to this embodiment. The semiconductor device 100A shown in Fig. 1 is a substrate-embedded semiconductor device having a Peltier element 60 formed by a coating method as a thermoelectric semiconductor element. The upper surface (second surface) of the semiconductor chip 30, the upper surface of the encapsulant layer 20, and the upper surface of the edge portion 10a of the circuit board 10 are arranged in the same plane, and the Peltier element 60 is provided on this plane. A heat sink 92 is provided on the upper surface of the Peltier element 60 (the surface opposite to the surface facing the semiconductor chip 30). In the semiconductor device 100A, two semiconductor chips 30 are arranged in the planar direction, but this is not limiting and the number may be one, or three or more. This also applies to the semiconductor devices in the following Figures 2 to 5. In FIG. 1 and the subsequent figures, when there are a plurality of similar components, only the most representative components are labeled to prevent the figures from becoming difficult to understand.

[0027] The circuit board 10 has a recess on its front surface (the surface facing the semiconductor chip 30) for accommodating the semiconductor chip, and has bumps 11 on its back surface (the surface opposite to the surface facing the semiconductor chip 30) that are connected to pads (not shown) provided within the circuit board 10. An electrode 12 is provided on the bottom surface of the recess of the circuit board 10, and the circuit formation layer 13, which is the layer to be connected, is composed of bumps 11 for external connection provided on the back surface of the circuit board 10, internal wiring (not shown) within the circuit board 10, etc.

[0028] The edge 10a that forms the wall surface of the recess of the circuit board 10 and faces the side surface of the semiconductor chip 30 constitutes the cover. Bumps 31 are formed on the lower surface (first surface) of the semiconductor chip 30, and connect to pads (not shown) provided in the semiconductor chip 30. The semiconductor chip 30 is electrically connected to the electrode formation layer 13 of the circuit board 10 via the bumps 31. The spaces between the lower surface (first surface) of the semiconductor chip 30, the bumps 31, and the electrode formation layer 13 of the circuit board 10 are filled with an underfill material to form an underfill layer 40. A sealing material is filled between the two semiconductor chips and between the edge 10a of the circuit board 10 and the side surfaces of the semiconductor chip 30 and the Peltier element 60, forming a sealing material layer 20. The cover 10a (that is, the edge of the circuit board 10 that faces the side surface of the semiconductor chip 30) has a through hole 10b formed therein. Vias 80 made of a conductor are arranged in the through holes 10b so as to fill the through holes 10b. Examples of the conductors that form the vias 80 include metals such as copper, gold, and silver. In Fig. 1, two systems of vias 80 are provided for inputting and outputting current to and from the Peltier element 60. Of the connection electrodes 63 of the Peltier element 60, those connected to the first and last thermoelectric semiconductor elements are electrically joined to the upper parts of the corresponding vias 80 as a pair of terminals for external connection. Also, in Fig. 1, the lower parts of the vias 80 are connected to bumps 11 provided on the back surface of the circuit board 10. With this configuration, power can be supplied to the Peltier element 60 via the bumps 11 on the back surface of the circuit board 10. When electricity is applied to the Peltier element 60, the upper surface becomes the heat dissipation side and the lower surface becomes the heat absorption side, and the surface on the heat absorption side comes into contact with or is close to the second surface of the semiconductor chip 30, thereby cooling the semiconductor chip 30.

[0029] Like the Peltier element 60 in the semiconductor device 100A shown in FIG. 1, the Peltier element may have an external connection electrode (connection electrode 63) that extends beyond the periphery of the single semiconductor chip or the periphery of all of the multiple semiconductor chips when viewed perpendicularly to the single or multiple semiconductor chips, and the circuit formation layer and the Peltier element may be electrically connected by this external connection electrode and a conductor arranged in the through hole.

[0030] The Peltier element 60 includes (a) connection electrodes 63 located on the undersides of the thermoelectric semiconductor elements and the insulator layer 65, electrically connecting the same surfaces of adjacent thermoelectric semiconductor elements and electrically connecting them to the outside, and an adhesive layer 64 located between each pair of adjacent connection electrodes 63; (b) P-type thermoelectric semiconductor elements 61, N-type thermoelectric semiconductor elements 62, and an insulator layer 65 located therebetween; and (c) the connection electrodes 63 and adhesive layer 64 located on the upper surfaces of the thermoelectric semiconductor elements and the insulator layer 65. The component (b) above is a fired body of a coating formed by applying a thermoelectric semiconductor material composition. From the viewpoint of accelerating heat transfer between the thermoelectric semiconductor elements and the connection electrodes 63 and the semiconductor chip 30, or between the thermoelectric semiconductor elements and the connection electrodes 63 and the heat sink 92, the adhesive layer 64 is preferably formed from an adhesive having thermal conductivity. Instead of providing the Peltier element with the pressure-sensitive adhesive layer, a passivation film may be provided, if necessary, on the flat surface, including the upper surface of the semiconductor chip 30, and the lower connection electrodes may be formed directly on the surface of the adherend or on the passivation film. Furthermore, by forming the above (b) by a coating method, the substrate required for a general-purpose Peltier element is not required. Therefore, the overall thickness of the semiconductor device can be reduced. Details of the formation methods (a) to (c) will be described later.

[0031] Furthermore, the above-described configuration facilitates connection between the external connection electrode 63 of the Peltier element 60 and the via 80, which is a conductor disposed in the through-hole 10b provided in the edge 10a of the circuit board, which is the covering covering the side surface of the semiconductor chip 30. This allows for a thicker and shorter conductive path, thereby reducing resistance. Furthermore, since there is no need to route thin metal wires as in wire bonding, the size of the semiconductor device can be reduced, which is advantageous for achieving a thinner design. Furthermore, compared to wire bonding connections using thin metal wires, this method is also advantageous in terms of impact resistance.

[0032] <Embodiment 2> Fig. 2 is a cross-sectional view showing another example of the semiconductor device according to this embodiment. The semiconductor device 100B shown in Fig. 2 is a fan-out type semiconductor device, and has a configuration in which a Peltier element 60 having a thermoelectric semiconductor layer formed by a coating method is provided on a semiconductor chip 30. A circuit formation layer 13, which is a rewiring layer made up of electrodes 12 and a passivation layer 14, is provided on a first surface of the semiconductor chip 30. Bumps 11 that connect to electrodes in the circuit formation layer are provided on the lower surface of the circuit formation layer 13 (the surface opposite to the surface facing the semiconductor chip 30). The semiconductor device 100B does not have the circuit board that the semiconductor device shown in FIG. 1 has, and therefore the entire semiconductor device can have a thin and simple configuration.

[0033] In the semiconductor device 100B, the second surface and the side surfaces of the semiconductor chip 30 are covered with a sealing material, and a sealing material layer 20 is formed. The peripheral portion 20a of the encapsulant layer 20 forms a covering that covers the side surface of the semiconductor chip 30. The lower surface of the peripheral portion 20a of the encapsulant layer 20 and the first surface of the semiconductor chip 30 are arranged in the same plane. The circuit formation layer 13 extends on the lower surface of the peripheral portion 20a of the encapsulant layer 20, which is located in the same plane as the first surface of the semiconductor chip 30. A through hole 20b is provided in the peripheral portion 20a of the sealing material layer 20, and a via 80, which is a conductor, is disposed in the through hole 20b. A pair of vias 80 is provided, and each is electrically connected to a pair of terminals provided on the Peltier element 60. At least one pair of electrodes among the electrodes 12 included in the circuit formation layer 13 are electrically connected to the lower surfaces of the pair of vias 80 .

[0034] A Peltier element 60 is laminated on the second surface of the circuit board 10 via the thin portion of the sealing material layer 20 . After applying the encapsulant composition, the Peltier element 60 is placed on the encapsulant composition layer before at least one of drying and curing of the encapsulant is performed, and then at least one of drying and curing of the encapsulant composition is performed, thereby making it possible to adhere and fix the Peltier element 60 to the semiconductor chip 30 without providing another adhesive layer. An adhesive layer, which will be described later, may be provided on one surface of the Peltier element 60 or the second surface of the semiconductor chip 30, and the Peltier element 60 may be adhered by this adhesive layer. In this case, the encapsulant layer 20 may or may not be present on the second surface of the semiconductor chip 30. A heat dissipation member such as the heat sink 92 in FIG. 1 may be provided on the top surface of the Peltier element 60 (the surface opposite to the surface facing the semiconductor chip 30).

[0035] <Embodiment 3> Fig. 3 is a cross-sectional view showing another example of the semiconductor device according to the present embodiment. The semiconductor device 100C shown in Fig. 3 has a configuration similar to that of Fig. 1, except that the Peltier element and the circuit formation layer are connected by metal wires. In the semiconductor device 100C, bumps 31 of the semiconductor chip 30 are connected to electrodes 12 formed on the surface of a flat circuit board 10, and an underfill material is filled between the first surface of the semiconductor chip 30 and the circuit board 10 to form an underfill layer 40. Furthermore, Peltier elements 60 are stacked on the second surfaces of the two semiconductor chips 30, and connection electrodes 63 of the Peltier elements 60 are connected to electrodes 12 on the circuit formation layer 13 of the circuit board 10 by metal wires 66. Furthermore, a sealing material is filled between the two semiconductor chips 30 and around the entire stack of the two semiconductor chips 30 and the Peltier elements, including the metal wires 66, to form a sealing material layer 20. Furthermore, a heat sink 92 is provided on the upper surface of the sealing material layer 20.

[0036] The semiconductor device 100C is less advantageous than the semiconductor device of FIGS. 1 and 2 in terms of thinning, but like the semiconductor device of FIGS. 1 and 2, the thermoelectric semiconductor element is formed by a coating method, so the Peltier element 60 itself can be made thinner. Furthermore, since the entire stack of the Peltier element 60 and the semiconductor chip 30 is sealed with a sealing material, it is not necessary to provide a separate layer for insulating the two.

[0037] <Embodiment 4> Fig. 4 is a cross-sectional view showing another example of the semiconductor device according to this embodiment. The semiconductor device 100D shown in Fig. 4 has a configuration in which a Peltier element having a thermoelectric semiconductor layer formed by a coating method is provided on the surface of the circuit board opposite to the surface on which the semiconductor chip is mounted. In the semiconductor device 100D, bumps 31 of a semiconductor chip 30 are connected to electrodes 12 formed on the surface of a flat circuit board 10, and an underfill material is filled between a first surface of the semiconductor chip 30 and the circuit board 10 to form an underfill layer 40. A second surface and a side surface of the semiconductor chip 30 are sealed with a sealing material to form a sealing material layer 20. A Peltier element 60 is laminated on the surface of the circuit board 10 opposite to the surface corresponding to the semiconductor chip 30. In other words, the Peltier element 60 is provided on the first surface of the semiconductor chip 30 via the circuit board as an intervening layer. The connection electrodes 63 of the Peltier element 60 contact and are electrically connected to the electrodes (electrodes formed on the surface opposite to the surface facing the semiconductor chip 30) of the circuit formation layer 13 of the circuit board 10. A heat sink 92 is provided on the back surface of the Peltier element 60 (the surface opposite to the surface facing the semiconductor chip 30).

[0038] In the semiconductor device 100D, the thermoelectric semiconductor element is formed by a coating method, so the Peltier element 60 itself can be made thin. Furthermore, as shown in Figures 1 to 3, no vias or metal wires for bonding are required to connect the Peltier element 60 to the circuit-forming layer 13, simplifying the configuration. However, since bumps 11 are provided on the surface of the circuit board 10 opposite the surface facing the semiconductor chip 30 for connection to the mounting portion of the semiconductor device, there may be little surplus area for providing the Peltier element 60. In such cases, an embodiment in which the Peltier element 60 is provided on the side opposite the surface facing the circuit-forming layer of the semiconductor chip 30, as shown in Figures 1 to 3, is preferable because it reduces design constraints.

[0039] <Embodiment 5> 5 is a cross-sectional view showing an example of a three-dimensional mounting type semiconductor device according to this embodiment. The semiconductor device 200 shown in FIG. 5 is a semiconductor device having a configuration in which a unit having a face-up type semiconductor chip 30B is stacked on top of a unit having a face-down type semiconductor chip 30A. A Peltier element 60 is located on the upper semiconductor chip 30B. Note that a face-up type semiconductor chip refers to a semiconductor chip in which the electrode terminal forming surface of the semiconductor chip is disposed on the opposite side from the surface facing the circuit board.

[0040] The semiconductor device 200 comprises a face-up semiconductor chip 30B, an adhesive layer 45 that adheres the surface (second surface) of the semiconductor chip 30B opposite to the electrode terminal forming surface to the circuit board 10B, and a metal wire 66 that connects the electrode terminal forming surface (first surface) of the semiconductor chip 30B to an electrode 12B of the circuit forming layer 13 of the circuit board 10B, and these are sealed by a sealant layer 22. 1 and the like is disposed on the upper surface of the sealant layer 22. The upper surface of the sealant layer 22 may be ground or polished to improve flatness and smoothness before the Peltier element 60 is provided, or may be processed to improve adhesion of the connection electrode 63 of the Peltier element 60. A through hole 22b is formed in an edge 22a of the encapsulant layer 22 facing the side surface of the semiconductor chip 30B. A through hole 10Bb is also formed in the circuit board 10B at a position corresponding to the through hole 22b. Vias 80 arranged in the through holes 22b and 10Bb electrically connect the external connection electrode 63 of the Peltier element 60 to the circuit formation layer 13 of the circuit board 10B.

[0041] In the lower unit, a face-down semiconductor chip 30A is mounted on the circuit surface of a circuit board 10A. Bumps 31 provided on the underside of the semiconductor chip 30A are electrically connected to electrodes 12A formed on the surface of the circuit board 10A. An underfill material is filled in the spaces between the underside of the semiconductor chip 30A, the bumps 31, and the circuit surface of the circuit board 10A to form an underfill layer 40. In addition, the side surfaces of the semiconductor chip 30A and the underfill layer 40 are covered and sealed with an encapsulant layer 20.

[0042] An adhesive layer 46 is provided on the upper surfaces of the semiconductor chip 30A and the sealing material layer 20, and they are adhesively fixed to the lower surface of the circuit board 10B of the upper unit. The electrical connection between circuit board 10B included in the upper unit and circuit board 10A included in the lower unit is made by bumps 81.

[0043] In three-dimensional packaging semiconductor devices, the distance between the Peltier element and the circuit formation layer tends to be long. Therefore, the conventional technique of connecting the Peltier element and the circuit formation layer by wire bonding poses a greater problem of high resistance. However, by electrically connecting the Peltier element and the circuit formation layer using a conductor disposed in a through-hole, as in the semiconductor device 200 shown in FIG. 5, the conductive path can be made thicker and shorter, reducing resistance. This makes it easier for the cooling capacity of the Peltier element to be fully utilized even in three-dimensional packaging semiconductor devices.

[0044] In the three-dimensional mounting type semiconductor device 200, one Peltier element 60 can efficiently cool two semiconductor chips 30A and 30B arranged above and below each other. 5, the semiconductor chip 30B is a single layer, but it may be a multi-tiered stack of multiple semiconductor chips. In this case, terminals can be provided on the stepped exposed ends of each semiconductor chip, and wire bonding can be performed to each terminal. Furthermore, a heat dissipation member such as the heat sink 92 in FIG. 1 may be provided on the top surface of the Peltier element 60 (the surface opposite to the surface facing the semiconductor chip 30B).

[0045] Next, the materials of each part constituting the Peltier element will be described.

[0046] [Thermoelectric semiconductor element] The thermoelectric semiconductor element used in the Peltier element is a sintered body of a composition containing a thermoelectric semiconductor material. The thermoelectric semiconductor element is preferably a sintered body of a coating film formed by applying a thermoelectric semiconductor composition containing a thermoelectric semiconductor material to the surface of a support, etc. When the thermoelectric semiconductor element is a sintered body of a coating film of the thermoelectric semiconductor composition, a sheet-like thermoelectric conversion module can be easily produced, and a thermoelectric semiconductor element with improved flexibility can also be easily obtained. The thickness of the thermoelectric semiconductor element is 25 μm or more, more preferably 50 μm or more, and even more preferably 75 μm or more, and is preferably 800 μm or less, more preferably 500 μm or less, and even more preferably 300 μm or less. When the thickness of the thermoelectric semiconductor element is within the above range, it is easy to produce thermoelectric semiconductor elements that exhibit good thermoelectric conversion performance with good productivity.

[0047] <Thermoelectric semiconductor composition> The thermoelectric semiconductor composition used to prepare the thermoelectric semiconductor layer contains at least a thermoelectric semiconductor material, preferably contains thermoelectric semiconductor particles made of the thermoelectric semiconductor material and a resin, and more preferably contains thermoelectric semiconductor particles, a polymer component, and an ionic compound. The ionic compound preferably contains at least one of an ionic liquid and an inorganic ionic compound. As will be described later, a thermoelectric semiconductor layer can be formed by a coating method using a thermoelectric semiconductor composition containing thermoelectric semiconductor particles, a polymer component, and an ionic compound.

[0048] (Thermoelectric semiconductor materials) The thermoelectric semiconductor materials contained in the P-type thermoelectric semiconductor element and the N-type thermoelectric semiconductor element are not particularly limited as long as they are capable of generating thermoelectric power when a temperature difference is applied, and examples thereof include bismuth-tellurium-based thermoelectric semiconductor materials such as P-type bismuth telluride and N-type bismuth telluride; telluride-based thermoelectric semiconductor materials such as GeTe and PbTe; antimony-tellurium-based thermoelectric semiconductor materials; zinc-antimony-based thermoelectric semiconductor materials such as ZnSb, Zn3Sb2, and Zn4Sb3; silicon-germanium-based thermoelectric semiconductor materials such as SiGe; bismuth selenide-based thermoelectric semiconductor materials such as Bi2Se3; β-FeSi2, CrSi2, and MnSi 1.73 Examples of thermoelectric semiconductor materials that can be used include silicide-based thermoelectric semiconductor materials such as Mg2Si; oxide-based thermoelectric semiconductor materials; Heusler materials such as FeVAl, FeVAlSi, and FeVTiAl; sulfide-based thermoelectric semiconductor materials such as TiS2; and skutterudite materials. Among these, from the viewpoint of facilitating high thermoelectric conversion performance, bismuth-tellurium-based thermoelectric semiconductor materials, telluride-based thermoelectric semiconductor materials, antimony-tellurium-based thermoelectric semiconductor materials, and bismuth selenide-based thermoelectric semiconductor materials are preferred. Among these, silicide-based thermoelectric semiconductor materials are preferred from the viewpoint of not containing rare metals whose supply is unstable due to geopolitical issues, and skutterudite materials are preferred from the viewpoint of making it easier to make the thermoelectric conversion module function in high-temperature environments.

[0049] Furthermore, from the viewpoint of high thermoelectric conversion performance in a low-temperature environment, the thermoelectric semiconductor material is preferably a bismuth-tellurium-based thermoelectric semiconductor material such as P-type bismuth telluride or N-type bismuth telluride. P-type bismuth telluride has a positive Seebeck coefficient and a positive carrier. X Te3Sb 2-XThose represented by are preferably used. In this case, X is preferably 0 < X ≤ 0.8, more preferably 0.4 ≤ X ≤ 0.6. When X is greater than 0 and less than or equal to 0.8, the Seebeck coefficient and the electrical conductivity increase, and the characteristics as a P-type thermoelectric conversion material are maintained, which is preferable. In addition, in N-type bismuth telluride, the carriers are electrons and the Seebeck coefficient is a negative value. For example, Bi2Te 3-Y Se Y Those represented by are preferably used. In this case, Y is preferably 0 ≤ Y ≤ 3 (when Y = 0: Bi2Te3), more preferably 0.1 < Y ≤ 2.7. When Y is 0 or more and 3 or less, the Seebeck coefficient and the electrical conductivity increase, and the characteristics as an N-type thermoelectric conversion material are maintained, which is preferable.

[0050] The thermoelectric semiconductor material used for the thermoelectric semiconductor layer is preferably in the form of particles having a predetermined size. For example, it is preferably thermoelectric semiconductor particles pulverized to a predetermined size by using a fine pulverization device such as a ball mill.

[0051] The blending amount of the thermoelectric semiconductor particles in the thermoelectric semiconductor composition is preferably 30 to 99% by mass. More preferably, it is 50 to 96% by mass, and still more preferably, it is 70 to 95% by mass. If the blending amount of the thermoelectric semiconductor particles is within the above range, the Seebeck coefficient (absolute value of the Peltier coefficient) is large, the decrease in electrical conductivity is suppressed, and only the thermal conductivity decreases, so that high thermoelectric performance is exhibited, and a film having sufficient film strength and appropriate flexibility can be obtained, which is preferable.

[0052] The average particle diameter of the thermoelectric semiconductor particles is preferably 10 nm to 200 μm, more preferably 10 nm to 30 μm, still more preferably 50 nm to 10 μm, and particularly preferably 1 to 6 μm. If it is within the above range, uniform dispersion becomes easy and the electrical conductivity can be increased. The method for pulverizing a thermoelectric semiconductor material to obtain thermoelectric semiconductor particles is not particularly limited, and the material may be pulverized to a predetermined size using a known fine pulverizing device such as a jet mill, ball mill, bead mill, colloid mill, conical mill, disk mill, edge mill, flour mill, hammer mill, pellet mill, Willy mill, or roller mill. In this specification, the average particle size of the thermoelectric semiconductor particles is obtained by measurement using a laser diffraction particle size analyzer (manufactured by CILAS, Model 1064), and is a value expressed as the median value of the particle size distribution.

[0053] Furthermore, the thermoelectric semiconductor particles are preferably heat-treated in advance (the "heat treatment" referred to here is different from the "annealing treatment" performed in the annealing treatment step referred to in the present invention). Heat treatment improves the crystallinity of the thermoelectric semiconductor particles and also removes the surface oxide film of the thermoelectric semiconductor particles, thereby increasing the Seebeck coefficient (absolute value of the Peltier coefficient) of the thermoelectric semiconductor material and further improving the thermoelectric figure of merit. The heat treatment is not particularly limited, but is preferably performed before preparing the thermoelectric semiconductor composition in an inert gas atmosphere such as nitrogen or argon, a reducing gas atmosphere such as hydrogen, or under vacuum conditions with a controlled gas flow rate to avoid adversely affecting the thermoelectric semiconductor particles. Heat treatment is more preferably performed in a mixed gas atmosphere of an inert gas and a reducing gas. The specific temperature conditions depend on the thermoelectric semiconductor particles used, but it is usually preferable to perform the heat treatment at a temperature below the melting point of the particles, at 100 to 1500°C, for several minutes to several tens of hours.

[0054] (polymer component) The polymer component that can be contained in the thermoelectric semiconductor composition has the effect of physically bonding the thermoelectric semiconductor material (thermoelectric semiconductor particles) together, and makes it easier to form a thin film by coating or the like for the Peltier element, which is a thermoelectric conversion module. The polymer component is preferably a heat-resistant resin or a binder resin.

[0055] The heat-resistant resin maintains its various physical properties such as mechanical strength and thermal conductivity as a resin without being impaired when the thin film made of the thermoelectric semiconductor composition is annealed or otherwise treated to cause crystal growth of thermoelectric semiconductor particles. The heat-resistant resin is preferably a polyamide resin, a polyamideimide resin, a polyimide resin, or an epoxy resin, because it has higher heat resistance and does not adversely affect the crystal growth of the thermoelectric semiconductor particles in the thin film, and more preferably a polyamide resin, a polyamideimide resin, or a polyimide resin, because it has excellent flexibility.

[0056] The heat-resistant resin preferably has a decomposition temperature of 300° C. or higher. If the decomposition temperature is within the above range, the resin will not lose its function as a binder and will be able to maintain flexibility even when a thin film made of the thermoelectric semiconductor composition is annealed, as will be described later.

[0057] The heat-resistant resin preferably has a mass loss rate of 10% or less, more preferably 5% or less, and even more preferably 1% or less at 300°C as measured by thermogravimetry (TG). As long as the mass loss rate is within the above range, as will be described later, even when a thin film made of the thermoelectric semiconductor composition is annealed, the resin does not lose its function as a binder and the flexibility of the thermoelectric semiconductor material chip can be maintained.

[0058] The content of the heat-resistant resin in the thermoelectric semiconductor composition is 0.1 to 40% by mass, preferably 0.5 to 20% by mass, more preferably 1 to 20% by mass, and even more preferably 2 to 15% by mass. When the content of the heat-resistant resin is within the above range, it functions as a binder for the thermoelectric semiconductor material, making it easier to form a thin film, and a film that achieves both high thermoelectric performance and film strength is obtained, and a resin portion is present on the outer surface of the chip of the thermoelectric semiconductor material.

[0059] The binder resin also facilitates the separation from the substrate, such as glass, alumina, or silicon, used in the production of the thermoelectric semiconductor element after the annealing treatment described below.

[0060] The binder resin refers to a resin that decomposes at 90% by mass or more at a baking (annealing) temperature or higher, more preferably a resin that decomposes at 95% by mass or more, and particularly preferably a resin that decomposes at 99% by mass or more. Furthermore, a resin that maintains various physical properties such as mechanical strength and thermal conductivity without being impaired when a coating film (thin film) made of a thermoelectric semiconductor composition is subjected to a baking (annealing) treatment or the like to cause crystal growth of thermoelectric semiconductor particles is more preferred. When a resin that decomposes at 90% by mass or more at temperatures equal to or higher than the firing (annealing) temperature, i.e., a resin that decomposes at a temperature lower than the heat-resistant resin described above, is used as the binder resin, the binder resin is decomposed by firing, and therefore the content of the binder resin that serves as an insulating component in the fired body is reduced, and crystal growth of the thermoelectric semiconductor particles in the thermoelectric semiconductor composition is promoted, thereby reducing voids in the thermoelectric semiconductor material layer and improving the filling rate. Whether or not a resin decomposes to a predetermined extent (e.g., 90% by mass) at or above the baking (annealing) temperature is determined by measuring the mass loss rate (the value obtained by dividing the mass after decomposition by the mass before decomposition) at the baking (annealing) temperature using thermogravimetry (TG).

[0061] Thermoplastic resins and curable resins can be used as such binder resins. Examples of thermoplastic resins include polyolefin resins such as polyethylene, polypropylene, polyisobutylene, and polymethylpentene; polycarbonate; thermoplastic polyester resins such as polyethylene terephthalate and polyethylene naphthalate; polyvinyl polymers such as polystyrene, acrylonitrile-styrene copolymer, polyvinyl acetate, ethylene-vinyl acetate copolymer, vinyl chloride, polyvinylpyridine, polyvinyl alcohol, and polyvinylpyrrolidone; polyurethane; and cellulose derivatives such as ethyl cellulose. Examples of curable resins include thermosetting resins and photocurable resins. Examples of thermosetting resins include epoxy resins and phenolic resins. Examples of photocurable resins include photocurable acrylic resins, photocurable urethane resins, and photocurable epoxy resins. These resins may be used alone or in combination. Among these, from the viewpoint of the electrical resistivity of the thermoelectric semiconductor material in the thermoelectric semiconductor material layer, thermoplastic resins are preferred, polycarbonate and cellulose derivatives such as ethyl cellulose are more preferred, and polycarbonate is particularly preferred.

[0062] The binder resin is appropriately selected depending on the temperature of the annealing treatment of the thermoelectric semiconductor material in the annealing treatment step. From the viewpoint of the electrical resistivity of the thermoelectric semiconductor material in the thermoelectric semiconductor material layer, it is preferable to perform the annealing treatment at a temperature equal to or higher than the final decomposition temperature of the binder resin. In this specification, the term "final decomposition temperature" refers to the temperature at which the mass reduction rate at the firing (annealing) temperature determined by thermogravimetry (TG) is 100% (the mass after decomposition is 0% of the mass before decomposition).

[0063] The final decomposition temperature of the binder resin is usually 150 to 600° C., preferably 200 to 560° C., more preferably 220 to 460° C., and particularly preferably 240 to 360° C. If a binder resin with a final decomposition temperature within this range is used, it functions as a binder for the thermoelectric semiconductor material, making it easier to form a thin film during printing.

[0064] The content of the binder resin in the thermoelectric semiconductor composition is 0.1 to 40 mass%, preferably 0.5 to 20 mass%, more preferably 0.5 to 10 mass%, and particularly preferably 0.5 to 5 mass%. When the content of the binder resin is within the above range, the electrical resistivity of the thermoelectric semiconductor material in the thermoelectric semiconductor material layer can be reduced.

[0065] The content of the binder resin in the thermoelectric semiconductor material is preferably 0 to 10 mass %, more preferably 0 to 5 mass %, and particularly preferably 0 to 1 mass %. If the content of the binder resin in the thermoelectric semiconductor material is within the above range, the electrical resistivity of the thermoelectric semiconductor material in the thermoelectric semiconductor material layer can be reduced.

[0066] (ionic liquid) The ionic liquid that can be contained in the thermoelectric semiconductor composition is a molten salt formed by combining a cation and an anion, and refers to a salt that can exist in liquid form at any temperature range from -50°C to less than 400°C. In other words, an ionic liquid is an ionic compound with a melting point in the range of -50°C to less than 400°C. The melting point of the ionic liquid is preferably -25°C to 200°C, more preferably 0°C to 150°C. Ionic liquids have characteristics such as extremely low vapor pressure and nonvolatility, excellent thermal and electrochemical stability, low viscosity, and high ionic conductivity. Therefore, as a conductive additive, they can effectively suppress a decrease in electrical conductivity between thermoelectric semiconductor materials. Furthermore, ionic liquids exhibit high polarity due to their aprotic ionic structure and excellent compatibility with heat-resistant resins, thereby enabling the thermoelectric semiconductor material to have a uniform electrical conductivity.

[0067] The ionic liquid may be a known or commercially available one. For example, a nitrogen-containing cyclic cationic compound such as pyridinium, pyrimidinium, pyrazolium, pyrrolidinium, piperidinium, or imidazolium, or a derivative thereof; a tetraalkylammonium-based amine-based cation and a derivative thereof; a phosphine-based cation such as phosphonium, trialkylsulfonium, or tetraalkylphosphonium, or a derivative thereof; a lithium cation and a derivative thereof; or a mixture of a cation component and a Cl cation. - , Br - , I - , AlCl4 - , Al2Cl7 - , BF4 - , PF6 - , ClO4 - , NO3 - , CH3COO - , CF3COO - , CH3SO3 - , CF3SO3 - , (FSO2)2N - , (CF3SO2)2N - , (CF3SO2)3C - , AsF6 - , SbF6 - , NbF6 - , TaF6- , F(HF) n - , (CN)2N - , C4F9SO3 - , (C2F5SO2)2N - , C3F7COO - , (CF3SO2)(CF3CO)N - and an anion component such as the above.

[0068] Among the above-mentioned ionic liquids, from the viewpoints of high-temperature stability, compatibility with thermoelectric semiconductor materials and resins, and suppression of a decrease in the electrical conductivity of the gaps between thermoelectric semiconductor materials, it is preferred that the cationic component of the ionic liquid contains at least one selected from pyridinium cations and derivatives thereof, and imidazolium cations and derivatives thereof.

[0069] Specific examples of ionic liquids whose cationic component contains a pyridinium cation and its derivatives include 4-methyl-butylpyridinium chloride, 3-methyl-butylpyridinium chloride, 4-methyl-hexylpyridinium chloride, 3-methyl-hexylpyridinium chloride, 4-methyl-octylpyridinium chloride, 3-methyl-octylpyridinium chloride, 3,4-dimethyl-butylpyridinium chloride, 3,5-dimethyl-butylpyridinium chloride, 4-methyl-butylpyridinium tetrafluoroborate, 4-methyl-butylpyridinium hexafluorophosphate, 1-butylpyridinium bromide, 1-butyl-4-methylpyridinium bromide, 1-butyl-4-methylpyridinium hexafluorophosphate, etc. Among these, 1-butyl-4-methylpyridinium bromide, 1-butylpyridinium bromide, and 1-butyl-4-methylpyridinium hexafluorophosphate are preferred.

[0070] Specific examples of ionic liquids in which the cation component contains an imidazolium cation or a derivative thereof include [1-butyl-3-(2-hydroxyethyl)imidazolium bromide], [1-butyl-3-(2-hydroxyethyl)imidazolium tetrafluoroborate], 1-ethyl-3-methylimidazolium chloride, 1-ethyl-3-methylimidazolium bromide, 1-butyl-3-methylimidazolium chloride, 1-hexyl-3-methylimidazolium chloride, 1-octyl-3-methylimidazolium chloride, 1-decyl-3-methylimidazolium chloride, and 1-decyl-3-methylimidazolium chloride. Examples of the imidazolium bromide include 1-dodecyl-3-methylimidazolium chloride, 1-tetradecyl-3-methylimidazolium chloride, 1-ethyl-3-methylimidazolium tetrafluoroborate, 1-butyl-3-methylimidazolium tetrafluoroborate, 1-hexyl-3-methylimidazolium tetrafluoroborate, 1-ethyl-3-methylimidazolium hexafluorophosphate, 1-butyl-3-methylimidazolium hexafluorophosphate, 1-methyl-3-butylimidazolium methyl sulfate, and 1,3-dibutylimidazolium methyl sulfate. Among these, 1-butyl-3-(2-hydroxyethyl)imidazolium bromide and 1-butyl-3-(2-hydroxyethyl)imidazolium tetrafluoroborate are preferred.

[0071] The above ionic liquid has an electrical conductivity of 10 -7 If the ionic conductivity is in the above range, the conductive additive can effectively suppress a decrease in the electrical conductivity between the thermoelectric semiconductor materials.

[0072] The ionic liquid preferably has a decomposition temperature of 300° C. or higher. If the decomposition temperature is within the above range, the ionic liquid can maintain its effect as a conductive additive even when a thin film made of the thermoelectric semiconductor composition is annealed, as described below.

[0073] Furthermore, the ionic liquid preferably has a mass loss rate of 10% or less, more preferably 5% or less, and even more preferably 1% or less at 300°C as measured by thermogravimetry (TG). If the mass loss rate is within the above range, the ionic liquid can maintain its effectiveness as a conductive additive even when a thin film made of the thermoelectric semiconductor composition is annealed, as described below.

[0074] The amount of the ionic liquid in the thermoelectric semiconductor composition is preferably 0.01 to 50 mass%, more preferably 0.5 to 30 mass%, and even more preferably 1.0 to 20 mass%. When the amount of the ionic liquid is within the above range, a decrease in electrical conductivity is effectively suppressed, and a film with high thermoelectric performance is obtained.

[0075] (inorganic ionic compounds) The inorganic ionic compound that can be contained in the thermoelectric semiconductor composition is a compound composed of at least a cation and an anion. The inorganic ionic compound exists in a solid state over a wide temperature range from 400 to 900°C and has characteristics such as high ionic conductivity, so that it can act as a conductive additive to suppress a decrease in electrical conductivity between thermoelectric semiconductor materials.

[0076] As the cation constituting the inorganic ionic compound, a metal cation is used. Examples of metal cations include alkali metal cations, alkaline earth metal cations, typical metal cations and transition metal cations, with alkali metal cations and alkaline earth metal cations being more preferred. Examples of alkali metal cations include Li + , Na + , K. + , Rb + , Cs + and Fr + etc. Examples of alkaline earth metal cations include Mg 2+ , Ca 2+ , Sr 2+ and Ba 2+ etc.

[0077] Examples of the anion constituting the inorganic ionic compound include F - , Cl - , Br - , I - , O.H. - , C.N. - , NO3 - , NO2 - , ClO - , ClO2 - , ClO3 - , ClO4 - , CrO4 2- , HSO4 - , SCN - , BF4 - , PF6 - etc.

[0078] The inorganic ionic compound contained in the thermoelectric semiconductor layer may be a known or commercially available one. For example, a cationic component such as potassium cation, sodium cation, or lithium cation and a Cl - , AlCl4 - , Al2Cl7 - , ClO4 - Chloride ions such as Br - bromide ions, such as I - Iodide ions such as BF4 - , PF6 - Fluoride ions such as F(HF) n - Halide anions such as NO3 - , O.H. - , C.N. - and an anion component such as the above.

[0079] Among the above inorganic ionic compounds, from the viewpoints of high-temperature stability, compatibility with thermoelectric semiconductor materials and resins, and suppression of a decrease in the electrical conductivity of the gaps between thermoelectric semiconductor materials, it is preferable that the cationic component of the inorganic ionic compound contains at least one selected from potassium, sodium, and lithium. Also, it is preferable that the anionic component of the inorganic ionic compound contains a halide anion, and Cl - , Br - , and I -It is more preferable that the composition contains at least one selected from the following:

[0080] Specific examples of inorganic ionic compounds in which the cationic component contains potassium cations include KBr, KI, KCl, KF, KOH, K2CO3, etc. Among these, KBr and KI are preferred. Specific examples of inorganic ionic compounds in which the cationic component contains a sodium cation include NaBr, NaI, NaOH, NaF, Na2CO3, etc. Among these, NaBr and NaI are preferred. Specific examples of inorganic ionic compounds in which the cationic component contains lithium cations include LiF, LiOH, LiNO3, etc. Among these, LiF and LiOH are preferred.

[0081] The above inorganic ionic compounds have an electrical conductivity of 10 -7 S / cm or more is preferable, and 10 -6 If the electrical conductivity is in the above range, the conductive additive can effectively suppress a decrease in electrical conductivity between thermoelectric semiconductor materials.

[0082] The inorganic ionic compound preferably has a decomposition temperature of 400° C. or higher. If the decomposition temperature is within the above range, the effect as a conductive additive can be maintained even when a thin film made of the thermoelectric semiconductor composition is annealed, as described below.

[0083] Furthermore, the inorganic ionic compound preferably exhibits a mass loss rate of 10% or less, more preferably 5% or less, and even more preferably 1% or less at 400°C as measured by thermogravimetry (TG). If the mass loss rate is within the above range, the compound can easily maintain its effectiveness as a conductive additive even when a thin film made of the thermoelectric semiconductor composition is annealed, as described below.

[0084] The amount of the inorganic ionic compound in the thermoelectric semiconductor composition is preferably 0.01 to 50 mass%, more preferably 0.5 to 30 mass%, and even more preferably 1.0 to 10 mass%. If the amount of the inorganic ionic compound is within the above range, a decrease in electrical conductivity can be effectively suppressed, resulting in a film with improved thermoelectric performance. When an inorganic ionic compound and an ionic liquid are used in combination, the total content of the inorganic ionic compound and the ionic liquid in the thermoelectric semiconductor composition is preferably 0.01 to 50 mass%, more preferably 0.5 to 30 mass%, and even more preferably 1.0 to 10 mass%.

[0085] (Method for preparing thermoelectric semiconductor composition) There are no particular limitations on the method for preparing the thermoelectric semiconductor composition. The thermoelectric semiconductor composition may be prepared by using a known device such as an ultrasonic homogenizer, a spiral mixer, a planetary mixer, a disperser, or a hybrid mixer to mix and disperse a thermoelectric semiconductor material, a heat-resistant resin, and, if necessary, one or both of an ionic liquid and an inorganic ionic compound, other additives, and a solvent. A solvent may be used when preparing the thermoelectric semiconductor composition. Examples of the solvent that may be used include toluene, ethyl acetate, methyl ethyl ketone, alcohol, tetrahydrofuran, methylpyrrolidone, and ethyl cellosolve. These solvents may be used alone or in combination of two or more. The solids concentration of the thermoelectric semiconductor composition is not particularly limited as long as the composition has a viscosity suitable for coating.

[0086] [Method of manufacturing semiconductor device] As an example of a method for manufacturing a semiconductor device, a method for manufacturing a semiconductor device having a coating-type Peltier element will be described.

[0087] <Formation of thermoelectric semiconductor element> When fabricating a semiconductor device having a coating-type Peltier element, the thermoelectric semiconductor element is not particularly limited, but can be obtained by, for example, applying the thermoelectric semiconductor composition to a substrate such as glass, alumina, silicon, or a resin film, or to a substrate on which a sacrificial layer (described later) is formed, obtaining a coating film, drying the film, and appropriately separating the film from the substrate. By forming the thermoelectric semiconductor element in this manner, a large number of thermoelectric semiconductor elements can be obtained easily and at low cost. The resin film is preferably heat-resistant, and films made of polyamide resin, polyamideimide resin, polyimide resin, etc. are preferred.

[0088] Methods for applying the thermoelectric semiconductor composition to form a coating film include, but are not limited to, known methods such as screen printing, flexographic printing, gravure printing, spin coating, dip coating, die coating, spray coating, bar coating, doctor blade, etc. When forming a coating film in a pattern, screen printing, slot die coating, etc., which allow for easy pattern formation using a screen plate having a desired pattern, are preferably used. The resulting coating film is then dried to form a thermoelectric semiconductor element, and the drying method may be a conventionally known drying method such as hot air drying, hot roll drying, infrared irradiation, etc. The heating temperature is usually 80 to 150°C, and the heating time varies depending on the heating method, but is usually several seconds to several tens of minutes.

[0089] When a solvent is used in preparing the thermoelectric semiconductor composition, the heating temperature is not particularly limited as long as it is within a temperature range that allows the solvent used to be dried.

[0090] The thickness of the coating film made of the thermoelectric semiconductor composition is not particularly limited, but from the viewpoint of thermoelectric performance and film strength, it is preferably 100 nm to 1000 μm, more preferably 300 nm to 600 μm, and even more preferably 5 to 400 μm.

[0091] The coating film of the thermoelectric semiconductor composition is preferably further annealed to form a fired body. Annealing stabilizes the thermoelectric performance and promotes crystal growth of the thermoelectric semiconductor particles in the thin film, further improving the thermoelectric performance. The annealing is not particularly limited, but is typically performed under a controlled gas flow rate in an inert gas atmosphere such as nitrogen or argon, a reducing gas atmosphere, or under vacuum conditions. Depending on the heat resistance temperature of the resin and ionic compound used, the annealing is performed at 100 to 500°C for several minutes to several tens of hours. Furthermore, during the annealing, the thermoelectric semiconductor composition may be pressed to increase its density.

[0092] The sacrificial layer can be made of a resin such as polymethyl methacrylate or polystyrene, or a release agent such as a fluorine-based release agent or a silicone-based release agent. By using the sacrificial layer, the thermoelectric semiconductor element formed on a substrate such as glass can be easily peeled off from the glass after annealing. The method for forming the sacrificial layer is not particularly limited, and can be performed by a known method such as flexographic printing or spin coating.

[0093] <Insulator filling> To ensure insulation between the obtained thermoelectric semiconductor elements, an insulator is filled between the thermoelectric semiconductor elements. The insulator in the N-type thermoelectric semiconductor element ensures insulation between the P-type thermoelectric semiconductor element and the N-type thermoelectric semiconductor element, and between the P-type thermoelectric semiconductor elements and between the N-type thermoelectric semiconductor elements, and also serves as a reinforcing material to maintain mechanical strength when the elements are integrated. There are no particular restrictions on the insulator as long as it can maintain insulation and strength, but examples include insulating resins and ceramics.

[0094] Examples of insulating resins include polyimide resins, silicone resins, rubber resins, acrylic resins, olefin resins, maleimide resins, and epoxy resins. From the viewpoint of heat resistance and mechanical strength, the insulating resin is preferably selected from polyimide resins, silicone resins, acrylic resins, maleimide resins, and epoxy resins. The insulating resin is preferably a curable resin or a foamable resin. The insulating resin may further contain a filler. A hollow filler is preferred as the filler. The hollow filler is not particularly limited, and known hollow fillers can be used. Examples of hollow fillers include inorganic hollow fillers such as glass balloons, silica balloons, shirasu balloons, fly ash balloons, and metal silicates, as well as organic resin hollow fillers such as acrylonitrile, vinylidene chloride, phenolic resins, epoxy resins, and urea resins. The use of hollow fillers reduces the thermal conductivity of the insulating resin, further improving thermoelectric performance. Examples of ceramics include materials containing aluminum oxide (alumina), aluminum nitride, zirconium oxide (zirconia), silicon carbide, etc. as their main components (50% by mass or more of the ceramics). In addition to the main components, rare earth compounds, for example, can also be added.

[0095] The insulator filling method can be performed by a known method. For example, a liquid resin is used to spread and fill the surface of a support on which chips of P-type thermoelectric semiconductor material and chips of N-type thermoelectric semiconductor material are alternately arranged using a coating member such as a squeegee. Alternatively, the resin is dripped from approximately the center of the support to the outside and then filled by spin coating. Furthermore, the support is immersed in a liquid resin reservoir or the like and then lifted up to fill. Furthermore, a sheet-like insulating resin is used to attach the sheet-like insulating resin to the surface of a support on which chips of P-type thermoelectric semiconductor material and chips of N-type thermoelectric semiconductor material are alternately arranged, and the sheet-like insulating resin is melted and filled by heating and / or pressing. After filling, thermal curing or the like is performed.

[0096] The support is not particularly limited and may be glass, silicon, ceramics, metal, plastic, or the like. Preferably, it is selected from glass, plastic, and silicon. When annealing or the like is performed at high temperatures, glass, silicon, ceramics, or metal is preferred. The thickness of the support is preferably from 100 to 1200 μm, more preferably from 200 to 800 μm, and even more preferably from 400 to 700 μm, from the viewpoints of process and dimensional stability. The support is peeled off after the integration of the thermoelectric semiconductor elements and the insulators positioned between them is obtained.

[0097] <Formation of connection electrodes> Next, connection electrodes are formed to be used for connecting the pair of thermoelectric semiconductor elements or for external connection. The connection electrodes are preferably formed of at least one film selected from the group consisting of a vapor-deposited film, a plated film, a conductive composition, and a metal foil. The metal material used for the connection electrodes is not particularly limited, but examples thereof include copper, gold, nickel, aluminum, rhodium, platinum, chromium, palladium, stainless steel, molybdenum, solder, and alloys containing any of these metals.

[0098] Methods for forming the connection electrodes include a method in which an electrode without a pattern is provided on the aforementioned integrated product of multiple thermoelectric semiconductor elements and an insulator layer, and then processed into a predetermined pattern shape by known physical or chemical treatments, mainly photolithography, or a combination of these, or a method in which a conductive paste made of a conductive composition containing the above-mentioned metal material, etc., is used to directly form an electrode pattern by screen printing, inkjet printing, etc. Examples of methods for forming electrodes without patterns include dry processes such as PVD (physical vapor deposition) methods such as vacuum deposition, sputtering, and ion plating, or CVD (chemical vapor deposition) methods such as thermal CVD and atomic layer deposition (ALD), or wet processes such as various coating methods and electrodeposition methods such as dip coating, spin coating, spray coating, gravure coating, die coating, and doctor blade methods, silver halide plating, electroplating, electroless plating, and metal foil lamination, which are appropriately selected depending on the electrode material. The metal foil lamination may be joined to a thermoelectric material or the like using solder. The connecting electrodes are required to have high electrical conductivity and high thermal conductivity in order to maintain thermoelectric performance, so it is more preferable to use electrodes formed by plating or vacuum film formation. Vacuum film formation methods such as vacuum deposition and sputtering, as well as electroplating and electroless plating, are preferred because they can easily achieve high electrical conductivity and high thermal conductivity. Depending on the dimensions and dimensional accuracy required for the formed pattern, a pattern can also be easily formed via a hard mask such as a metal mask.

[0099] The thickness of the connection electrode layer is preferably 10 nm to 200 μm, more preferably 30 nm to 150 μm, and even more preferably 50 nm to 120 μm. If the thickness of the connection electrode layer is within the above range, the electrical conductivity is high and the resistance is low, and sufficient strength as a connection electrode is obtained.

[0100] <Formation of adhesive layer> An adhesive layer is provided on at least one surface of a Peltier element, which is a thermoelectric conversion module. Specifically, when a connection electrode connecting one end of adjacent thermoelectric semiconductor elements is defined as a first electrode and a connection electrode connecting the other end of adjacent thermoelectric semiconductor elements is defined as a second electrode, an adhesive layer is provided on both or either of the first and second electrodes, including the gap between adjacent first electrodes and the gap between adjacent second electrodes. The adhesive layer can be used to easily attach the Peltier element to, for example, a semiconductor chip, which is an adherend. Furthermore, the inclusion of the gap between the first electrodes and the gap between the second electrodes can improve weather resistance. Furthermore, insulation between the adherend and the connection electrodes of the Peltier element can be ensured. The adhesive layer may be formed in advance on the surface of the adherend.

[0101] The pressure-sensitive adhesive layer is not particularly limited as long as it can be easily adhered to an adherend such as a semiconductor chip, which is an object to be cooled, but it preferably contains an adhesive resin, and may optionally contain pressure-sensitive adhesive additives such as a crosslinking agent, a tackifier, a polymerizable compound, a polymerization initiator, a silane coupling agent, an antistatic agent, an antioxidant, an ultraviolet absorber, a light stabilizer, a softener, a filler, a refractive index adjuster, a colorant, etc. Among these, from the viewpoint of improving the thermal conductivity of the pressure-sensitive adhesive layer, boron nitride filler, alumina filler, etc. may be used as the filler. In this specification, the term "tacky adhesive resin" is a concept that includes both a resin having tackiness and a resin having adhesive properties, and includes, for example, not only resins that themselves have tacky adhesive properties, but also resins that exhibit tackiness when used in combination with other components such as additives, and resins that exhibit adhesive properties in the presence of a trigger such as heat or water.

[0102] Examples of adhesive resins include rubber-based resins such as acrylic resins, urethane resins, and polyisobutylene resins, polyester resins, olefin resins, silicone resins, and polyvinyl ether resins. The thickness of the adhesive layer is not particularly limited, but is preferably 1 to 50 μm, and more preferably 2 to 30 μm.

[0103] The adhesive layer may be formed directly on the electrode on the integrated product from an adhesive composition containing an adhesive resin by a known method, such as spin coating, spray coating, bar coating, knife coating, roll coating, roll knife coating, blade coating, die coating, or gravure coating.

[0104] At least one surface of the pressure-sensitive adhesive layer may be covered with a release film until it is bonded to the adherend. The release film is not particularly limited, but from the viewpoint of ease of handling, it is preferable that the release film comprises a release substrate and a release agent layer formed by applying a release agent to the release substrate. The release film may comprise a release agent layer on only one side of the release substrate, or on both sides of the release substrate. Examples of release substrates include paper substrates, laminated paper obtained by laminating a thermoplastic resin such as polyethylene to the paper substrate, and plastic films. Examples of paper substrates include glassine paper, coated paper, and cast-coated paper. Examples of plastic films include polyester films such as polyethylene terephthalate, polybutylene terephthalate, and polyethylene naphthalate, as well as polyolefin films such as polypropylene and polyethylene. Examples of release agents include olefin-based resins, rubber-based elastomers (e.g., butadiene-based resins, isoprene-based resins, etc.), long-chain alkyl resins, alkyd-based resins, fluorine-based resins, and silicone-based resins.

[0105] The thickness of the release film is not particularly limited, but is usually 20 to 200 μm, and preferably 25 to 150 μm. The thickness of the release agent layer is not particularly limited, but when the release agent layer is formed by applying a solution containing a release agent, the thickness of the release agent layer is preferably 0.01 to 2.0 μm, and more preferably 0.03 to 1.0 μm. When a plastic film is used as the release substrate, the thickness of the plastic film is preferably 3 to 50 μm, and more preferably 5 to 40 μm.

[0106] The adhesive layer having a release film is produced, for example, through the following steps. First, a pressure-sensitive adhesive composition is applied onto a release film to form a coating film. Next, the coating film is dried to form a pressure-sensitive adhesive layer. Next, the pressure-sensitive adhesive layer on the release film and the electrode on the integrated product are bonded together to produce the electrode.

[0107] <Installation of Peltier element> The Peltier element is attached to an adherend such as a semiconductor chip by the adhesive layer, thereby mounting the Peltier element on the back surface of the semiconductor chip.

[0108] [Another Example of a Manufacturing Method for a Semiconductor Device] When the annealing treatment is not performed or when the annealing temperature is not high (for example, about 180 to 300° C.), the thermoelectric semiconductor element can be produced on an adherend instead of on the substrate. In this case, the method for manufacturing a semiconductor device can include the following steps (i) and (ii). (i) a coating step of applying a composition containing a thermoelectric semiconductor material onto a first surface of the semiconductor chip on which electrode terminals are formed, or onto a second surface opposite to the first surface, to obtain a coating film; and (ii) an annealing step of annealing the coating film to obtain a thermoelectric semiconductor layer that constitutes the Peltier element;

[0109] More specifically, instead of providing the Peltier element with the above-mentioned adhesive layer, a passivation film is formed on the adherend as needed, and then a lower connection electrode is formed directly on the surface of the adherend or on the passivation film, or an upper connection electrode is formed on the surface of the circuit board opposite to the surface on which the semiconductor chip is mounted. A thermoelectric semiconductor material composition is then applied, and drying and annealing treatments are performed as needed to produce a thermoelectric semiconductor element. Then, after filling the spaces between the thermoelectric semiconductor elements with the above-mentioned insulator, a connection electrode is formed on the side opposite to the side on which the electrode has already been formed. Thereafter, as needed, an adhesive layer is formed on the connection electrode on the side on which the electrode has been formed later. In this case, if the adhesive layer is curable, the adhesiveness of the adhesive layer on the later-formed, exposed side can be easily eliminated by curing the adhesive layer.

[0110] In the coating step, a coating film may be obtained by coating a composition containing the thermoelectric semiconductor material on the second surface of a semiconductor chip of a component for a semiconductor device, the component comprising the semiconductor chip and a connection layer electrically connected by electrode terminals on the first surface of the semiconductor chip. Here, the component for a semiconductor device refers to a semi-finished product including a semiconductor chip before the semiconductor device is completed, and for example, a circuit board on which a semiconductor chip is mounted before a Peltier element is provided corresponds to the component for a semiconductor device.

[0111] In this way, by forming the thermoelectric semiconductor element on the adherend by a coating method, the Peltier element can be formed and positioned following the step of preparing the adherend including the semiconductor chip, thereby improving the productivity of the semiconductor device.

[0112] Figure 6 is a schematic process diagram showing an example of a method for manufacturing a semiconductor device including the above steps (i) and (ii), and is an example of a method for manufacturing a semiconductor device 100E having a configuration similar to that of the semiconductor device 100A of Figure 1. 6(a), a semiconductor device component is first prepared in advance according to a known manufacturing method, in which a semiconductor chip 30 is mounted in a recess of a circuit board 10. In the semiconductor device component, an underfill layer 40 is formed in the spaces between the lower surface (first surface) of the semiconductor chip 30, the bumps 31, and the electrode formation layer 13 of the circuit board 10, and an encapsulant layer 20 is formed between the two semiconductor chips and between an edge portion 10a of the circuit board 10 and the side surfaces of the semiconductor chip 30 and Peltier element 60. The upper surface (second surface) of the semiconductor chip 30, the upper surface of the encapsulant layer 20, and the upper surface of the edge portion 10a of the circuit board 10 are arranged in the same plane. A via 80 made of a conductor is disposed in a through hole 10b formed in the edge portion 10a of the circuit board 10, and the upper surface of the via 80 is exposed to the upper surface of the edge portion 10a and is included in the above plane.

[0113] 6(b), an insulating material is applied to form an insulating thin film 69 as a passivation film on the flat surface. At this time, a mask or the like is provided on the upper surface of the via 80 to prevent the formation of the insulating thin film 69. As with the insulator layer 65 described above, an insulating resin such as polyimide resin can be used as the insulating material. However, the insulating material used for the insulating thin film 69 does not need to have low thermal conductivity; rather, the thermal conductivity may be increased by adding a thermally conductive filler or the like.

[0114] 6(c), the lower surface side connection electrode 63 is patterned on the insulating thin film 69 using the procedure described above. At this time, a conductor such as solder is placed on the upper surface of the via 80, and the connection electrode 63, which serves as a terminal for external connection, is formed in a position overlapping the conductor on the upper surface of the via 80, thereby electrically connecting the connection electrode 63 and the via 80. Note that the formation of the insulating thin film 69 may be omitted, and the connection electrode 63 may be formed directly on the flat surface.

[0115] 6(d), the thermoelectric semiconductor composition is applied onto the connection electrodes 63 according to the above-described procedure, and is dried and annealed as necessary to form the thermoelectric semiconductor elements 61 and 62. Furthermore, an insulator is disposed according to the above-described procedure between adjacent thermoelectric semiconductor elements and around the thermoelectric semiconductor elements located at the ends to form an insulator layer 65.

[0116] 6(e), the upper surface connection electrodes 63 are formed on the upper surfaces of the thermoelectric semiconductor elements 61, 62 using the procedure described above. Then, an adhesive is placed on the upper surfaces of the connection electrodes 63 and the insulator layer 65 to form an adhesive layer 64. As a result, the Peltier element 60 is formed on the second surface of the semiconductor chip 30, and the semiconductor device 100E is obtained. If necessary, a heat dissipation member such as a heat sink 92 may be provided on the adhesive layer 64. The adhesive layer 64 may be cured to eliminate its adhesive properties, or a covering layer other than the adhesive layer 64 may be provided. [Industrial Applicability]

[0117] The semiconductor element of the present invention can provide a semiconductor device and a manufacturing method thereof that can easily enhance the cooling effect and can be easily thinned, and thus can be used as a semiconductor device for applications requiring high output or applications requiring installation in limited or narrow spaces. [Explanation of symbols]

[0118] 10, 10A, 10B: Circuit board 10a: Edge of circuit board (covering) 10b, 10Bb: Through hole 11, 31, 81: Bump 12, 12A, 12B: Electrode 13: Circuit formation layer (connected layer) 14: Passivation layer 20, 22: Encapsulant layer 20a, 22a: Peripheral portion of the sealing material layer (covering body) 20b, 22b: Through hole 30, 30A, 30B: Semiconductor chip 40: Underfill layer 45, 46: Adhesive layer 60: Peltier element 61: P-type thermoelectric semiconductor element 62: N-type thermoelectric semiconductor element 63: Connection electrode 64:Adhesive layer 65: Insulator layer 66: Metal wire 69: Insulating thin film 80: Via (conductor) 92: Heat sink 100A, 100B, 100C, 100D, 100E: Semiconductor device 200: Three-dimensional packaging type semiconductor device

Claims

1. a semiconductor chip having a first surface on which electrode terminals are formed and a second surface opposite to the first surface; and a Peltier element provided on the second surface or the first surface; the Peltier element has a thermoelectric semiconductor layer including a plurality of thermoelectric semiconductor elements; the thermoelectric semiconductor element is a sintered body of a coating film of a composition containing a thermoelectric semiconductor material, The semiconductor device further comprises insulating resin filled between the plurality of thermoelectric semiconductor elements, the insulating resin being thermally cured.

2. a connection layer facing the first surface of the semiconductor chip and electrically connected to the semiconductor chip; 2. The semiconductor device according to claim 1, wherein the semiconductor chip is electrically connected to the connection layer by electrode terminals on the first surface, and the Peltier element is provided on the second surface.

3. 3. The semiconductor device according to claim 1, wherein adjacent said thermoelectric semiconductor elements are spaced apart from each other, and a reinforcing material is filled in the gaps between adjacent said thermoelectric semiconductor elements.

4. 4. The semiconductor device according to claim 1, wherein the composition containing the thermoelectric semiconductor material comprises a polymer component, an ionic compound, and thermoelectric semiconductor particles.

5. A method for manufacturing a semiconductor device including a Peltier element having a thermoelectric semiconductor layer including a plurality of thermoelectric semiconductor elements, comprising: (i) a coating step of applying a composition containing a thermoelectric semiconductor material onto a first surface of a semiconductor chip on which electrode terminals are formed, or onto a second surface opposite to the first surface, to obtain a coating film; (ii) an annealing step of annealing the coating film to obtain a thermoelectric semiconductor layer that constitutes the Peltier element; and (iii) filling an insulating resin between the plurality of thermoelectric semiconductor elements and thermally curing the insulating resin.

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein in the coating step, a composition containing the thermoelectric semiconductor material is applied onto a second surface of a semiconductor chip of a semiconductor device component comprising the semiconductor chip and a connection layer electrically connected by electrode terminals on a first surface of the semiconductor chip to obtain a coating film.

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