Comparator circuit and power supply

Abstract

A comparator circuit (2) according to the present invention comprises a comparator (5) which detects an abnormal voltage of a secondary battery (1) and uses a PMOS transistor or an NMOS transistor as a differential pair. The comparator circuit (2) comprises a control circuit (3) that provides such control that voltages of two input terminals of the comparator (5) are equal to each other in a standby state in which an operation of the comparator circuit (2) is in a stop state.

Description

Technical Field

[0001] The present invention relates to a comparator circuit using, for example, a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) or an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) as a differential pair, and a power supply device using the comparator. circuit

Background Art

[0002] Conventionally, various techniques for countermeasures against characteristic degradation due to NBTI (Negative Bias Temperature Instability) have been disclosed in a comparator circuit using a PMOS transistor as a differential pair.

[0003] When the chip temperature rises with the substrate potential negative with respect to the gate electrode of the PMOS transistor, the absolute value of the threshold voltage of the PMOS transistor gradually increases, and the characteristics (Ids, Vth) of the PMOS transistor fluctuate. Here, the phenomenon in which the degradation of the element progresses regardless of the operation of the PMOS transistor in a state where a negative bias voltage is applied is called NBTI. In particular, characteristic degradation occurs by varying the threshold value in a state where the drain voltage is higher than the gate voltage.

[0004] For example, in Patent Document 1, a comparator circuit according to a conventional example has been proposed for easily suppressing an increase in the drain voltage of a PMOS transistor constituting a differential pair. The comparator circuit includes a first and a second PMOS transistor constituting a differential pair, a first switching transistor having a main current path connected between an input terminal and the gate of the first PMOS transistor, a voltage source for applying a reference voltage to the gate of the second PMOS transistor, and a first bias circuit for applying a first bias voltage to the control electrode of the first switching transistor.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-120320 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] In the conventional battery voltage monitoring circuit including the comparator circuit described above, an input potential difference is likely to occur in the comparator circuit, and it is not possible to suppress the occurrence of NBTI when the reference voltage circuit is stopped. In particular, in lithium battery protection circuits, the circuit may remain in standby mode for a long period of time, such as in factory default mode, and at that time the reference voltage circuit may stop, causing NBTI to occur. Furthermore, in comparator circuits using NMOS transistors as differential pairs, characteristic degradation due to PBTI (Positive Bias Temperature Instability) occurs in a similar manner to NBTI.

[0007] The object of the present invention is to solve the above problems and to provide a comparator circuit that uses PMOS transistors or NMOS transistors as a differential pair and can suppress the generation of NBTI or PBTI regardless of the input potential difference of the comparator circuit, and a power supply device using the comparator circuit. [Means for solving the problem]

[0008] A comparator circuit according to one aspect of the present invention is: A comparator for detecting abnormal voltage in a secondary battery, comprising a comparator circuit that uses PMOS transistors or NMOS transistors as a differential pair, The system includes a control circuit that controls the voltages at the two input terminals of the comparator to be equal when the comparator circuit is in a standby state where it is not operating. [Effects of the Invention]

[0009] Accordingly, according to one aspect of the present invention, in a comparator circuit using PMOS transistors or NMOS transistors as a differential pair, the occurrence of NBTI or PBTI can be suppressed regardless of the input potential difference of the comparator circuit. [Brief explanation of the drawing]

[0010] [Figure 1] This is a circuit diagram showing an example of the configuration of a comparator circuit according to Embodiment 1. [Figure 2] This is a circuit diagram showing an example configuration of a comparator circuit according to Embodiment 2. [Figure 3] This is a circuit diagram showing an example configuration of a power supply device using a comparator circuit according to Embodiment 3. [Figure 4] This is a circuit diagram showing an example configuration of a power supply device using a comparator circuit according to Embodiment 4. [Figure 5] This is a circuit diagram showing an example configuration of a power supply unit using a standby control circuit according to Embodiment 5. [Figure 6] This is a circuit diagram showing the configuration of a comparator circuit related to a comparative example. [Figure 7] This is a circuit diagram showing the configuration of a comparator circuit related to a comparative example. [Figure 8] This is a circuit diagram showing a known configuration of a comparator circuit related to a comparative example. [Modes for carrying out the invention]

[0011] Embodiments and modified examples of the present invention will be described below with reference to the drawings. The same or similar components are denoted by the same reference numerals.

[0012] (Inventor's insights) FIG. 6 is a circuit diagram showing the configuration of a comparator circuit according to a comparative example. The comparator circuit in FIG. 6 is a circuit used in, for example, an abnormal voltage detection circuit used in a lithium battery protection IC, and includes a comparator 101 that uses a PMOS transistor as a differential pair as in Patent Document 1, voltage dividing resistors R101 and R102, a reference voltage source 102 having a reference voltage Vref, and switches SW101 and SW102.

[0013] In the comparator circuit configured as described above, when set to the manufacturing and shipping mode, switch SW101 is turned off and switch SW102 is turned on. At this time, a predetermined bias voltage is applied to the inverting input terminal of the comparator circuit, and an input potential difference of the comparator occurs. That is, NBTI occurs in a state where the operation of the reference voltage circuit is stopped.

[0014] In order to solve this problem, the present inventors devised a comparator circuit according to the following embodiment. An example of a comparator using a PMOS transistor as a differential pair used in FIG. 6 and the like will be described below with reference to FIG. 7.

[0015] FIG. 7 is a circuit diagram showing the configuration of a comparator circuit according to a comparative example disclosed in Patent Document 1. The comparator circuit in FIG. 7 is, for example, an abnormal voltage detection circuit that detects a case where an input voltage Vin is lower than a reference voltage Vref as an abnormality. The comparator circuit 201 has PMOS transistors M1 and M2 that form a differential pair. The sources of the PMOS transistors M1 and M2 are commonly connected to one end of a current source 212. The other end of the current source 212 is connected to a power supply line 211. The gate of the PMOS transistor M1 is connected to an input terminal T201 to which the input voltage Vin is applied via an NMOS transistor M5. The gate of the PMOS transistor M2 is connected to a reference voltage source 203 that supplies the reference voltage Vref.

[0016] The NMOS transistor M5 has a source-drain path, which is the main current path, connected between the input terminal T201 and the gate of the PMOS transistor M1. The drain of the NMOS transistor M5 is connected to the input terminal T201, and the source is connected to the gate of the PMOS transistor M1. A bias voltage V1 is applied to the gate of the NMOS transistor M5 by the bias circuit 220.

[0017] The bias circuit 220 has an NMOS transistor M6 connected in diode configuration. The drain and the gate of the NMOS transistor M6 are connected to one end of the constant current source 221, and the source is connected to the reference voltage source 203. The other end of the constant current source 221 is connected to the power supply line 211. The gate voltage of the NMOS transistor M6 becomes a voltage that is higher than the reference voltage Vref by the gate-source voltage Vgs of the NMOS transistor M6. Therefore, the bias voltage V1 is Vref + Vgs.

[0018] An NMOS transistor M3 with a source-drain path, which is the main current path, connected between the drain of the PMOS transistor M1 and the ground is provided. The NMOS transistor M3 forms a diode connection in which the drain and the gate are commonly connected. An NMOS transistor M4 with a source-drain path, which is the main current path, connected between the drain of the PMOS transistor M2 and the ground is provided. The gate of the NMOS transistor M4 is connected to the gate of the NMOS transistor M3. The NMOS transistors M3 and M4 form a current mirror circuit. The connection point of the PMOS transistor M2 and the NMOS transistor M4 is connected to the output terminal T202, and the output terminal T202 outputs an output voltage Vout1.

[0019] In the comparator circuit according to the conventional example of FIG. 7, an input potential difference in the comparator circuit is likely to occur, and generation of NBTI cannot be suppressed in a state where the operation of the reference voltage circuit has stopped. In particular, in a protection circuit for a lithium battery, it may be in a standby state for a long time in a factory shipment mode or the like, and at that time, the reference voltage circuit stops and NBTI may occur.

[0020] (Embodiment 1) Figure 1 is a circuit diagram showing an example configuration of a comparator circuit according to Embodiment 1. The comparator circuit 2 in Figure 1 is a circuit for detecting an abnormal voltage in a secondary battery 1, such as a nickel-ion battery, and has terminals T1 to T3, and is configured to include a standby control circuit 3 and a voltage detection circuit 4. Here, the voltage detection circuit 4 is configured to include voltage divider resistors R1 and R2, switches SW1 and SW2, a reference voltage source 6 having a reference voltage Vref, and a comparator 5 using PMOS transistors as a differential pair.

[0021] In Figure 1, a secondary battery 1 is connected between terminals T1 and T2, and a standby control circuit 3 is connected to it. Terminal T1 is connected to terminal T2 via switch SW1 and voltage divider resistors R1 and R2. The battery voltage from the secondary battery 1 is divided by voltage divider resistors R1 and R2 via switch SW1, and the divided voltage is applied to the inverting input terminal of comparator 5. The reference voltage Vref of the reference voltage source 6 is applied to the non-inverting input terminal of comparator 5.

[0022] In Figure 1, the standby control circuit 3 is, for example, the circuit described later in Embodiment 5 of Figure 5, and detects the standby state (circuit operation stopped state) of the shipping mode during manufacturing and shipment under the following conditions. (1) When the voltage across the secondary battery 1 is less than or equal to a predetermined standby voltage and the load detection circuit detects that a predetermined load is connected between the external load terminals, (2) When a standby control signal is input to the external input terminal of the MCU (Micro-Controller Unit) (see Figure 5), which is a system controller using the comparator circuit 2.

[0023] When the standby control circuit 3 detects the standby state, it generates control signals S1 and S2 that switch switch SW1 from on to off and switch SW2 from off to on, and outputs them to the respective control terminals of switches SW1 and SW2. This shorts the input terminal pair of the comparator 5 through resistor R2, making the input voltages of the comparator 5 equal.

[0024] With the comparator circuit 2 configured as described above, the standby control circuit 3 detects the standby state and controls the input voltages of the comparator 5 to become equal, i.e., the input voltage difference to zero, according to the control signals S1 and S2. This suppresses characteristic degradation due to NBTI in the PMOS transistors, which are the differential pair within the comparator 5.

[0025] (Embodiment 2) Figure 2 is a circuit diagram showing an example configuration of a comparator circuit according to Embodiment 2. The comparator circuit in Figure 2 is an abnormal voltage detection circuit for detecting abnormal voltages of secondary batteries B1 and B2, and comprises terminals T11 to T17, voltage divider resistors R11, R12; R13, R14, NMOS transistors Q1, Q2, Q3, switches SW11, SW12, SW13, SW21, SW22, comparators 11 and 12 using PMOS transistors as a differential pair, and a control circuit 10. Here, the NMOS transistors Q1 to Q3 and switches SW13 to SW22 constitute a reference voltage circuit 7. The control circuit 10 is a circuit that controls the operation of the comparator circuit, and generates control signals S11 to S22 to control the on or off operation of switches SW11 to SW22 and outputs them to the respective control terminals of switches SW11 to SW22.

[0026] In Figure 2, secondary batteries B1 and B2 are connected in series, with the positive terminal of secondary battery B1 connected to terminal T11, the negative terminal of secondary battery B1 and the positive terminal of secondary battery B2 connected to terminal T12, and the negative terminal of secondary battery B2 connected to terminal T13 and grounded.

[0027] Terminal T11 of the power supply voltage VDD is connected to terminal T13 of the ground voltage VSS via voltage divider resistors R11 and R12, switches SW11 and SW12, and voltage divider resistors R13 and R14. Here, the connection point between switch SW11 and switch SW12 is connected to terminal T12 of the intermediate voltage VC. Furthermore, terminal T11 is connected to terminal T13 via the drain and source of diode-connected NMOS transistor Q1, the drain and source of diode-connected NMOS transistor Q2, switch SW13, and the drain and source of diode-connected NMOS transistor Q3. In addition, switch SW21 is connected in parallel with NMOS transistor Q1, and switch SW22 is connected in parallel with NMOS transistor Q3.

[0028] The voltage V11 divided by voltage divider resistors R11 and R12 is applied to the inverting input terminal of comparator 11, and the voltage V12 divided by voltage divider resistors R13 and R14 is applied to the non-inverting input terminal of comparator 12. The voltage Vth1 at the connection point of NMOS transistors Q1 and Q2 is applied to the non-inverting input terminal of comparator 11, and the voltage Vth2 at the connection point of switch SW13 and NMOS transistor Q3 is applied to the inverting input terminal of comparator 12. The output terminal of comparator 11 is connected to terminal T16, and the output terminal of comparator 12 is connected to terminal T17.

[0029] The control circuit 10 controls switches SW11 to SW22 by outputting control signals to turn on switches SW11 to SW13 and turn off switches SW21 and SW22 when the comparator circuit is operating. In addition, the control circuit 10 controls switches SW11 to SW22 by outputting control signals to turn off switches SW11 to SW13 and turn on switches SW21 and SW22 when the standby state is active.

[0030] In the comparator circuit configured as described above, comparator 11 outputs an H-level abnormal voltage detection signal Vout1 from terminal T16 when V11 ≤ Vth1 and the power supply voltage VDD on the higher potential side exceeds a predetermined threshold voltage. Comparator 12 outputs an H-level abnormal voltage detection signal Vout2 from terminal T17 when V12 ≥ Vth2 and the intermediate voltage VC on the intermediate potential side exceeds a predetermined threshold voltage.

[0031] Furthermore, according to the comparator circuit of this embodiment, when in the standby state, switches SW11 to SW13 are turned off and switches SW21 and SW22 are turned on, so that each input terminal of comparator 11 is short-circuited via resistor R11 and set to the power supply voltage VDD, and each input terminal of comparator 12 is short-circuited via resistor R14 and set to the ground voltage VSS. In other words, the input voltage differences of the two comparators 11 and 12 become the same potential. This makes it possible to suppress characteristic degradation due to NBTI in the PMOS transistors which are the differential pair in comparators 11 and 12.

[0032] (Embodiment 3) Figure 3 is a circuit diagram showing an example configuration of a power supply device using a comparator circuit according to Embodiment 3. The comparator circuit in Figure 3 is an over-discharge and overcharge detection circuit 31 using the comparator circuit in Figure 2, and has terminals T11 to T22. In addition to the comparator circuit in Figure 2, it is configured to include an Oagate 13, a charge / discharge control circuit 20, and NMOS transistors Q11 and Q12 which are charge / discharge control switch elements. Furthermore, the power supply device 30 is configured with secondary batteries B1 and B2 and the over-discharge and overcharge detection circuit 31. The differences from Figure 2 will be explained below.

[0033] In Figure 3, the series voltage of secondary batteries B1 and B2 is transmitted through NMOS transistors Q11 and Q12 and terminals T21 and T22 to the load resistor R LThe signal is output to the following: Comparator 11 outputs an abnormal voltage detection signal Vout1 to the charge / discharge control circuit 20 via the Oagate 13, and comparator 12 outputs an abnormal voltage detection signal Vout2 to the charge / discharge control circuit 20 via the Oagate 13. The charge / discharge control circuit 20 performs charge / discharge control processing as follows, and also performs characteristic degradation suppression processing by NBTI on the comparator circuit in the standby state.

[0034] Comparator 11 compares the divided voltage V11 across voltage divider resistors R11 and R12 (divided voltage from the voltage of secondary battery B1 when switch SW11 is ON) with a reference voltage Vth1 for the power supply voltage VDD. When V11 ≤ Vth1, it detects that the power supply voltage VDD, which is the cell voltage, has exceeded a predetermined threshold and outputs an H-level abnormal voltage detection signal Vout1. Comparator 12 compares the divided voltage V12 across voltage divider resistors R13 and R14 (divided voltage from the voltage of secondary battery B2 when switch SW12 is ON) with a reference voltage Vth2 for the intermediate voltage VC. When V12 ≥ Vth2, it detects that the intermediate voltage VC has exceeded a predetermined threshold and outputs an H-level abnormal voltage detection signal Vout2. When either the abnormal voltage detection signal Vout1 or Vout2 reaches a high level, the charge / discharge control circuit 20 receives a high-level signal from the Oa gate 13. In response, it outputs a low-level control signal to the gates of NMOS transistors Q11 and Q12, thereby controlling the charge and stopping abnormal charging.

[0035] The over-discharge and overcharge detection circuit 31, which uses the comparator circuit configured as described above, employs the comparator shown in Figure 2, and therefore can suppress characteristic degradation due to NBTI in the PMOS transistors that are the differential pair within the comparators 11 and 12.

[0036] (Embodiment 4) FIG. 4 is a circuit diagram showing a configuration example of a power supply device using a comparator circuit according to Embodiment 4. The comparator circuit in FIG. 4 is an over-discharge and over-charge detection circuit 31A using the comparator circuit in FIG. 1. The over-discharge and over-charge detection circuit 31A has terminals T11 to T15, voltage dividing resistors R11, R12; R13, R14; R21, R22; R23, R24, reference voltage sources B11, B12, comparator circuits 41 to 44 each using the comparator circuit in FIG. 1, OR gates 45, 46, a standby control circuit 3, a discharge control circuit 51, and a charge control circuit 52. Further, the power supply device 30A is constituted by secondary batteries B1, B2 and the over-discharge and over-charge detection circuit 31A. Hereinafter, differences from FIGS. 2 and 3 will be described.

[0037] In FIG. 4, the divided voltage V11 obtained by dividing the battery voltage of the secondary battery B1 by the voltage dividing resistors R11, R12 is applied to the non-inverting input terminal of the comparator circuit 41, and the reference voltage Vth11 of the reference voltage source B11 is applied to the inverting input terminal of the comparator circuit 41. Also, the divided voltage V12 obtained by dividing the battery voltage of the secondary battery B1 by the voltage dividing resistors R13, R14 is applied to the non-inverting input terminal of the comparator circuit 42, and the reference voltage Vth12 of the reference voltage source B12 is applied to the inverting input terminal of the comparator circuit 42. Further, the divided voltage V21 (<V11) obtained by dividing the battery voltage of the secondary battery B1 by the voltage dividing resistors R21, R22 is applied to the inverting input terminal of the comparator circuit 43, and the reference voltage Vth11 of the reference voltage source B11 is applied to the non-inverting input terminal of the comparator circuit 43. Also, the divided voltage V22 (<V12) obtained by dividing the battery voltage of the secondary battery B2 by the voltage dividing resistors R23, R24 is applied to the non-inverting input terminal of the comparator circuit 44, and the reference voltage Vth12 of the reference voltage source B11 is applied to the inverting input terminal of the comparator circuit 44.

[0038] The abnormal voltage detection signal Vout11 from comparator circuit 41 is input to the discharge control circuit 51 via Oagate 45, and the abnormal voltage detection signal Vout12 from comparator circuit 42 is input to the discharge control circuit 51 via Oagate 45. In addition, the abnormal voltage detection signal Vout13 from comparator circuit 43 is input to the charge control circuit 52 via Oagate 46, and the abnormal voltage detection signal Vout14 from comparator circuit 44 is input to the charge control circuit 52 via Oagate 46. Furthermore, the standby control circuit 3 generates control signals S1 and S2 based on the signals from the discharge control circuit 51 and the charge control circuit 52 and outputs them to the comparator circuits 41 to 44.

[0039] In the over-discharge and overcharge detection circuit 31A configured as described above, when at least one of the abnormal voltage detection signals Vout11 and Vout12 reaches a high level, a high-level signal is input to the discharge control circuit 51. In response, the discharge control circuit 51 applies a low-level signal to the gate of the NMOS transistor Q11, thereby turning off the NMOS transistor Q11. This enables discharge control and stops abnormal discharge. Similarly, when at least one of the abnormal voltage detection signals Vout13 and Vout14 reaches a high level, a high-level signal is input to the charge control circuit 52. In response, the charge control circuit 52 applies a low-level signal to the gate of the NMOS transistor Q12, thereby turning off the NMOS transistor Q12. This enables charge control and stops abnormal charging.

[0040] Therefore, the over-discharge and overcharge detection circuit 31A in Figure 4 can perform the above-mentioned discharge control and charge control, and also includes comparator circuits 41-44 using the comparator circuit in Figure 1, so comparator circuits 41- 44 This can suppress characteristic degradation due to NBTI in the PMOS transistors, which are the differential pairs within the device.

[0041] (Embodiment 5) Figure 5 is a circuit diagram showing an example configuration of a power supply unit using the standby control circuit 3 according to Embodiment 5. The standby control circuit 3 in Figure 5 comprises a standby voltage detection circuit 60, an AND gate 61, an OR gate with inverting output 62, an over-discharge and over-charge detection circuit 63, a charge / discharge control circuit 64, and a load detection circuit 65.

[0042] In Figure 5, the standby voltage detection circuit 60 detects that the voltage of the secondary battery B1 is below a predetermined standby voltage, and the load detection circuit 65 detects, for example, that a load is connected between terminals T21 and T22 by current detection, or a standby control signal is input to the external input terminal from an MCU 70 or the like that receives power from the secondary battery B1, then an L-level signal is input to the over-discharge and overcharge detection circuit 63, and the system transitions to the standby state. The charge / discharge control circuit 64 operates in the same manner as the charge / discharge control circuit 20 in Figure 3 or the control circuit 10 in Figure 2.

[0043] (modified version) The embodiments described above disclose a comparator circuit using PMOS transistors as a differential pair that can suppress the occurrence of NBTI regardless of the input potential difference of the comparator circuit. However, the present invention is not limited to this, and a similar circuit can be constructed in a comparator circuit using NMOS transistors as a differential pair that can suppress the occurrence of PBTI regardless of the input potential difference of the comparator circuit (Figure 8). For example, the circuit includes a control circuit that controls the voltages of the two input terminals of the comparator to be equal when the comparator circuit is in a standby state where it is not operating. This suppresses the occurrence of PBTI.

[0044] Figure 8 is a circuit diagram showing a known configuration of a comparator circuit according to a comparative example. In Figure 8, the comparator circuit has input terminals T211, T212 and output terminal T213, and is configured with a differential pair of NMOS transistors M11, M12, PMOS transistors M13, M14 that constitute a current mirror circuit, and a constant current source 213 between the power supply line 211 and ground. [Industrial applicability]

[0045] As described in detail above, according to the present invention, in a comparator circuit using PMOS transistors or NMOS transistors as a differential pair, the occurrence of NBTI can be suppressed regardless of the input potential difference of the comparator circuit. [Explanation of symbols]

[0046] 1,B1,B2 Secondary battery 2 Comparator Circuits 3. Standby control circuit 4. Voltage detection circuit 5 Comparator 6. Reference voltage source 7. Reference voltage circuit 10 Control circuits 11,12 Comparators 13 Oagate 20 Charge / Discharge Control Circuit 30,30A,30B power supply 31,31A Over-discharge and over-charge detection circuit 41-44 Comparator Circuits 45, 46 Oagate 51 Discharge control circuit 52 Charging control circuit 60 Standby Voltage Detection Circuit 61 Andgate 62 Oagate with Inverted Output 63 Over-discharge and over-charge detection circuit 64 Charge / Discharge Control Circuit 65 Load detection circuit 70 MCU 101 Comparator 102 Reference voltage source 201 Comparator Circuit 203 Reference voltage source 211 Power Line 212 constant current source 213 Constant current source 220 Bias Circuit 221 Constant current source B1,B2 Secondary battery B11, B12 Reference voltage source M1, M2, M13, M14 PMOS transistors M3, M4, M5, M6, M11, M12, Q1~Q12 NMOS transistors R1~R14, R101, R102 voltage divider resistors R L Load resistance SW1~SW22 Switches Terminals T1~T213

Claims

1. A comparator for detecting abnormal voltage in a secondary battery, comprising a comparator circuit that uses a PMOS transistor or an NMOS transistor as a differential pair, A first switch connected to the secondary battery, A pair of voltage divider resistors connected to the secondary battery via the first switch, the pair of voltage divider resistors that divide the voltage of the secondary battery and output the divided voltages to the inverting input terminal of the comparator, A reference voltage source that generates a predetermined reference voltage and outputs it to the non-inverting input terminal of the comparator, A second switch connected to both ends of the aforementioned reference voltage source, The circuit includes a control circuit that controls the first switch and the second switch in a standby state in which the comparator circuit is in a stopped state and in a circuit operating state that is not in a standby state. The control circuit controls the first switch to be turned off and the second switch to be turned on in the standby state, thereby short-circuiting the two input terminals of the comparator and controlling the voltages of the two input terminals to be equal, while controlling the first switch to be turned on and the second switch to be turned off in the circuit operating state, a comparator circuit.

2. The secondary battery includes first and second secondary batteries connected in series with each other. The comparator includes a first and a second comparator, The voltage divider resistors include first and second voltage divider resistors, The aforementioned reference voltage source includes a first and a second reference voltage source, The voltage of the first secondary battery is divided by the first voltage divider resistor, and the resulting voltage is input to the inverting input terminal of the first comparator. The reference voltage of the first reference voltage source is input to the non-inverting input terminal of the first comparator. The voltage of the second secondary battery is divided by the second voltage divider resistor, and the resulting voltage is input to the inverting input terminal of the second comparator. The reference voltage of the second reference voltage source is input to the non-inverting input terminal of the second comparator. The control circuit, in the standby state, stops supplying voltage from the first and second secondary batteries to the first and second voltage divider resistors, respectively, and controls the voltages at the two input terminals of the first and second comparators to be equal to each other. The comparator circuit according to claim 1.

3. A power supply device comprising a comparator circuit according to claim 1 or 2, The aforementioned control circuit is a charge / discharge control circuit. power supply.

4. A power supply device comprising a comparator circuit according to claim 1 or 2, The secondary battery includes first and second secondary batteries connected in series with each other. A comparator circuit according to claim 1 or 2, comprising a first comparator circuit for detecting an abnormal discharge voltage related to the first secondary battery, A comparator circuit according to claim 1 or 2, comprising a second comparator circuit for detecting an abnormal discharge voltage related to the second secondary battery, A comparator circuit according to claim 1 or 2, comprising a third comparator circuit for detecting an abnormal charging voltage related to the first secondary battery, A comparator circuit according to claim 1 or 2, comprising a fourth comparator circuit for detecting an abnormal charging voltage related to the second secondary battery, A discharge control circuit that performs discharge control based on the abnormal voltage detection signal from the first comparator circuit and the abnormal voltage detection signal from the second comparator circuit, A charging control circuit that performs charging control based on the abnormal voltage detection signal from the third comparator circuit and the abnormal voltage detection signal from the fourth comparator circuit, A power supply unit equipped with the following features.

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