A memory device including a tiled array of independently and simultaneously operating memory transistors.

Abstract

To provide a memory device including a tiled arrangement of memory transistors capable of operating independently and concurrently, and a memory system including a multi-channel configuration for high-bandwidth access.SOLUTION: In a memory device, each tile of a plurality of tiles of a memory circuit is electrically connected to a module control circuit and includes a physically separated memory array operated by the module control circuit. The memory array includes a three-dimensional array of storage transistors configured by a plurality of memory pages in a storage transistor, and each storage transistor is accessed by a word line and a bit line. Each tile is individually addressed by the associated module control circuit and operates independently of each other to perform memory operations on memory pages of storage transistors in the memory array in response to memory access commands specified for the tile.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a memory system having a large capacity and a high bandwidth, and particularly to a memory device including a tile array of memory transistors that can operate independently and simultaneously, and to a memory system having a multi-channel configuration for high-bandwidth access.

Background Art

[0002] High-density memory arrays, such as three-dimensional arrays of NOR-type memory strings ("three-dimensional NOR-type memory arrays"), are disclosed, for example, in U.S. Patent No. 10,121,553 (Patent Document 1) entitled "Capacitively Coupled Nonvolatile Thin-Film Transistor NOR String in a Three-Dimensional Array," filed on August 26, 2016, and issued on November 6, 2018. The entire disclosure of Patent Document 1 is incorporated herein by reference for all purposes. The storage transistors or memory transistors of Patent Document 1 are configured as a three-dimensional array of NOR-type memory strings formed on the plane of a semiconductor substrate. Such three-dimensional NOR-type memory arrays can provide a very desirable speed of memory circuit comparable to conventional memory circuits, such as dynamic random access memory ("DRAM"), which have a much lower circuit density and significantly higher power consumption, in addition to providing a high memory density and capacity.

[0003] Furthermore, the memory circuit described in Patent Document 1 is also called "quasi-volatile memory" or "QV memory." Each memory cell in QV memory stores data bits as electric charge in a charge storage material (e.g., ONO), similar to the memory cells in non-volatile memory (NVM). Due to the properties of the charge storage layer, typical QV memory cells have a much longer data retention time than DRAM cells, and therefore a lower refresh rate than DRAM cells. For example, while a typical DRAM system is designed to refresh every 64 milliseconds, a QV memory with equivalent effective access performance may refresh every 10 minutes. Such a reduction in refresh rate offers QV memory significant advantages, including reduced power consumption, reduced heat dissipation, and improved memory availability for better host performance. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent No. 10,121,553 [Patent Document 2] U.S. Patent Application No. 17 / 812, 375 [Patent Document 3] U.S. Patent Application No. 17 / 936, 320 [Patent Document 4] U.S. Patent Application No. 17 / 525, 712 [Overview of the project] [Means for solving the problem]

[0005] The present disclosure provides a memory device comprising an array of tiles of memory transistors that can operate independently and simultaneously. The present disclosure also provides a memory system having a multi-channel configuration for high-bandwidth access. The present disclosure is substantially shown and / or described below, for example with reference to at least one figure, and is more fully described in the claims.

[0006] In one embodiment, the memory device of the present disclosure comprises a plurality of tiles of a memory circuit, each tile comprising a physically isolated array of storage transistors ("memory array") electrically connected to and operated by a module control circuit, the memory array having a three-dimensional array of storage transistors configured in a plurality of memory pages of storage transistors, each storage transistor being accessed by word lines and bit lines, and the module control circuit communicating with the memory array to perform memory operations on one or more memory pages of the storage transistors, the tiles comprising each tile being individually addressed by the associated module control circuit and configured to operate independently of each other to perform memory operations on a unit of memory pages of storage transistors in the memory array in response to a memory access command specified for the tile, and two or more randomly addressed tiles of the memory circuit being configured to perform overlapping memory operations simultaneously.

[0007] In another embodiment, the memory module of the present disclosure comprises a plurality of semiconductor memory dies, each semiconductor memory die comprising a three-dimensional array of storage transistors divided into a plurality of compartments, wherein corresponding compartments across the plurality of semiconductor memory dies form a memory channel, and the plurality of compartments across the plurality of semiconductor memory dies form a first number of independently accessible memory channels; and a memory controller die comprising a memory control circuit for accessing and operating the plurality of semiconductor memory dies, wherein the plurality of semiconductor memory dies are connected to the memory controller die via a first set of interconnection structures, and the memory control circuit comprises a first number of channel controllers, each channel controller being connected to operate one of the memory channels to perform a memory operation on the storage transistor associated with each memory channel, independently of the other memory channels and in parallel with the memory operations performed on the storage transistors of the other memory channels.

[0008] In some embodiments, another memory module of the present disclosure comprises a plurality of semiconductor memory dies, each semiconductor memory die comprising a plurality of memory arrays, each memory array comprising a three-dimensional array of storage transistors, wherein the plurality of semiconductor memory dies comprises a first number of semiconductor memory dies providing a designated memory capacity of the memory module and at least one spare semiconductor memory die providing redundant memory capacity; and a memory controller die comprising a memory control circuit that accesses and operates the plurality of semiconductor memory dies to perform memory operations, wherein the plurality of semiconductor memory dies are connected to the memory controller die via a first set of interconnection structures, the memory controller die receiving input requests for memory operations from a host processor which are addressed in a first memory address space that spans the first number of semiconductor memory dies and excludes the memory space of at least one spare semiconductor memory die.

[0009] The above and other advantages, aspects and novel features of the present invention, as well as details of the exemplary embodiments thereof, will be better understood by referring to the following description and accompanying drawings. [Brief explanation of the drawing]

[0010] Various embodiments of the present invention are disclosed in the following detailed description and accompanying drawings. While the drawings depict various embodiments of the present invention, the present invention is not limited to the embodiments depicted. It should be understood that in the drawings, similar reference numerals indicate similar structural elements. Furthermore, it should be understood that the depictions in the drawings are not necessarily drawn to a consistent scale.

[0011] [Figure 1A] Figure 1A shows a memory module according to an embodiment of the present disclosure. [Figure 1B] Figure 1B shows a memory module structure formed as a stacked memory die according to an embodiment of the present disclosure. [Figure 2A] Figure 2A shows a memory module comprising multiple memory channels that are independently accessible from one another, according to an embodiment of the present disclosure. [Figure 2B] Figure 2B shows a memory module having a stacked memory die configuration according to several embodiments. [Figure 3] Figure 3 is a top view of a semiconductor memory die showing the configuration of a storage transistor according to an embodiment of the present disclosure. [Figure 4A] Figure 4A shows a memory structure containing a three-dimensional array of NOR-type memory strings in several embodiments. [Figure 4B] Figure 4B shows a memory structure containing a three-dimensional array of NOR-type memory strings in several embodiments. [Figure 5] Figure 5 is a circuit diagram showing a memory array of a NOR-type memory string according to an embodiment of the present disclosure. [Figure 6] Figure 6 is a schematic diagram showing an exemplary support circuit connected to the bit lines of a NOR-type memory string according to an embodiment of the present disclosure. [Figure 7] Figure 7 is a schematic diagram of a memory controller according to an embodiment of the present disclosure. [Figure 8] Figure 8 is a schematic diagram of a channel controller implemented in the memory controller of Figure 7 according to an embodiment of the present disclosure. [Figure 9] Figure 9 is a cross-sectional view in the YZ plane of a tile in a memory device according to an embodiment of the present invention. [Figure 10] Figure 10 shows a two-dimensional array of tiles forming part of a memory device according to an embodiment of the present invention. [Figure 11] Figure 11 is a block diagram showing a modular control circuit that can be incorporated into each tile of a memory device to provide intelligent, semi-autonomous memory operation control according to several embodiments of the present invention. [Figure 12]FIG. 12 is a block diagram showing a module control circuit that can be incorporated into each tile of a memory device according to another embodiment of the present invention. [Figure 13] FIG. 13 is a block diagram showing a bit line selection and sense amplifier configuration in a module control circuit according to an embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

[0012] In an embodiment of the present invention, a memory module includes a plurality of semiconductor memory dies connected to a memory controller. The semiconductor memory dies are divided into a plurality of memory channels that can be accessed independently of each other, and each memory channel is formed across a plurality of semiconductor memory dies. That is, a memory channel is formed from each memory section of a plurality of semiconductor memory dies. The memory controller includes a channel controller corresponding to each memory section in order to control the memory operation in each memory section independently from the memory operations in other sections. With such a configuration, the memory module realizes a large-capacity memory having a high-bandwidth access enabled by a plurality of memory channels that can be accessed in parallel and independently.

[0013] In other embodiments of the present invention, the memory system includes a memory device of storage transistors (or memory transistors) configured in a plurality of memory arrays or “tiles”, and the memory device interacts with a controller device to perform read and write operations. In one embodiment, each tile is an operating unit for memory access and is also referred to herein as a “memory bank”. In some embodiments, the controller device is configured to issue write commands and write end commands specifying memory banks to the memory device. The write command instructs the memory device to start a write operation on a specified memory bank in the memory device, and the write end command instructs the memory device to end the memory operation in the memory bank. In some embodiments, the controller device issues a write interrupt (abort) command as a write end command to end a write operation in progress in a certain memory bank of the memory device in order to issue a read command to the memory device to read data from the same memory bank. In some examples, the read command is directed to a memory page in a memory bank different from the memory page where the write operation was in progress. The completed write operation can be resumed after completion of the read operation.

[0014] In this specification, the terms “semiconductor memory die,” “memory die,” “semiconductor memory device,” or “memory device” are used interchangeably to refer to a memory circuit of memory transistors or storage transistors formed on a semiconductor substrate. In embodiments of this disclosure, a semiconductor memory device includes a three-dimensional array of storage transistors. In some embodiments, a semiconductor memory device is configured using a three-dimensional array of NOR-type memory strings formed on a semiconductor substrate, as described in Patent Document 1. In embodiments of this disclosure, a semiconductor memory device includes a memory array of quasi-volatile storage transistors and is also referred to as “quasi-volatile memory” or “QV memory.” Because quasi-volatile storage transistors have a much longer retention time than typical DRAM memory cells, a quasi-volatile memory device is refreshed much less frequently than a typical DRAM memory device. For example, a DRAM memory device needs to refresh its DRAM memory cells every 64 milliseconds, while a quasi-volatile memory device only needs to refresh its quasi-volatile storage transistors at intervals of 10 minutes or more. In this specification, a NOR-type memory string includes storage transistors formed on a plane of a semiconductor substrate that share a common source region and a common drain region, and each storage transistor can be individually addressed and accessed. In some examples, a three-dimensional array can be formed by providing NOR-type memory strings on multiple planes (e.g., eight or sixteen planes) on a semiconductor substrate and arranging the NOR-type memory strings on each plane in a row. In this specification, the term “memory device” may also refer to a single memory die or a set of memory dies connected to a memory controller.

[0015] In this specification, the term “storage transistor” is used interchangeably with “memory transistor” to refer to a data storage structure formed on a memory die as described herein. In some examples, a semiconductor memory device of the present disclosure, including a NOR memory string of randomly accessible storage transistors (or memory transistors), can have applications in a computer system as main memory where data storage locations are directly accessible by the computer system's processor, in a role previously played by conventional random access memories (RAM), such as dynamic RAM (DRAMS) and static RAM (SRAM). For example, the memory structure of the present disclosure can be applied to a computer system to function as random access memory to support the operation of a microprocessor, a graphical processor, and an artificial intelligence processor. In other examples, the memory structure of the present disclosure can also be applied to provide long-term data storage in a computer system, to form a storage system such as a solid-state drive, or to replace a hard drive.

[0016] In some embodiments, the semiconductor memory device is formed using thin-film storage transistors that perform charge trapping as a data storage mechanism, and the data is stored in the charge storage film of each storage transistor. For example, the charge storage film includes a tunnel dielectric layer, a charge trapping layer, and a blocking layer, which can be realized as a multilayer in which silicon oxide, silicon nitride, and silicon oxide are stacked in that order, and is also called an ONO layer. An electric field applied to the charge storage film changes the threshold voltage of the storage transistor by adding charge to or removing charge from the charge trapping layer of the charge storage film, thereby encoding a given logic state into the storage transistor.

[0017] In other embodiments, the semiconductor memory device is formed using a ferroelectric field-effect transistor as the storage transistor. More specifically, the ferroelectric field-effect transistor (hereinafter also referred to as a ferroelectric transistor or FeFET) is formed by using a ferroelectric material as the gate dielectric layer between the gate conductor and the channel of the field-effect transistor. The ferroelectric transistor realizes the memory function by storing data as a polarization state in the ferroelectric gate dielectric layer (also referred to as a ferroelectric insulating layer). Specifically, a voltage applied to the gate conductor induces electric polarization in the ferroelectric insulating layer, and this polarization can be reversed by applying a voltage of the opposite polarity. The induced polarization state of the ferroelectric gate dielectric layer changes the threshold voltage of the ferroelectric storage transistor. Different logic states of data can be represented using the change or shift in the threshold voltage of the ferroelectric storage transistor due to different polarization states. For example, two logic states (e.g., "0" and "1") can be represented by a high threshold voltage and a low threshold voltage of the ferroelectric transistor as a result of two induced electric polarization states in the ferroelectric insulating layer. A three-dimensional array of NOR-type memory strings of thin-film ferroelectric transistors is disclosed, for example, in U.S. Patent Application No. 17 / 812,375, “Three-Dimensional Memory String Array of Thin-Film Ferroelectric Transistors” (Patent Document 2), filed on 13 July 2022 (the entire disclosure of Patent Document 2 is incorporated herein by reference).

[0018] In some embodiments, the ferroelectric insulating layer is a doped hafnium oxide layer. In some examples, the doped hafnium oxide layer comprises one or more of the following hafnium oxides: zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and zirconium impurities.

[0019] In yet another embodiment, a three-dimensional array of NOR-type memory strings is formed using junction-less ferroelectric storage transistors. That is, the ferroelectric storage transistor does not include a p / n junction as the drain or source region within the channel. Instead, the drain and source regions are formed by conductive layers such as a metal layer, and the semiconductor channel region is formed by an amorphous oxide semiconductor material such as indium gallium zinc oxide (IGZO). In some examples, the source / drain conductive layer can be formed from a metal layer or a low-resistance metallic conductive material, such as molybdenum (Mo), tungsten (W), tungsten nitride (WN), ruthenium, or titanium-tungsten alloy (TiW). In some examples, the semiconductor channel region may be formed from other oxide semiconductor materials, such as indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO). A three-dimensional array of NOR-type memory strings of junctionless thin-film ferroelectric transistors is disclosed, for example, in U.S. Patent Application No. 17 / 936,320, filed on September 28, 2022, entitled "Memory structure including a three-dimensional NOR-type memory string of a junctionless ferroelectric memory transistor and a method for manufacturing the same" (Patent Document 3) (the entire disclosure of Patent Document 3 is incorporated herein by reference).

[0020] Figure 1A shows a memory module according to an embodiment of the present disclosure. Referring to Figure 1A, the memory module 10 is constructed as a multi-die structure comprising one or more semiconductor memory dies 12 on which a memory array is formed, and a memory controller die 14 (memory controller) on which a control circuit is formed. In the example shown in Figure 1A, the memory module 10 comprises two semiconductor memory dies 12, namely memory die A (memory device A) and memory die B (memory device B), connected to each other by an interconnection structure 13 such as a through-silicon via (TSV). The memory dies 12 communicate with the memory controller 14 (chiplet) via a memory array interface 15. In some embodiments, the memory array interface 15 is a high-bandwidth data interface implemented on an interconnection structure (e.g., a TSV or hybrid bond) that connects the memory dies 12 to the controller die 14 (memory controller). The memory controller 14 also includes one or more external interfaces, such as memory interfaces for host access or other system functions. For example, the memory controller 14 includes a host interface 16 for communicating with a host processor. The host interface 16 communicates with the host processor to receive requests from the host, for example, to read data from the memory module 10 or to write data to the memory module, and to send responses to the host, such as a response confirming the completion of the write operation or the read data.

[0021] In this specification, “memory module” refers to one or more semiconductor memory dies connected to an associated memory controller die to form a high-density, high-capacity memory system. Each semiconductor memory die (also referred to as a memory die or memory device) includes multiple three-dimensional arrays of storage transistors (also referred to as memory transistors or memory cells) for storing memory data. In this specification, a memory controller die is also referred to as a “memory controller,” “controller die,” “controller device,” or “chiplet,” and includes a control circuit for accessing and operating the memory device and performing other memory control functions such as data routing and error correction. The control circuit may also include one or more external interfaces, such as a memory interface for host access. In this embodiment, the memory module is constructed as a multi-die structure having a memory device formed on one semiconductor die and a memory controller formed on another semiconductor die. The memory dies and memory controller dies can be integrated using various integration techniques such as TSVs, hybrid bonds, exposed contacts, interposers, printed circuit boards, and other suitable interconnection techniques, particularly techniques for high-density interconnection.

[0022] With this configuration, the memory module 10 of this disclosure can integrate one or more semiconductor memory dies and one memory controller die, thereby realizing a large-capacity memory system with faster memory controller operation and faster memory performance. In addition, the memory dies and controller dies can be manufactured separately using dedicated manufacturing processes to optimize the performance of each integrated circuit. More specifically, the memory module 10 can be manufactured using a manufacturing process optimized for the memory circuit and a manufacturing process optimized for the memory controller. For example, the memory controller can be manufactured using a manufacturing process optimized for forming low-voltage and high-speed logic circuits. In this way, the performance of the memory circuit and the memory controller can be individually optimized, and as a result, a memory module 10 with large capacity, high bandwidth, and high-speed memory operation can be realized.

[0023] In one embodiment, the memory controller is formed as a separate semiconductor die or integrated circuit customized for use as a memory controller, for example, as an application-specific integrated circuit. In another embodiment of the present invention, the memory controller is implemented by a general-purpose integrated circuit (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a communications chip, or a field-programmable gate array). The functional blocks forming the memory controller are incorporated into the general-purpose integrated circuit, and the memory array interface of the memory controller is electrically and physically connected to the memory device using one of the techniques described above. With such a configuration, the incorporated memory controller does not include a host interface circuit but can communicate directly with logic circuits via interconnection lines formed within or on the general-purpose integrated circuit. Such a configuration is also referred to as "in-memory computing." In-memory computing is particularly desirable in data-intensive artificial intelligence and machine learning applications that require a large amount of memory in close proximity to the CPU or GPU core processor incorporated into the memory controller functional block.

[0024] Figure 1B shows a memory module structure formed as a stacked memory die according to an embodiment of the present disclosure. For example, the memory module 10 in Figure 1A is formed by stacking two or more memory dies together and integrating the stacked memory die with a memory controller die, as shown in Figure 1B. Referring to Figure 1B, the memory module 20 comprises a plurality of memory devices 22 formed by stacking them together. For example, the memory module 20 comprises stacked memory devices 22-1 and 22-2. The stacked memory devices 22 (or "memory stack") are then integrated with a controller die 24. In some embodiments, the memory devices 22 (memory stack) are interconnected to the controller die 24 via through-silicon vias 23 (TSVs) formed through the memory devices 22 and connected to contact pads on the controller die 24. In other embodiments, other methods of interconnecting the stacked memory devices 22 to the controller die 24 may be used, such as hybrid bonds, copper studs, interposers, or other suitable interconnection methods. By integrating multiple memory devices (memory dies), the memory module 20 can realize a large-capacity memory circuit in a small footprint. The resulting advantages are particularly evident when stacking multiple memory devices (memory dies) to provide high memory capacity while sharing a memory controller among the multiple memory devices (memory dies) to reduce the cost per unit.

[0025] Memory channel configuration

[0026] Figure 2A shows a memory module comprising multiple memory channels that are independently accessible from one another, according to an embodiment of the present disclosure. Similar elements in Figures 1A and 2A are denoted by the same reference numerals for the sake of simplicity of explanation. Referring to Figure 2A, the memory module 30 comprises a plurality of semiconductor memory dies 12 (memory devices) connected to one another via interconnection structures 13, such as through-silicon vias (TSVs). In this embodiment, the memory module 30 comprises four memory dies 12, named memory die 0 to memory die 3. The memory dies 12 communicate with a memory controller 14 via a memory array interface 32. The memory controller 14 includes one or more external interfaces, such as a memory interface 16 for communicating with a host or host processor.

[0027] In embodiments of this disclosure, each memory die 12 is divided into N partitions, and the corresponding partitions in all memory dies 12 are grouped to form N memory channels that are independently accessible from one another (where N is an integer greater than or equal to 2). In this embodiment, these are illustrated as four memory channels Ch0 to Ch3. In other embodiments, the memory module may be divided into an appropriate number of memory channels based on factors such as bandwidth and / or reliability and quality of service requirements. In such a configuration, each memory channel operates independently of the others to provide memory functionality using the storage transistors within the channel partition. The memory controller 14 operates each memory channel independently and in parallel with the other channels to perform memory operations such as read or write operations. The memory array interface 32 provides a separate memory channel interface for each memory channel. That is, memory channels Ch0 to Ch3 are independently accessible from one another via their respective memory channel interfaces 32-0 to 32-3. In embodiments of the present invention, the memory controller 14 has channel controllers 0 to 3, indicated by 17-0 to 17-3, to access each memory channel Chn via each memory array interface 32-n. The memory controller 14 has a control logic circuit 18, which includes a control circuit for controlling the channel controllers 17-n, a host interface circuit for communicating with the host via the memory interface 16, and other circuits for controlling memory operation. The memory controller 14 sends read or write requests received from the host to the respective channel controllers 17-n, storing memory data in the corresponding memory channel or retrieving memory data from the corresponding memory channel. By dividing the memory die 12 into individually accessible memory channels and operating them accordingly, the memory module 30 can provide the host with high-bandwidth data transfer.

[0028] A notable feature of the memory channel configuration in the memory module 30 is that each memory channel is formed across multiple semiconductor memory dies 12, and each memory channel is individually controlled by a channel controller of the memory controller 14. That is, memory channel Ch0 is formed from the respective sections of memory die 0 to memory die 3. Similarly, memory channels Ch1 to Ch3 are each formed from the respective sections of memory die 0 to memory die 3. The memory channel configuration of the present invention is particularly advantageous when applied to a memory module having a stacked memory die configuration. Figure 2B shows a memory module 30 having a stacked memory die configuration according to several embodiments. The stacked memory die configuration is formed by stacking memory dies 0 to 3 on top of each other and stacking them on a memory controller 14. The stacked memory dies 0-3 are connected to the memory controller 14 by an interconnection structure. In embodiments of the present invention, each memory die 12 is divided into N memory sections. The corresponding memory sections in the multiple stacked memory dies 12 form a memory channel. In other words, each memory channel Ch-n includes the memory sections of memory die 0 to memory die 3. In the diagram shown in Figure 2B, memory channels Ch-n are formed by traversing multiple stacked memory dies. The N memory channels are formed parallel to each other, traversing multiple stacked memory dies. Each memory channel has its own channel controller, so each memory channel is individually controlled and accessed in parallel to receive input memory data and provide memory output data.

[0029] The memory channel configuration of the present invention, realized by the memory module 30, has several advantages. First, the memory channel configuration can be adapted to any number of memory dies 12 used to form the memory module. For N memory channels, the memory controller 14 can easily be modified to address any number of memory dies included in the memory stack by configuring a memory address bit designated for selecting a memory die from the memory channel. Thus, the memory channel configuration of the present invention enables a scalable design of the memory module. Second, the memory channel configuration of the present invention allows the memory controller to utilize parallelism in memory access, and as a result, storage transistors on each memory die can be utilized more efficiently. During operation, the memory controller 14 minimizes access contention by distributing memory access among the N memory channels, thereby increasing the utilization rate of the numerous storage transistors formed on each memory die 12. The memory channel configuration of the present invention enables simultaneous and parallel access of numerous storage transistors across N channels, thereby achieving high-bandwidth memory access.

[0030] Figure 3 is a top view of a semiconductor memory die showing the configuration of a storage transistor according to an embodiment of the present disclosure. Referring to Figure 3, the semiconductor memory die 40 (memory device) includes a plurality of three-dimensional arrays (memory arrays) of thin-film storage transistors. The memory array is configured as a two-dimensional array of tiles 42 formed on or within a semiconductor substrate (i.e., the tiles are arranged in a matrix). Each tile 42 (also referred to as a “memory tile”) includes a three-dimensional array of thin-film storage transistors formed on a plane of the semiconductor substrate. In this specification, a tile 42 in the memory die 40 refers to a physically isolated array of memory cells having a local modular control circuit, where the tiles can operate simultaneously with other tiles, and each tile performs a memory operation based on a unit of memory data access, such as a page of memory data. Thus, a tile 42 in the memory die 40 refers to a regular array in an addressable modular structure of regularly arranged memory cells. In some embodiments, each tile 42 includes a memory array of quasi-volatile storage transistors configured as a three-dimensional array of NOR-type memory strings. In this specification, the memory array in the memory die 40 is also referred to as a quasi-volatile memory circuit.

[0031] In the memory die 40, each tile 42 can be configured to be individually and independently addressable. In embodiments of the present invention, each tile 42 is used as an operational unit for memory access and is also referred to as a “memory bank” or “bank”. Thus, a memory bank consists of one tile as an operational unit for memory access, and each tile or memory bank operates on one access unit of memory data (e.g., a page of memory data or “memory page”) for each memory operation. That is, each memory access from the host is performed on a memory data access unit. An access unit is also referred to as a memory data page or memory page. In the memory die 40, each memory bank contains one tile, and one tile alone provides an entire memory data access unit or an entire memory page of memory data. For example, each memory page contains 512 bits of memory data. This is in contrast to conventional memory devices in which the memory die contains multiple memory banks, each memory bank providing only a portion of the memory data access units, and the entire memory data access unit must be obtained by combining memory data from multiple memory banks.

[0032] More specifically, in some embodiments, each tile consists of multiple memory pages of storage transistors, and each memory page contains a subset of the storage transistors within the tile. For example, a memory page contains 512 storage transistors, and the tile contains memory pages of more than 120K storage transistors. With such a configuration, the storage transistors in the memory device are accessed in units of memory pages having a predetermined byte size. That is, each read or write operation to the memory device is performed in units of memory pages. In one example, the memory device is accessed with memory page sizes of 64 bytes or 512 bits.

[0033] In the embodiments described herein, a memory bank is described as consisting of a single tile. In other embodiments, one or more tiles may be configured to form a memory access operating unit or memory bank. For example, a row of tiles or a two-dimensional block of tiles may be configured to be addressed together as a memory bank. In other words, in another embodiment, a memory bank may include a single tile 42, or a block of tiles, such as a row or section of tiles. Such a configuration allows the tile 42 to be a building block that provides flexibility in configuring the memory module to suit the requirements of the application.

[0034] In this specification, “tile” refers to a physically isolated memory array of memory cells having local modular control circuits, and “memory bank” refers to a unit of operation or logical unit of memory access. In this specification, a memory bank includes one tile, and the terms “memory bank” or “bank” are used interchangeably with the term “tile” to refer to a unit of operation of memory access consisting of a single tile or a single physically isolated memory array. Note that in general, “tile” refers to a physical memory array, and “memory bank” refers to a logical unit of operation of memory access.

[0035] On the memory die 40, support circuits for operating the thin-film storage transistors of each tile are locally formed on or within the semiconductor substrate beneath the memory array. In some embodiments, the support circuits for each tile are locally formed and provided for modularization on a portion of the semiconductor substrate beneath each memory array. The tile-based support circuits, also referred to as modular control circuits or “under-array circuits” (“CuA”), may include various voltage sources for power supply, grounding, programming, erasing, or read voltages, sense amplifiers, various data latches or registers, various logic circuits, various analog circuits, and other circuits used in memory operation. Examples of logic circuits include timing control circuits, address decoder circuits, redundant logic circuits, and control circuits. Examples of analog circuits include data drivers, word line and bit line drivers and selection transistors, and bias control transistors. Furthermore, in embodiments of this disclosure, each CuA includes a state machine or sequencer for executing instructions (commands) performed on the associated tile. Each CuA incorporates a sequencer that functions as the CuA's local processor, allowing the CuA to form an intelligent control circuit that enables each tile to operate independently and self-contained, as well as enabling multiple tiles to operate simultaneously and independently.

[0036] During operation, the sequencer within each CuA associated with each tile receives commands from the controller circuit targeting the associated tile and decodes the commands to perform memory operations on the associated tile. For example, the sequencer performs read and write operations on the associated tile in response to commands received from the controller device. The sequencer also issues instructions (commands) to execute an entire read or write operation sequence on the memory page within the tile specified by the memory address associated with the memory operation. Importantly, in the memory die 40, the complete circuitry of the local module control circuit (CuA) is replicated for each tile so that each tile operates independently to perform memory operations in response to commands from the controller device addressed to that particular tile.

[0037] In embodiments of the present invention, a tile-based support circuit is formed on a semiconductor substrate by a first manufacturing process, and then the semiconductor substrate on which the tile-based support circuit is formed is subjected to a second manufacturing process for forming a thin-film storage transistor.

[0038] In this configuration, each tile 42 within the memory die 40 operates as a semi-autonomous miniarray of memory cells within the memory die 40. Intelligent CuA support circuitry allows each tile 42 to operate semi-autonomously, independently of other tiles within the memory die 40. Each tile 42 has its own associated CuA, enabling simultaneous memory access to multiple storage transistors within the memory die 40, resulting in improved memory throughput and reduced latency. In some embodiments, two adjacent tiles may share specific support circuitry within their CuA. For example, a tile may include a set of sense amplifiers that it shares with its adjacent tile. When each tile is selected for access, it uses its own set of sense amplifiers and the set of sense amplifiers of its adjacent tile. In this case, the tile whose set of sense amplifiers has been borrowed is marked as inaccessible until the borrowed sense amplifiers have finished operating.

[0039] In the embodiment shown in Figure 3, the memory die 40 is illustrated as containing tiles arranged in an 8x8 grid. The embodiment shown in Figure 3 is illustrative and not intended to limit the scope. For example, the memory die may contain 1024 tiles arranged in a 32x32 grid, or 2048 tiles arranged in a 64x32 grid. The number and arrangement of tiles within the memory die 40 can be selected based on various design factors, such as the size and dimensions of the memory die or the arrangement of interconnection structures.

[0040] In embodiments of the present disclosure, the memory die 40 is divided into a plurality of sections to form individual memory channels by dividing a two-dimensional array of tiles. In this embodiment, the memory die 40 is divided into four sections by tile rows to form four memory channels Ch0 to Ch3. In this embodiment, each memory channel (Ch0 to Ch3) includes two rows of eight tiles, with a total of 16 tiles per memory channel. In another example, in a memory die having 1024 tiles, the memory die can be divided into eight sections by tile rows to form eight memory channels, each memory channel including four rows of 32 tiles, with a total of 128 tiles per memory channel.

[0041] In embodiments of this disclosure, the memory die 40 includes a data interface area 43 for forming an interconnection structure 45 for connecting to a memory controller. In this embodiment, the data interface area is located in the center of the memory die 40 and midway between two tile rows. Furthermore, to support a memory channel configuration, the interconnection structure 45 is divided according to the channel configuration, with interconnection structures 45-0 to 45-3 provided for memory channels Ch0 to Ch3. For example, the interconnection structure 45 is a through-silicon via (TSV), and each memory channel has a dedicated set of interconnection structures or TSVs for transferring data for that memory channel to and from the memory controller, and more specifically, to the associated channel controller within the memory controller. As shown in Figure 3, the memory die 40 may include an additional set of interconnection structures 44 for supplying power and ground connections to the memory array formed within the tile 42. In some embodiments, as shown in Figure 2B, multiple memory dies 40 are used to form a memory stack, and the formed memory stack is stacked on a memory controller to form a memory module. Within the memory stack, memory channels are formed by tiles in the same channel section across all memory dies in the memory stack.

[0042] Figure 4A shows a memory structure 50 including a three-dimensional array of NOR-type memory strings according to several embodiments. In embodiments of this disclosure, the memory structure 50 of Figure 4A is used to form a three-dimensional array of storage transistors on tiles of the memory die 40 of Figure 3. Various methods for forming three-dimensional NOR-type memory strings are described in the aforementioned Patent Document 1. Referring to Figure 4A, the memory structure 50 includes thin-film storage transistors 60 formed as NOR-type memory strings along the horizontal direction (Y direction) in multiple planes, each plane being formed by a pair of active layers 56. Specifically, the memory structure 50 includes a number of active layers 56 formed on the plane of a semiconductor substrate 52. Buffer oxide layers 54 are provided between the semiconductor substrate 52 and the active layers 56. The active layers 56 are stacked on top of each other along the Z direction (i.e., the direction perpendicular to the plane of the semiconductor substrate 52) and are separated from each other by insulating dielectric layers 55, such as silicon oxide carbide (SiOC) layers. The active layer 56 is divided into narrow strips ("active strips") 57 in the X direction. The active strips 57 are stacked on top of each other to form a stack of active strips ("active stack") extending in the Y direction.

[0043] Each active layer 56 includes a first doped semiconductor layer 62 and a second doped semiconductor layer 64 (e.g., n+ polysilicon, or heavily doped n-type polysilicon) separated from each other by a dielectric layer 63 (e.g., silicon oxide). The first doped semiconductor layer 62 and the second doped semiconductor layer 64 form the drain and source regions of the storage transistor 60. Each active layer 56 includes one or more conductive layers 61, 65 (e.g., tungsten (W) lined with titanium nitride (TiN)). Each conductive layer 61, 65 is formed adjacent to one of the doped semiconductor layers 62, 64 to reduce the resistivity of the doped semiconductor layer in contact with it. During the intermediate processing step, the active layer includes a sacrificial layer (e.g., silicon nitride or carbon), which is later replaced by a conductive layer. In a subsequent processing step, a channel region 66 (e.g., p-polysilicon or lightly doped p-type polysilicon), a charge storage film 67, and a gate conductor or gate electrode 68 (e.g., TiN-lined W) are formed in narrow trenches between the active stacks, which are separated from each other. The gate electrode 68 and the charge storage film 67 are formed as columnar structures extending in the Z direction. In this embodiment, the columnar structure is formed by the charge storage film 67 surrounding the gate electrode 68. In this specification, the gate electrode 68 is also referred to as the "local word line," and the gate electrode 68 and the surrounding charge storage film 67 are collectively referred to as the local word line (LWL) structure 58.

[0044] In the embodiment shown in Figure 4A, the storage transistor in the three-dimensional memory array is a charge-trap type storage transistor, and the charge storage film 67 includes a tunnel dielectric layer, a charge trapping layer, and a blocking layer. The tunnel dielectric layer may be any silicon oxide (SiOx), silicon nitride (SixNy), silicon oxide nitride (SiON), any aluminum oxide (AlOx), any hafnium oxide (HfOx), zirconium oxide (ZrOx), any hafnium silicon oxide (HfSixOy), any hafnium zirconium oxide (HfZrO), or any combination thereof. The charge trapping layer may be multilayer and may include any silicon nitride (SixNy), hafnium oxide (HfO2), or hafnium silicon nitride (HfSiON). The blocking layer may be any silicon oxide (SiOx), aluminum oxide, or both. In one example, the charge storage film 67, also called an ONOA file, includes a silicon oxide layer (SiOx), a silicon nitride layer (SiN), a silicon oxide layer (SiOx), and an aluminum oxide layer (Al2O3), which are stacked in order from the channel layer towards the gate conductor layer.

[0045] The first and second doped semiconductor layers of each active strip form the source region 64 ("common source line") and drain region 62 ("common bit line") of the storage transistors formed along one or both sides of the active strip 57. Specifically, the storage transistors 60 are formed at the junction of the active strip 57 and the channel region 66 and the LWL structure 58. In the example of Figure 4A, the LWL structure 58 is formed alternately (staggered) within trenches adjacent to the active strip 57 so that the storage transistors formed on both sides of the active strip 57 are offset from each other in the Y direction along the memory string. When the storage transistors are ferroelectric storage transistors, the first and second doped semiconductor layers are omitted, and the conductive layers 61 and 65 function as source and drain terminals, as will be described in detail later.

[0046] In this configuration, the storage transistor 60 is composed of a first doped semiconductor layer 62 that forms a drain region (common bit line), a second doped semiconductor layer 64 that forms a source region (common source line), a channel region 66 that is in contact with both the drain region 62 and the source region 64, a gate electrode 68, and a charge storage film 67 located between the gate electrode 68 and the channel region 66. Each storage transistor 60 is isolated from adjacent storage transistors along the active stack (in the Z direction) by an insulating dielectric layer 55. In this configuration, along each active strip (in the Y direction), storage transistors that share a common source line and a common bit line form a NOR-type memory string (also referred to herein as a "horizontal NOR-type memory string" or "HNOR-type memory string").

[0047] In another embodiment, the storage transistors in the three-dimensional memory array are junction-less ferroelectric storage transistors. In some embodiments, the ferroelectric storage transistors are constructed in a similar manner to charge-trapped storage transistors by replacing the charge storage film with a ferroelectric gate dielectric layer incorporating a ferroelectric material. Figure 4B shows a memory structure including a three-dimensional array of NOR-type memory strings according to several embodiments. More specifically, Figure 4B shows an exemplary three-dimensional memory array of junction-less ferroelectric storage transistors. Similar elements in Figures 4A and 4B are denoted by the same reference numerals and their descriptions are omitted. Referring to Figure 4B, the memory structure 50B includes junction-less thin-film ferroelectric storage transistors 60B formed as NOR-type memory strings along the horizontal direction (Y direction) in multiple planes, each plane being formed by a pair of active layers 56. Each active layer 56 includes a first conductive layer 61 and a second conductive layer 65 (e.g., tungsten (W) lined with titanium nitride (TiN)) separated from each other by a dielectric layer 63 (e.g., silicon oxide). The first conductive layer 61 and the second conductive layer 65 of the ferroelectric storage transistor function as the drain terminal and source terminal. In a subsequent processing step, a channel region 66B (e.g., an oxide semiconductor material such as IGZO), a ferroelectric insulating layer 67B, and a gate conductor or gate electrode 68 (e.g., W lined with TiN) are formed in a narrow trench between the isolated active stacks. The gate electrode 68 and the ferroelectric insulating layer 67B are formed as a columnar structure extending in the Z direction. In this specification, the gate electrode 68 is also referred to as a "local word line," and the gate electrode 68 and the surrounding ferroelectric insulating layer 67B are collectively referred to as the local word line structure 58.

[0048] In the embodiment shown in Figure 4B, the storage transistor in the three-dimensional memory array is a junction-less ferroelectric storage transistor. In some embodiments, the ferroelectric gate dielectric layer 67B is a doped hafnium oxide (HfO2) layer. In one example, the hafnium oxide is doped with zirconium oxide (ZrO2) to form a hafnium-zirconium oxide layer (HZO). In another example, the hafnium oxide is doped with silicon (Si), iridium (Ir), and lanthanum (La). In some embodiments, the gate dielectric layer may further include an interface layer, such as a material having a high dielectric constant, between the channel region and the gate dielectric layer.

[0049] The first and second conductive layers of each active strip form the source line ("common source line") and drain line ("common bit line") of storage transistors formed along one or both sides of the active strip 57. In the example shown in Figure 4B, the storage transistors are formed on only one side of the active strip 57, while the other side of the active strip is adjacent to an auxiliary trench 59. The auxiliary trench 59 does not contain any active transistor elements. The ferroelectric storage transistor 60B is formed at the junction of the active strip 57 and the channel region 66B and the LWL structure 58. With this configuration, storage transistors sharing a common source line and a common bit line along each active strip (in the Y direction) form a NOR-type memory string or an HNOR-type memory string. In some examples, a three-dimensional array of NOR-type memory strings of junctionless thin-film ferroelectric transistors is disclosed in Patent Document 3 (the entire disclosure of Patent Document 3 is incorporated herein by reference). The memory structure 50B in Figure 4B can be constructed based on the memory structure described in Patent Document 3.

[0050] Referring to both Figures 4A and 4B, various types of support circuits that support the operation of NOR-type memory strings are formed inside or on the surface of the semiconductor substrate 52 to complete the memory circuit. As described above, the support circuits for the storage transistors in a tile are formed locally beneath each tile and are referred to as “circuit under array” or CuA. The circuits within the CuA may include power supplies, sense amplifiers, data latches, logic circuits, and analog circuits, as described above. In embodiments of this disclosure, the CuA includes a state machine or sequencer for controlling and executing memory operations in the storage transistors within each tile. By incorporating a state machine into each CuA, multiple tiles in the memory die can be accessed for simultaneous memory operations.

[0051] In an exemplary embodiment, each tile in the memory die includes eight active layers, i.e., eight storage transistor layers. Each active layer includes 2,000 bit lines (or 2,000 active stacks) with storage transistors formed on both sides of the bit lines, and each tile includes 4,000 word lines (gate electrodes), for a total of 8,000 bits per layer, and 64,000 bits or 64,000 storage transistors within one tile.

[0052] In some embodiments, memory operations on a memory die are performed in units of memory pages of memory data, also referred to as memory data access units. Each memory access, in this embodiment, is performed on one memory page within a memory bank (or tile). More specifically, the bit lines of storage transistors within the memory page are simultaneously selected, and the storage transistors are simultaneously identified to provide read data, or the storage transistors are driven by the same write operation to store write data. In one example, a memory page of memory data is 512 bits. Therefore, each time a read or write operation is performed, 512 storage transistors are accessed within the tile. In one embodiment, each memory access selects one of the 32 memory pages for the memory operation by activating a word line (WL) associated with 32 memory pages and selecting the bit lines associated with the storage transistors within the selected memory page.

[0053] In embodiments of this disclosure, each tile support circuit (CuA) includes the same number of sense amplifiers as the number of data bits in the memory page. Therefore, in each read operation, all sense amplifiers are used to read the stored data from the selected bit lines, thus eliminating the need for additional address bits to select a subset of sense amplifiers. Similarly, in write operations, all sense amplifiers are used to drive write data to the selected bit lines, thus eliminating the need for additional address bits to select sense amplifiers. This contrasts with conventional memory devices, which require one or more column address bits to select a subset of sense amplifiers to provide read data. By providing the same number of sense amplifiers as the number of data bits in the memory page within a CuA, the size of the CuA can be kept small, making it possible to form a CuA beneath each tile. Furthermore, memory operation is simplified because the address bits required to select a subset of sense amplifiers are eliminated. In some embodiments, the support circuit may include additional sense amplifiers to identify or drive additional bit lines related to other data stored in the memory array, such as refresh pointer data, metadata, or memory health indicator bits.

[0054] In one embodiment, the interconnection structure 45 (Figure 3) for each memory channel includes an interconnection structure for at least the number of data bits in the memory page. In one example, each set of interconnection structures 45 includes 300 through-silicon vias (TSVs) for each memory channel to output 512 data bits in the memory page over two clock cycles (256 bits per clock cycle), plus additional data bits for error correction and control signals.

[0055] In this description, the memory structure 50 in Figure 4A includes a storage transistor that implements charge trapping as a data storage mechanism, and the memory structure 50B in Figure 4B includes a storage transistor that implements ferroelectricity as a data storage mechanism. The exact nature of the data storage mechanism implemented in the memory structures of the present invention is not important to the implementation of the invention. As will be understood by those skilled in the art, the bias conditions applied to the storage transistor for read and write operations are a function of the data storage mechanism implemented. For illustrative purposes, the bias conditions for a ferroelectric storage transistor are used in the following description.

[0056] Figure 5 is a schematic diagram showing a memory array of a NOR-type memory string according to an embodiment of the present disclosure. Figure 5 shows a memory circuit of a NOR-type memory string that can be formed by the memory structure of Figure 4A or Figure 4B. Referring to Figure 5, a memory array 70 of storage transistors 72 is shown, representing a portion of the storage transistors in the three-dimensional memory array of Figure 4A or Figure 4B. The memory array 70 includes a plurality of memory strings 75 formed on each active layer, and each memory string 75 includes a series of storage transistors 72 connected in parallel to each other between a common bit line 74 and a common source line 76. Since the storage transistors are connected in parallel to each other in a NOR configuration, the memory strings 75 are also referred to as NOR-type memory strings. The NOR-type memory strings 75 of storage transistors form a basic structural block that can form a two-dimensional or three-dimensional array of storage transistors. That is, a plurality of strings of storage transistors can be used to form a two-dimensional array of storage transistors, or a plane of storage transistors. Furthermore, a three-dimensional array of storage transistors can be formed by stacking multiple planes of two-dimensional arrays of storage transistors. In this description, the semiconductor memory device is implemented by an array or multiple arrays of storage transistors, and the exact configuration or arrangement of the storage transistor strings is not important for the implementation of the invention.

[0057] The storage transistor 72 is a thin-film storage transistor having a drain terminal connected to a bit line 74, a source terminal connected to a source line 76, a gate terminal or control terminal connected to a word line 78, and a data storage film for storing data of the storage transistor. For example, the data storage film may be a set of charge storage films or a ferroelectric insulating layer. More specifically, the gate terminal of the storage transistor 72 is driven by a word line (WLx) 78, and each word line WLx activates one storage transistor 72 in a certain NOR-type memory string 75 and simultaneously activates other storage transistors in other NOR-type memory strings. With this configuration, when a word line WL is selected, all storage transistors 72 connected to that word line (e.g., WLn) are activated. During operation, the selected word line activates P memory pages. Each memory page contains Q storage transistors associated with Q NOR-type memory strings. The bit lines belonging to the selected memory page are selected for memory operation. Thus, the selected word line and the selected bit line select a memory page, thereby allowing access to the Q storage transistors within the selected memory page.

[0058] For example, the bit lines of each memory string are connected to a sense amplifier circuit to sense the data stored during a memory read operation. The sense amplifier circuit and other circuit elements, as well as control signals to facilitate the operation of the sense amplifier and memory array, are not shown in Figure 5. For example, the bit lines may include discharge transistors for discharging the bit lines after a read or write operation. In another example, the sense amplifier circuit may include transistors and devices for implementing a reset function of the sense amplifier. Furthermore, the sense amplifier circuit may include a latch circuit for latching the output of the sense amplifier. Details of an exemplary sense amplifier circuit will be discussed later with reference to Figure 6.

[0059] In embodiments of this disclosure, a memory device includes a storage transistor (or “memory cell”) that can be read, programmed, or erased. Programming and erasing operations are collectively referred to as write operations. The memory device performs memory operations that include read operations, which read data from the storage transistor, and write operations, which write data to the storage transistor. The memory device may perform other operations, such as refresh operations, but these are not described in this description. In this description, a write operation includes two operations or two phases: an erase operation or erase phase and a program operation or program phase. In these embodiments, the erase operation relates to writing a first logical state (e.g., logical “1”) to the memory cell, and the program operation relates to writing a second logical state (e.g., logical “0”) to the memory cell. Note that the specific logical states assigned to the erase operation or program operation are arbitrary and not important to the implementation of the invention. In other embodiments, the erase step relates to writing logical “0”) to the memory cell, and the program step relates to writing logical “1”) to the memory cell. In this embodiment, the erase operation is also referred to as the set 1 operation, and the program operation is also referred to as the set 0 operation.

[0060] In the memory array 70, each storage transistor in a NOR-type memory string is read, programmed, or erased by applying an appropriate bias to its associated word line 78 (WLx) and a common bit line 74 (BLy) shared with other storage transistors in the NOR-type memory string 75. The associated word line of a storage transistor is shared with storage transistors in other NOR-type memory strings aligned with the storage transistor along a direction perpendicular to the plane of the semiconductor substrate ("orthogonal direction"). Also, each word line is shared between two storage transistors in adjacent NOR-type memory strings on the same plane (see Figures 4A and 4B). In some embodiments, the common source line is typically electrically floating; that is, the common source line is not connected to any potential. During read, program, or erase operations, the common source line of a NOR-type memory string is typically supplied with a relatively constant voltage maintained by a voltage source or charge in an associated capacitor ("virtual ground"), such as the parasitic capacitance of the common source line. For example, the common source line of a NOR-type memory string can be biased to a given voltage by a pre-charge operation in which a desired voltage is supplied to the common bit line and the common source line is charged to the voltage on the bit line via one or more pre-charge transistors. To program or erase a storage transistor, a considerable voltage difference (e.g., 8V for charge-storage type storage transistors, 3V for ferroelectric storage transistors) is imposed between the common bit line and the word line. To mitigate disturbance to unselected storage transistors, undesirable erasure or programming of unselected storage transistors can be suppressed by imposing a predetermined voltage difference between the associated word line of an unselected storage transistor and its common bit line that is considerably lower than the voltage required for programming or erasing.

[0061] Figure 6 is a schematic diagram showing exemplary support circuitry connected to the bit lines of a NOR-type memory string according to embodiments of the present disclosure. Specifically, Figure 6 shows sense amplifier circuits and associated circuit elements for performing read and write memory operations. For simplicity of explanation, additional circuit elements and control signals are omitted. Referring to Figure 6, each bit line 74 is connected to a sense amplifier 80 via a bit line selector (not shown). In practice, each bit line selector is connected to P bit lines, and one of the P bit lines is selected for sensing by the associated sense amplifier. In other words, each bit line selector is connected to the bit lines of the same data bits across P memory pages. If the access unit contains 512 bits of memory data, there are 512 bit line selectors to select the bit lines of the memory pages selected for access. With such a configuration, the selected word lines activate P memory pages (e.g., 32 memory pages), and the set of bit line selectors in each sense amplifier selects the bit lines associated with the memory pages selected for access. Figure 6 shows the selected bit lines 74 connected to the sense amplifier 80. In Figure 6, for simplification, the bit line selector and other bit lines sharing the same sense amplifier are omitted.

[0062] During a read operation, the sense amplifier 80 senses a voltage signal indicating the bit line current on a selected bit line to determine the logic state of the selected storage transistor and generates a sense amplifier output SAOUT (node ​​82) in response to the sensing. In this embodiment, the sense amplifier output SAOUT (node ​​82) is connected to a pair of data latches 84 and 86. In this embodiment, the first data latch 84 (DL1) can be used to locally store data such as read data for a refresh operation in a memory tile. The second data latch 86 (DL2) can be used to store data exchanged with the memory controller, such as read data read from the selected storage transistor or write data received from the memory controller. It should be noted that the sense amplifier circuit configuration including the two data latches 84 and 86 is illustrative and not intended to be limiting. Other sense amplifier circuit configurations are possible. In one embodiment, the sense amplifier 80 itself may be configured to function as a data latch for storing read data, by incorporating the data latch function into the sense amplifier itself. In this case, the support circuit for each tile includes three data latches: a first data latch DL1, a second data latch DL2, and a third data latch DL3 as a sense amplifier. In this case, the third data latch DL3 (sense amplifier) ​​is used to store read data read from the selected storage transistor, and the second data latch DL2 is used to store write data received from the memory controller.

[0063] During a read operation, the sense amplifier 80 senses a voltage signal on the selected bit line 74 that indicates the bit line current associated with the erase or program state of the selected storage transistor. The sense amplifier 80 generates a sense amplifier output signal SAOUT having a logic state indicating the sensed bit line voltage signal. In one embodiment, during a read operation, the read data is stored in the data latch DL2. The read data is sent to the data bus 90 by the data driver 88 and provided to the memory controller. In practice, the data driver 88 is controlled by a clock signal and can send the read data to the data bus 90 in synchronization with the clock signal.

[0064] During a write operation, write data from the memory controller is sent to the data bus 90, and the write driver 92 sends the write data to the data latch DL2. The write driver 92 is also controlled by a clock signal and can send write data to the data latch DL2 in response to the clock signal. To perform an erase or program operation, the bit line (BL) bias control circuit 94, under the control of the state machine in CuA, applies a program voltage or erase voltage to the bit line 74 according to the logic state of the write data being written to the storage transistor.

[0065] Memory controller architecture

[0066] Figure 7 is a schematic diagram of a memory controller according to an embodiment of the present disclosure. In some examples, the memory controller 100 of Figure 7 can be used to realize the memory controller 14 of the memory module 30 of Figure 2A. Specifically, the memory controller 100 is configured to operate a memory device configured to have multiple memory channels that are accessed independently of each other. Referring to Figure 7, the memory controller 100 includes a host interface circuit 106 for interface with a host, a memory control circuit 110 for interface with the memory device 101, and a processor 108 that controls the operation of the host interface circuit 106 and the memory control circuit 110. The memory controller 100 operates on one or more clock signals. For example, the host interface circuit 106 may use a clock signal of a first clock frequency, and the memory control circuit 110 and the processor 108 may use a clock signal of a second clock frequency different from the first clock frequency. The clock signals for operating the memory controller are not shown in Figure 7 for the sake of simplicity, but it should be understood that the memory controller 100 operates on one or more clock signals.

[0067] The host interface circuit 106 is connected to the host interface bus 102 for communicating with a host, such as a host processor. The memory controller 100 receives requests from the host processor via the host interface circuit 106 and sends responses to the host processor. For example, the memory controller 100 receives read requests and write requests with write data from the host via the host interface bus 102. The memory controller 100 provides read data and write completion responses to the host via the host interface bus 102. In an exemplary embodiment, the host interface circuit 106 communicates with the host via the PCIe 5.0 serial bus using the CXL (Compute Express Link™) protocol. In the CXL protocol, the host processor issues a Request Without Data (REQ) as a read request and a Request with Data (RwD) as a write request with write data. Also in the CXL protocol, the memory controller 100 issues a Response with Data (DRS) as read data and a Response Without Data (NDR) as a write completion response.

[0068] The memory control circuit 110 operates on the memory channels of the memory device 101 and is configured to communicate with the memory device via the memory array interface 103. In embodiments of this disclosure, the memory device 101 is a memory stack comprising a plurality of memory dies formed by stacking them together. In this embodiment, the memory stack 101 includes four memory dies, namely die 0, die 1, die 2, and die 3. The memory dies in the memory stack 101 are divided into N independently accessible memory channels according to the memory channel configuration scheme described above. In this embodiment, the four memory dies, namely die 0, die 1, die 2, and die 3, are divided into four memory channels, namely Ch0, Ch1, Ch2, and Ch3. In other examples, the memory dies may be divided into four or sixteen channels. Under the memory channel configuration scheme in the exemplary embodiments of this disclosure, each memory channel Chn is formed across all semiconductor dies in the memory stack 101. That is, each memory channel Ch0 to Ch3 contains memory compartments from the memory dies, namely die 0 to die 3. The memory control circuit 110 communicates with the memory stack 101 via a memory array interface 103, which includes individual memory channel interfaces 104-0 to 104-3 for each memory channel Ch0 to Ch3. Specifically, each memory channel interface 104-n includes a data interface and a command interface for each memory channel.

[0069] The configuration of the memory device 101 in Figure 7 is illustrative and not intended to limit the scope. The memory control circuit 110 is configured to operate a memory device of any configuration, such as a single semiconductor memory die or multiple semiconductor dies. The memory control circuit 110 is configured to operate on the memory channels of a memory device, where the memory channels may be configured in various ways. The exact channel configuration of the memory device is not important to the implementation of the present invention. In Figure 7, the memory device is a memory stack, and the channel configuration spans the memory dies in the stack. In another example, the memory device includes a plurality of memory dies (e.g., k memory dies) arranged planarly adjacent to a memory controller, and each memory die includes a plurality of memory channels (e.g., n memory channels). The memory control circuit 110 of the memory controller 100 can be configured to operate k × n memory channels across the k memory dies.

[0070] The memory control circuit 110 includes a channel controller 116 which is instantiated N times to provide one channel controller 116 for each memory channel. In this embodiment, four instances of the four channel controllers 116, including channel controllers 0 to 3, are provided for the four memory channels of the memory stack 101. Each channel controller 116 communicates with the memory channel via each memory channel interface 104-n. In this way, each memory channel Ch0 to Ch3 of the memory stack 101 is accessible independently of each other, and high-bandwidth memory access can be achieved by accessing memory channels Ch0 to Ch3 in parallel.

[0071] The memory control circuit 110 further includes an address translation circuit 114 and a channel arbiter 112, both of which communicate with all channel controllers 116. The host interface 106 receives input requests from the host, and input requests such as read requests (REQ) and write requests (RwD) are provided to the address translation circuit 114 of the memory control circuit 110. The address translation circuit 114 decodes the logical address in each request to determine which memory channel the request should be sent to, and sends the request to the channel controller 116 of the specified memory channel. Once the memory operation is complete, each channel controller 116 provides a response, such as read data or a write completion response, to the channel arbiter 112. The channel arbiter 112, under the control of channel arbitration logic, selects which responses to send to the host interface 106. For example, the channel arbitration logic returns responses in the same order as the corresponding requests received. In another example, the channel arbitration logic implements a credit management scheme that determines which responses to return to the host processor from which memory channel. In some examples, the channel arbitration logic is implemented within processor 108.

[0072] Figure 8 is a schematic diagram of a channel controller implemented in the memory controller of Figure 7 according to an embodiment of the present disclosure. As described above with reference to Figure 7, the memory controller 100 receives input requests on the host interface bus 102, and the received requests are provided to the address translation circuit 114 of the memory control circuit 110. The address translation circuit 114 decodes the logical address in the request and generates the physical address of the memory device 101 corresponding to that logical address. In this specification, the physical address is also referred to as the memory address. Based on the channel address indicated in the decoded physical address, the requests are provided to each channel control unit 116. In some embodiments, the address bit for selecting a memory channel is the lower address bit of the physical address. In this way, input requests are distributed to different memory channels, reducing channel contention and consequently improving memory utilization. As a result of address translation, each channel controller 116 receives input requests for a specified read or write operation for its memory channel.

[0073] It should be noted that the operation of the channel controller 116 is based on one or more clock signals. Typically, the channel controller 116 operates based on a controller clock signal at a given clock frequency. Signals sent to and from the channel controller may cross over different clock domains (i.e., different clock frequencies). In this case, a buffer or clock crossing FIFO circuit may be used for signals that cross over at two different clock frequencies. For the sake of simplicity, the clock signals and associated clock crossing circuits are not shown in Figure 8. It should be understood that the operation of the channel controller is synchronized with the controller clock signal. For example, the channel controller 116 sends commands to the memory device 101 in each clock cycle of the controller clock signal. In one example, the controller clock signal has a frequency of 500 MHz, and the channel controller sends commands to memory devices where available commands exist, every clock cycle or every two clock cycles, i.e., every 2 ns or every 4 ns.

[0074] In some embodiments, the address translation circuit 114 decodes the logical address in the request into a physical address that includes a memory channel address, a memory bank address, a memory die address, a word line address, and a memory page address. Thus, the decoded physical address selects a memory channel from N memory channels and a memory die from K memory dies within the selected memory channel. The physical address further selects a memory bank (or memory tile) within the selected memory die of the selected memory channel. Within the selected memory bank, the physical address selects a word line, thereby activating P memory pages within the memory tile. The physical address finally selects one memory page from the P memory pages associated with the selected word line. As described above, each memory page contains Q data bits, for example, 512 bits.

[0075] Referring to Figure 8, the channel controller 116 receives input read requests or input write requests from the address translation circuit 114 and stores the requests in their respective ingress buffers. Specifically, input read requests are stored in the ingress read buffer 120, and input write requests are stored in the ingress write buffer 122. Input write requests are then provided to and stored in the write staging buffer 128 as pending write requests. The ingress channel arbiter 124 adjusts the flow of pending read and write requests to the read queue 130 and write queue 132 based on one or more predetermined priority rules provided by the read / write arbitration logic circuit 125. Specifically, the ingress channel arbiter 124, based on predetermined priority rules, arbitrates pending read requests from the read ingress buffer 120 and pending write requests evicted from the write staging buffer 128, and selects which requests to send to the read queue 130 and write queue 132. For example, the ingress channel arbiter 124 may prioritize read requests as long as the write staging buffer is not nearly full for one or more memory banks. The ingress channel arbiter 124 may also consider additional attributes such as the elapsed time of the request and the state of the memory banks when determining priority. In another example, the ingress channel arbiter 124 may forward read requests to a read queue or write requests to a write queue to avoid excessive bank contention.

[0076] The read queue 130 and write queue 132 store read and write requests and generate commands for the memory device 101 based on the stored requests. The read queue 130 and write queue 132 generate commands to bid access to the memory device 101 via a command selector 135, also called a global arbitration circuit or global scheduler. The command selector 135 selects the commands to be sent to the relevant memory channels of the memory device 101 in order to perform memory operations at the destination memory addresses associated with each request. The commands selected by the command selection unit 135 are also called "winning commands".

[0077] In embodiments of this disclosure, the channel controller 116 in Figure 8 is adapted to a memory device where the write latency is much longer than the read latency. A notable feature of the channel controller of the present invention is that the channel controller is configured to mask what may be a long write latency from the host. In some embodiments, the channel controller 116 stores an input write request and the write data in a write staging buffer 128 and returns a write completion response to the host before the write operation is actually performed on the memory device, i.e., before the write data is stored on the memory device. At the same time, the channel controller 116 manages the write request and performs the write operation to the memory device in the background of the host operation, thereby hiding the extended write latency on the memory device from the host system, so that the host system can operate as if there were only the nominal write latency on the memory device.

[0078] In some embodiments, in the channel controller 116, each write request stored in the ingress write buffer 122 is first evicted to the write staging buffer 128, and then the pending write request entries in the write staging buffer 128 are provided to the ingress channel arbiter 124 for arbitration with read requests from the ingress read buffer 120. In one example, using the write staging buffer 128 can prevent a back pressure on the ingress write buffer 122 caused by too many write requests to the same memory bank on the memory channel being sent to the write queue 132, which would fill the write queue. In some embodiments, the write staging buffer 128 is sized to store a large number of write requests sufficient to handle the write latency of the memory device masked from the host. In this embodiment, the evicting of write requests from the ingress write buffer 122 to the write staging buffer 128 notifies the host of a write completion response. In other words, each time a write request is evicted from the ingress write buffer 122 and transferred to the write staging buffer 128, a write completion response for that write request is sent to the host. From the host's perspective, that particular write request is completed while the channel controller 116 maintains and processes the write requests that should be completed in the memory device 101. In this embodiment, write completion responses for each memory channel n (e.g., NDR under the CXL protocol) are provided to the channel arbiter 112b, which receives write completion responses from all memory channels (e.g., Chn, x~z). The channel arbiter 112b selects write completion responses from the memory channels provided to the host via the host interface, based on predetermined arbitration rules.

[0079] As described above, the ingress channel arbiter 124 arbitrates read requests from the ingress read buffer 120 and write requests from the write staging buffer 128 based on predetermined priority rules, and selects which requests to send to the read and write queues. In another example, the ingress channel arbiter 124 may forward read requests to the read queue or write requests to the write queue to avoid excessive bank contention. For example, if there are pending write requests for a given memory bank on a given memory die in the write queue, the ingress channel arbiter 124 will not forward additional write requests for the same memory bank on the same memory die to the write queue, but instead will forward write requests destined for other memory banks to the write queue. In this way, the ingress channel arbiter 124 avoids sending an excessive number of write requests to the write queue 132 for the same memory bank on the same memory die, which would cause the write queue to become full if the memory device has a long write latency.

[0080] In embodiments of the present disclosure, the ingress channel arbiter 124 further evaluates incoming read requests to determine whether the read request is for the same memory address as a write request pending in the write staging buffer 128. In embodiments of the present disclosure, the ingress read buffer 120 transfers the memory address ("read address") of the pending read request to the write staging buffer 128. The write staging buffer 128 determines whether the read request is for the same memory address as a pending write request in the write staging buffer 128. If the write staging buffer 128 determines that the read request has a memory address that matches the destination memory address of the pending write request in the write staging buffer, the channel controller 116 employs various techniques to provide the write data of the matching pending write request as the read data for the read request. In one example, the read request is satisfied by the write data from the write staging buffer 128. In another example, the channel controller 116 forwards matching pending write requests to the write queue 132, and read requests are satisfied by write data from the write queue 132 (more specifically, the write data storage 134 associated with the write queue).

[0081] In this embodiment, the read queue 130 is a data structure that stores pending read requests to the associated memory channel. The read queue 130 stores pending read requests along with the destination memory address, such as the memory bank address or memory page address for that read request. The read queue 130 further stores other attributes associated with each read request, such as the state of the memory bank indicated by the destination memory address, and commands being processed in the memory bank. The state of the memory bank ("bank state") is used to indicate whether the read request is eligible to be sent to the memory device. In this embodiment, each entry in the read queue 130 can request the transmission of an activation command, a read command, or an interrupt command. An activation command instructs the memory device to use a sense amplifier circuit to begin sensing data stored in a specified memory page of a specified memory bank, and to store the sensed data in a data latch connected to the sense amplifier circuit (e.g., data latch DL2 in Figure 6). A read command outputs the sensed data stored in the data latch to the channel controller 116. For example, data read from memory device 100 is stored in read data storage 142. Details of the interrupt command will be described later.

[0082] In this embodiment, the write queue 132 is a data structure that stores active write requests to the associated memory channel. The write queue 132 stores active write requests along with the destination memory address (e.g., memory bank address, memory page address) for each write request. In this embodiment, the write data for each write request is stored in the write data storage unit 134, which communicates with the write queue 132. For each write request, the write queue 132 further stores other attributes associated with each write request, such as the state of the memory bank indicated by the destination memory address and commands being processed in the memory bank. The memory bank state ("bank state") is used to indicate whether the write request is eligible to be sent to the memory device. In this embodiment, each entry in the write queue 131 can request the sending of a write command. The write command is sent to the memory device along with the associated write data stored in the write data storage unit 134, instructing the memory device to write the data to a specified memory page in a specified memory bank. In some embodiments, the write data is first stored in a data latch (e.g., data latch DL2 in Figure 6), and the bit line bias control circuit sends the write data to the storage transistor.

[0083] In this embodiment, the channel controller 116 includes an issued write queue 133. The write queue 132 assigns an active write request entry to the issued write queue 133 if the command selector 135 indicates that the active write request is a winning command. Specifically, the write queue 132 sends a write command along with the write data to the memory device 101 in response to an active write request selected by the command selector 135. For example, the write data is sent to the memory device 101 and stored in a data latch (e.g., data latch DL2) for the specified memory page. The write queue 132 then forwards the write request to the issued write queue 133. The issued write queue 133 processes the rest of the write operation flow. For example, each entry in the issued write queue 133 can send a commit command to instruct the memory device 101 to begin a bias voltage sequence for writing the previously sent write data to the storage transistor at the destination memory address. For example, a commit command is sent to activate a program, erase, or refresh operation flow in the support circuit (CuA) of a specified memory tile, and the support circuit (CuA) applies the appropriate voltage to the bit line of the storage transistor associated with the selected memory page. The issued write queue 133 releases the write request when the write flow is complete, i.e., when the erase and program operations in the storage transistor are complete. Furthermore, in this embodiment, each entry in the issued write queue 133 may also send a write resume command, as will be described in detail later.

[0084] In some embodiments, the issued write queue 133 stores the issued write requests until they are completed. Note that the use of the issued write queue 133 is optional and may be omitted in other embodiments. In other embodiments, the issued write requests may be stored in the write queue 132 itself until the write requests are completed.

[0085] In this embodiment, an active read or write request in each read / write queue is eligible for a bid access if the destination memory bank does not currently have any memory operations running. For example, a read or write request is eligible if the destination memory bank is not currently being read from or written to. Eligible read or write requests bid for access to the memory device 101 via the command selector 135. The command selector 135 arbitrates the commands received from eligible read or write requests and determines the command to send to the memory device 101 each clock cycle (or every x clock cycles) ("winning command").

[0086] In embodiments of this disclosure, the command selector 135 selects commands to send to the memory device 101 based on a predetermined priority rule. In these embodiments, the command selector 135 sends commands to the respective memory channels of the memory device via two command buses: (1) a memory command bus 144 for non-data commands such as activation commands, interrupt commands, commit commands, and write resume commands, and (2) a data command bus 146 for data commands such as read commands and write commands. In some embodiments, the command selector 135 includes a memory command selector 136 and a data command selector 138 for selecting from eligible commands provided by read queues 130 and write queues 132. The memory command selector 136 selects commands to be sent to the memory device on the memory command bus 144, and the data command selector 138 selects commands to be sent to the memory device on the data command bus 146. In these embodiments, a command provided to the memory command selector 136 is, for example, an activation command for setting up a read operation. Commands sent on the memory command bus 144 are not associated with read data or write data. On the other hand, examples of commands provided to the data command selector 138 include read commands and write commands. Synchronized with the provision of a write command on the data command bus 146, the associated write data is provided from the write data storage 134 onto the data bus 148. In response to a read command, the memory device 101 provides read data onto the data bus 148 and stores the read data in the read data storage 142. The read data is provided as a read data response to the memory channel.

[0087] In this embodiment, a read data response (e.g., DRS) for each memory channel n is provided to the channel arbiter 112a, and the channel arbiter 112a receives read data responses from all memory channels (e.g., Chn, x~z). Based on predetermined arbitration rules, the channel arbiter 112a selects which memory channels to provide to the host via the host interface.

[0088] In embodiments of this disclosure, the channel controller 116 is configured to operate in a manner that maximizes the performance of the memory device. For example, in one embodiment, the channel controller is configured to operate in a greedy mode, always attempting to send commands to the memory device for execution as long as there are pending requests. Thus, the read queue 130 and the write queue 132 always send eligible commands to the command selector 135 in order to bid for access to the memory device. The command selector 135, on the other hand, operates based on a predetermined priority rule and selects a winning command to send to the memory device every x clock cycles (where x is 1 or greater). In one example, the command selector 135 is configured in a read-first mode, where commands for write operations are sent in the free clock cycles between commands for read operations. In another example, the command selector 135 is configured in a write-first mode, where commands for read operations are sent in the free clock cycles between commands for write operations. In some embodiments, the predetermined priority rule includes a fixed priority rule or a dynamic priority rule.

[0089] During operation, the read queue 130 and write queue 132 store active read and write requests to the memory device, with each read / write request relating to a destination memory page in the destination memory bank of the destination memory die of the memory channel. The read queue 130 and write queue 132 determine which of the pending requests stored therein are eligible to be executed on the memory device. The read queue 130 and write queue 132 always attempt to send all eligible commands to the command selector 135. The command selector 135 arbitrates the commands using predetermined priority rules and selects a winning command every clock cycle (or x clock cycles). The winning command is then sent to the memory device 101 (along with the write data on the data bus 148) via the respective memory command bus 144 or data command bus 146. To track the memory operations being performed on the memory device, the winning command is provided to a command tracker 140, which operates to track the progress of each command sent to the memory device. Winning commands are also provided to the bank tracker 145, which tracks the status of each memory bank in the memory channel. The read queue 130 and write queue 132, as well as the issued write queue 133, use the information in the bank tracker 145 and command tracker 140 to determine the status of each memory bank for which a request is pending, and based on the determined bank status, the command selector 135 determines a command that is eligible for a bid to access.

[0090] In some embodiments, the bank tracker 145 is a data structure that stores bank state data for each memory bank in the memory channel, where the bank state indicates whether a given memory bank is inactive (i.e., eligible to receive commands) or busy (i.e., not eligible to receive commands). The bank tracker may further store data indicating memory operations being performed on the busy memory bank. The read queue 130 and the write queue 132 obtain the state of each memory bank related to their respective pending requests from the bank tracker 145.

[0091] In some embodiments, the command tracker 140 tracks each command being sent and executed in each memory bank of the memory device based on clock timing. In one embodiment, each command executed in the memory device 101 is assigned a predetermined command execution time. The command tracker 140 tracks commands issued for execution in the memory device and indicates that a given command has completed when the predetermined command execution time assigned to that command has expired. In some examples, the progress of each executed command is tracked using clock cycles. In one example, commands sent to the memory device 101 share the same time base, for example, commands are sent every 4ns. In some embodiments, the command tracker 140 is implemented as a shift register. In one example, a winning command is assigned to the beginning of the shift register and is shifted every clock cycle to track the progress of commands being executed in the memory device. In some embodiments, configurable tap points are provided within the shift register to indicate associated timing limits. Commands progressing through the shift register are compared with each tap point. A tap point match indicates that the time or clock cycles elapsed from the issued command to a given tap point. In this way, the command tracker tracks the progress of each command issued to the memory device. A command that has progressed beyond the tap point associated with its allocated command execution time is shown as a completed command, and its associated memory bank is shown as free.

[0092] In this configuration, the read queue 130 and write queue 132 determine the bank status and ongoing memory operations for each memory bank where a request is pending. Based on the bank status and progress of memory operations, the read and write queues can determine whether a pending request is associated with a busy memory bank or with an inactive or free memory bank. For pending requests associated with an inactive memory bank, the read and write queues issue commands that are eligible to bid for access. The memory command selector 136 and data command selector 138 of the command selector 135 select a winning command from the eligible commands each clock cycle and send it to the memory device 101. The command tracker 140 and bank tracker 145 update their respective states each clock cycle in response to the winning command. In this way, the winning command is identified to the read queue 130 and write queue 132, and the bank status associated with the memory bank of the winning command is updated to busy. As a result, pending requests for the same memory bank become ineligible to bid.

[0093] This specification describes the structure and operation of a channel controller in order to illustrate the process flow from receiving a request to generating a command to the memory device. It should be understood that the channel controller may include other circuit elements not shown or described to support memory operation. For example, the channel controller may perform error detection and correction. The channel controller may also include an ECC encoder for performing error correction coding and an ECC decoder for detecting and correcting bit errors, thereby preventing data loss. The ECC circuit and other supporting circuits of the channel controller are omitted in Figure 8 for the sake of simplicity.

[0094] In the embodiments described above, the memory device is formed by a memory stack of K memory dies, each having memory channel partitions across the memory dies in the stack. In another embodiment of the present invention, the K memory dies of the memory device are arranged side by side on an interconnect structure such as an interposer, adjacent to a memory controller die formed on the same interconnect structure. Such a packaging structure is also referred to as 2.5-dimensional packaging. In some examples, when formed on an interposer, the interposer provides high-density die-to-die connectivity between the K memory dies and the memory controller die. In some embodiments, each memory die is divided into S memory channels, and together with the K memory dies, they form S × K memory channels. Such a configuration provides the memory device with a large number of memory channels, thereby having the beneficial effect of reducing access contention and increasing the availability of memory banks in the K memory dies.

[0095] In the embodiments described above, the memory device includes a memory stack of K memory dies formed by stacking them on top of each other, and the K memory dies provide the intended or specified memory capacity of the memory module. In embodiments of the present invention, the memory stack includes at least one additional spare memory die used to provide redundant memory capacity within the memory module. In some embodiments, the spare memory die is formed as part of the memory stack and is connected to the K memory dies via the same interconnect structure that connects the K memory dies, such as a TSV.

[0096] Therefore, in some embodiments, the memory module includes a memory device integrated with a memory controller, and the memory device is formed by a memory stack containing K+1 memory dies. In such a configuration, preferably, the K memory dies provide the intended or specified memory capacity of the memory module, and one additional memory die ("spare memory die") provides additional memory capacity for redundancy. In such a configuration, the memory address space of the spare memory die is unknown to the host processor and known only to the memory controller. That is, the host processor is unaware of the physical existence of the spare memory die or the memory address space associated with it. The host processor is only aware of the memory address space of the K memory dies ("host address space"). That is, requests sent from the host processor to the memory module are directed only to the memory address space across the K memory dies that is known to the host processor. The memory controller, on the other hand, controls the physical memory address space across the K+1 memory dies and manages the mapping of logical memory addresses in the host address space to physical memory addresses, including mapping to the spare memory die when redundancy substitution is applied. In other words, the memory controller communicates with the host processor over a memory address space spanning K memory dies and manages memory operations in a memory address space spanning K+1 memory dies. In some embodiments, the memory controller controls and directs access to a spare memory die via an address translation circuit, for example, when the memory capacity of a spare memory die is applied to replace a non-functional or faulty memory tile in the known address space of the K memory dies.

[0097] In another embodiment, the memory module includes a memory device integrated with a memory controller, the memory device being formed by K+1 memory dies arranged side-by-side on an interconnect structure with the memory controller in a packaging structure also referred to as 2.5-dimensional packaging. In some examples, the interconnect structure is an interposer. In other examples, the K+1 memory dies are arranged side-by-side surrounding the memory controller on the interconnect structure. Importantly, the K+1 memory dies of the memory device of the present invention may have various packaging structures, either stacked (3-dimensional) or 2.5-dimensional packaging. The specific packaging structure of the K+1 memory dies and the memory controller die thereof is not important to the implementation of the present invention.

[0098] In some embodiments, the memory controller is configured to monitor the operational or health status of memory arrays (or tiles) within each memory die. For example, the memory controller can acquire health information of storage transistors while performing a refresh operation. The memory controller can also perform error correction on memory data read during a read operation and determine the health or operational status of the memory array and / or storage transistors within the memory array. The memory controller can determine that one or more memory arrays are not functioning properly, have lost function, are faulty, or are of degraded health. In this specification, a memory array (tile) is considered not functioning properly or is faulty if one or more storage transistors within the memory array are not functioning properly or are faulty, or if other transistors or circuit elements within the memory array are not functioning properly or are faulty. For example, a faulty storage transistor or a storage transistor with degraded health refers to a storage transistor that is still functioning but has degraded electrical characteristics, such as having a smaller memory window than expected, a lower-than-expected transistor "on" current (Ion), or significantly deviating from the storage transistor's performance specifications. In another example, a memory controller detects that one or more memory arrays are not functioning properly or have failed by detecting a significant deviation from the performance specifications of the memory devices.

[0099] In some embodiments, the memory controller is configured to determine whether one or more memory arrays (tiles) that are not functioning properly or are faulty should be replaced. If the memory controller determines that redundant replacement should be applied to tiles in K memory dies, it replaces the faulty memory tiles with redundant memory tiles in a spare memory die. The memory controller manages address mapping information so that future requests received from host processors addressing the replaced memory tiles in the host address space are directed to the replaced memory tiles in the spare memory die.

[0100] For example, if, during the operational life of a memory module, one of the K memory dies is detected to be failing or in the process of failing, the memory controller replaces the suspected tile with a working tile from a spare memory die. In some embodiments, redundant substitution can be performed on individual tiles or groups of tiles. In some embodiments, the memory controller's address translation circuitry manages the mapping of logical memory addresses in the host address space to physical memory addresses, so that requests from the host processor to the replacement memory bank of the K memory dies are redirected to the replacement memory bank in the spare memory die. The tile swapping operation using the physical memory addresses of the spare memory die is completely transparent to the host processor and is managed internally within the memory module by the memory controller. The host processor can continue to operate using the logical memory addresses in the host address space. Meanwhile, the memory controller controls the physical memory address space of the K+1 memory dies and manages the mapping of logical memory addresses to physical memory addresses, including the mapping to the spare memory die when redundant substitution is applied. In this way, the memory module continues to support the full specified memory capacity even if some tiles or some storage transistors within a tile within the K memory dies malfunction or fail. Furthermore, the memory controller anticipates the imminent failure or degradation of one or more tiles and initiates redundancy replacement, thereby improving the operational reliability of the memory module.

[0101] In some embodiments, the memory controller's address translation circuit (e.g., address translation circuit 114 in Figure 8) is configured to process requests input from the host processor and be received by the memory module, with each request containing a logical memory address in the host address space of K semiconductor memory dies. The memory controller's address translation circuit translates the logical memory address of the input request into a physical memory address that identifies a storage transistor in one of the K+1 semiconductor memory dies. Specifically, the memory controller's address translation circuit addresses a non-functioning or failed memory array and manages the mapping of logical memory addresses in the host address space to physical memory addresses in the memory address space of a spare memory die. The host processor continues to send requests to the memory module using the logical memory addresses in the host address space of the K memory dies, while the memory controller manages the mapping of logical memory addresses to physical memory addresses on the K+1 memory dies, including mapping the logical memory addresses to physical memory addresses on the spare memory dies when redundant substitution is applied, via the address translation circuit.

[0102] Memory device architecture

[0103] In embodiments of the present invention, the memory device described herein implements a tile-based architecture including an array or arrangement of tiles of memory transistors that can operate independently and simultaneously, each tile including memory transistors arranged in a three-dimensional array and a local modular control circuit that operates the memory transistors within the tile. The tile-based architecture of the present invention enables simultaneous memory access to multiple tiles within the memory device, thereby enabling independent and simultaneous memory operations across multiple tiles. Tile-based simultaneous access to the memory device has the advantage of increasing memory bandwidth and reducing the tail latency of the memory device by ensuring high availability of storage transistors.

[0104] In this specification, concurrency of memory access means that multiple memory operations are performed simultaneously on multiple randomly addressed tiles of a memory device, each tile performing a memory operation on a unit of memory data access or a memory page. In some examples, memory operations include read operations, write operations, and refresh operations. In other words, the memory device operates with overlapping memory operations performed across multiple tiles, and while the memory device is executing previously received commands, it continues to receive commands from the controller device, each command being executed by or directed to a different tile within the memory device. If the memory device is divided into multiple memory channels, concurrency of memory access means that multiple memory operations are performed simultaneously on multiple tiles in each channel of the memory device. Furthermore, in this description, multiple memory operations are performed asynchronously. That is, multiple memory operations do not start in the same clock cycle, but rather start in different clock cycles when the memory device (or memory channel) receives a command.

[0105] Concurrency of memory access is particularly beneficial in memory devices with asymmetric read / write latencies. In exemplary embodiments of the present invention, a memory device may have a write latency much longer than its read latency. For example, the write latency may be 300 ns to 1 μs, and the read latency may be 70 to 90 ns. In this case, overlapping read and write operations occur simultaneously on different tiles, improving memory performance by continuing to provide high memory bandwidth and high memory availability despite the long write latency of the memory device. Conventional memory devices (e.g., DRAM) that do not have asymmetric read and write latencies, or have short read and write latencies, typically do not need to implement concurrency of memory access because they operate by completing each memory operation before the next operation. In memory devices having asymmetric read latency / write latency, or write latency longer than read latency, such as the memory device in the embodiments of this disclosure, overlapping memory operations can be performed to mask those with long write latency, so that the memory device behaves as if it had short read latency and write latency.

[0106] In embodiments of the present disclosure, a memory structure for forming a memory device of the present invention includes a memory array portion configured as described above with reference to Figures 4A and 4B to form a three-dimensional array of NOR memory strings of randomly accessible storage transistors. To complete the memory device, the memory structure includes a stepped portion provided at the end (Y direction) of the memory string, as shown in Figure 9. The thin-film storage transistors of the NOR memory string are formed within the memory array portion, and the stepped portion on the opposite side of the array portion includes a stepped structure that provides connections via conductive vias to a common bit line and optionally a common source line of the NOR memory string. In some embodiments, the common source line is pre-charged to function as a virtual voltage reference source during programming, read, and erase operations, thereby eliminating the need for continuous electrical connections to support circuits during such operations. Herein, the common source line is described as electrically floating to mean that there is no continuous electrical connection to the common source line. In embodiments of the present disclosure, various processing steps can be used to form the stepped structure within the memory structure. The processing step for forming the staircase structure may be performed before, after, or in between the processing steps for forming the memory array portion.

[0107] Referring to Figures 4A and 4B, the memory structure described above illustrates the configuration of a memory array including a three-dimensional array of NOR-type memory strings. This memory structure can be used as a building block for forming high-capacity, high-density memory devices. In embodiments of the present disclosure, the memory structure described above can be used as a building block for forming tiles, which include memory arrays as modular memory units and local modular control circuits formed beneath the memory arrays. The memory devices of the present disclosure are formed using arrays of tiles. In one exemplary embodiment, the memory device is configured as a two-dimensional array of tiles arranged along the X and Y directions, where each tile includes a three-dimensional array of storage transistors with support circuits and control circuits formed beneath each tile. More specifically, the memory device includes multiple memory arrays of thin-film storage transistors configured as a two-dimensional array of “tiles” formed on a plane of a semiconductor substrate (i.e., the tiles are arranged in a matrix). Each tile is configured to be individually addressable. Such a configuration makes the tiles modular units, allowing for flexibility in configuring memory modules to suit application requirements.

[0108] Figure 9 is a cross-sectional view in the YZ plane of a tile in a memory device according to an embodiment of the present invention. Referring to Figure 9, a tile 201 is formed on a semiconductor substrate 200. The memory structure of the tile 201 is formed in an insulating film 211, and a protective film 212 (passivation film) is formed on the insulating film 211. In some embodiments, the insulating film 211 is silicon oxide (SiO2). x) is formed from, and the protective film 212 is formed from polyimide. In this embodiment, the memory structure includes a three-dimensional array of storage transistors ("memory array") configured as described above with reference to the memory structure of Figure 4A or Figure 4B. More specifically, the memory structure may be a three-dimensional array of charge-trap type storage transistors (Figure 4A) or a three-dimensional array of junction-less ferroelectric storage transistors (Figure 4B).

[0109] A P-type or N-type diffusion region 221 is formed on the upper surface of the semiconductor substrate 200. Other structures (not shown in Figure 9), such as isolation structures or shallow trench isolation (STI) structures, may also be formed on the semiconductor substrate 200. A gate electrode 222 is formed on the semiconductor substrate 200 and is insulated from the semiconductor substrate by a gate dielectric layer. For example, the gate dielectric layer may be a thin silicon oxide layer. The gate electrode 222, together with the P-type and N-type diffusion regions 221, forms a transistor within the semiconductor substrate 200. This transistor can be used to form a circuit element. For example, this transistor can be used to form a support circuit for operating a storage transistor in a three-dimensional NOR-type memory array formed on a tile 201. The circuit elements are interconnected by interconnection portions 224 formed within the insulating film 211 of the lower interconnection portion 232, and by contacts 223 connected to one or more layers of vias 225, forming a support circuit. In some embodiments, the support circuit for the storage transistor is provided in the circuit element portion 231 and the lower interconnection portion 232. For example, support circuits forming a module control circuit for an array of storage transistors are formed in the circuit element portion 231 and the lower interconnect portion 232.

[0110] In tile 201, a three-dimensional NOR-type memory array 210 is formed in the memory array portion 233. An upper interconnect portion 234 is formed above the memory array portion 233. The insulating film 211 of the upper interconnect portion 234 is provided with interconnect portions 226 and vias 227 for forming further electrical connections. In some embodiments, conductive pads 228 for connecting to external circuit elements of the semiconductor memory device are provided on the upper interconnect portion 234. For example, a protective film 212 is formed on the upper interconnect portion 234, sealing the upper interconnect portion 234 and having openings that expose at least a portion of the conductive pads 228.

[0111] In the memory array portion 233, thin-film storage transistors are configured as a three-dimensional array of NOR-type memory strings within the memory array portion 202. The memory array portion 202 is located between the stair portion 203a and the stair portion 203b. The stair portion 203a and the stair portion 203b are formed on opposite sides of the tile 201. Connections to the common bit line and optionally a common source line of the NOR-type memory strings are provided in the stair portion 203a and the stair portion 203b via conductive vias. In some embodiments, the common source line is pre-charged and then maintained at a relatively constant voltage to function as a virtual voltage reference during programming, erasing, and reading operations, thereby eliminating the need for continuous electrical connections to support circuits during such operations. In Figure 9, the array portion 202, the stair portion 203a, and the stair portion 203b are not drawn to scale. For example, the array portion 202 may have a much larger area than either the stair portion 203a or the stair portion 203b.

[0112] In the memory array section 202, thin-film storage transistors are formed at the intersection of the common drain line and common source line (collectively indicated by reference numeral 204) and the local word line 205. A gate dielectric layer 206 is formed between the conductive local word line and the channel layer (not shown in Figure 9). The common drain line and common source line are arranged in multiple planes extending in the Y direction, and the local word line 205 is arranged in the Y direction as a columnar structure extending in the Z direction. As a result, the storage transistors are formed in a three-dimensional array on multiple planes in the Z direction, arranged in multiple rows in the X direction along each memory string in the Y direction. In Figure 9, the global word line conductor 208 provides an electrical connection between the lower circuit 222 of the memory array 210 and the local word line 205 associated with the three-dimensional memory stack.

[0113] In the embodiments described above, the support circuit was described as being formed on the underside of the memory array portion 233. Such configurations are illustrative and not intended to be limiting. For example, in other embodiments, both the memory array portion and the support circuit may be formed directly on the semiconductor substrate 200. In this case, for example, the support circuit may be located around the memory array portion. In other embodiments, the support circuit may be formed on a separate semiconductor substrate. In this case, for example, the semiconductor substrate on which the memory array portion is formed and the semiconductor substrate on which the support circuit is formed are joined to each other after the respective memory elements and circuit elements are formed.

[0114] Figure 9 shows one exemplary embodiment of a storage transistor tile, or physically isolated memory array. The depiction of tile 201 in Figure 9 is illustrative and not intended to limit. Figure 9 is provided to illustrate the incorporation of the memory structure of Figure 4B or Figure 4A for forming a tile that includes a module memory unit (memory array) and a module control circuit. This tile can then be used as a building block to form a memory device that includes multiple arrays of three-dimensional storage transistors, such as junctionless ferroelectric storage transistors, to provide a desired memory capacity at a high density level.

[0115] In embodiments of the present invention, tile 201 realizes a horizontal NOR (HNOR) memory architecture in which bit lines are stacked on multiple planes and word lines are formed as columnar structures. Bit lines are connected to bit line driver circuits (including bit line selection transistors) to select and drive memory pages of bit lines for memory operation. Word lines are connected to word line driver circuits (including word line selection transistors) to select one of the word lines in tile 201 for memory operation. With this configuration, in the support circuit formed on the underside of the memory array, the bit line driver circuits are located on the underside of the stepped portions 203a and 203b, and the word line driver circuits are located on the underside of the memory array portion 202. With this configuration, since bit line driver / selection transistors are generally smaller in size than word line driver / selection transistors, a compact (small) under-array circuit can be formed. In memory devices of thin-film storage transistors such as charge-trap storage transistors and ferroelectric storage transistors, word line driver / selection transistors are typically configured to have a larger on / off voltage difference than bit line driver / selection transistors. Therefore, word line driver circuits are typically much larger than bit line driver circuits.

[0116] The HNOR memory architecture of this disclosure allows for the formation of compact under-array circuits because bit-line drive / selection transistors require a smaller footprint and can be pulled and formed below the staircase portion, while larger word-line drive / selection transistors are located below the memory array portion where there is more space to accommodate the larger transistors. Thus, the tile 201 in this embodiment is scalable because the size of the tile 201 is not limited by the size of the staircase structure or the driver circuit. This is in contrast to conventional memory architectures (e.g., NAND flash memory) where word lines are stacked and bit lines are formed in columnar structures. In these conventional memory architectures, larger word-line drive / selection transistors must be placed below the staircase portion, so the size of the tile is determined by the size of the word-line drive / selection transistors, or the size of the memory tile is limited to a minimum size. Conventional memory architectures with stacked word lines cannot support memory devices with a large number of tiles because each tile needs to have a large tile size to accommodate the word-line drive / selection transistors that must be placed below the staircase portion. The HNOR-type memory architecture implemented in the memory device of the present invention enables the formation of a compact tile size, allowing the memory device to be configured to include a large number of tiles. A memory device with a large number of tiles enables concurrent memory operations and increases the memory bandwidth and memory availability of the memory device.

[0117] Figure 10 shows a two-dimensional array of tiles forming part of a memory device according to an embodiment of the present invention. Referring to Figure 10, in an embodiment of the present disclosure, the memory device 280 includes a two-dimensional array of tiles 201, each tile including a memory array 210 of a three-dimensional array of storage transistors and a module control circuit 250. The tile 201 can be configured as described above with reference to Figures 3, 4A, 4B, and 9. The memory array 210 of tile 201 is formed on a semiconductor substrate portion 240. An insulating layer 253 is provided between the semiconductor substrate portion 240 and the memory array 210 formed thereon. A module control circuit (CuA) 250 for implementing support circuits for operating the storage transistors in each tile is formed on the semiconductor substrate portion 240. Specifically, each tile 201 includes its own module control circuit (CuA) 250 formed beneath its respective memory array 210. In this specification, the semiconductor substrate portion 240 refers to the semiconductor substrate 241 and the interconnection structure 242 formed on the semiconductor substrate 241. Furthermore, in embodiments of the present invention, each module control circuit 250 has substantially the same planar dimensions (in the XY plane) as the memory array 210.

[0118] In the memory device 280, each tile is controlled by its own module control circuit 250, which performs memory operations on the storage transistors in the memory array. The memory device also includes additional peripheral control circuits in the areas between tiles or around the memory device. In some examples, the peripheral control circuits include input / output circuits for communicating with the memory controller, protection circuits (e.g., against electrostatic discharge), data path circuits, interface circuits, and other control logic circuits. The peripheral control circuits may further include analog circuits (e.g., regulators, voltage reference circuits, temperature sensors) and non-volatile memory (e.g., electronic fuse memory, one-time programmable memory) for storing trimming data. The circuits of the peripheral control circuits support the operation of each module control circuit 250, but do not directly control memory operations on the storage transistors, such as reading from or writing to the storage transistors.

[0119] With this configuration, the memory device 280 implementing the tile-based architecture of the present invention includes a large number of tiles, each tile being formed as a module memory unit by a physically isolated memory cell array, and each module memory unit is operated by a local module control circuit (CuA). In other words, the memory array includes a large number of tiles, and each tile operates independently of the others by a module control circuit formed on each tile. Each module memory unit is a physically isolated memory cell array, and each module memory unit includes its own three-dimensional array of memory cells and its own stepped structure for connecting the memory cells to the module control circuit. Each module memory unit is a memory array that can operate individually and independently, and multiple module memory units are multiple instances of the same module memory unit structure, and each individual module memory unit is physically isolated from other module memory units. Each module memory unit operates by its own local module control circuit and performs semi-autonomous memory operations (e.g., read operations, write operations).

[0120] In embodiments of the present invention, the memory device interacts with a memory controller, such as the memory controller described above with reference to Figures 1A, 1B, 2A, 2B, 7, and 8, to receive input commands having addresses for executing memory operations specified by commands in each memory tile specified by an address. In this specification, each tile having a module control circuit is described as operating semi-autonomously, in that the module control circuit operates independently to receive commands having addresses specifying its associated memory array and to execute memory operations specified by commands in its associated memory array. The module control circuit may receive regulated voltage levels or clock signals from peripheral control circuits, but does not receive control signals related to memory operations from peripheral control circuits. Rather, the module control circuit is itself a processing unit for its associated module memory unit and generates all control signals for controlling its associated module memory unit (or memory array) to execute memory operations.

[0121] A notable feature of the memory device of the present invention is that each tile is used as the unit of operation for memory access; that is, each tile operates on a unit of access for memory data, such as a page of memory data or a memory page. Therefore, each command from the memory controller is addressed to a single tile, and each tile operates on the command independently of commands addressed to other tiles, reading from or writing to a memory page of memory data. As described above, as used herein, a unit of access for memory data or a memory page refers to the number of data bits of memory data in each memory access request from the host device to the memory controller. In some examples, the unit of access is 512 bits of memory data. It is useful to note that this description will discuss only the memory data within the unit of access, understanding that each memory access may include additional data bits such as metadata bits, error flags, or other data bits used by the host but not strictly memory data.

[0122] When the memory device 280 is connected to and operated by the memory controller, it achieves memory access concurrency, where multiple memory operations are executed simultaneously on multiple tiles, each memory operation is executed independently of the others, and overlapping memory operations are executed on different memory tiles. The memory controller receives memory access requests from the host device and issues commands (with memory addresses) to the memory device in response to the received memory access requests. For example, the memory controller issues commands to each tile of the memory device every 4ns or 5ns. In embodiments of this disclosure, the memory controller implements a tile or bank contention avoidance scheme to avoid sending a new command to a tile that is processing an existing command. Tile contention avoidance is particularly beneficial when the memory device has asymmetric latencies, such as a write latency being much longer than the read latency. For example, if the write latency (e.g., 1 μs) is much longer than the read latency (e.g., 90 ns), the memory controller enables concurrency by executing a write operation on one tile and overlapping the read and write operations performed on other tiles. In this way, even with long write latency, read operations are not held up while waiting for the write operation to complete. An example of a tile or bank contention avoidance scheme is shown above with reference to Figure 8.

[0123] In this configuration, the memory device receives commands from the memory controller, each command is addressed to a specific tile, and no commands are issued to tiles currently executing another command. Therefore, the memory device receives commands to activate other tiles that are not currently executing commands. Furthermore, each command is issued for the entire unit of memory data access, and each tile operates independently of the others, performing memory operations on the entire unit of memory data access or memory page. In this way, the tiles within the memory device can be addressed individually and operate individually and simultaneously so that each tile operates on the entire memory page of the memory data for each memory access request. The memory device operated by the memory controller ensures high tile availability, thereby increasing memory bandwidth and reducing the tail latency of memory access requests. Importantly, by dividing the memory address space of the memory device into many tiles, the probability of memory access contention, where incoming memory accesses are addressed to the same tile, is significantly reduced, resulting in reduced tail latency of the memory device and improved service level quality. Specifically, the tail latency of the memory device of this disclosure is improved by having a large number of tiles available for host memory access, thereby avoiding situations where host memory access must be stopped in order to activate all or most of the memory banks.

[0124] In embodiments of the present invention, each tile of the memory device is operated by a local modular control circuit (CuA). Continuing with reference to Figure 10, each modular control circuit 250 is a complete control circuit replicated for each tile, such that the memory operations within each tile are self-contained. The modular control circuit 250 includes a sequencer that functions as an intelligent processing unit, executing commands received from the memory controller and addressed to each tile, and triggering memory operations in the associated tile in response to the received commands. Exemplary embodiments of the modular control circuit are described below with reference to Figures 11 and 12. The structures and configurations of the modular control circuits described herein are illustrative and not intended to be limiting. Other configurations and design schemes may be used in other embodiments.

[0125] Figure 11 is a block diagram showing a modular control circuit that can be incorporated into each tile of a memory device to provide intelligent, semi-autonomous memory operation control according to several embodiments of the present invention. In some examples, the modular control circuit 300 of Figure 11 can be used to realize the modular control circuit 250 of Figure 10, or the support circuit or CuA described in the embodiments above. Referring to Figure 11, the modular control circuit (CuA) 300 realizes the support circuit for a modular memory unit and is formed locally beneath each memory array. The modular control circuit 300 includes a circuit portion formed beneath the staircase portion of the tile and a circuit portion formed beneath the memory cell array portion of the tile. Generally, the modular control circuit 300 includes bit line (BL) and word line (WL) selection circuits for selecting memory pages of storage transistors from the memory array in response to a received address, and a bias control circuit that controls the voltage bias applied to the selected bit line and word line to perform memory operations triggered by a received command.

[0126] To facilitate the explanation of the present invention, the following exemplary memory device configuration is used. In some examples, each memory array within the memory device or within the memory channel of the memory device contains M word lines. In each memory operation, one of the M word lines is activated to select P memory pages. Each memory page contains Q data bits. Thus, each memory array contains P × Q bit lines formed on multiple planes of the memory array, and each bit line is associated with a NOR-type memory string containing M storage transistors. The word lines are activated to select P memory pages, and the Q bit lines are selected to select memory pages of the storage transistors. In this specification, the staircase portion of the tile is also referred to as the upper staircase portion and the lower staircase portion. The terms "upper" and "lower" are used to facilitate the reference to the figures and are not intended to indicate a particular orientation or arrangement of circuit elements.

[0127] In embodiments of the present invention, the module control circuit 300 includes a circuit portion 252 formed in the central part of the module control circuit. The circuit portion 252 includes a control circuit also referred to as a tile logic circuit. In some embodiments, the tile logic circuit 252 includes a sequencer or processor unit that executes a memory operation sequence in a memory array. Specifically, the sequencer receives input commands from a memory controller addressed to the associated tile, along with the associated memory address and write data (if applicable). The sequencer decodes each received command, such as by decoding the microcode within each command, and executes instructions according to the command to perform a memory operation in the memory array, each memory operation including an operation sequence or step that operates on the storage transistors of the memory array. For example, a command may be a read command for reading data from a specific memory page in the memory array. In another example, a command may be a write command with write data for storing data in a specific memory page in the memory array. In yet another example, a command may be a refresh command for refreshing the stored data on a specific page in the memory array. Specifically, the sequencer generates control signals for executing the operation sequence in the memory array and the timing of each memory operation. For example, the sequencer generates control signals that instruct timing sequences for executing various operation sequences, such as selecting word and bit lines, applying bias voltages, and sensing, programming, and erasing selected storage transistors. Importantly, the sequencers within each module control circuit operate independently of each other, without requiring control from circuit elements outside the module control circuit. In this way, the sequencers within the tile logic circuit 252 impart intelligence to the module control circuit, enabling semi-autonomous memory operations in the module control circuit 300.

[0128] In embodiments of the present invention, the module control circuit 300 includes circuit portions 254A and 254B that implement row circuits for selecting and activating word lines in a memory array. In this embodiment, the row circuit is divided into two circuit portions 254A and 254B formed adjacent to a tile logic circuit portion 252 in the central part of the module control circuit. In other embodiments, the row circuit may be formed in a single circuit portion 254 and provided on one side of the tile logic circuit portion 252. The row circuit includes a row decoder circuit 255, a row bias control circuit 256, and a word line selection circuit 257, also referred to as a word line (WL) driver circuit. In this embodiment, circuit portions 254A and 254B can be configured to control half of the word lines in the memory array, respectively. For example, circuit portion 254A can be configured to control the upper half of the word lines in the memory array, and circuit portion 254B can be configured to control the lower half of the word lines in the memory array.

[0129] The row decoder circuit 255 is configured to decode the memory address associated with the command received by the tile logic circuit 252 and determine the word line to be activated for memory operation. The row bias control circuit 256 generates and controls word line voltage values ​​to bias the selected word line as a function of the memory operation to be performed. The row bias control circuit 256 also generates and controls word line voltage values ​​for unselected word lines to minimize disturbance of unselected memory cells, for example. In one example, a first voltage value for read operations and a second voltage value different from the first voltage value for write operations are applied to the selected word line. In another example, a forbidden voltage value is applied to the unselected word line to minimize disturbance of data stored in unselected memory cells. Finally, the word line driver circuit 257 includes word line drive / selection transistors connected to the M word lines in the memory array. In response to the decoded address from the row decoder 255 that specifies the word line for selection, the word line driver circuit 257 selects the specified word line and applies an appropriate bias voltage value to the selected word line that relates to the memory operation to be performed. The word line driver circuit 257 also applies a prohibition voltage to the other M-1 unselected word lines. The row circuits (circuit sections 254A, 254B) operate in this manner to select and drive one word line from the M word lines for the memory operation.

[0130] The module control circuit 300 includes circuit sections 258A and 258B that implement column circuits for selecting and activating bit lines in the memory array. In this embodiment, the column circuit is divided into two circuit sections 258A and 258B formed adjacent to row circuit sections 254A and 254B. In other embodiments, the column circuit may be formed within a single circuit section 258 and provided on one side of the tile logic circuit section 252. The column circuit includes a column decoder circuit and a column bias control circuit. In this embodiment, circuit sections 258A and 258B can be configured to control half of the bit lines in the memory array, respectively. For example, circuit section 258A can be configured to control the upper half of the bit lines in the memory array, and circuit section 258B can be configured to control the lower half of the bit lines in the memory array.

[0131] The column decoder circuit within column circuit 258A or 258B is configured to decode the memory address associated with the command received by the tile logic circuit 252 to determine the memory page of the bit line to be activated for memory operation. The column bias control circuit within column circuit 258A or 258B generates and controls the bit line voltage values ​​to drive the selected bit line as a function of the memory operation being performed. The column bias control circuit also generates and controls the bit line voltage values ​​of unselected bit lines to minimize disturbance to unselected memory cells. In one example, the selected bit line is subjected to a third voltage value for read operations and a fourth different voltage value distinct from the third voltage value for write operations. In another example, the unselected bit line is subjected to a forbidden voltage value to minimize disturbance to data stored in unselected memory cells.

[0132] The module control circuit 300 includes circuit sections 260A and 260B that implement the sense circuit and the latch circuit. In this embodiment, the sense circuit and the latch circuit are divided into two circuit sections 260A and 260B, which are formed adjacent to the column circuit sections 258A and 258B, respectively. The arrangement and division of the sense circuit and the latch circuit depend on the configuration of the staircase structure of the tiles that provide the bit lines of the NOR type memory strings of the memory array for connection to the module control circuit. If the staircase structure includes two sections formed at both ends of the tile, arranging the corresponding sense circuit and the latch circuit near their respective bit line staircase sections is beneficial for better sensing and driving performance.

[0133] In circuit sections 260A and 260B, the sense amplifier circuit includes Q sense amplifiers corresponding to the number of data bits in the memory page. The Q sense amplifiers are connected to Q selected bit lines. Therefore, each memory operation is performed on the memory page of data bits, and selection of sense amplifiers is unnecessary. By providing the same number of sense amplifiers as the number of data bits in the memory page within the module control circuit 300, the size of the module control circuit can be kept compact, and the module control circuit can be formed below each memory array. In this embodiment, Q selected bit lines are provided through the upper and lower stair sections. Therefore, half of the sense amplifiers are provided in circuit section 260A and connected to Q / 2 selected bit lines in the upper stair section, and the remaining half of the sense amplifiers are provided in circuit section 260B and connected to Q / 2 selected bit lines in the lower stair section.

[0134] The data latch circuit may include two or more data latches or registers for storing output read data or input write data. The sense amplifier control circuit directs the operation of the sense amplifier and data latches, sensing read data from selected bit lines or providing write data to selected bit lines. In some examples, the sense amplifier, data latches, and bias control circuit can be configured as described above with reference to Figure 6.

[0135] In embodiments of the present invention, the module control circuit 300 includes circuit sections 262A and 262B that implement a bit line (BL) driver circuit for selecting and driving bit lines (e.g., Q bit lines) of selected memory pages in the memory array. The bit line driver circuit includes a pair of bit line selection transistors that select and drive the selected bit lines. In this embodiment, the bit line selection circuit is divided into two circuit sections 262A and 262B formed at both ends of the module control circuit. The two circuit sections of the bit line selection circuit are also formed beneath the respective stair sections at both ends of the tile.

[0136] More specifically, the bit line selection circuit includes a first set of bit line selection transistors formed below the upper staircase portion and a second set of bit line selection transistors formed below the lower staircase portion. As described above, in this embodiment, P × Q bit lines are provided through the upper and lower staircase portions. That is, half of the bit lines of the memory array are connected to a staircase structure formed at the first end (e.g., the upper end) of the tile and connected to bit line selection transistors formed below the staircase structure. The remaining half of the bit lines of the memory array are connected to a staircase structure formed at the second end (e.g., the lower end) opposite the first end of the tile and connected to bit line selection transistors formed below the staircase structure. With this configuration, the first set of bit line selection transistors (circuit portion 262A) is formed below the upper staircase portion to connect to (P × Q) / 2 bit lines and to select and drive Q / 2 bit lines for memory operation. The second set of bit line selection transistors (circuit section 262B) are connected to (P × Q) / 2 bit lines and are formed below the lower step section to select and drive Q / 2 bit lines for memory operation. Thus, the bit line selection circuit selects Q bit lines from P × Q bit lines in the memory array to perform memory operation.

[0137] In this configuration, the first and second sets of bit line selection transistors are connected to the bit lines of the NOR-type memory string in the upper and lower staircase sections to select bit lines and apply the appropriate voltage levels to the selected bit lines for read and write operations. Specifically, the bit line selection transistors select Q memory pages of bit lines from all P × Q bit lines in response to a column decoder that decodes the memory address associated with a command received by the tile logic circuit 252. The bit line selection transistors apply the bias voltage generated by the column bias control circuit to the selected bit lines via the sense amplifier circuit and perform the specified memory operation. Unselected bit lines remain electrically floating or are not actively biased to a specific voltage potential.

[0138] During operation, in the module control circuit 300, the tile logic circuit 252 receives input commands and memory addresses. The row decoder 255 decodes the memory address and determines the word line to be selected. The row bias control circuit 256 generates bias voltage levels for the selected and unselected word lines. The word line driver circuit 257 selects one specified word line from M word lines for memory operation. Meanwhile, the column decoder (circuit sections 258A, 258B) decodes the memory address and determines the memory page to be selected. The column bias control circuit generates bias voltage levels for the selected bit lines. The bit line driver circuits (circuit sections 262A, 262B) select Q bit lines of the selected memory page, which are connected to the sense amplifier. The sequencer within the tile logic circuit 252 controls the sequence and timing of the various steps for executing the memory operation. For example, in a read operation, the sense amplifier first precharges the selected bit line and then senses the current or voltage value on the selected bit line as a result of the storage transistor in the selected memory page being activated by the selected word line. The sensed data value of the Q data bit is stored in a data latch (circuit sections 260A and 260B) so that it can be read by the memory controller on the memory device's I / O bus. In a write operation, the sense amplifier precharges the selected bit line and applies a bit line bias voltage to the selected bit line according to the write data value (stored in the data latch), and the selected bit line is stored in the storage transistor in the selected memory page which is activated by the selected word line. In some embodiments, the unselected bit line is biased to a forbidden voltage value by virtual capacitive coupling with the unselected word line. The sequencer performs the read and write operations, each operation involving various stages with different bias voltage values ​​and timings. The sequencer manages the sequence of stages in each memory operation and the timing of each other stage.

[0139] In this embodiment, the module control circuit 300 is configured with a tile logic circuit 252 in the center, and a decoder circuit, bias control circuit, selection circuit, sense circuit, and latch circuit on either side of it. In this configuration, control signals from the tile logic circuit 252 to other circuits can be routed across the tile area by using conductive interconnects and vias in the interconnection section 232 (Figure 9).

[0140] The configuration of the module control circuit 300 in Figure 11 is illustrative and not intended to limit. The circuits within the module control circuit 300 may be arranged in other configurations depending on other design requirements such as the size of the transistors or circuit elements and the need for signal routing. Figure 12 is a block diagram showing a module control circuit that can be incorporated into each tile of a memory device according to another embodiment of the present invention. Referring to Figure 12, the module control circuit 350 includes the same circuit elements as the module control circuit 300 in Figure 11, and the same elements are denoted by the same reference numerals for simplicity of explanation. The module control circuit 350 consists of a tile logic circuit 252 located on the tile area side. The row circuit, including a row decoder 255, a row bias control circuit 256, and a word line driver circuit 257, is located in the central part adjacent to the tile logic circuit 252. The column decoders and bias control circuits 258A and 258B are similarly located on either side of the row circuit, adjacent to the tile logic circuit 252. In some examples, the circuit layout of the modular control circuit 350 accommodates sense amplifiers or column decoder circuits that occupy a larger area, allowing for more efficient use of the tile area by placing the tile logic circuits on the sides. In the configuration of the modular control circuit 350, the routing of control signals from the tile logic circuits 252 to other circuit elements can include routing in two different directions.

[0141] In the module control circuit 300 of Figure 11, control signals from the tile logic circuit 252 to other circuits can be routed in only one direction on the tile area, for example, from top to bottom or vice versa, as indicated by the arrows in Figure 11. In this case, command signals and address signals can be routed to the module control circuit 350 of each tile using the inter-tile routing area in the memory device or using several areas on the tile. In the module control circuit 350 of Figure 12, control signals from the tile logic circuit 252 to other circuits can be routed both horizontally and vertically, as indicated by the arrows in Figure 12. In this case, command signals and address signals to the module control circuit 350 of each tile are generally routed using the inter-tile routing area in the memory device.

[0142] Figure 13 is a block diagram showing the bit line selection and sense amplifier configuration in a module control circuit according to an embodiment of the present invention. The circuit elements in the block diagram of Figure 13 are illustrative of the circuit elements in the module control circuit of Figure 11 or Figure 12. Furthermore, for the sake of clarity, it is assumed that the memory array has 16,384 bit lines, each word line selects one memory page from 32 memory pages, and the size of the memory page is 512 bits. Additional data bits for metadata or error correction or health indication may be provided but are not included in this figure for simplicity. Referring to Figure 13, the 16k bit lines of the memory array are divided into two parts and connected to the module control unit via two staircase structures. In this embodiment, the upper staircase section is connected to 8,192 bit lines, and the lower staircase section is connected to another 8,192 bit lines. In each staircase section, the bit lines are connected to their respective bit line driver circuits, each circuit selects half of the memory pages, i.e., 256 bit lines. For example, in the upper staircase section, the bit line driver circuit includes 256 selector circuits, each of which selects one bit line out of 32. Similarly, in the lower staircase section, the bit line driver circuit includes 256 selector circuits, each of which selects one bit line out of 32. The selector circuits receive a page address and determine which bit line to select. The outputs of the 256 x 2 selector circuits corresponding to the 256 x 2 selected bit lines are connected to their respective sense amplifier circuits. The upper section has a set of 256 sense amplifiers, and the lower section also has a set of 256 sense amplifiers. Next, the 256 x 2 sense amplifiers are connected to their respective data latches. For example, one pair of data latches 261A is connected to sense amplifier 260A, and one pair of data latches 261B is connected to sense amplifier 260B.

[0143] Figure 13 shows the data flow for a read operation. Detected data from 256 × 2 sense amplifiers is stored in data latches 261A and 261B for output to the memory controller. Thus, each set of data latches provides 256 bits or 32 bytes of output data. The memory controller receives and combines data from the two sets of data latches 261A and 261B to obtain a memory page of 512 bits or 64 bytes of memory data. The configuration in Figure 13 also applies to a write operation, in which case 512 bits of write data are received by the module control circuit and stored in the two sets of data latches 261A and 261B. The bit line driver circuit selects the 512-bit line of the memory page to be written, and the sense amplifiers provide the write data on the selected bit line.

[0144] In this configuration, the module control circuit includes a number of sense amplifiers equal to the number of data bits in the memory page for sensing or driving the bit lines. No selection signals are used to select the sense amplifiers. Rather, the selection of the bit lines is used only to connect the memory page size of the bit lines to the sense amplifiers. This configuration allows for the formation of a compact module control circuit, simplifying circuit design and control, and enabling high-bandwidth operation.

[0145] In the embodiments described above, the memory device includes an array of tiles, each tile providing a unit of access to memory data, such as a memory page of memory data (e.g., 512 bits). Note that the above description concerns memory operations in which each memory access from the host responds to a host request based on the unit of access to memory data. In actual implementation, each tile may perform additional auxiliary memory operations that are not part of the host memory request, such as refreshing or wear leveling. In some cases, each memory operation performed on a target memory page within a tile may include additional auxiliary memory operations on other related memory pages within the same tile. A module control circuit (CuA) works with the memory controller to control the auxiliary memory operations.

[0146] In embodiments of this disclosure, a write operation is performed in conjunction with a partial refresh operation, so that each time a memory page is written, another memory page associated with the same word line is selected and simultaneously refreshed. As described above, the destination memory address activates the selected word line and activates P memory pages. While one of the P memory pages is selected for the write operation, the partial refresh operation selects another memory page belonging to the activated word line for refresh. The partial refresh operation can be advantageously applied to reduce disturbances experienced by unselected storage transistors associated with the activated word line. The partial refresh operation is disclosed in U.S. Patent Application No. 17 / 525, 712, titled “Methods For Reducing Disturb Errors By Refreshing Data Alongside Programming Or Erase Operations,” filed November 12, 2021 (Patent Document 4) (the entire disclosure of Patent Document 4 is incorporated herein by reference). When a partial refresh operation is performed, each write operation within a tile is performed on the specified memory page and the memory page being refreshed; that is, each write operation is performed on two memory pages. However, the unit of memory access remains a single memory page, with input write data being written to only one memory page, while the other memory page is simply refreshed. This description of memory operations performed within a tile based on the unit of memory data access does not preclude additional auxiliary memory operations performed on other memory pages within the same tile.

[0147] Furthermore, in the embodiments described above, the tile-based support circuit or module control circuit (CuA) for each tile was described as being formed in or on the semiconductor substrate on which the storage transistor array is formed. In another embodiment, the module control circuit (CuA) may be formed on a different semiconductor substrate than the one on which the storage transistors are formed. In such a configuration, the memory array of storage transistors is formed on a first semiconductor die, and the module control circuit for each array of storage transistors is formed on a second semiconductor die. The memory device is formed by electrically and mechanically connecting the first semiconductor die to the second semiconductor die, and each memory array and associated module control circuit forms a tile within the memory device, and the memory device includes an array of tiles formed by the junction of the first semiconductor die and the second semiconductor die. Tiles, including module control circuits and associated memory arrays, can be individually addressed by an external memory controller.

[0148] For example, tile 201 in Figure 9 may be formed by two semiconductor dies, with the memory array portion 210 formed on a first semiconductor die and the module control circuit formed on a second semiconductor die. The second semiconductor die may be bonded to the first semiconductor die via an interconnect structure formed on the underside (or bottom) or topside of the memory array portion 210. For example, the interconnect structure may be a hybrid bond. Forming the memory array portion and the module control circuit on separate semiconductor dies has the beneficial effect of allowing the manufacturing process to be optimized separately for the memory circuit and the control circuit.

[0149] In some embodiments, the circuitry of each module control circuit may be divided into a portion of the control circuit formed below or above the memory array of storage transistors in a first semiconductor die, and the remaining control circuit formed in a second semiconductor die. For example, the bit line selector / driver circuit for each tile may be formed in or above the semiconductor substrate of the first semiconductor die below each memory array. Alternatively, in another example, the bit line selector / driver circuit for each tile may be formed as a vertical thin-film transistor above each memory array (on the opposite side of the semiconductor substrate). In this embodiment, the first semiconductor die only needs to provide a global bit line connection to the second semiconductor die. Such configurations allow the memory device of the present invention to be configured in various ways to provide an array of storage transistor tiles having module control circuits. The memory device may be formed on a monolithic semiconductor die, or it may be formed in a multi-die configuration to allow optimization of the manufacturing process between the memory circuitry and the support circuitry. Whether formed monolithically or in a multi-die configuration, the memory tiles, including the module control circuits and associated memory arrays, can be individually addressed by an external memory controller.

[0150] In this detailed description, process steps described in one embodiment may be used in another embodiment even if they are not explicitly described in another embodiment. Where this specification refers to a method including two or more defined steps, the defined steps may be performed in any order or simultaneously, unless the context indicates or specific instructions are otherwise provided herein. Furthermore, unless the context indicates or specific instructions are otherwise provided, the method may also include one or more other steps performed before any defined step, between two defined steps, or after all defined steps.

[0151] In this detailed description, various embodiments or examples of the present invention can be carried out in various forms, such as processes, apparatus, systems, and compositions of materials. A detailed description of one or more embodiments of the present invention is provided above, along with accompanying drawings illustrating the principles of the present invention. Although the present invention has been described in relation to such embodiments, the present invention is not limited to any embodiment. Various modifications and variations are possible within the scope of the present invention. The scope of the present invention is limited only by the appended claims, and the present invention encompasses various alternative forms, modifications, and equivalents. In order to provide a complete understanding of the present invention, numerous specific details are described herein. These details are provided for illustrative purposes only, and the present invention can be carried out in accordance with the claims without some or all of these specific details. For clarity, technical matters known in the art relating to the present invention are not described in detail so as not to unnecessarily obscure the present invention. The present invention is defined by the appended claims.

Claims

1. It is a memory module, A plurality of semiconductor memory dies, each semiconductor memory die comprising a plurality of tiles of memory circuitry, each tile comprising a memory array which is an array of physically isolated storage transistors, each tile being electrically connected to a corresponding module control circuit and operated by the module control circuit, each memory array being a three-dimensional array of storage transistors, and the plurality of semiconductor memory dies comprising a first number of semiconductor memory dies providing a specified memory capacity of the memory module and at least one spare semiconductor memory die providing redundant memory capacity, each tile being individually addressed by the module control circuit associated with each tile, and performing memory operations on the storage transistors in the memory array in response to a memory access command specified for the tile, and two or more randomly addressed tiles being configured to perform overlapping memory operations simultaneously, A memory controller die including a memory control circuit that accesses and operates the plurality of semiconductor memory dies in order to perform memory operations, wherein the plurality of semiconductor memory dies are connected to the memory controller die via a first set of interconnection structures, The memory controller die is a memory module that receives input requests for memory operations from a host processor, which are addressed in a first memory address space that spans a first number of semiconductor memory dies and excludes the memory space of at least one spare semiconductor memory die.

2. A memory module according to claim 1, A memory module in which the memory controller die is configured to initiate replacing the memory array in the first number of semiconductor memory dies with a redundant memory array in the at least one spare semiconductor memory die in response to the detection of a predetermined state in the memory array.

3. A memory module according to claim 2, The memory controller die is a memory module that performs memory operations on the memory array in a second memory address space spanning both the first number of semiconductor memory dies and the at least one spare semiconductor memory die.

4. A memory module according to claim 1, The first number of semiconductor memory dies includes K semiconductor memory dies, and together with the spare semiconductor memory dies, forms a group of K+1 semiconductor memory dies. The first number of semiconductor memory dies define the first memory address space, A memory module in which the group of K+1 semiconductor memory dies defines a second memory address space.

5. A memory module according to claim 4, The memory controller die further includes an address translation circuit configured to process input requests received by the memory module, Each of the aforementioned input requests includes a logical memory address directed to the first memory address space, The address translation circuit of the memory controller die translates the logical memory address into a physical memory address that identifies the corresponding storage transistor in the K+1 semiconductor memory die, and is a memory module.

6. A memory module according to claim 5, The address translation circuit is a memory module that translates a first logical memory address directed to the first memory address space to a physical memory address in the second memory address space.

7. A memory module according to claim 1, A memory module in which the plurality of semiconductor memory dies are stacked on top of each other and connected to each other via a second set of interconnection structures.

8. A memory module according to claim 7, The first set of interconnection structures includes one of a silicon through-via (TSV), a hybrid bond, a copper stud, and an interposer. The second set of interconnection structures is a memory module, including through-silicon vias (TSVs).

9. A memory module according to claim 4, The memory controller die is a memory module that communicates with the host processor via the first memory address space and manages memory operations via the second memory address space.

10. A memory module according to claim 1, The first set of interconnection structures includes an interposer, A memory module in which the plurality of semiconductor memory dies are arranged side by side on the interposer together with the memory controller die.

11. A memory module according to claim 1, The plurality of semiconductor memory dies are formed by stacking them on top of each other, The stacked semiconductor memory dies are formed by stacking them on the memory controller die. The first set of interconnection structures is a memory module that electrically connects the stacked plurality of semiconductor memory dies to the memory controller die.

12. A memory module according to claim 1, Each of the memory arrays includes a three-dimensional array of storage transistors, The three-dimensional array of the NOR-type memory strings is arranged in parallel in a first direction and stacked in multiple layers in a second direction. Each of the aforementioned NOR-type memory strings includes a plurality of storage transistors that share a common source line and a common drain line. Each layer of the aforementioned NOR-type memory string extends along a third direction, forming a memory module.

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