Array antenna device

Abstract

Provided is an array antenna device that can be used in a 300 GHz band. An array antenna device 100 comprises: a first layer 10 in which a plurality of antenna elements 11 are arranged in a grid shape; and a second layer 20 stacked on the first layer 10. The second layer 20 includes: a plurality of mixers 21 that are arranged in a plurality of grid regions 30 overlapping the plurality of antenna elements 11 in plan view, that each include an LO signal terminal 23, an IF signal terminal 24, and an RF signal terminal 22, with the RF signal terminals 22 electrically connected to the plurality of antenna elements 11; a plurality of LO signal lines 25 which are provided to respective columns of the plurality of mixers 21 and to each of which the LO signal terminals of mixers 21 of the same column are commonly connected; and a plurality of IF signal lines 27 that are provided to respective rows of the plurality of mixers 21 and to each of which the IF signal terminals of mixers 21 of the same row are commonly connected.

Description

Array Antenna Device

[0001] The present invention relates to a wireless device equipped with an array antenna, and more particularly to an array antenna device suitable for a transceiver using the 300 GHz band.

[0002] Figure 12 is a graph showing the relationship between frequency band and S / N ratio for each received power of radio waves. The horizontal axis of the graph is frequency band, and the vertical axis is S / N ratio. The graph plots the relationship between frequency band and S / N ratio when the received power Pr is 0.1 μW (equivalent to -40 dBm), 1 μW (equivalent to -30 dBm), and 10 μW (equivalent to -20 dBm). As can be seen from this graph, the S / N ratio decreases as the frequency band increases, regardless of the magnitude of Pr.

[0003] The graph shows the results of modulation schemes QPSK (Quadrature Phase Shift Keying), 16QAM (16 Quadrature Amplitude Modulation), and 64QAM (64 Quadrature Amplitude Modulation) with a BER (Bit Error Rate) of less than 10 －３ An auxiliary line is drawn to indicate the S / N ratio required to achieve this. According to this, if the frequency band is 25 GHz, communication is possible using any of the modulation methods QPSK, 16QAM, and 64QAM with a Pr of 0.1 μW or more, but if the frequency band is 50 GHz, a Pr of 0.1 μW will make the S / N ratio too small, making QPSK communication difficult. Furthermore, to perform stable QPSK communication at an even higher frequency band of around 100 GHz, a receiving power of 1 μW or more is required.

[0004] The sixth-generation mobile communication system (6G) aims to achieve data rates of 100 Gb / s or more using the 300 GHz band, which is even higher than the fifth-generation mobile communication system (5G). Therefore, in next-generation mobile communication systems where frequencies and data rates are becoming increasingly higher, it is necessary to increase the transmitter output power to maintain high reception power. Previous approaches to increasing the output power of transceivers using the 300 GHz band have included using lenses or horns to increase antenna gain, or using a rat-race power combiner to combine multiple RF signals to increase the output power of a single transceiver (see, for example, Patent Document 1).

[0005] International Publication No. 2020 / 110814

[0006] When evaluating the received power from the perspective of EIPR (equivalent isotropically radiated power), the received power is Pr = EIRP · Ar / 4πd, where d is the distance from the transmitter to the receiver and Ar is the antenna area of ​​the receiver. ２ That is, the magnitude of the received power is determined by the antenna area Ar of the receiver regardless of the frequency band, and the larger the antenna area, the larger the antenna gain and the greater the received power.

[0007] An effective way to increase antenna gain is to use an array antenna with multiple antenna elements. Furthermore, using a phased array antenna enables the use of beamforming technology, which adjusts the signal phase of each antenna element to transmit radio waves in a specific direction or receive radio waves from a specific direction, as well as beam sweep, which allows the beam direction to be freely changed. This allows for a wider beam control angle than using lenses or horns, and also makes beamforming easier.

[0008] In an array antenna, antenna elements are arranged at a pitch of half the wavelength of the radio wave. In the 300 GHz band, antenna elements must be arranged at a pitch of approximately 500 μm. Therefore, if an array antenna in which antenna elements are arranged in a two-dimensional grid pattern is to be adopted in a transceiver using the 300 GHz band, the transceiver circuitry must be packed into an area of ​​approximately 500 μm square. Although transistor size can be reduced through miniaturization of semiconductor processes, passive elements such as inductance elements and capacitance elements are difficult to miniaturize, making it difficult to pack a circuit such as that disclosed in Patent Document 1 into such a narrow area. Thus, it is difficult to adopt an array antenna in a transceiver using the 300 GHz band due to the constraints on circuit layout area.

[0009] In view of the above problems, an object of the present invention is to provide an array antenna device that can be used in the 300 GHz band.

[0010] An array antenna device according to one aspect of the present invention comprises a first layer on which a plurality of antenna elements are arranged in a grid pattern, and a second layer stacked on the first layer, wherein the second layer is arranged in a plurality of grid areas that overlap the plurality of antenna elements in a planar view, and is characterized by having a plurality of mixers each having an LO signal terminal, an IF signal terminal, and an RF signal terminal, the RF signal terminals being electrically connected to the plurality of antenna elements, a plurality of LO signal lines provided for each column of the plurality of mixers, and to which the LO signal terminals of the mixers in the same column are commonly connected, and a plurality of IF signal lines provided for each row of the plurality of mixers, and to which the IF signal terminals of the mixers in the same row are commonly connected.

[0011] According to the present invention, an array antenna can transmit and receive radio waves in the 300 GHz band, which makes it possible to easily increase antenna gain in the 300 GHz band.

[0012] FIG. 1 is a schematic planar configuration diagram of an array antenna device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of a mixer-first configuration transmitter according to an example. FIG. 3 is a schematic planar configuration diagram of an array antenna device according to a second embodiment of the present invention. FIG. 4 is a circuit diagram of a mixer-first configuration receiver according to an example. FIG. 5 is a schematic planar configuration diagram of an array antenna device according to a third embodiment of the present invention. FIG. 6 is a schematic planar configuration diagram of an array antenna device according to a fifth embodiment of the present invention. FIG. 7 is a schematic planar configuration diagram of an array antenna device according to a sixth embodiment of the present invention. FIG. 8 is a schematic planar configuration diagram of an array antenna device according to a seventh embodiment of the present invention. FIG. 9 is a schematic planar configuration diagram of an example of a semiconductor substrate for a transmitter that supports a scalable configuration. FIG. 10 is a graph showing the relationship between frequency band and S / N ratio for each received power of radio waves.

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed description of well-known matters or redundant description of substantially identical configurations may be omitted. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art. Note that the inventors provide the accompanying drawings and the following description to enable those skilled in the art to fully understand the present invention, and are not intended to limit the subject matter described in the claims. Furthermore, the dimensions of each component depicted in the drawings, the detailed shapes of the details, and the like may differ from the actual ones.

[0014] (First embodiment) Fig. 1 is a schematic plan view of an array antenna device according to a first embodiment of the present invention. The array antenna device 100 according to this embodiment is a 300 GHz band silicon CMOS transmitter formed by stacking a printed circuit board 10 and a semiconductor substrate 20. Note that, for convenience, Fig. 1 shows the plan views of the printed circuit board 10 and the semiconductor substrate 20 side by side, but in reality, these are stacked by flip-chip bonding.

[0015] Antenna elements 11, such as rectangular microstrip patch antennas, are arranged in a 4x4 grid on the printed circuit board 10. Considering that the desired RF frequency of the array antenna device 100 is 252 to 296 GHz (wavelength of approximately 1000 to 1200 μm), for example, the sum of the lengths of the two sides of the antenna elements 11 is 300 to 350 μm, which is one-quarter wavelength of the RF signal with some margin, and the arrangement pitch of the antenna elements 11 in the row and column directions (corresponding to the horizontal and vertical directions in FIG. 1 ) is 600 to 700 μm, which is one-half wavelength of the RF signal with some margin.

[0016] A transmitting circuit 201 is mounted on the semiconductor substrate 20. The transmitting circuit 201 is a collection of individual transmitters that transmit RF signals (radio frequency signals) from the individual antenna elements 11. The individual transmitters are mixarst-configured transmitters in which a mixer that generates an RF signal by upconverting an IF signal (intermediate frequency signal) with an LO signal (local oscillation frequency signal) is arranged in the final stage. This type of mixarst configuration is adopted in 300 GHz band silicon CMOS transmitters in which a power amplifier cannot be arranged in the final stage.

[0017] 2 is a circuit diagram of an example of a mixer-type transmitter, which includes a mixer 21, an LO signal generator 31, and an IF signal amplifier 41. An RF signal terminal 22 of the mixer 21 is connected to the antenna element 11, an LO signal terminal 23 is connected to the LO signal generator 31, and an IF signal terminal 24 is connected to the IF signal amplifier 41.

[0018] More specifically, the LO signal generator 31 includes a balun 32, a preamplifier 33, and a 9-multiplier 34. The balun 32 converts an unbalanced LO source signal supplied from an oscillator (not shown) into a balanced signal. For example, the frequency of the LO source signal is 25 GHz. The preamplifier 33 amplifies the balanced signal output from the balun 32. The 9-multiplier 34 multiplies the frequency of the preamplifier output signal by 9 to output a 225 GHz LO signal. The output signal of the 9-multiplier 34 is input to the mixer 21 via the LO signal terminal 23 of the mixer 21. The IF signal amplifier 41 is composed of multiple amplifiers connected together and amplifies a balanced IF signal of approximately 50 GHz input from an external source. The output signal of the IF signal amplifier 41 is input to the mixer 21 via the IF signal terminal 24 of the mixer 21. A 275 GHz RF signal is generated at the RF signal terminal 22 of the mixer 21.

[0019] It is also possible to set the frequency of the LO original signal to 75 GHz and replace the nine-multiplier 34 with a tripler that triples the frequency of the input signal.

[0020] Returning to FIG. 1 , the mixers 21 of the individual transmitters described above are arranged in a grid pattern in 4×4 grid regions 30 on the semiconductor substrate 20. Each mixer 21 is composed of one or more transistors and one or more passive elements. The length of one side of each grid region 30 is 600 to 700 μm, the same as the arrangement pitch of the antenna elements 11, and one antenna element 11 can fit in one grid region 30 in a planar view. In other words, if the printed circuit board 10 is the upper layer and the semiconductor substrate 20 is the lower layer, each mixer 21 is arranged directly below each antenna element 11 in a planar view. The RF signal terminal 22 of each mixer 21 on the semiconductor substrate 20 is electrically connected to the corresponding antenna element 11 on the printed circuit board 10 via bumps (not shown).

[0021] An LO signal line 25 is wired for each column of mixers 21 arranged in a grid pattern. In this embodiment, there are four LO signal lines 25 in total. These LO signal lines 25 are arranged at equal intervals, that is, at the same pitch as the arrangement pitch of the antenna elements 11, along the arrangement of the columns of mixers 21. To each LO signal line 25, the LO signal terminals 23 of the four mixers 21 in the same column are commonly connected.

[0022] An LO phase shifter 26 is connected to the end of each LO signal line 25. Furthermore, the above-mentioned LO signal generator 31 is connected to each LO phase shifter 26. Each LO phase shifter 26 receives an LO signal from the LO signal generator 31, adjusts its phase, and supplies the phase-adjusted LO signal to each LO signal line 25. The amount of phase adjustment by each LO phase shifter 26 is controlled by a controller 29. In this way, LO signals of the same phase are input to the mixers 21 in the same column, and the phase of the LO signal can be adjusted for each column of mixers 21 independently of the mixers 21 in other columns. This allows beam sweeping in the row direction of the array of antenna elements 11 by adjusting the phase of the LO signal of each LO signal line 25.

[0023] An IF signal line 27 is wired for each row of mixers 21 arranged in a grid pattern. In this embodiment, there are a total of four IF signal lines 27. These IF signal lines 27 are arranged at equal intervals, i.e., at the same pitch as the arrangement pitch of the antenna elements 11, along the row arrangement of the mixers 21, across multiple grid regions 30. To each IF signal line 27, the IF signal terminals 24 of the four mixers 21 in the same row are commonly connected.

[0024] An IF phase shifter 28 is connected to the end of each IF signal line 27. Furthermore, the above-mentioned IF signal amplifier 41 is connected to each IF phase shifter 28. Each IF phase shifter 28 receives the IF signal amplified by the IF signal amplifier 41, adjusts its phase, and supplies the phase-adjusted IF signal to each IF signal line 27. The amount of phase adjustment by each IF phase shifter 28 is controlled by a controller 29. In this way, IF signals of the same phase are input to the mixers 21 in the same row, and the phase of the IF signal can be adjusted for each row of mixers 21 independently of the mixers 21 in other rows. This allows beam sweeping in the column direction of the array of antenna elements 11 by adjusting the phase of the IF signal of each IF signal line 27.

[0025] As described above, each grid area 30 is a narrow area with a side length of 600 to 700 μm, making it impossible to place many circuit elements. Therefore, circuits of a certain size, such as the LO phase shifter 26, the LO signal generator 31, the IF phase shifter 28, the IF signal amplifier 41, and the controller 29, are all placed outside the grid area 30. For example, as shown in FIG. 1 , the LO phase shifter 26 connected to the end of the LO signal line 25 extending in the column direction of the grid area 30 and the LO signal generator 31 connected thereto may be placed in an empty area in the column direction of the grid area 30, the IF phase shifter 28 connected to the end of the IF signal line 27 extending in the row direction of the grid area 30 and the IF signal amplifier 41 connected thereto may be placed in an empty area in the row direction of the grid area 30, and the controller 29 may be placed in the remaining empty area.

[0026] As described above, this embodiment employs an array antenna in a 300 GHz silicon CMOS transmitter to increase transmission power. Furthermore, the phases of the LO signal and IF signal can be adjusted to sweep the transmission RF signal in two dimensions, vertically and horizontally. Furthermore, by arranging the mixer 21, LO phase shifter 26, LO signal generator 31, IF phase shifter 28, IF signal amplifier 41, and controller 29 on the same layer of the semiconductor substrate 20, heat generated by the various circuit elements is less likely to build up and is easier to dissipate than when these elements are stacked. This prevents performance degradation of the transmitter circuit 201 due to heat generated by the semiconductor substrate 20.

[0027] 1, an LO signal generator 31 is provided in a one-to-one correspondence with an LO phase shifter 26, but an LO signal may be distributed and supplied from a single LO signal generator 31 to a plurality of LO phase shifters 26. Also, in the example of FIG. 1, an IF signal amplifier 41 is provided in a one-to-one correspondence with an IF phase shifter 28, but an IF signal may be distributed and supplied from a single IF signal amplifier 41 to a plurality of IF phase shifters 28. Also, the order of connection of the IF phase shifter 28 and the IF signal amplifier 41 may be reversed, so that the IF signal phase-adjusted by the IF phase shifter 28 is amplified by the IF signal amplifier 41 and supplied to the IF signal line 27. That is, the IF phase shifter 28 may be connected to the IF signal line 27 directly or via the IF signal amplifier 41.

[0028] The amount of circuitry that can be packed into the grid area 30 depends on the size of the standard cell, which is determined by the arrangement pitch of the antenna elements 11. If there is still room in the grid area 30, other components than the mixer 21, such as the 9-multiplier 34 (or a tripler or other multiplier in some cases) of the LO signal generator 31, the final stage amplifier that constitutes the IF signal amplifier 41, and a buffer circuit (not shown) connected to the mixer 21, may be arranged in the grid area 30. By arranging the circuit elements connected to the mixer 21 as close as possible to the mixer 21 in this way, the wiring distance from the circuit elements to the mixer 21 can be shortened as much as possible, suppressing attenuation of the signal input to the mixer 21 and improving the noise figure of the transmitter.

[0029] Second Embodiment Fig. 3 is a schematic plan view of an array antenna device according to a second embodiment of the present invention. The array antenna device 200 according to this embodiment is a 300 GHz band silicon CMOS receiver formed by stacking a printed circuit board 10 and a semiconductor substrate 20. Note that, for convenience, Fig. 3 shows the plan views of the printed circuit board 10 and the semiconductor substrate 20 side by side, but in reality, they are stacked by flip-chip bonding.

[0030] Antenna elements 11, such as rectangular microstrip patch antennas, are arranged in a 4x4 grid on the printed circuit board 10. Considering that the desired RF frequency of the array antenna device 200 is 252 to 296 GHz (wavelength of approximately 1000 to 1200 μm), for example, the sum of the lengths of the two sides of the antenna elements 11 is 300 to 350 μm, which is one-quarter wavelength of the RF signal with some margin, and the arrangement pitch of the antenna elements 11 in the row and column directions (corresponding to the horizontal and vertical directions in FIG. 3 ) is 600 to 700 μm, which is one-half wavelength of the RF signal with some margin.

[0031] A receiving circuit 202 is mounted on the semiconductor substrate 20. The receiving circuit 202 is a collection of individual receivers that process RF signals received by the individual antenna elements 11. Each individual receiver is a mixer-first configuration receiver in which a mixer that downconverts the RF signal with an LO signal to generate an IF signal is located in the first stage. This type of mixer-first configuration is adopted in 300 GHz band silicon CMOS receivers in which a low-noise amplifier cannot be located in the first stage.

[0032] 4 is a circuit diagram of an example mixer-first configuration receiver. The receiver includes a mixer 21, an LO signal generator 31, and an IF signal amplifier 42. The RF signal terminal 22 of the mixer 21 is connected to the antenna element 11, the LO signal terminal 23 is connected to the LO signal generator 31, and the IF signal terminal 24 is connected to the IF signal amplifier 42.

[0033] More specifically, the LO signal generator 31 includes a balun 32, a preamplifier 33, and a 9-multiplier 34. The balun 32 converts an unbalanced LO original signal input from an oscillator (not shown) into a balanced signal. As an example, the RF signal at the RF signal terminal 22 of the mixer 21 has a frequency of 275 GHz, and the LO original signal has a frequency of 25 GHz. The preamplifier 33 amplifies the balanced signal output from the balun 32. The 9-multiplier 34 multiplies the frequency of the preamplifier output signal by 9 to output a 225 GHz LO signal. The output signal of the 9-multiplier 34 is input to the mixer 21 via the LO signal terminal 23 of the mixer 21. The IF signal amplifier 42 is composed of a plurality of amplifiers connected together and amplifies the balanced IF signal of approximately 50 GHz output from the IF signal terminal 24 of the mixer 21.

[0034] It is also possible to set the frequency of the LO original signal to 75 GHz and replace the nine-multiplier 34 with a tripler that triples the frequency of the input signal.

[0035] Returning to FIG. 3 , the mixers 21 of the individual receivers described above are arranged in a grid pattern in 4×4 grid regions 30 on the semiconductor substrate 20. Each mixer 21 is composed of one or more transistors and one or more passive elements. The length of one side of each grid region 30 is 600 to 700 μm, the same as the arrangement pitch of the antenna elements 11, and one antenna element 11 can fit in one grid region 30 in a planar view. In other words, if the printed circuit board 10 is the upper layer and the semiconductor substrate 20 is the lower layer, each mixer 21 is arranged directly below each antenna element 11 in a planar view. The RF signal terminal 22 of each mixer 21 on the semiconductor substrate 20 is electrically connected to the corresponding antenna element 11 on the printed circuit board 10 via bumps (not shown).

[0036] An LO signal line 25 is wired for each column of mixers 21 arranged in a grid pattern. In this embodiment, there are four LO signal lines 25 in total. These LO signal lines 25 are arranged at equal intervals, that is, at the same pitch as the arrangement pitch of the antenna elements 11, along the arrangement of the columns of mixers 21. To each LO signal line 25, the LO signal terminals 23 of the four mixers 21 in the same column are commonly connected.

[0037] An LO phase shifter 26 is connected to the end of each LO signal line 25. Furthermore, the above-mentioned LO signal generator 31 is connected to each LO phase shifter 26. Each LO phase shifter 26 receives an LO signal from the LO signal generator 31, adjusts its phase, and supplies the phase-adjusted LO signal to each LO signal line 25. The amount of phase adjustment by each LO phase shifter 26 is controlled by a controller 29. In this way, LO signals of the same phase are input to the mixers 21 in the same column, and the phase of the LO signal can be adjusted for each column of mixers 21 independently of the mixers 21 in other columns. This allows beam sweeping in the row direction of the array of antenna elements 11 by adjusting the phase of the LO signal of each LO signal line 25.

[0038] An IF signal line 27 is wired for each row of mixers 21 arranged in a grid pattern. In this embodiment, there are a total of four IF signal lines 27. These IF signal lines 27 are arranged at equal intervals, i.e., at the same pitch as the arrangement pitch of the antenna elements 11, along the row arrangement of the mixers 21, across multiple grid regions 30. To each IF signal line 27, the IF signal terminals 24 of the four mixers 21 in the same row are commonly connected.

[0039] An IF phase shifter 28 is connected to the end of each IF signal line 27. Furthermore, the above-mentioned IF signal amplifier 42 is connected to each IF phase shifter 26. The IF phase shifters 28 and the IF signal amplifiers 42 connected thereto are arranged in empty spaces in the row direction of the grid area 30. Each IF phase shifter 28 receives an IF signal from the IF signal line 27 and adjusts its phase. The IF signal amplifier 42 amplifies the IF signal whose phase has been adjusted by the IF phase shifter 28. The IF signals of each phase are amplified by the IF signal amplifier 42 and then power-combined to become a received IF signal. The amount of phase adjustment by each IF phase shifter 28 is controlled by the controller 29. In this way, IF signals of the same phase are output from the mixers 21 in the same row, and the phase of the IF signal can be adjusted for each row of mixers 21 independently of the mixers 21 in other rows. This makes it possible to perform beam sweep in the column direction of the array of antenna elements 11 by adjusting the phase of the IF signal on each IF signal line 27 .

[0040] As described above, each grid area 30 is a narrow area with a side length of 600 to 700 μm, making it impossible to place many circuit elements. Therefore, circuits of a certain size, such as the LO phase shifter 26, the LO signal generator 31, the IF phase shifter 28, the IF signal amplifier 41, and the controller 29, are all located outside the grid area 30. For example, as shown in FIG. 3 , the LO phase shifter 26 connected to the end of the LO signal line 25 extending in the column direction of the grid area 30 and the LO signal generator 31 connected thereto are located in the empty space in the column direction of the grid area 30, the IF phase shifter 28 connected to the end of the IF signal line 27 extending in the row direction of the grid area 30 and the IF signal amplifier 42 connected thereto are located in the empty space in the row direction of the grid area 30, and the controller 29 is located in the remaining empty space.

[0041] As described above, this embodiment employs an array antenna in a 300 GHz silicon CMOS receiver to increase received power. Furthermore, the phases of the LO signal and IF signal can be adjusted to sweep the received RF signal in two dimensions, vertically and horizontally. Furthermore, by arranging the mixer 21, LO phase shifter 26, LO signal generator 31, IF phase shifter 28, IF signal amplifier 42, and controller 29 on the same layer of the semiconductor substrate 20, heat generated by the various circuit elements is less likely to build up and is easier to dissipate than if they were stacked. This prevents performance degradation of the receiver circuit 202 due to heat generated by the semiconductor substrate 20.

[0042] 3, an LO signal generator 31 is provided in a one-to-one correspondence with the LO phase shifter 26, but an LO signal may be distributed and supplied from a single LO signal generator 31 to multiple LO phase shifters 26. Also, in the example of FIG. 3, an IF signal amplifier 42 is provided in a one-to-one correspondence with the IF phase shifter 28, but output signals from multiple IF phase shifters 28 may be power-combined and then the combined IF signal may be input to a single IF signal amplifier 42. Alternatively, the order in which the IF phase shifters 28 and the IF signal amplifiers 42 are connected may be reversed, so that the IF signal from the IF signal line 27 is amplified by the IF signal amplifier 42 and then phase-adjusted by the IF phase shifter 28. That is, the IF phase shifter 28 may be connected to the IF signal line 27 directly or via the IF signal amplifier 41.

[0043] The amount of circuitry that can be packed into the grid area 30 depends on the size of the standard cell, which is determined by the arrangement pitch of the antenna elements 11. If there is still room in the grid area 30, other components than the mixer 21, such as the 9-multiplier 34 (or a tripler or other multiplier in some cases) of the LO signal generator 31, the first-stage amplifier that constitutes the IF signal amplifier 42, and a buffer circuit (not shown) connected to the mixer 21, may be arranged in the grid area 30. In this way, by arranging circuit elements that supply signals directly to the mixer 21 or that receive signals directly from the mixer 21 as close as possible to the mixer 21, the wiring distance from the circuit element to the mixer 21 can be minimized, suppressing attenuation of the signal input to or output from the mixer 21 and improving the noise figure of the receiver.

[0044] (Third Embodiment) Figure 5 is a schematic plan view of an array antenna device according to a third embodiment of the present invention. The array antenna device 300 according to this embodiment is a 300 GHz band transmitter formed by laminating a printed circuit board 10 and an opto-electrical substrate 50. Note that, for convenience, the plan views of the printed circuit board 10 and the opto-electrical substrate 50 are drawn side by side in Figure 5, but in reality they are laminated by flip-chip bonding. Below, a description of the same points as in the first embodiment will be omitted, and only the differences will be described.

[0045] Antenna elements 11, such as rectangular microstrip patch antennas, are arranged in a 4x4 grid on the printed circuit board 10. Considering that the desired RF frequency of the array antenna device 300 is 252 to 296 GHz (wavelength of approximately 1000 to 1200 μm), for example, the sum of the lengths of the two sides of the antenna elements 11 is 300 to 350 μm, which is one-quarter wavelength of the RF signal with a slight margin, and the arrangement pitch of the antenna elements 11 in the row and column directions (corresponding to the horizontal and vertical directions in FIG. 5 ) is 600 to 700 μm, which is one-half wavelength of the RF signal with a slight margin.

[0046] An optoelectronic conversion circuit 203 is mounted on the optoelectronic board 50. Specifically, mixers 51 are arranged in a grid pattern in a 4×4 grid region 30 on the optoelectronic board 50. The mixers 51 are uni-traveling-carrier photodiodes (UTC-PDs). When two optical signals with a frequency difference are input to the UTC-PD, terahertz waves are generated as a beat signal of those optical signals. For example, by inputting two optical signals (an LO signal and an IF signal, described below) with a frequency difference of about 300 GHz into the mixer 51, electromagnetic waves in the 300 GHz band are generated in the mixer 51, and 300 GHz radio waves are output from the antenna element 11.

[0047] The length of one side of each grid area 30 is 600 to 700 μm, the same as the arrangement pitch of the antenna elements 11, and one antenna element 11 can fit in one grid area 30 in plan view. That is, if the printed circuit board 10 is the upper layer and the opto-electrical board 50 is the lower layer, each mixer 51 is arranged directly below each antenna element 11 in plan view. The RF signal terminal (not shown) of each mixer 51 on the opto-electrical board 50 is electrically connected to the corresponding antenna element 11 on the printed circuit board 10 via a bump (not shown).

[0048] An LO signal line 55 is wired for each column of mixers 51 arranged in a grid pattern. The LO signal lines 55 are optical waveguides, and there are four in total in this embodiment. These LO signal lines 55 are arranged at equal intervals, that is, at the same pitch as the arrangement pitch of the antenna elements 11, along the rows of mixers 51. Each LO signal line 55 is commonly connected to the LO signal terminals (not shown) of the four mixers 51 in the same column.

[0049] An LO phase shifter 56 is connected to the end of each LO signal line 55. The LO phase shifter 56 is an optical phase shifter that adjusts the phase of an input optical signal. Each LO phase shifter 56 receives an LO signal, which is an optical signal, adjusts its phase, and supplies the phase-adjusted LO signal to each LO signal line 55. As an example, the LO signal is near-infrared light with a wavelength of approximately 1.5 μm. The amount of phase adjustment by each LO phase shifter 56 is controlled by a controller 59. In this way, LO signals of the same phase are input to the mixers 51 in the same column, and the phase of the LO signal can be adjusted for each column of mixers 51 independently of the mixers 51 in other columns. This allows beam sweeping in the row direction of the array of antenna elements 11 by adjusting the phase of the LO signal of each LO signal line 55.

[0050] An IF signal line 57 is wired for each row of mixers 51 arranged in a grid pattern. The IF signal lines 57 are optical waveguides, and there are four in total in this embodiment. These IF signal lines 57 are arranged at equal intervals, i.e., at the same pitch as the arrangement pitch of the antenna elements 11, along the arrangement of the rows of mixers 51, across multiple grid areas 30. Each IF signal line 57 is commonly connected to the IF signal terminals (not shown) of the four mixers 51 in the same row.

[0051] An IF phase shifter 58 is connected to the end of each IF signal line 57. The IF phase shifter 58 is an optical phase shifter that adjusts the phase of an input optical signal. Each IF phase shifter 58 receives an IF signal, which is an optical signal, adjusts its phase, and supplies the phase-adjusted IF signal to each IF signal line 57. As an example, the IF signal is near-infrared light with a wavelength of approximately 1.5 μm, and the frequency difference with the LO signal is approximately 300 GHz. The amount of phase adjustment by each IF phase shifter 58 is controlled by a controller 59. In this way, IF signals of the same phase are input to the mixers 51 in the same row, and the phase of the IF signal can be adjusted for each row of mixers 51 independently of the mixers 51 in other rows. This allows beam sweeping in the column direction of the array of antenna elements 11 by adjusting the phase of the IF signal of each IF signal line 57.

[0052] As described above, each grid area 30 is a narrow area with a side length of 600 to 700 μm, and therefore it is not possible to arrange many circuit elements in it. Therefore, the LO phase shifter 56, the IF phase shifter 58, and the controller 59 are all arranged outside the grid area 30. For example, as shown in FIG. 5 , the LO phase shifter 26 connected to the end of the LO signal line 55 extending in the column direction of the grid area 30 may be arranged in an empty area in the column direction of the grid area 30, the IF phase shifter 58 connected to the end of the IF signal line 57 extending in the row direction of the grid area 30 may be arranged in an empty area in the row direction of the grid area 30, and the controller 59 may be arranged in the remaining empty area.

[0053] As described above, according to this embodiment, the transmission power can be increased by adopting an array antenna in a 300 GHz band transmitter as a wireless interface for an optical communication device. Furthermore, the phases of the LO signal and the IF signal can be adjusted to sweep the transmission RF signal in two dimensions, vertically and horizontally.

[0054] (Fourth Embodiment) It is also possible to integrate the transmitter according to the first embodiment and the receiver according to the second embodiment. Fig. 6 is a schematic plan view of the configuration of an array antenna device according to a fourth embodiment of the present invention. The array antenna device 400 according to this embodiment is a 300 GHz band silicon CMOS transceiver formed by stacking a printed circuit board 10 and a semiconductor substrate 20. Note that, for convenience, the plan views of the printed circuit board 10 and the semiconductor substrate 20 are drawn side by side in Fig. 6, but in reality they are stacked by flip-chip bonding.

[0055] Antenna elements 11, such as rectangular microstrip patch antennas, are arranged in a 4x4 grid on the printed circuit board 10. Considering that the desired RF frequency of the array antenna device 400 is 252 to 296 GHz (wavelength of approximately 1000 to 1200 μm), for example, the sum of the lengths of the two sides of the antenna elements 11 is 300 to 350 μm, which is a quarter wavelength of the RF signal with a slight margin, the arrangement pitch of the antenna elements 11 in the row direction (horizontal direction in FIG. 6 ) is 600 to 700 μm, which is a half wavelength of the RF signal with a slight margin, and the arrangement pitch in the column direction (vertical direction in FIG. 6 ) is 300 to 350 μm, which is a quarter wavelength of the RF signal with a slight margin. In other words, the arrangement pitch of the antenna elements 11 in the column direction is half that of the first and second embodiments.

[0056] A transmission / reception circuit 204 is mounted on the semiconductor substrate 20. The transmission / reception circuit 204 is a collection of individual mixarist-configured transmitters that transmit RF signals (radio frequency signals) from the individual antenna elements 11 and individual mixer-first-configured receivers that process the RF signals received by the individual antenna elements 11. The mixarist-configured transmitters and mixer-first-configured receivers have been described with reference to FIGS. 2 and 4.

[0057] The individual transmitter and receiver mixers 21 described above are arranged in a grid pattern in 4×4 grid regions 30 on the semiconductor substrate 20. Each mixer 21 is composed of one or more transistors and one or more passive elements. The length of each grid region 30 is 300 to 350 μm vertically and 600 to 700 μm horizontally, the same as the arrangement pitch of the antenna elements 11 in the column and row directions, respectively, and one antenna element 11 can fit in one grid region 30 in a planar view. In other words, if the printed circuit board 10 is the upper layer and the semiconductor substrate 20 is the lower layer, each mixer 21 is arranged directly below each antenna element 11 in a planar view. The RF signal terminal 22 of each mixer 21 on the semiconductor substrate 20 is electrically connected to the corresponding antenna element 11 on the printed circuit board 10 via bumps (not shown).

[0058] An LO signal line 25 is wired for each column of mixers 21 arranged in a grid pattern. In this embodiment, there are four LO signal lines 25 in total. These LO signal lines 25 are arranged at equal intervals, that is, at the same pitch as the arrangement pitch of the antenna elements 11, along the arrangement of the columns of mixers 21. To each LO signal line 25, the LO signal terminals 23 of the four mixers 21 in the same column are commonly connected.

[0059] An LO phase shifter 26 is connected to the end of each LO signal line 25. Furthermore, the above-mentioned LO signal generator 31 is connected to each LO phase shifter 26. Each LO phase shifter 26 receives an LO signal from the LO signal generator 31, adjusts its phase, and supplies the phase-adjusted LO signal to each LO signal line 25. The amount of phase adjustment by each LO phase shifter 26 is controlled by a controller 29. In this way, LO signals of the same phase are input to the mixers 21 in the same column, and the phase of the LO signal can be adjusted for each column of mixers 21 independently of the mixers 21 in other columns. This allows beam sweeping in the row direction of the array of antenna elements 11 by adjusting the phase of the LO signal of each LO signal line 25.

[0060] An IF signal line 27 is wired for each row of the mixers 21 arranged in a grid pattern. In this embodiment, there are four IF signal lines 27 in total. These IF signal lines 27 are arranged at equal intervals across a plurality of grid regions 30 along the rows of the mixers 21, i.e., at the same pitch as the arrangement pitch of the antenna elements 11 in the column direction. To each IF signal line 27, the IF signal terminals 24 of the four mixers 21 in the same row are commonly connected.

[0061] An IF phase shifter 28 is connected to the end of each IF signal line 27. Furthermore, the above-mentioned IF signal amplifiers 41 and 42 are alternately connected to each IF phase shifter 28. The IF phase shifters 28 and the IF signal amplifiers 42 and 42 connected thereto are arranged in the row-wise empty spaces of the grid area 30. That is, the individual transmitter and receiver circuit elements are alternately arranged in the column-wise direction of the antenna elements 11 arranged in a grid pattern. Each IF phase shifter 28 of the transmitter receives the IF signal amplified by the IF signal amplifier 41, adjusts its phase, and supplies the phase-adjusted IF signal to each IF signal line 27. Each IF phase shifter 28 of the receiver receives the IF signal from the IF signal line 27 and adjusts its phase. The IF signal amplifier 42 of the receiver amplifies the IF signal phase-adjusted by the IF phase shifter 28. The IF signals of each phase are amplified by the IF signal amplifier 42 and then power-combined to form a received IF signal. The amount of phase adjustment by each IF phase shifter 28 is controlled by a controller 29. In this way, IF signals of the same phase are input to the mixers 21 in the same row in the transmitter, and IF signals of the same phase are output from the mixers 21 in the same row in the receiver, so that the phase of the IF signal can be adjusted for each row of mixers 21 independently of the mixers 21 in other rows. Thus, by adjusting the phase of the IF signal on each IF signal line 27, beam sweep in the column direction of the array of antenna elements 11 is possible in both transmission and reception.

[0062] As described above, each grid area 30 is a narrow area measuring 300 to 350 μm in length and 600 to 700 μm in width, making it impossible to place many circuit elements. Therefore, circuits of a certain size, such as the LO phase shifter 26, the LO signal generator 31, the IF phase shifter 28, the IF signal amplifier 41, the IF signal amplifier 42, and the controller 29, are all located outside the grid area 30. For example, as shown in FIG. 6 , the LO phase shifter 26 connected to the end of the LO signal line 25 extending in the column direction of the grid area 30 and the LO signal generator 31 connected thereto are located in the empty column area of ​​the grid area 30, the IF phase shifter 28 connected to the end of the IF signal line 27 extending in the row direction of the grid area 30 and the IF signal amplifier 41 and the IF signal amplifier 42 connected thereto are located in the empty row area of ​​the grid area 30, and the controller 29 is located in the remaining empty area.

[0063] As described above, this embodiment employs an array antenna in a 300 GHz silicon CMOS transceiver to increase transmission power and reception power. Furthermore, the phases of the LO signal and IF signal can be adjusted to sweep the transmission RF signal and reception RF signal in two dimensions, both vertically and horizontally. Furthermore, by arranging the mixer 21, LO phase shifter 26, LO signal generator 31, IF phase shifter 28, IF signal amplifier 41, IF signal amplifier 42, and controller 29 on the same layer of the semiconductor substrate 20, heat generated by the various circuit elements is less likely to build up and is easier to dissipate than if they were stacked. This prevents performance degradation of the transceiver circuit 204 due to heat generated by the semiconductor substrate 20.

[0064] 6, an LO signal generator 31 is provided in a one-to-one correspondence with the LO phase shifter 26, but an LO signal may be distributed and supplied from a single LO signal generator 31 to a plurality of LO phase shifters 26. Also, in the example of FIG. 6, an IF signal amplifier 41 is provided in a one-to-one correspondence with the IF phase shifter 28, but an IF signal may be distributed and supplied from a single IF signal amplifier 41 to a plurality of IF phase shifters 28. Also, in the example of FIG. 6, an IF signal amplifier 42 is provided in a one-to-one correspondence with the IF phase shifter 28, but output signals from a plurality of IF phase shifters 28 may be power-combined and then the combined IF signal may be input to a single IF signal amplifier 42. Also, the order of connection of the IF phase shifter 28 and the IF signal amplifier 41 may be reversed, so that the IF signal phase-adjusted by the IF phase shifter 28 is amplified by the IF signal amplifier 41 and supplied to the IF signal line 27. That is, the IF phase shifter 28 of the transmitter may be connected to the IF signal line 27 either directly or via the IF signal amplifier 41. Furthermore, the connection order of the IF phase shifter 28 and the IF signal amplifier 42 may be reversed so that the IF signal from the IF signal line 27 is amplified by the IF signal amplifier 42 and then phase-adjusted by the IF phase shifter 28. That is, the IF phase shifter 28 of the receiver may be connected to the IF signal line 27 either directly or via the IF signal amplifier 41.

[0065] The amount of circuitry that can be packed into the grid area 30 depends on the size of the standard cell, which is determined by the arrangement pitch of the antenna elements 11. If there is still room in the grid area 30, other components may be arranged in the grid area 30 in addition to the mixer 21, such as the 9-multiplier 34 (or a tripler or other multiplier in some cases) of the LO signal generator 31, the final-stage amplifier that constitutes the IF signal amplifier 41, the first-stage amplifier that constitutes the IF signal amplifier 42, and a buffer circuit (not shown) connected to the mixer 21. By arranging circuit elements that supply signals directly to the mixer 21 or that receive signals directly from the mixer 21 as close as possible to the mixer 21 in this way, the wiring distance from the circuit elements to the mixer 21 can be minimized, which suppresses attenuation of signals input to or output from the mixer 21 and improves the noise figures of the transmitter and receiver.

[0066] In the above configuration, receiving antenna elements 11 (e.g., antenna elements 11 in odd-numbered rows in the antenna array) are not used during transmission, and transmitting antenna elements 11 (e.g., antenna elements 11 in even-numbered rows in the antenna array) are not used during reception, resulting in poor antenna element utilization efficiency. Therefore, to enable transmission and reception using all antenna elements 11, the arrangement pitch of the antenna elements 11 in the column direction may be doubled, i.e., 600 to 700 μm, which is half the wavelength of the RF signal with a slight margin, as in the first and second embodiments. In this case, the arrangement pitch of the transmitting and receiving antenna elements 11 is equivalent to one wavelength, but the circuit is configured so that during transmission, the receiving antenna element 11 transmits an RF signal with a phase intermediate between the RF signals transmitted from the transmitting antenna elements 11 on either side, and during reception, the transmitting antenna element 11 receives an RF signal with a phase intermediate between the RF signals received by the receiving antenna elements 11 on either side. This effectively arranges the transmitting and receiving antenna elements 11 at a pitch equivalent to half the wavelength.

[0067] Fifth Embodiment The semiconductor substrate 20 of the array antenna device 100 according to the first embodiment may be formed of a compound semiconductor or a bipolar CMOS (BiCMOS). FIG. 7 is a plan view of a schematic configuration of an array antenna device according to a fifth embodiment of the present invention. In the antenna device 100A according to this embodiment, the semiconductor substrate 20 is a compound semiconductor substrate such as GaAs, InP, or InGaAlP, or a SiGe-BiCMOS substrate. Because compound semiconductors and BiCMOS have excellent high-frequency characteristics, it is possible to provide a power amplifier 61 downstream of the mixer 21, i.e., between the antenna element 11 and the mixer 21, for amplifying the 300 GHz-band RF signal output from the mixer 21. The power amplifier 61 downstream of the mixer 21 is arranged in the grid region 30 together with the mixer 21.

[0068] In the case of an array antenna device 100 configured with silicon CMOS as shown in FIG. 1, the output power per mixer 21 is relatively small, so many antenna elements 11 must be used to ensure the required transmission power. This requires a large number of mixer-configured transmitters, as shown in FIG. 2, which increases power consumption. Furthermore, if an upper limit on the power consumption of the semiconductor substrate 20 is set, the number of transmitters that can be driven is limited, which may result in insufficient transmission power. On the other hand, although compound semiconductors and BiCMOS have higher manufacturing costs than silicon CMOS, they can increase the transmission power per antenna element 11 by placing a power amplifier 61 after the mixer 21, thereby reducing the number of transmitters required to ensure the required transmission power. In other words, compound semiconductors and BiCMOS can achieve high transmission power with a smaller circuit scale than silicon CMOS, thereby overcoming the problem of increased manufacturing costs.

[0069] Sixth Embodiment The semiconductor substrate 20 of the array antenna device 200 according to the second embodiment may be formed of a compound semiconductor or a bipolar CMOS (BiCMOS). FIG. 8 is a plan view of a schematic configuration of an array antenna device according to a sixth embodiment of the present invention. In the antenna device 200A according to this embodiment, the semiconductor substrate 20 is a substrate of a compound semiconductor such as GaAs, InP, or InGaAlP, or a SiGe-BiCMOS substrate. Because compound semiconductors and BiCMOS have excellent high-frequency characteristics, it is possible to provide a low-noise amplifier 62 upstream of the mixer 21, i.e., between the antenna element 11 and the mixer 21, for amplifying the weak 300 GHz-band RF signal received by the antenna element 11. The low-noise amplifier 62 upstream of the mixer 21 is arranged in the grid region 30 together with the mixer 21.

[0070] In the case of an array antenna device 200 configured with silicon CMOS as shown in FIG. 2, the power of the RF signal input to each mixer 21 is relatively small, so many antenna elements 11 must be used to ensure the required reception power. This requires a large number of mixer-first configuration receivers as shown in FIG. 4, which increases power consumption. Furthermore, if an upper limit on the power consumption of the semiconductor substrate 20 is set, the number of receivers that can be driven is limited, which may result in insufficient reception power. On the other hand, although compound semiconductors and BiCMOS have higher manufacturing costs than silicon CMOS, placing a low-noise amplifier 62 in the front stage of the mixer 21 increases the power of the RF signal input to the mixer 21, thereby reducing the number of receivers required to ensure the required reception power. In other words, compound semiconductors and BiCMOS can achieve greater reception power with a smaller circuit scale than silicon CMOS, thereby overcoming the problem of increased manufacturing costs.

[0071] Seventh Embodiment The semiconductor substrate 20 of the array antenna device 400 according to the fourth embodiment may be formed of a compound semiconductor or a bipolar CMOS (BiCMOS). FIG. 9 is a plan view schematic diagram of an array antenna device according to the seventh embodiment of the present invention. In the antenna device 400A according to this embodiment, the semiconductor substrate 20 is a substrate of a compound semiconductor such as GaAs, InP, or InGaAlP, or a SiGe-BiCMOS substrate. Because compound semiconductors and BiCMOS have excellent high-frequency characteristics, it is possible to provide a power amplifier 61 after the mixer 21, i.e., between the antenna element 11 and the mixer 21, for amplifying the 300 GHz RF signal output from the mixer 21 in the transmitter. Also, it is possible to provide a low-noise amplifier 62 before the mixer 21, i.e., between the antenna element 11 and the mixer 21, for amplifying the weak 300 GHz RF signal received by the antenna element 11 in the receiver. A power amplifier 61 in the subsequent stage of the mixer 21 and a low noise amplifier 62 in the previous stage of the mixer 21 are arranged in the grid area 30 together with the mixer 21 .

[0072] In the case of an array antenna device 400 configured with silicon CMOS as shown in FIG. 6, the output power per mixer 21 is relatively small, and the power of the RF signal input to each mixer 21 is also relatively small. Therefore, a large number of mixer-first configuration transmitters and mixer-first configuration receivers as shown in FIGS. 2 and 4 are required, which increases power consumption. Furthermore, if an upper limit on the power consumption of the semiconductor substrate 20 is set, the number of transmitters and receivers that can be driven is limited, which may result in insufficient transmission and reception power. On the other hand, although compound semiconductors and BiCMOS have higher manufacturing costs than silicon CMOS, they can increase the transmission power per antenna element 11 by placing a power amplifier 61 after the mixer 21, and can increase the power of the RF signal input to the mixer 21 by placing a low-noise amplifier 62 before the mixer 21. This reduces the number of transmitters and receivers required to ensure the required transmission and reception power. That is, compound semiconductors and BiCMOS can obtain larger transmission and reception power with a smaller circuit scale than silicon CMOS, and therefore overcome the problem of increased manufacturing costs.

[0073] <<Modifications>> The mixer 21 or the mixer 51 does not necessarily have to be disposed directly below the antenna element 11, but may be disposed in an appropriate location in the grid area 30. In this sense, the mixers 21 or the mixers 51 do not have to be disposed at equal intervals, and may be disposed in a staggered pattern, for example.

[0074] The LO signal lines 25 or LO signal lines 55 do not need to be arranged at equal intervals, and for example, two LO signal lines 25 or LO signal lines 55 may be arranged between the first and second columns of the mixers 21 or 51, and the remaining two LO signal lines 25 or LO signal lines 55 may be arranged between the third and fourth columns of the mixers 21 or 51. Similarly, the IF signal lines 27 or IF signal lines 57 do not need to be arranged at equal intervals, and for example, two IF signal lines 27 or IF signal lines 57 may be arranged between the first and second rows of the mixers 21 or 51, and the remaining two IF signal lines 27 or IF signal lines 57 may be arranged between the third and fourth rows of the mixers 21 or 51. This ensures a total of four grid areas 30 with circuit layout space, two grid areas in the vertical and two grid areas in the horizontal directions, and circuit elements other than the mixer 21 or the mixer 51 can be arranged in the grid areas 30 .

[0075] The antenna elements 11 may be mounted on the redistribution layer (RDL) of the semiconductor substrate 20 instead of on the printed circuit board 10. In this way, an array antenna device can be realized on a single chip.

[0076] Needless to say, the number of antenna elements 11 is not limited to 16 (4 × 4). Increasing the number of antenna elements 11 increases the antenna gain. For example, by increasing the number of antenna elements 11 to 1,024 (32 × 32), the antenna gain is 64 times greater than when there are 16 antenna elements 11. When the number of antenna elements 11 is large, the length of the LO signal line 25 or LO signal line 55 and the IF signal line 27 or IF signal line 57 increases, which may result in significant signal attenuation at the terminal end of the signal line. Therefore, a buffer circuit may be provided at an appropriate location along the signal line to ensure that a signal of a certain magnitude or greater can be transmitted to the terminal end. Furthermore, the LO phase shifter 26 may be connected directly to the LO signal line 25 or via a buffer circuit.

[0077] If it is sufficient for the RF signal to sweep in only one direction, the phase shift amount of either the LO phase shifter or the IF phase shifter may be set to a fixed value, or one of the LO phase shifter and IF phase shifter may be omitted, and a signal of the same phase or a signal with a predetermined phase difference may be connected to the signal line where the phase shifter is omitted.

[0078] If sweeping of the RF signal is not necessary and beamforming in a specific direction is all that is required, the controller may be omitted and the phase amounts of the LO phase shifter and IF phase shifter may be set to fixed values, or the LO phase shifter and IF phase shifter may also be omitted and an LO signal and an IF signal that are in phase or have a predetermined phase difference may be connected to the LO signal line and the IF signal line.

[0079] The array antenna device can be configured scalably by connecting the circuit elements of the LO phase shifter 26, IF phase shifter 28, LO phase shifter 56, and IF phase shifter 58 in series in each of the above embodiments. Figure 10 is a plan view schematic diagram of an example of a semiconductor substrate for a transmitter compatible with a scalable configuration. For convenience, in Figure 10, the mixer 21 and the power amplifier 61 in the case of a compound semiconductor, which are shown in Figures 1 and 7, are referred to as a "mixer array" and are not shown, and the controller 29 is also not shown. On the semiconductor substrate 20, multiple LO phase shifters 26 are connected in series in a row direction at the same pitch as the row-wise arrangement pitch of the mixers (not shown) in the mixer array. An LO signal is input to the first-stage LO phase shifter 26 (the leftmost LO phase shifter 26 in the example of Figure 10) from an LO signal generator (not shown). The LO phase shifter 26 has a phase shifter 261, a frequency multiplier 262, and a buffer circuit 263. The LO signal input to the LO phase shifter 26 is phase-adjusted by the phase shifter 261 and split into two. One is amplified twice via a buffer circuit (not shown) and input to the frequency multiplier 262, while the other is amplified twice via a buffer circuit (not shown) and input to the next-stage LO phase shifter 26. The amount of phase adjustment by the phase shifter 261 is controlled by a controller (not shown). The LO signal input to the frequency multiplier 262 has its frequency multiplied and is supplied to the LO signal line 25 via the buffer circuit 263. Furthermore, on the semiconductor substrate 20, a plurality of IF phase shifters 28 are connected in series in a row at the same pitch as the column-wise arrangement pitch of the mixers (not shown) in the mixer array. An IF signal is input to the first-stage IF phase shifter 28 (the uppermost IF phase shifter 28 in the example of FIG. 10 ), and an LO signal is also input from an LO signal generator (not shown). The IF phase shifter 28 has a phase shifter 281 and a mixer 282. The LO signal input to the IF phase shifter 28 is phase-adjusted by the phase shifter 281 and split into two signals, one of which is amplified twice via a buffer circuit (not shown) and input to the mixer 282, and the other is amplified twice via a buffer circuit (not shown) and input to the next-stage IF phase shifter 28.The IF signal input to the IF phase shifter 28 is split into two, one of which is amplified twice via a buffer circuit (not shown) and input to the mixer 282, and the other of which is amplified twice via a buffer circuit (not shown) and input to the next-stage IF phase shifter 28. The mixer 282 mixes the IF signal with the phase-adjusted LO signal to generate a phase-adjusted IF signal, which is then amplified by the IF signal amplifier 41 and supplied to the IF signal line 27.

[0080] FIG. 11 is a plan view schematic diagram of an example of a receiving semiconductor substrate compatible with a scalable configuration. For convenience, in FIG. 11 , the mixers 21 and the low-noise amplifiers 62 in the case of compound semiconductors shown in FIGS. 3 and 8 are referred to as a "mixer array" and are not shown, and the controller 29 is also not shown. In the semiconductor substrate 20, a plurality of LO phase shifters 26 are connected in series in a row direction at the same pitch as the row-direction arrangement pitch of the mixers (not shown) in the mixer array. The configuration of the LO phase shifter 26 is as described with reference to FIG. 10 . In the semiconductor substrate 20, a plurality of IF phase shifters 28 are connected in series in a row direction at the same pitch as the column-direction arrangement pitch of the mixers (not shown) in the mixer array. The first-stage IF phase shifter 28 (the uppermost IF phase shifter 28 in the example of FIG. 11 ) receives as input the amplified IF signal from the IF signal amplifier 42, an LO signal from an LO signal generator (not shown), and also receives as input the IF signal output from the next-stage IF phase shifter 28. The IF phase shifter 28 has a phase shifter 281, a mixer 282, and a power combiner 283. The LO signal input to the IF phase shifter 28 is phase-adjusted by the phase shifter 281 and split into two, one of which is amplified twice via a buffer circuit (not shown) and input to the mixer 282, and the other is amplified twice via a buffer circuit (not shown) and input to the next-stage IF phase shifter 28. The IF signal input to the IF phase shifter 28 is also input to the mixer 282, where it is mixed with the phase-adjusted LO signal to generate a phase-adjusted IF signal. The phase-adjusted IF signal and the IF signal output from the next-stage IF phase shifter 28 are input to the power combiner 283, and these IF signals are power-combined and output. That is, the IF signal output from the last-stage IF phase shifter 28 is input one after another to the previous-stage IF phase shifter 28 and cumulatively power-combined, and the received IF signal is output from the first-stage IF phase shifter 28.

[0081] 10 and 11, the LO signal phase-adjusted by phase shifter 261 or phase shifter 281 is split into two and one is input to phase shifter 261 or phase shifter 281 in the next stage, but the LO signal before phase adjustment may be split into two and one may be input to its own phase shifter 261 or phase shifter 281 and the other to phase shifter 261 or phase shifter 281 in the next stage. Also, by following the above-mentioned modifications, the transmitter-receiver integrated array antenna devices shown in FIGS. 6 and 9 can be configured to be scalable.

[0082] As described above, the embodiments have been described as examples of the technology of the present invention. For this purpose, the accompanying drawings and detailed description have been provided. Therefore, the components described in the accompanying drawings and detailed description may include not only components essential for solving the problem, but also components that are not essential for solving the problem in order to exemplify the above technology. Therefore, the fact that these non-essential components are described in the accompanying drawings or detailed description should not be interpreted as immediately indicating that these non-essential components are essential. Furthermore, because the above-described embodiments are intended to exemplify the technology of the present invention, various modifications, substitutions, additions, omissions, etc. may be made within the scope of the claims or their equivalents.

[0083] The array antenna device according to the present invention can be widely used as a wireless communication device or wireless sensor that uses not only the 300 GHz band but also the terahertz band of 100 GHz or more.

[0084] 100, 200, 300, 400, 100A, 200A, 400A Array antenna device 10 Printed circuit board (first layer) 11 Antenna element 20 Semiconductor substrate (second layer) 30 Grid area 21 Mixer 22 RF signal terminal 23 LO signal terminal 24 IF signal terminal 25 LO signal line 26 LO phase shifter 27 IF signal line 28 IF phase shifter 29 Controller 50 Opto-electrical board (second layer) 51 Mixer 55 LO signal line 56 LO phase shifter 57 IF signal line 58 IF phase shifter 59 Controller

Claims

1. An array antenna device comprising: a first layer on which a plurality of antenna elements are arranged in a grid pattern; and a second layer laminated on said first layer, wherein said second layer has: a plurality of mixers arranged in a plurality of grid areas that overlap said plurality of antenna elements in a planar view, said mixers having an LO signal terminal, an IF signal terminal, and an RF signal terminal, said RF signal terminals being electrically connected to said plurality of antenna elements; a plurality of LO signal lines provided for each column of said plurality of mixers, said LO signal terminals of said mixers in the same column being commonly connected; and a plurality of IF signal lines provided for each row of said plurality of mixers, said IF signal terminals of said mixers in the same row being commonly connected.

2. The array antenna device of claim 1, wherein the second layer has a plurality of phase shifters connected to at least one of the plurality of LO signal lines and the plurality of IF signal lines, and the plurality of phase shifters are arranged outside the plurality of grid areas.

3. An array antenna device as described in claim 2, wherein the second layer has a controller that controls signal phase adjustment by the phase shifter, and the controller is arranged outside the plurality of grid regions.

4. The array antenna device according to claim 2, wherein the plurality of phase shifters are connected in series.

5. The array antenna device according to claim 4, wherein the plurality of phase shifters are arranged at the same pitch as the plurality of mixers.

6. An array antenna device according to any one of claims 1 to 5, wherein the plurality of LO signal lines are arranged in parallel at equal intervals.

7. An array antenna device according to any one of claims 1 to 5, wherein the plurality of IF signal lines are arranged in parallel at equal intervals.

8. An array antenna device according to any one of claims 1 to 5, wherein the first layer is a printed circuit board, and the second layer is a semiconductor substrate.

9. The array antenna device according to claim 8, wherein the semiconductor substrate is a compound semiconductor substrate or a BiCMOS substrate, and an amplifier is provided between the antenna elements and the mixer, the amplifier being arranged in the grid area.

10. The array antenna device according to claim 8, wherein the array antenna device is an integrated transmitter-receiver device.

11. The array antenna device according to claim 10, wherein the semiconductor substrate is a compound semiconductor substrate or a BiCMOS substrate, and an amplifier is provided between the antenna elements and the mixer, the amplifier being arranged in the grid area.

12. An array antenna device as described in any one of claims 1 to 5, wherein the first layer is a printed circuit board, the second layer is an opto-electrical board, the mixer is a uni-traveling carrier photodiode, and the signal connected to the LO signal line and the signal connected to the IF signal line are optical signals.