Semiconductor equipment

Abstract

Provided is a display device that drives at high speed. This display device has pixels, a scanning line driving circuit, and a power supply circuit. The pixels each have first and second transistors, and the second transistor is provided with a semiconductor layer inside an opening formed in an interlayer insulating layer on a substrate. A first conductive layer that functions as a gate electrode of the first transistor has a region that extends in a first direction, and is electrically connected to the scanning line driving circuit. A second conductive layer that functions as a source electrode or a drain electrode of the second transistor is provided below the opening. The second conductive layer has a region that extends in a second direction perpendicular to the first direction, and is electrically connected to the power supply circuit. The first conductive layer and the second conductive layer have respective regions that overlap each other with the interlayer insulating layer interposed therebetween.

Description

display device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a display device, a semiconductor device, a display module, and an electronic device. 2. Description of the Related Art One embodiment of the present invention relates to a method for manufacturing a display device and a method for manufacturing a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for higher integration and higher speed of the semiconductor devices. For example, when a semiconductor device is applied to a high-resolution display device, a highly integrated semiconductor device is required. As one means for increasing the integration degree of transistors, the development of fine-sized transistors is underway.

[0004] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproducibility in order to enhance the sense of realism and immersion. Examples of display devices applicable to such devices include liquid crystal display devices, organic electroluminescence (EL) elements, and light-emitting devices equipped with light-emitting elements such as light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a display device for VR that uses an organic EL element (also called an organic EL device).

[0006] International Publication No. 2018 / 087625

[0007] When the resolution of a display device is increased and the number of pixels per unit area is increased, it is preferable to drive the display device at high speed in order to ensure a certain frame frequency, for example.

[0008] Therefore, an object of one embodiment of the present invention is to provide a display device that operates at high speed and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a high-resolution display device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device including a transistor with a small size and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device including a transistor with high on-state current and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device with favorable electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a novel display device, a novel semiconductor device, and a manufacturing method thereof.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0010] One embodiment of the present invention includes a pixel, a power supply circuit, and a scan line driver circuit. The pixel includes a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer, and the first insulating layer has a first opening reaching the first conductive layer. The first conductive layer is electrically connected to a power supply circuit. The second conductive layer is provided over the first insulating layer. The second conductive layer has a second opening having a region overlapping with the first opening. The first semiconductor layer has a region in contact with the first conductive layer and a region in contact with the second conductive layer and located inside the first opening and a region in contact with the second conductive layer. the second insulating layer is provided on the first semiconductor layer so as to have a region located inside the first opening and a region located inside the second opening; the third conductive layer has a region located inside the first opening and a region located inside the second opening, and is provided so as to have a region facing the first semiconductor layer with the second insulating layer sandwiched therebetween; the second transistor has the second insulating layer, a second semiconductor layer below the second insulating layer, and a fourth conductive layer on the second insulating layer, the fourth conductive layer having a region overlapping with the second semiconductor layer, and the fourth conductive layer is electrically connected to a scanning line driver circuit, and the fourth conductive layer has a region overlapping with the first conductive layer via the first insulating layer and the second insulating layer.

[0011] Alternatively, in the above aspect, the second transistor may have a fifth conductive layer in contact with the second semiconductor layer, and the fifth conductive layer may be electrically connected to the third conductive layer.

[0012] Alternatively, in the above embodiment, the display device may include a signal line driver circuit, the second transistor may include a sixth conductive layer in contact with the second semiconductor layer, and the sixth conductive layer may be electrically connected to the signal line driver circuit.

[0013] Alternatively, in the above embodiment, the pixel may include a display element, and a pixel electrode of the display element may be electrically connected to the second conductive layer.

[0014] Alternatively, in the above aspect, the display device includes a reference potential generating circuit, and the pixel includes a third transistor. The third transistor includes a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a third semiconductor layer, and a second insulating layer. The first insulating layer is provided on the seventh conductive layer, and the first insulating layer has a third opening that reaches the seventh conductive layer. The seventh conductive layer is electrically connected to the pixel electrode. The eighth conductive layer is provided on the first insulating layer, and the eighth conductive layer has a fourth opening that has a region overlapping with the third opening. The eighth conductive layer is electrically connected to the reference potential generating circuit. The ninth conductive layer may have a region in contact with the eighth conductive layer and a region located inside the third opening and a region located inside the fourth opening, the second insulating layer may be provided on the third semiconductor layer so as to have a region located inside the third opening and a region located inside the fourth opening, the ninth conductive layer may have a region located inside the third opening and a region located inside the fourth opening, and may have a region facing the third semiconductor layer with the second insulating layer sandwiched therebetween, the ninth conductive layer may be electrically connected to a scanning line driving circuit, and the eighth conductive layer may have a region overlapping with the fourth conductive layer and a region overlapping with the ninth conductive layer.

[0015] Alternatively, one embodiment of the present invention includes a pixel, a scan line driver circuit, and a power supply circuit. The pixel includes a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer, and the first insulating layer has a first opening reaching the first conductive layer. The second conductive layer is provided over the first insulating layer, and the second conductive layer has a second opening having a region overlapping with the first opening. The first semiconductor layer the second insulating layer is provided on the first semiconductor layer so as to have a region located inside the first opening and a region located inside the second opening; the third conductive layer has a region located inside the first opening and a region located inside the second opening, and is provided so as to have a region facing the first semiconductor layer with the second insulating layer sandwiched between them; the third conductive layer is provided on the first semiconductor layer so as to have a region located inside the first opening and a region located inside the second opening, and is provided on the second insulating layer so as to have a region facing the first semiconductor layer with the second insulating layer sandwiched between them; the second transistor is electrically connected to a power supply circuit, the second transistor has a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a second semiconductor layer, and a second insulating layer, the first insulating layer is provided on the fourth conductive layer, and the first insulating layer has a third opening reaching the fourth conductive layer, the fourth conductive layer is electrically connected to a power supply circuit, the fifth conductive layer is provided on the first insulating layer, and the fifth conductive layer has a fourth opening having a region overlapping with the third opening, the second semiconductor layer has a region in contact with the fourth conductive layer and a region in contact with the fifth conductive layer, and the third opening the second insulating layer is provided on the second semiconductor layer so as to have a region located inside the third opening and a region located inside the fourth opening; the sixth conductive layer has a region located inside the third opening and a region located inside the fourth opening, and is provided so as to have a region facing the second semiconductor layer with the second insulating layer sandwiched therebetween; and the third conductive layer has a region overlapping with the fourth conductive layer via the first insulating layer and the second insulating layer.

[0016] Alternatively, in the above embodiment, the display device may include a signal line driver circuit, the first conductive layer may be electrically connected to the signal line driver circuit, and the first conductive layer may have a region overlapping with the third conductive layer.

[0017] Alternatively, in the above aspect, the second conductive layer may be electrically connected to the sixth conductive layer.

[0018] Alternatively, in the above aspect, the pixel may include a display element, and a pixel electrode of the display element may be electrically connected to the fifth conductive layer.

[0019] Alternatively, in the above aspect, the display device includes a reference potential generating circuit, the pixel includes a third transistor, the third transistor includes a seventh conductive layer, an eighth conductive layer, a ninth conductive layer, a third semiconductor layer, and a second insulating layer, the first insulating layer is provided on the seventh conductive layer, the first insulating layer has a fifth opening reaching the seventh conductive layer, the seventh conductive layer is electrically connected to the pixel electrode, the eighth conductive layer is provided on the first insulating layer, the eighth conductive layer has a sixth opening having a region overlapping with the fifth opening, the eighth conductive layer is electrically connected to the reference potential generating circuit, and the third semiconductor layer has a region in contact with the seventh conductive layer, and The ninth conductive layer may have a region in contact with the eighth conductive layer and a region located inside the fifth opening and a region located inside the sixth opening, the second insulating layer may be provided on the third semiconductor layer so as to have a region located inside the fifth opening and a region located inside the sixth opening, the ninth conductive layer may have a region located inside the fifth opening and a region located inside the sixth opening, and may have a region facing the third semiconductor layer with the second insulating layer sandwiched between them, the ninth conductive layer may be electrically connected to a scanning line driving circuit, and the eighth conductive layer may have a region overlapping with the third conductive layer and a region overlapping with the ninth conductive layer.

[0020] Alternatively, in the above-described embodiment, the first to third semiconductor layers may each contain a metal oxide, for example, indium, zinc, and M (wherein M is one or more elements selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium, and hafnium).

[0021] According to one embodiment of the present invention, a display device that operates at high speed and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a high-resolution display device and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a display device including a transistor with a small size and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a display device including a transistor with high on-state current and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a display device with favorable electrical characteristics and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a novel display device, a novel semiconductor device, and a manufacturing method thereof can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0023] FIG. 1A is a block diagram showing an example of the configuration of a display device. FIG. 1B is a plan view showing an example of the configuration of a pixel. FIGS. 1C and 1D are circuit diagrams showing an example of the configuration of a pixel. FIG. 2A is a block diagram showing an example of the configuration of a display device. FIG. 2B is a circuit diagram showing an example of the configuration of a pixel. FIGS. 3A to 3C are circuit diagrams showing an example of the configuration of a pixel. FIGS. 4A1 to 4A3 are plan views showing an example of the configuration of a display device. FIG. 4B is a cross-sectional view showing an example of the configuration of a display device. FIG. 5A is a plan view showing an example of the configuration of a display device. FIG. 5B is a cross-sectional view showing an example of the configuration of a display device. FIG. 6 is a plan view showing an example of the configuration of a display device. FIG. 7 is a cross-sectional view showing an example of the configuration of a display device. FIG. 8A is a plan view showing an example of the configuration of a display device. FIG. 8B is a cross-sectional view showing an example of the configuration of a display device. FIG. 9 is a plan view showing an example of the configuration of a display device. FIG. 10A is a plan view showing an example of the configuration of a display device. FIG. 10B is a cross-sectional view showing an example of the configuration of a display device. FIG. 11 is a plan view showing an example of the configuration of a display device. FIG. 12A is a plan view showing an example of the configuration of a display device. FIG. 12B is a cross-sectional view showing an example of the configuration of a display device. FIG. 13 is a plan view showing an example of the configuration of a display device. FIG. 14A is a plan view showing an example of the configuration of a display device. FIG. 14B is a cross-sectional view showing an example of the configuration of a display device. FIG. 15A is a plan view showing an example of the configuration of a display device. FIG. 15B is a cross-sectional view showing an example of the configuration of a display device. FIG. 16 is a plan view showing an example of the configuration of a display device. FIG. 17 is a plan view showing an example of the configuration of a display device. FIG. 18 is a plan view showing an example of the configuration of a display device. FIG. 19 is a plan view showing an example of the configuration of a display device. FIG. 20A is a plan view showing an example of the configuration of a display device. FIG. 20B is a cross-sectional view showing an example of the configuration of a display device. FIG. 21A is a plan view showing an example of the configuration of a display device. FIG. 21B is a cross-sectional view showing an example of the configuration of a display device. FIG. 22A is a plan view showing an example of the configuration of a display device. FIG. 22B is a cross-sectional view showing an example of the configuration of a display device. FIG. 23 is a plan view showing an example of the configuration of a display device. FIG. 24A is a plan view showing an example of the configuration of a display device. FIG. 24B is a cross-sectional view showing an example of the configuration of a display device. FIG. 25 is a plan view showing an example of the configuration of a display device. 26A and 26B are plan and cross-sectional views illustrating an example of the configuration of a display device.FIG. 27 is a plan view showing an example of the configuration of a display device. FIG. 28A is a plan view showing an example of the configuration of a display device. FIG. 28B is a cross-sectional view showing an example of the configuration of a display device. FIG. 29 is a plan view showing an example of the configuration of a display device. FIG. 30A is a plan view showing an example of the configuration of a display device. FIG. 30B is a cross-sectional view showing an example of the configuration of a display device. FIG. 31 is a plan view showing an example of the configuration of a display device. FIG. 32A is a plan view showing an example of the configuration of a display device. FIG. 32B is a cross-sectional view showing an example of the configuration of a display device. FIG. 33 is a plan view showing an example of the configuration of a display device. FIG. 34A is a plan view showing an example of the configuration of a display device. FIG. 34B is a cross-sectional view showing an example of the configuration of a display device. FIG. 35 is a plan view showing an example of the configuration of a display device. FIG. 36A is a plan view showing an example of the configuration of a display device. FIG. 36B is a cross-sectional view showing an example of the configuration of a display device. FIG. 37 is a plan view showing an example of the configuration of a display device. FIG. 38A is a plan view showing an example of the configuration of a display device. FIG. 38B is a cross-sectional view showing an example of the configuration of a display device. FIG. 39A is a block diagram showing an example of the configuration of a memory device. 39B to 39F are circuit diagrams showing an example of the configuration of a memory cell. FIGS. 40A to 40C are plan views showing an example of the configuration of a display device. FIG. 41A is a plan view showing an example of the configuration of a display device. FIG. 41B is a cross-sectional view showing an example of the configuration of a display device. FIG. 42A is a plan view showing an example of the configuration of a display device. FIG. 42B is a cross-sectional view showing an example of the configuration of a display device. FIG. 43A is a plan view showing an example of the configuration of a display device. FIGS. 43B1 to 43B3 are cross-sectional views showing an example of the configuration of a display device. FIGS. 44A and 44B are plan views showing an example of the configuration of a display device. FIGS. 45A1 and 45A2 are plan views showing an example of the configuration of a display device. FIG. 45B is a cross-sectional view showing an example of the configuration of a display device. FIG. 46A is a plan view showing an example of the configuration of a display device. FIG. 46B is a cross-sectional view showing an example of the configuration of a display device. FIG. 47A is a plan view showing an example of the configuration of a display device. FIG. 47B is a cross-sectional view showing an example of the configuration of a display device. FIG. 48A is a plan view showing an example of the configuration of a display device. FIG. 48B is a cross-sectional view showing an example of the configuration of a display device. 49A1 and 49A2 are plan views showing an example of the configuration of a display device, and Fig. 49B is a cross-sectional view showing an example of the configuration of a display device.FIG. 50A is a plan view showing an example of the configuration of a display device. FIG. 50B is a cross-sectional view showing an example of the configuration of a display device. FIG. 51A is a plan view showing an example of the configuration of a display device. FIG. 51B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 52A and 52B are plan views showing an example of the configuration of a display device. FIGS. 53A1 and 53A2 are plan views showing an example of the configuration of a display device. FIG. 53B is a cross-sectional view showing an example of the configuration of a display device. FIG. 54A is a plan view showing an example of the configuration of a display device. FIGS. 54B1 and 54B2 are cross-sectional views showing an example of the configuration of a display device. FIGS. 55A and 55B are cross-sectional views showing an example of the configuration of a display device. FIGS. 56A and 56B are cross-sectional views showing an example of the configuration of a display device. FIGS. 57A and 57B are cross-sectional views showing an example of the configuration of a display device. FIG. 58A is a plan view showing an example of the configuration of a display device. FIG. 58B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 59A and 59B are plan views showing an example of the configuration of a display device. FIG. 60A is a plan view showing an example of the configuration of a display device. FIG. 60B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 61A to 61C are plan views showing an example of the configuration of a display device. FIGS. 62A to 62C are plan views showing an example of the configuration of a display device. FIGS. 63A and 63B are plan views showing an example of the configuration of a display device. FIG. 64A is a plan view showing an example of the configuration of a display device. FIG. 64B is a cross-sectional view showing an example of the configuration of a display device. FIG. 65A is a plan view showing an example of the configuration of a display device. FIG. 65B is a cross-sectional view showing an example of the configuration of a display device. FIG. 66 is a plan view showing an example of the configuration of a display device. FIGS. 67A to 67C are plan views showing an example of the configuration of a display device. FIGS. 68A and 68B are plan views showing an example of the configuration of a display device. FIG. 69A is a plan view showing an example of the configuration of a display device. FIG. 69B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 70A1 and 70A2 are plan views showing an example of the configuration of a display device. FIG. 70B is a cross-sectional view showing an example of the configuration of a display device. FIG. 71A is a plan view showing an example of the configuration of a display device. Fig. 71B is a cross-sectional view showing an example of the configuration of a display device. Fig. 72A is a plan view showing an example of the configuration of a display device. Fig. 72B is a cross-sectional view showing an example of the configuration of a display device. Fig. 73A is a plan view showing an example of the configuration of a display device.FIG. 73B is a cross-sectional view showing a structural example of a display device. FIGS. 74A to 74C are plan views showing a structural example of a display device. FIGS. 75A to 75C are plan views showing a structural example of a display device. FIGS. 76A and 76B are plan views showing a structural example of a display device. FIG. 77A is a plan view showing a structural example of a display device. FIG. 77B is a cross-sectional view showing a structural example of a display device. FIGS. 78A1 and 78B1 are plan views showing an example of a method for manufacturing a display device. FIGS. 78A2 and 78B2 are cross-sectional views showing an example of a method for manufacturing a display device. FIGS. 79A1 and 79B1 are plan views showing an example of a method for manufacturing a display device. FIGS. 79A2 and 79B2 are cross-sectional views showing an example of a method for manufacturing a display device. FIGS. 80A1 and 80B1 are plan views showing an example of a method for manufacturing a display device. FIGS. 80A2 and 80B2 are cross-sectional views showing an example of a method for manufacturing a display device. FIGS. 81A1 and 81B1 are plan views illustrating an example of a method for manufacturing a display device. FIGS. 81A2 and 81B2 are cross-sectional views illustrating an example of a method for manufacturing a display device. FIGS. 82A1 and 82B1 are plan views illustrating an example of a method for manufacturing a display device. FIGS. 82A2 and 82B2 are cross-sectional views illustrating an example of a method for manufacturing a display device. FIGS. 83A to 83G are plan views illustrating an example of a pixel configuration. FIGS. 84A to 84K are plan views illustrating an example of a pixel configuration. FIG. 85 is a perspective view illustrating an example of a display device. FIG. 86 is a cross-sectional view illustrating an example of a display device. FIG. 87 is a cross-sectional view illustrating an example of a display device. FIG. 88 is a cross-sectional view illustrating an example of a display device. FIG. 89 is a cross-sectional view illustrating an example of a display device. FIG. 90 is a cross-sectional view illustrating an example of a display device. FIG. 91 is a cross-sectional view illustrating an example of a display device. FIGS. 92A to 92D are diagrams illustrating examples of electronic devices. FIGS. 93A to 93F are diagrams illustrating examples of electronic devices. 94A to 94G are diagrams showing an example of an electronic device.

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations are omitted. Also, when similar functions are indicated, the same hatching pattern may be used and no particular reference numeral may be used. Furthermore, multiple layers that can be formed in the same process may be denoted by the same hatching pattern.

[0026] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0027] It should be noted that the terms "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0028] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0029] In this specification and the like, a structure in which at least light-emitting layers are separately formed for light-emitting elements with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and facilitating improvements in brightness and reliability.

[0030] In this specification and the like, a light-emitting element (also referred to as a light-emitting device) has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). Note that the carrier injection layer, the carrier transport layer, and the carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes, characteristics, etc. Furthermore, one layer may have two or three functions of the carrier injection layer, the carrier transport layer, and the carrier block layer.

[0031] In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes.

[0032] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also referred to as the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0033] In this specification, when the side surface of a layer has a tapered shape, the outermost part of the side surface of the layer is referred to as the edge of the layer unless otherwise specified. For example, when the bottom surface edge of a layer is located outward from the top surface edge, the bottom surface edge of the layer is simply referred to as the edge unless otherwise specified.

[0034] Furthermore, in this specification, terms indicating positions such as "upper," "lower," "left," and "right" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0035] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0036] Embodiment 1 In this embodiment, a display device of one embodiment of the present invention, a manufacturing method thereof, and the like will be described with reference to drawings.

[0037] One embodiment of the present invention relates to a display device including a display portion, a scan line driver circuit, a signal line driver circuit, and a power supply circuit, and in which pixels are arranged in a matrix in the display portion. Each pixel includes a first transistor and a second transistor in addition to a display element (also referred to as a display device). The first transistor can be a transistor in which a first semiconductor layer is provided inside an opening formed in an interlayer insulating layer over a substrate, and the second transistor can be a transistor in which a second semiconductor layer is provided inside an opening formed in the interlayer insulating layer over the substrate, different from the opening. With this configuration, the channel length of the transistor can be aligned along a side surface of the interlayer insulating layer in the opening. Therefore, the channel length is not affected by the performance of an exposure device used to fabricate the transistor, and the channel length can be made shorter than the limiting resolution of the exposure device.

[0038] Here, a first conductive layer provided under the opening is used as one of the source electrode or drain electrode of the first transistor. Specifically, an interlayer insulating layer is provided on the first conductive layer, and an opening is provided in the interlayer insulating layer so as to reach the first conductive layer. Then, a first semiconductor layer is provided so as to have a region in contact with the first conductive layer inside the opening. Furthermore, a second conductive layer surrounding the periphery of the opening in a plan view is used as the other of the source electrode or drain electrode of the first transistor. Then, a gate insulating layer is provided on the first semiconductor layer and the second conductive layer, and a third conductive layer functioning as the gate electrode of the first transistor is provided on the gate insulating layer.

[0039] In this specification and the like, a plan view may be referred to as a top view in some cases, and a plan view may be referred to as a top view in some cases.

[0040] The second transistor can have a structure similar to that of the first transistor. A fourth conductive layer provided under the opening is used as one of the source electrode and the drain electrode of the second transistor. A fifth conductive layer surrounding the periphery of the opening in a plan view is used as the other of the source electrode and the drain electrode of the second transistor. The gate insulating layer is also provided on the second semiconductor layer and the fifth conductive layer, and a sixth conductive layer functioning as the gate electrode of the second transistor is provided on the gate insulating layer.

[0041] The first conductive layer or the second conductive layer is electrically connected to a signal line driving circuit. The third conductive layer has a region extending in the row direction and is electrically connected to a scanning line driving circuit. The fourth conductive layer has a region extending in the column direction and is electrically connected to a power supply circuit. Since the third conductive layer has a region extending in the row direction and the fourth conductive layer has a region extending in the column direction, the third conductive layer and the fourth conductive layer have an overlapping region.

[0042] In a display device according to one embodiment of the present invention, in a region where the third conductive layer and the fourth conductive layer overlap, an interlayer insulating layer is provided on the fourth conductive layer, the gate insulating layer is provided on the interlayer insulating layer, and the third conductive layer is provided thereon. This reduces the parasitic capacitance formed by the third conductive layer and the fourth conductive layer compared to when, for example, the insulating layer provided between the third conductive layer and the fourth conductive layer is only a gate insulating layer. This reduces the time required for the signal to be supplied to a pixel after the scanning line driver circuit outputs the signal to the third conductive layer. Therefore, the display device can be driven at high speed.

[0043] 1A is a block diagram illustrating a structural example of a display device 10, which is a display device of one embodiment of the present invention. The display device 10 includes a display portion 20, a scanning line driver circuit 11, a signal line driver circuit 13, and a power supply circuit 15. The display portion 20 includes a plurality of pixels 21 arranged in a matrix.

[0044] The scanning line driving circuit 11 is electrically connected to the pixels 21 via wiring 41. The wiring 41 extends, for example, in the row direction of the matrix.

[0045] The signal line driving circuit 13 is electrically connected to the pixels 21 via wiring 43. The wiring 43 extends, for example, in the column direction of the matrix.

[0046] The power supply circuit 15 is electrically connected to the pixels 21 via wiring 45. For example, all of the pixels 21 can be electrically connected to the power supply circuit 15 via the same wiring 45.

[0047] The pixel 21 has a display element, and can display an image on the display unit 20 by using the display element. As the display element, for example, a light-emitting element, specifically an organic EL element, can be used. Alternatively, a liquid crystal element (also called a liquid crystal device) can be used as the display element.

[0048] The scanning line driver circuit 11 has a function of selecting, for example, the pixels 21 to which image data is to be written, row by row. Specifically, the scanning line driver circuit 11 can select the pixels 21 to which image data is to be written by outputting a signal to a wiring 41. Here, the scanning line driver circuit 11 can select all the pixels 21 by outputting the signal to the wiring 41 in the first row, for example, and then to the wiring 41 in the second row, and so on, in order up to the wiring 41 in the final row. Therefore, the signal that the scanning line driver circuit 11 outputs to the wiring 41 is a scanning signal, and the wiring 41 can be called a scanning line.

[0049] The signal line driver circuit 13 has a function of generating image data. The image data is supplied to the pixels 21 via wirings 43. For example, the image data can be written to all the pixels 21 included in the row selected by the scanning line driver circuit 11. Here, the image data can be expressed as a signal (image signal). Therefore, the wirings 43 can be called signal lines.

[0050] The power supply circuit 15 has a function of generating a power supply potential and supplying it to the wiring 45. The power supply circuit 15 has a function of generating, for example, a high power supply potential (hereinafter simply referred to as "high potential" or "VDD") and supplying it to the wiring 45. The power supply circuit 15 may also have a function of generating a low power supply potential (hereinafter simply referred to as "low potential" or "VSS"). Because a power supply potential is supplied to the wiring 45, the wiring 45 can be referred to as a power supply line.

[0051] FIG. 1B is a plan view showing an example of the configuration of a pixel 21. The pixel 21 has a plurality of sub-pixels 23. FIG. 1B illustrates an example in which the pixel 21 has sub-pixels 23R, 23G, and 23B. Here, when the pixel 21 has a light-emitting element as a display element, for example, the planar shape of the sub-pixels shown in FIG. 1B corresponds to the planar shape of the light-emitting region of the light-emitting element. Note that FIG. 1B illustrates the sub-pixels 23R, 23G, and 23B as having the same or approximately the same aperture ratio (which can also be referred to as the size or the size of the light-emitting region), but this is not a limitation of one embodiment of the present invention. The aperture ratios of the sub-pixels 23R, 23G, and 23B can be determined as appropriate. The aperture ratios of the sub-pixels 23R, 23G, and 23B may be different from one another, or two or more of them may be the same or approximately the same.

[0052] In this specification and the like, when describing matters common to, for example, the subpixels 23R, 23G, and 23B, the alphabets that distinguish them may be omitted and they may be referred to as subpixels 23. When describing matters common to other elements that are distinguished by alphabets, they may also be described using symbols without the alphabets.

[0053] 1B, a stripe arrangement is applied as an arrangement method of the sub-pixels 23. Note that an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, a Pentile arrangement, or the like may also be applied as an arrangement method of the sub-pixels 23. For an example of the planar shape of the sub-pixels, the arrangement of the sub-pixels, and the like, refer to the second embodiment.

[0054] The sub-pixels 23R, 23G, and 23B each emit light of a different color. Examples of the sub-pixels 23R, 23G, and 23B include sub-pixels of three colors: red (R), green (G), and blue (B), and sub-pixels of three colors: yellow (Y), cyan (C), and magenta (M). The pixel 21 may also be provided with four or more sub-pixels 23. For example, the pixel 21 may be provided with sub-pixels of four colors: R, G, B, and white (W). As described above, the display device 10 can display a full-color image on the display unit 20 by having the pixel 21 include a plurality of sub-pixels 23 that emit light of different colors. The pixel 21 may also be provided with sub-pixels of R, G, B, and infrared (IR) light.

[0055] The display unit 20 may be provided with a sensor, for example, a sensor may be provided in the pixel 21. For example, the display unit 20 may have a function as a fingerprint sensor. For example, the display unit 20 may have a function as an optical or ultrasonic fingerprint sensor.

[0056] 1C is a circuit diagram showing an example of the configuration of the sub-pixel 23. The sub-pixel 23 shown in FIG.

[0057] The pixel circuit 40A includes a transistor 51, a transistor 52, and a capacitor 57. In other words, the pixel circuit 40A is a 2Tr1C type pixel circuit.

[0058] In the pixel circuit 40A, one of the source and the drain of the transistor 51 is electrically connected to the wiring 43. The other of the source and the drain of the transistor 51 is electrically connected to the gate of the transistor 52. The gate of the transistor 52 is electrically connected to one electrode of the capacitor 57. The gate of the transistor 51 is electrically connected to the wiring 41.

[0059] One of the source and drain of the transistor 52 is electrically connected to the wiring 45. The other of the source and drain of the transistor 52 is electrically connected to the other electrode of the capacitor 57. The other electrode of the capacitor 57 is electrically connected to one electrode of the light-emitting element 60. The other electrode of the light-emitting element 60 is electrically connected to the wiring 47. Here, the one electrode of the light-emitting element 60 is also referred to as a pixel electrode. Furthermore, since the wiring 47 can be shared by all the sub-pixels 23, for example, the other electrode of the light-emitting element 60 can also be referred to as a common electrode.

[0060] As described above, the wiring 41 functions as a scanning line, the wiring 43 functions as a signal line, and the wiring 45 functions as a power supply line. The wiring 47 also functions as a power supply line, and when a high power supply potential is supplied to the wiring 45, a low power supply potential is supplied to the wiring 47. The wiring 47 can be electrically connected to the power supply circuit 15, for example.

[0061] The transistor 51 functions as a switch and is also referred to as a selection transistor. The transistor 51 controls conduction and non-conduction between the wiring 43 and the gate of the transistor 52 based on the potential of the wiring 41. Image data is written to the pixel circuit 40A by turning on the transistor 51, and the written image data is held by turning off the transistor 51.

[0062] The transistor 52 has a function of controlling the amount of current flowing to the light-emitting element 60 and is also referred to as a driving transistor. The capacitor 57 has a function of holding a gate potential of the transistor 52. The light emission luminance of the light-emitting element 60 is controlled in accordance with a potential corresponding to image data that is supplied to the gate of the transistor 52. Specifically, when a high power supply potential is supplied to the wiring 45 and a low power supply potential is supplied to the wiring 47, the amount of current flowing from the wiring 45 to the wiring 47 is controlled in accordance with the gate potential of the transistor 52, thereby controlling the light emission luminance of the light-emitting element 60.

[0063] OS transistors are preferably used as the transistors 51 and 52. OS transistors have higher field-effect mobility than, for example, transistors using amorphous silicon. Therefore, by using OS transistors as the transistors 51 and 52, the display device 10 can be driven at high speed.

[0064] Furthermore, an OS transistor has an extremely small source-drain leakage current (also referred to as off-state current) in an off state. Therefore, by using an OS transistor as the transistor 51, charge stored in the capacitor 57 can be held for a long period of time. This allows image data written to the subpixel 23 to be held for a long period of time, thereby reducing the frequency of refresh operations (rewriting image data to the subpixel 23). As a result, the power consumption of the display device 10 can be reduced.

[0065] Here, to increase the emission luminance of the light-emitting element 60, it is necessary to increase the amount of current flowing through the light-emitting element 60. To achieve this, it is necessary to increase the source-drain voltage of the transistor 52, which is a driving transistor. Because an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (also referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the transistor 52, it is possible to increase the amount of current flowing through the light-emitting element 60 and increase the emission luminance of the light-emitting element 60.

[0066] When the transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as the transistor 52, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage. This allows for precise control of the amount of current flowing through the light-emitting element 60. This allows for precise control of the luminance of light emitted by the subpixel 23. This increases the number of gray levels that can be expressed by the subpixel 23.

[0067] In terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as the transistor 52, a stable current can be passed through the light-emitting element 60, even when the current-voltage characteristics of each light-emitting element 60 vary from one light-emitting element 60 to another. In other words, when an OS transistor operates in a saturation region, the source-drain current hardly changes even when the source-drain voltage increases, and thus the light-emitting luminance of the light-emitting element 60 can be stabilized.

[0068] As described above, by using an OS transistor for the transistor 52, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," and "suppression of variation in light emission luminance of each light-emitting element 60," etc.

[0069] 1C, the transistors 51 and 52 are n-channel transistors, but one or both of the transistors 51 and 52 may be p-channel transistors. The same applies to other transistors described in this specification.

[0070] It is preferable to use, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) as the light-emitting element 60. Examples of the light-emitting material contained in the light-emitting element 60 include a fluorescent material (fluorescent material), a phosphorescent material (phosphorescent material), a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material), and an inorganic compound (e.g., a quantum dot material). Furthermore, an LED such as a micro LED (light-emitting diode) can also be used as the light-emitting element 60.

[0071] 1D is a circuit diagram showing an example of the configuration of the sub-pixel 23. The sub-pixel 23 shown in FIG.

[0072] The pixel circuit 40B includes a transistor 51 and a capacitor 57. That is, the pixel circuit 40B is a 1Tr1C type pixel circuit.

[0073] In the pixel circuit 40B, one of the source and drain of the transistor 51 is electrically connected to a wiring 43. The other of the source and drain of the transistor 51 is electrically connected to one electrode of a capacitor 57. One electrode of the capacitor 57 is electrically connected to one electrode of a liquid crystal element 69. The gate of the transistor 51 is electrically connected to a wiring 41. The other electrode of the capacitor 57 and the other electrode of the liquid crystal element 69 are electrically connected to a wiring 45. Here, the one electrode of the liquid crystal element 69 is also referred to as a pixel electrode. The other electrode of the liquid crystal element 69 may also be referred to as a common electrode. In the pixel circuit 40B, a ground potential, for example, can be supplied to the wiring 45.

[0074] In the pixel circuit 40B, the transistor 51 functions as a switch and controls electrical continuity or non-conduction between the wiring 43 and one electrode of the liquid crystal element 69 based on the potential of the wiring 41. When the transistor 51 is turned on, image data is written to the pixel circuit 40B, and when the transistor 51 is turned off, the written image data is held.

[0075] The capacitor 57 has a function of holding the potential of one electrode of the liquid crystal element 69. The alignment state of the liquid crystal element 69 is controlled in accordance with the potential that is supplied to one electrode of the liquid crystal element 69 and corresponds to image data.

[0076] The modes of the liquid crystal element 69 include, for example, TN (Twisted Nematic) mode, STN (Super-Twisted Nematic) mode, VA (Vertical Alignment) mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Opticaly Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, MVA (Multidomain Vertical Alignment) mode, and PVA (Patterned Vertical Alignment mode, In Plane Switching (IPS) mode, Fringe Field Switching (FFS) mode, or Transverse Bend Alignment (TBA) mode may be used. Other examples include Electrically Controlled Birefringence (ECB) mode, Polymer Dispersed Liquid Crystal (PDLC) mode, Polymer Network Liquid Crystal (PNLC) mode, and Guest-Host mode. However, the present invention is not limited to these, and various other modes may be used.

[0077] Fig. 2A is a block diagram showing an example of the configuration of the display device 10, which is a modified example of the display device 10 shown in Fig. 1A. The display device 10 shown in Fig. 2A differs from the display device 10 shown in Fig. 1A in that the display device 10 includes wiring 41a and wiring 41b as wiring 41 and in that a reference potential generating circuit 17 is provided.

[0078] The reference potential generating circuit 17 is electrically connected to the pixels 21 via the wiring 48. For example, all of the pixels 21 can be electrically connected to the reference potential generating circuit 17 via the same wiring 48. The reference potential generating circuit 17 has a function of generating a reference potential to correct variations in the gate-source potential of each transistor 52, for example, and supplying the reference potential to the wiring 48. Since the potential of the wiring 48 serves as the reference potential, the wiring 48 can be referred to as a reference potential line. The reference potential generating circuit 17 may also be referred to as a power supply circuit. Furthermore, the power supply circuit 15 and the reference potential generating circuit 17 may be integrated into a single circuit. For example, the reference potential generating circuit 17 may be included in the power supply circuit 15.

[0079] Fig. 2B is a circuit diagram showing an example configuration of the sub-pixel 23 included in the pixel 21 shown in Fig. 2A. The sub-pixel 23 shown in Fig. 2B includes a pixel circuit 40C and a light-emitting element 60. The pixel circuit 40C has a configuration in which a transistor 53 is added to the pixel circuit 40A. The pixel circuit 40C is a 3Tr1C type pixel circuit.

[0080] In the pixel circuit 40C, the gate of the transistor 51 is electrically connected to a wiring 41a. One of the source and the drain of the transistor 53 is electrically connected to the other of the source and the drain of the transistor 52, the other electrode of the capacitor 57, and one electrode of the light-emitting element 60. The other of the source and the drain of the transistor 53 is electrically connected to a wiring 48. The gate of the transistor 53 is electrically connected to a wiring 41b.

[0081] The transistor 53 functions as a switch and controls, based on the potential of the wiring 41 b, whether the wiring 48 is electrically connected or disconnected from one electrode of the light-emitting element 60. For example, a reference potential is supplied to the wiring 48. The reference potential of the wiring 48 supplied via the transistor 53 can suppress variations in the gate-source potential of each transistor 52.

[0082] Furthermore, a current value that can be used to set pixel parameters can be obtained based on the current value of the wiring 48. More specifically, the wiring 48 can function as a monitor line for outputting the current flowing through the transistor 52 or the current flowing through the light-emitting element 60 to the outside of the pixel 21. The current output to the wiring 48 can be converted into a potential by, for example, a source follower circuit, or into a digital signal by, for example, an A-D converter. Note that when the wiring 48 functions as a monitor line, the display device 10 does not need to include the reference potential generating circuit 17. Furthermore, when the wiring 48 functions as a monitor line, the pixels 21 can be electrically connected to different wirings 48 for each column.

[0083] An OS transistor is preferably used as the transistor 53. As described above, an OS transistor has higher field-effect mobility than, for example, a transistor using amorphous silicon. Therefore, by using an OS transistor as the transistor 53, the display device 10 can be driven at high speed.

[0084] 3A, 3B, and 3C are circuit diagrams showing examples of the configuration of the sub-pixel 23 included in the pixel 21 shown in Fig. 2A. The sub-pixel 23 shown in Fig. 3A includes a pixel circuit 40D and a light-emitting element 60. The pixel circuit 40D has a configuration in which a transistor 54 and a capacitor 58 are added to the pixel circuit 40C. The pixel circuit 40D is a 4Tr2C type pixel circuit.

[0085] In the pixel circuit 40D, one of the source and the drain of the transistor 52 is electrically connected to one of the source and the drain of the transistor 54. The other of the source and the drain of the transistor 54 is electrically connected to a wiring 45. The gate of the transistor 54 is electrically connected to a wiring 41c. One electrode of the capacitor 58 is electrically connected to the other of the source and the drain of the transistor 52, one of the source and the drain of the transistor 53, the other electrode of the capacitor 57, and one electrode of the light-emitting element 60.

[0086] The wiring 41c is electrically connected to the scanning line driving circuit 11. In other words, when the sub-pixel 23 of the pixel 21 has the configuration shown in FIG. 3A , the wiring 41 includes wirings 41a, 41b, and 41c provided in the display device 10.

[0087] The transistor 54 functions as a switch and controls conduction and non-conduction between the wiring 45 and one of the source and the drain of the transistor 52 based on the potential of the wiring 41c.

[0088] By turning on the transistor 54, a current having a magnitude corresponding to the gate potential of the transistor 52 flows, for example, from the wiring 45 to the wiring 47. This causes the light-emitting element 60 to emit light with a luminance corresponding to the gate potential of the transistor 52. On the other hand, by turning off the transistor 54, no current flows through the light-emitting element 60, and therefore the light-emitting element 60 does not emit light.

[0089] An OS transistor is preferably used as the transistor 54. As described above, an OS transistor has higher field-effect mobility than, for example, a transistor using amorphous silicon. Therefore, by using an OS transistor as the transistor 54, the display device 10 can be driven at high speed.

[0090] 3B includes a pixel circuit 40E and a light-emitting element 60. The pixel circuit 40E has a configuration in which a transistor 54 is added to the pixel circuit 40C. The pixel circuit 40E is a 4Tr1C type pixel circuit.

[0091] In the pixel circuit 40E, one of the source and the drain of the transistor 54 is electrically connected to the other of the source and the drain of the transistor 51, the gate of the transistor 52, and one electrode of the capacitor 57. The other of the source and the drain of the transistor 54 is electrically connected to a wiring 49. The gate of the transistor 54 is electrically connected to a wiring 41c. When the subpixel 23 has the structure shown in FIG. 3B , wirings 41a, 41b, and 41c are provided as the wiring 41 in the display device 10.

[0092] By turning on the transistor 54, the gate potential of the transistor 52 can be set to the potential of the wiring 49. Here, for example, a low potential can be supplied to the wiring 49. As a result, for example, no current flows through the light-emitting element 60, and the light-emitting element 60 does not emit light.

[0093] The sub-pixel 23 shown in FIG. 3C includes a pixel circuit 40F and a light-emitting element 60.

[0094] The pixel circuit 40F includes a transistor 61, a transistor 62, a transistor 63, a transistor 64, a transistor 65, a transistor 66, a capacitor 67, and a capacitor 68. That is, the pixel circuit 40F is a 6Tr2C type pixel circuit.

[0095] In the pixel circuit 40F, one of the source and the drain of the transistor 61 is electrically connected to a wiring 45. The other of the source and the drain of the transistor 61 is electrically connected to one of the source and the drain of the transistor 62. The one of the source and the drain of the transistor 62 is electrically connected to one of the source and the drain of the transistor 63. The gate of the transistor 61 is electrically connected to a wiring 41d.

[0096] The other of the source and the drain of the transistor 62 is electrically connected to the gate of the transistor 63. The gate of the transistor 63 is electrically connected to one electrode of the capacitor 67. The gate of the transistor 62 is electrically connected to the wiring 41e.

[0097] One of the source and the drain of the transistor 64 is electrically connected to the wiring 43. The other of the source and the drain of the transistor 64 is electrically connected to the other of the source and the drain of the transistor 63. The other of the source and the drain of the transistor 63 is electrically connected to the one of the source and the drain of the transistor 65. The gate of the transistor 64 is electrically connected to the wiring 41f.

[0098] The other of the source and the drain of the transistor 65 is electrically connected to one of the source and the drain of the transistor 66. The other of the source and the drain of the transistor 66 is electrically connected to the other electrode of the capacitor 67. The other electrode of the capacitor 67 is electrically connected to one electrode of the capacitor 68. One electrode of the capacitor 68 is electrically connected to one electrode of the light-emitting element 60. The gate of the transistor 65 is electrically connected to a wiring 41g.

[0099] The other of the source and the drain of the transistor 66 is electrically connected to the wiring 48. The gate of the transistor 66 is electrically connected to the wiring 41e.

[0100] The other electrode of the capacitor 68 is electrically connected to the wiring 41 f. The other electrode of the light emitting element 60 is electrically connected to the wiring 47 .

[0101] The wiring 41d, the wiring 41e, the wiring 41f, and the wiring 41g are electrically connected to the scanning line driving circuit 11. That is, when the subpixel 23 of the pixel 21 has the configuration shown in FIG. 3C , the wiring 41d, the wiring 41e, the wiring 41f, and the wiring 41g are provided in the display device 10 as the wiring 41.

[0102] The transistors 61, 62, 64, 65, and 66 function as switches. The transistor 61 controls conduction and non-conduction between the wiring 45 and one of the source or drain of the transistor 62 and one of the source or drain of the transistor 63, based on the potential of the wiring 41d. The transistor 62 controls conduction and non-conduction between the other of the source or drain of the transistor 61, one of the source or drain of the transistor 63, the gate of the transistor 63, and one electrode of the capacitor 67, based on the potential of the wiring 41e. The transistor 64 controls conduction and non-conduction between the wiring 43, the other of the source or drain of the transistor 63, and one of the source or drain of the transistor 65, based on the potential of the wiring 41f. The transistor 65 has a function of controlling, based on the potential of the wiring 41g, electrical continuity and non-conduction between the other of the source or the drain of the transistor 63 and the other of the source or the drain of the transistor 64 and one electrode of the light-emitting element 60. The transistor 66 has a function of controlling, based on the potential of the wiring 41e, electrical continuity and non-conduction between the wiring 48 and one electrode of the light-emitting element 60.

[0103] OS transistors are preferably used as the transistors 61 to 66. OS transistors have higher field-effect mobility than, for example, transistors using amorphous silicon. Therefore, by using OS transistors as the transistors 61 to 66, the display device 10 can be driven at high speed.

[0104] <Configuration Example 1 of Semiconductor Device> Figure 4A1 is a plan view illustrating a configuration example of a semiconductor device included in a display device of one embodiment of the present invention, specifically, a plan view illustrating a configuration example of a transistor 50, which is a transistor included in the display device of one embodiment of the present invention, and its surroundings. Figure 4B is a cross-sectional view along dashed dotted line A1-A2 in Figure 4A1. Note that some components of the transistor 50, such as an insulating layer, are omitted in Figure 4A1. In the plan views of the transistor, some components, such as an insulating layer, are also omitted in the subsequent drawings.

[0105] The transistor 50 can be applied to, for example, a transistor included in the pixel 21. For example, the transistor 50 can be applied to transistors 51 to 54 and transistors 61 to 66. The transistor 50 may also be applied to at least some of the transistors included in the scan line driver circuit 11, the signal line driver circuit 13, the power supply circuit 15, and the reference potential generation circuit 17.

[0106] The transistor 50 is provided over a substrate 101. The transistor 50 includes a conductive layer 111, a conductive layer 112, a semiconductor layer 113, an insulating layer 105, and a conductive layer 115. In FIG. 4A1, the conductive layer 112 extends in a direction parallel to the conductive layer 111 and in a direction perpendicular to the conductive layer 115.

[0107] 4A1 and 4B, as shown on the coordinate axes, the direction in which the conductive layer 112 extends is the X direction. The direction perpendicular to the X direction and parallel to, for example, the upper surface of the substrate 101 is the Y direction, and the direction perpendicular to the upper surface of the substrate 101 is the Z direction. The definitions of the X direction, Y direction, and Z direction may be the same or different in the subsequent drawings. The X direction, Y direction, and Z direction may be perpendicular to each other.

[0108] The conductive layer 111 functions as one of a source electrode and a drain electrode of the transistor 50. The conductive layer 112 functions as the other of the source electrode and the drain electrode of the transistor 50. The insulating layer 105 functions as a gate insulating layer of the transistor 50. The conductive layer 115 functions as a gate electrode of the transistor 50.

[0109] In the semiconductor layer 113, an entire region that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. In addition, in the semiconductor layer 113, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0110] A conductive layer 111 is provided over a substrate 101, an insulating layer 103 is provided over the substrate 101 and the conductive layer 111, and a conductive layer 112 is provided over the insulating layer 103. The insulating layer 103 can function as an interlayer insulating layer. The conductive layers 111 and 112 overlap each other through the insulating layer 103. The thickness of the insulating layer 103, which functions as an interlayer insulating layer, can be thicker than the thickness of the insulating layer 105, which functions as a gate insulating layer of the transistor 50.

[0111] The insulating layer 103 has an opening 121 that reaches the conductive layer 111. The conductive layer 112 has an opening 123 that reaches the opening 121. In other words, the opening 123 has a region that overlaps with the opening 121.

[0112] 4A1 shows conductive layers 111, 112, semiconductor layers 113, conductive layers 115, openings 121, and 123 as components of the transistor 50. Here, FIG. 4A2 shows a configuration example in which the conductive layer 115 is omitted from the components shown in FIG. 4A1. That is, FIG. 4A2 shows the conductive layers 111, 112, semiconductor layers 113, openings 121, and 123. Furthermore, FIG. 4A3 shows a configuration example in which the semiconductor layer 113 is further omitted from the components shown in FIG. 4A2. That is, FIG. 4A3 shows the conductive layers 111, 112, openings 121, and 123.

[0113] 4A3 and 4B , the conductive layer 112 has an opening 123 in a region overlapping with the conductive layer 111. As shown in Fig. 4A3 , the conductive layer 112 can be configured to cover the entire outer periphery of the opening 121 in a plan view. Here, it is preferable that the conductive layer 112 is not provided inside the opening 121. In other words, it is preferable that the conductive layer 112 not contact the side surface of the insulating layer 103 on the opening 121 side.

[0114] 4A1, 4A2, and 4A3 show an example in which the shapes of the openings 121 and 123 are each circular in a plan view. By making the planar shapes of the openings 121 and 123 circular, the processing accuracy when forming the openings 121 and 123 can be improved, and the openings 121 and 123 can be formed with a fine size. Note that in this specification, a circle is not limited to a perfect circle. Furthermore, the planar shapes of the openings 121 and 123 may be, for example, elliptical.

[0115] 4B shows an example in which the end of the conductive layer 112 on the opening 123 side coincides with or roughly coincides with the end of the insulating layer 103 on the opening 121 side. It can also be said that the planar shape of the opening 123 coincides with or roughly coincides with the planar shape of the opening 121. Note that in this specification, the end of the conductive layer 112 on the opening 123 side and the end of the opening 123 refer to the lower surface end of the conductive layer 112 on the opening 123 side. The lower surface of the conductive layer 112 refers to the surface on the insulating layer 103 side. The end of the insulating layer 103 on the opening 121 side and the end of the opening 121 refer to the upper surface end of the insulating layer 103 on the opening 121 side. The upper surface of the insulating layer 103 refers to the surface on the conductive layer 112 side. Furthermore, the planar shape of the opening 123 refers to the planar shape of the lower surface end of the conductive layer 112 on the opening 123 side. The planar shape of the opening 121 refers to the planar shape of the upper surface edge of the insulating layer 103 on the opening 121 side.

[0116] Incidentally, "the edges coincide or approximately coincide" can also be said to mean that the edges are aligned or approximately aligned. When the edges are aligned or approximately aligned, and when the planar shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, it is also said that the edges are approximately aligned or the planar shapes are approximately aligned.

[0117] The opening 121 can be formed, for example, using the resist mask used to form the opening 123. Specifically, after the conductive layer 111 is first formed over the substrate 101, the insulating layer 103, a conductive film to be the conductive layer 112 over the insulating layer 103, and a resist mask over the conductive film are formed over the substrate 101 and the conductive layer 111. Then, the opening 123 is formed in the conductive film using the resist mask, and then the opening 121 is formed in the insulating layer 103 using the resist mask. This allows the edge of the opening 121 to coincide or approximately coincide with the edge of the opening 123. This structure can simplify the process.

[0118] The semiconductor layer 113 is provided to cover the openings 121 and 123 and to have regions located inside the openings 121 and 123. The semiconductor layer 113 has a shape that follows the top surface and side surfaces of the conductive layer 112, the side surfaces of the insulating layer 103, and the top surface of the conductive layer 111. The semiconductor layer 113 has regions that are in contact with, for example, the top surface and side surfaces of the conductive layer 112, the side surfaces of the insulating layer 103, and the top surface of the conductive layer 111.

[0119] The semiconductor layer 113 preferably covers the end of the conductive layer 112 on the opening 123 side. For example, FIG. 4B shows a structure in which the end of the semiconductor layer 113 is located on the conductive layer 112. It can also be said that the end of the semiconductor layer 113 is in contact with the top surface of the conductive layer 112.

[0120] 4B shows the semiconductor layer 113 having a single-layer structure, one embodiment of the present invention is not limited thereto, and the semiconductor layer 113 may have a stacked structure of two or more layers.

[0121] The insulating layer 105, which functions as a gate insulating layer of the transistor 50, is provided to cover the openings 121 and 123 and to have regions located inside the openings 121 and 123. The insulating layer 105 is provided over the semiconductor layer 113, the conductive layer 112, and the insulating layer 103. The insulating layer 105 can have regions in contact with the top surface and side surfaces of the semiconductor layer 113, the top surface and side surfaces of the conductive layer 112, and the top surface of the insulating layer 103. The insulating layer 105 has a shape that follows the top surface of the insulating layer 103, the top surface and side surfaces of the conductive layer 112, and the top surface and side surfaces of the semiconductor layer 113.

[0122] The conductive layer 115 functioning as the gate electrode of the transistor 50 is provided over the insulating layer 105 and can have a region in contact with the top surface of the insulating layer 105. The conductive layer 115 has a region overlapping with the semiconductor layer 113 with the insulating layer 105 interposed therebetween.

[0123] For example, as shown in FIG. 4B , the conductive layer 115 is provided so as to have a region located inside the opening 121 and a region located inside the opening 123, and to have a region facing the semiconductor layer 113 with the insulating layer 105 sandwiched therebetween. In the example shown in FIG. 4B , the conductive layer 115 has regions overlapping with the conductive layer 111 and the conductive layer 112 via the insulating layer 105 and the semiconductor layer 113. The conductive layer 115 also covers the entire semiconductor layer 113. With this configuration, a gate electric field can be applied to the entire semiconductor layer 113, thereby improving the electrical characteristics of the transistor 50 and increasing, for example, the on-state current of the transistor. Furthermore, by providing the insulating layer 103 between the conductive layer 111 and the conductive layer 115 in addition to the insulating layer 105 functioning as a gate insulating layer, the parasitic capacitance formed by the conductive layer 111 and the conductive layer 115 is reduced compared to when, for example, the insulating layer 103 is the only insulating layer provided between the conductive layer 111 and the conductive layer 115.

[0124] The transistor 50 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 113. Furthermore, since the bottom surface of the semiconductor layer 113 has a region in contact with the source electrode and the drain electrode, the transistor 50 can be called a TGBC (Top Gate Bottom Contact) transistor.

[0125] The channel length and channel width of the transistor 50 will now be described with reference to FIGS. 5A and 5B. FIG. 5A is an enlarged plan view showing an example of the configuration of the transistor 50 and its surroundings shown in FIG. 4A1. FIG. 5B is a cross-sectional view taken along dashed line A1-A2 shown in FIG. 5A.

[0126] In the semiconductor layer 113, a region in contact with the conductive layer 111 functions as one of a source region and a drain region, a region in contact with the conductive layer 112 functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0127] The channel length of the transistor 50 is the distance between the source region and the drain region. In Figure 5B, the channel length L50 of the transistor 50 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L50 is the distance between the edge of the region where the semiconductor layer 113 and the conductive layer 111 contact each other and the edge of the region where the semiconductor layer 113 and the conductive layer 112 contact each other.

[0128] Here, the channel length L50 of the transistor 50 corresponds to the length of the side surface of the insulating layer 103 on the opening 121 side when viewed from the XZ plane. In other words, the channel length L50 is determined by the film thickness T103 of the insulating layer 103 and the angle θ103 between the side surface of the insulating layer 103 on the opening 121 side and the surface on which the insulating layer 103 is to be formed (here, the upper surface of the conductive layer 111), and is not affected by the performance of the exposure device used to fabricate the transistor. Therefore, the channel length L50 can be made smaller than the limit resolution of the exposure device, and a transistor with a fine size can be realized. For example, the channel length L50 is preferably 0.01 μm or more and less than 3.0 μm, more preferably 0.05 μm or more and less than 3.0 μm, even more preferably 0.10 μm or more and less than 3.0 μm, even more preferably 0.15 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.0 μm, even more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, and even more preferably 0.50 μm or more and 1.0 μm or less. In FIG. 5B, the thickness T103 of the insulating layer 103 is indicated by a dashed line with a double-headed arrow.

[0129] The reduction in the channel length L50 can increase the on-state current of the transistor 50. Therefore, by using the transistor 50 as a transistor included in the display device 10, for example, as a transistor included in the pixel 21, the display device 10 can be driven at high speed.

[0130] By adjusting the thickness T103 and angle θ103 of the insulating layer 103, the channel length L50 can be controlled.

[0131] The film thickness T103 of the insulating layer 103 is preferably 0.01 μm or more and less than 3.0 μm, more preferably 0.05 μm or more and less than 3.0 μm, even more preferably 0.10 μm or more and less than 3.0 μm, even more preferably 0.15 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.0 μm, even more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.2 μm, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and less than 1.0 μm, even more preferably 0.50 μm or more and less than 1.0 μm.

[0132] The side surface of the insulating layer 103 on the opening 121 side is preferably tapered. The angle θ103 formed between the side surface of the insulating layer 103 on the opening 121 side and the surface on which the insulating layer 103 is to be formed (here, the top surface of the conductive layer 111) is preferably less than 90 degrees. By reducing the angle θ103, the coverage of a layer (e.g., the semiconductor layer 113) provided on the insulating layer 103 can be improved. However, reducing the angle θ103 reduces the contact area between the semiconductor layer 113 and the conductive layer 111, which may increase the contact resistance between the semiconductor layer 113 and the conductive layer 111. The angle θ103 is preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and less than 90 degrees, even more preferably 55 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 80 degrees, and even more preferably 70 degrees or more and less than 80 degrees. By setting the angle θ103 within the above range, the channel length of the transistor 50 can be shortened while improving the coverage of the conductive layer 111 and the layer (e.g., the semiconductor layer 113) formed on the insulating layer 103, and defects such as discontinuities or voids in the layer can be suppressed. Furthermore, the contact resistance between the semiconductor layer 113 and the conductive layer 111 can be reduced.

[0133] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0134] 5B shows a cross-sectional view in which the side surface of the insulating layer 103 on the opening 121 side has a straight line shape, but one embodiment of the present invention is not limited to this. In the cross-sectional view, the side surface of the insulating layer 103 on the opening 121 side may have a curved line shape, or the side surface may have both a straight line region and a curved line region.

[0135] The channel width of the transistor 50 is the width of the source region or the width of the drain region in a direction perpendicular to the channel length direction. That is, the channel width is the width of the region where the semiconductor layer 113 and the conductive layer 111 contact each other or the width of the region where the semiconductor layer 113 and the conductive layer 112 contact each other in a direction perpendicular to the channel length direction. Here, the channel width of the transistor 50 is described as the width of the region where the semiconductor layer 113 and the conductive layer 112 contact each other in a direction perpendicular to the channel length direction. In Figures 5A and 5B, the channel width W50 of the transistor 50 is indicated by a solid double-headed arrow. The channel width W50 is the length of the bottom end of the conductive layer 112 on the opening 123 side in a plan view.

[0136] The channel width W50 is determined by the planar shape of the opening 123. In Figures 5A and 5B, the width D123 of the opening 123 is indicated by a two-dot chain line with a double arrow. The width D123 indicates the short side of the smallest rectangle circumscribing the opening 123 in a planar view. When the opening 123 is formed using photolithography, the width D123 of the opening 123 is equal to or greater than the resolution limit of the exposure device. The width D123 is, for example, preferably 0.20 μm or more and less than 5.0 μm, more preferably 0.20 μm or more and less than 4.5 μm, even more preferably 0.20 μm or more and less than 4.0 μm, even more preferably 0.20 μm or more and less than 3.5 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.0 μm, even more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, and even more preferably 0.50 μm or more and 1.0 μm or less. When the planar shape of the opening 123 is circular, the width D123 corresponds to the diameter of the opening 123, and the channel width W50 can be made equal to the length of the periphery of the opening 123 in a planar view, and can be calculated as "D123 x π".

[0137] <Pixel Configuration Example 1> Fig. 6 is a plan view showing a configuration example of the pixel circuit 40A shown in Fig. 1C. Fig. 7 is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 6, showing a configuration example of the transistor 51 and the capacitor 57. Fig. 6 shows pixel circuits 40A arranged in two rows and two columns (pixel circuit 40A[i,j], pixel circuit 40A[i,j+1], pixel circuit 40A[i+1,j], and pixel circuit 40A[i+1,j+1]). Here, i and j are integers equal to or greater than 1. Note that other plan views showing configuration examples of pixel circuits also show pixel circuits arranged in two rows and two columns.

[0138] 6 and 7 , the structures of the transistors 51 and 52 are similar to the structure of the transistor 50 shown in FIGS. 4A1 and 4B . Here, the conductive layer 111, the conductive layer 112, the semiconductor layer 113, and the conductive layer 115 of the transistor 51 are referred to as the conductive layer 111a, the conductive layer 112a, the semiconductor layer 113a, and the conductive layer 115a, respectively. The conductive layer 111, the conductive layer 112, the semiconductor layer 113, and the conductive layer 115 of the transistor 52 are referred to as the conductive layer 111b, the conductive layer 112b, the semiconductor layer 113b, and the conductive layer 115b, respectively. Furthermore, the openings 121 and 123 provided in the transistor 51 are referred to as the openings 121a and 123a, respectively, and the openings 121 and 123 provided in the transistor 52 are referred to as the openings 121b and 123b, respectively.

[0139] The capacitor 57 includes a conductive layer 112b over the insulating layer 103, an insulating layer 105 over the conductive layer 112b, and a conductive layer 115b that is provided over the insulating layer 105 and has a region overlapping with the conductive layer 112b. That is, the other of the source electrode and drain electrode of the transistor 52 and the other electrode of the capacitor 57 can be formed using the same conductive layer. Furthermore, the gate electrode of the transistor 52 and one electrode of the capacitor 57 can be formed using the same conductive layer.

[0140] The insulating layer 105 has an opening 125 that reaches the conductive layer 112a, and the conductive layer 112a and the conductive layer 115b are electrically connected by the opening 125. Specifically, for example, inside the opening 125, the conductive layer 112a and the conductive layer 115b are in contact with each other.

[0141] In FIG. 6, the shape of the opening 125 in a plan view is circular; however, one embodiment of the present invention is not limited to this, and the opening 125 can have the same shape as the opening 121 or the opening 123 .

[0142] At least a part of the conductive layer 111a functions as a wiring 43 that functions as a signal line and is electrically connected to the signal line driver circuit 13 shown in Fig. 1A. At least a part of the conductive layer 111b functions as a wiring 45 that functions as a power supply line and is electrically connected to the power supply circuit 15 shown in Fig. 1A. At least a part of the conductive layer 115a functions as a wiring 41 that functions as a scan line and is electrically connected to the scan line driver circuit 11 shown in Fig. 1A.

[0143] The conductive layer 115a has a region extending in the X direction. Furthermore, the conductive layers 111a and 111b have regions extending in the Y direction. The conductive layer 115a has regions overlapping with the conductive layers 111a and 111b. Specifically, a portion of the region of the conductive layer 115a extending in the X direction overlaps a portion of the region of the conductive layer 111a extending in the Y direction. Furthermore, a portion of the region of the conductive layer 115a extending in the X direction overlaps a portion of the region of the conductive layer 111b extending in the Y direction.

[0144] Here, it may be said that the region of the conductive layer 115a extending in the X direction functions as the wiring 41, or that the entire conductive layer 115a functions as the wiring 41. It may be said that the region of the conductive layer 111a extending in the Y direction functions as the wiring 43, or that the entire conductive layer 111a functions as the wiring 43. It may be said that the region of the conductive layer 111b extending in the Y direction functions as the wiring 45, or that the entire conductive layer 111b functions as the wiring 45. Unless otherwise specified, the above also applies to other conductive layers having a region that functions as the wiring 41, the wiring 43, or the wiring 45.

[0145] 6 and 7 , in a region where the conductive layer 111a and the conductive layer 115a overlap, the insulating layer 103 is provided on the conductive layer 111a, the insulating layer 105 is provided on the insulating layer 103, and the conductive layer 115a is provided on the insulating layer 105. This reduces the parasitic capacitance formed by the conductive layer 111a and the conductive layer 115a compared to a case where, for example, the insulating layer 105 is the only insulating layer provided between the conductive layer 111a and the conductive layer 115a. Furthermore, in a region where the conductive layer 111b and the conductive layer 115a overlap, the insulating layer 103 is provided on the conductive layer 111b, the insulating layer 105 is provided on the insulating layer 103, and the conductive layer 115a is provided on the insulating layer 105. As a result, the parasitic capacitance formed by the conductive layer 111b and the conductive layer 115a is smaller than when the insulating layer provided between the conductive layer 111b and the conductive layer 115a is, for example, only the insulating layer 105. As a result, the time from when the scan line driver circuit 11 outputs a signal to the conductive layer 115a until the signal is supplied to the pixel circuit 40A can be shortened. Therefore, the display device of one embodiment of the present invention can be driven at high speed.

[0146] Fig. 8A shows a configuration example in which a pixel electrode 311 of a light-emitting element 60 is added to the plan view shown in Fig. 6. Fig. 8B is a cross-sectional view taken along dashed dotted line B3-B4 shown in Fig. 8A, and shows a configuration example of, for example, the transistor 52. Fig. 8B also shows a configuration example of layers above the transistor 52. Note that some of the reference numerals shown in Fig. 6 are omitted in Fig. 8A.

[0147] An insulating layer 218 and an insulating layer 235 over the insulating layer 218 are provided so as to cover the transistor 51, the transistor 52, and the capacitor 57. A light-emitting element 60 is provided over the insulating layer 235, and a protective layer 331 is provided so as to cover the light-emitting element 60. A substrate 152 is attached to the protective layer 331 with an adhesive layer 142.

[0148] The light-emitting element 60 includes a pixel electrode 311 over the insulating layer 235, an island-shaped layer 313 over the pixel electrode 311, and a common electrode 315 over the island-shaped layer 313. The layer 313 includes at least a light-emitting layer. The layer 313 can be referred to as an EL layer. The common electrode is also referred to as a counter electrode.

[0149] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0150] The insulating layer 105, the insulating layer 218, and the insulating layer 235 have an opening 129 that reaches the conductive layer 112b. A pixel electrode 311 is provided to cover the opening 129. The pixel electrode 311 has a shape that follows the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, and the upper surface of the conductive layer 112b. The pixel electrode 311 has regions that contact, for example, the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, and the upper surface of the conductive layer 112b. The pixel electrode 311 can be electrically connected to the conductive layer 112b inside the opening 129.

[0151] An insulating layer 237 can be provided so as to cover the upper end portion of the pixel electrode 311. The insulating layer 237 functions as a partition wall (also referred to as a bank, a spacer, or a partition wall). By providing the insulating layer 237, it is possible to prevent the pixel electrode 311 and the common electrode 315 from coming into contact with each other, thereby preventing the light-emitting element 60 from being short-circuited.

[0152] A recess is formed in the pixel electrode 311 so as to cover the opening 129, and the recess is filled with an insulating layer 237. For example, after forming the insulating layer 237 that covers the upper surface end of the pixel electrode 311 and the opening 129, the layer 313 can be formed using a fine metal mask (FMM).

[0153] The pixel electrode 311 may have a region overlapping with a region of the conductive layer 111a extending in the Y direction, or may have a region overlapping with a region of the conductive layer 115a extending in the X direction. This can increase the aperture ratio of the pixel. On the other hand, by not having a region of the pixel electrode 311 overlapping with a region of the conductive layer 111a extending in the Y direction or a region of the conductive layer 115a extending in the X direction, it is possible to suppress propagation of noise caused by signals supplied to the conductive layer 111a and noise caused by signals supplied to the conductive layer 115a to the pixel electrode 311.

[0154] A light-shielding layer 317 may be provided on the surface of the substrate 152 on the adhesive layer 142 side. The light-shielding layer 317 can be provided between adjacent light-emitting elements 60. By providing the light-shielding layer 317, light emitted from adjacent sub-pixels 23 is blocked. This makes it possible to suppress color mixing. Note that a configuration in which the light-shielding layer 317 is not provided is also possible.

[0155] <Pixel Configuration Example 2> Below, a configuration example of a pixel circuit will be described, the configuration of which is partially different from that of Fig. 6 and Fig. 7. Note that, below, descriptions of parts that overlap with Fig. 6 and Fig. 7 may be omitted.

[0156] 9 is a plan view showing an example of the configuration of pixel circuit 40A, and shows an example in which at least a portion of transistor 51 is provided in a region where wiring 41 and wiring 43 overlap, and at least a portion of transistor 52 is provided in a region where wiring 45 extends in the Y direction. Specifically, Fig. 9 shows an example in which semiconductor layer 113a, opening 121a, and opening 123a are provided in the region where wiring 41 and wiring 43 overlap, and semiconductor layer 113b, opening 121b, and opening 123b are provided in a region where wiring 45 extends in the Y direction. Fig. 9 also shows an example in which semiconductor layer 113a, opening 121a, and opening 123a overlap with a region of conductive layer 111a extending in the Y direction and a region of conductive layer 115a extending in the X direction. Furthermore, FIG. 9 shows an example in which the semiconductor layer 113b, the opening 121b, and the opening 123b overlap with a region of the conductive layer 111b that extends in the Y direction.

[0157] By configuring the pixel circuit 40A as shown in Fig. 9, it is possible to miniaturize the pixel while ensuring the area of ​​the capacitor 57, compared to when the pixel circuit 40A has the configuration shown in Fig. 6. On the other hand, by configuring the pixel circuit 40A as shown in Fig. 6, it is possible to increase the degree of freedom in the layout of the pixel circuit 40A, compared to when the pixel circuit 40A has the configuration shown in Fig. 9.

[0158] Fig. 10A is a plan view showing an example of the configuration of pixel circuit 40A, illustrating an example in which at least a portion of conductive layer 112a functions as wiring 43 that functions as a signal line. Fig. 10B is a cross-sectional view taken along dashed dotted line B5-B6 shown in Fig. 10A. In the example shown in Fig. 10A, conductive layer 112a has a region extending in the Y direction, and a portion of this region overlaps with conductive layer 115a.

[0159] 10B , the opening 125 is provided in the insulating layer 103 and the insulating layer 105 so as to reach the conductive layer 111a. The conductive layer 111a and the conductive layer 115b are electrically connected by the opening 125. Specifically, for example, the conductive layer 111a and the conductive layer 115b are in contact with each other inside the opening 125.

[0160] 10A , the wiring 43 and the wiring 45 are conductive layers provided in different layers. This allows the distance between the wiring 43 and the wiring 45 to be shorter than when the wiring 43 and the wiring 45 are conductive layers provided in the same layer. Therefore, the display device of one embodiment of the present invention can be a high-resolution display device. Meanwhile, by using the conductive layer 111a as the wiring 43 as shown in FIG. 6 , the parasitic capacitance formed in the region where the wiring 41 and the wiring 43 overlap can be smaller than that in the configuration shown in FIG. 10A .

[0161] 10A , for example, the distance in a plan view between a region of conductive layer 111b extending in the Y direction and a region of conductive layer 112a extending in the Y direction can be made shorter than the width of the region of conductive layer 111b extending in the Y direction, and can also be made shorter than the width of the region of conductive layer 112a extending in the Y direction. In other words, the length in the X direction between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112a extending in the Y direction can be made shorter than the length in the X direction of the region of conductive layer 111b extending in the Y direction, and can also be made shorter than the length in the X direction of the region of conductive layer 112a extending in the Y direction.

[0162] 10A , for example, the distance in a plan view between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112a extending in the Y direction can be shorter than the distance between conductive layer 111a and conductive layer 111b, and can also be shorter than the distance between conductive layer 112a and conductive layer 112b. For example, the distance between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112a extending in the Y direction can be shorter than the shortest distance between conductive layer 111a and conductive layer 111b in the X direction or the Y direction, and can also be shorter than the shortest distance between conductive layer 112a and conductive layer 112b in the X direction or the Y direction.

[0163] 10A, the conductive layer 111b and the conductive layer 112a may have an overlapping region, in which case the distance between the conductive layer 111b and the conductive layer 112a in plan view can be said to be zero.

[0164] 11 is a modified example of the configuration shown in FIG. 10A , and illustrates an example in which at least a portion of a transistor 51 is provided in a region where the wiring 41 and the wiring 43 overlap, and at least a portion of a transistor 52 is provided in a region where the wiring 45 extends in the Y direction. Specifically, FIG. 11 illustrates an example in which a semiconductor layer 113a, an opening 121a, and an opening 123a are provided in a region where the wiring 41 and the wiring 43 overlap, and a semiconductor layer 113b, an opening 121b, and an opening 123b are provided in a region where the wiring 45 extends in the Y direction. Also, FIG. 11 illustrates an example in which the semiconductor layer 113a, the opening 121a, and the opening 123a overlap with a region of the conductive layer 112a extending in the Y direction and a region of the conductive layer 115a extending in the X direction. Furthermore, FIG. 11 shows an example in which the semiconductor layer 113b, the opening 121b, and the opening 123b overlap with a region of the conductive layer 111b that extends in the Y direction.

[0165] Fig. 12A is a plan view showing a configuration example of the pixel circuit 40C shown in Fig. 2B. Fig. 12B is a cross-sectional view taken along the dashed dotted line B7-B8 shown in Fig. 12A, showing a configuration example of the transistor 53 and the capacitor 57.

[0166] 12A and 12B, the structures of the transistor 51, the transistor 52, and the transistor 53 are similar to those shown in FIGS. 4A1 and 4B. Here, the conductive layer 111, the conductive layer 112, the semiconductor layer 113, and the conductive layer 115 included in the transistor 53 are referred to as the conductive layer 111c, the conductive layer 112b, the semiconductor layer 113c, and the conductive layer 115c, respectively. Furthermore, the openings 121 and 123 provided in the transistor 53 are referred to as the openings 121c and 123c, respectively.

[0167] The conductive layer 111c functions as one of the source electrode and the drain electrode of the transistor 53, and the conductive layer 112b functions as the other of the source electrode and the drain electrode of the transistor 53. Here, Figure 12A shows an example in which the same conductive layer 112b is used for the other of the source electrode and the drain electrode of the transistor 52, the other of the source electrode and the drain electrode of the transistor 53, and the other electrode of the capacitor 57.

[0168] 12B, the insulating layer 105 has an opening 125a that reaches the conductive layer 112a, and the conductive layer 112a and the conductive layer 115b are electrically connected to each other through the opening 125a. Specifically, the conductive layer 112a and the conductive layer 115b are in contact with each other inside the opening 125a, for example.

[0169] 12A and 12B, the conductive layer 115a functions as the wiring 41a, and at least a part of the conductive layer 115c functions as the wiring 41b. The conductive layer 131 is shown as the wiring 48, and is electrically connected to the reference potential generating circuit 17 shown in FIG.

[0170] The insulating layer 103 and the insulating layer 105 have an opening 125b that reaches the conductive layer 111c and an opening 125c that reaches the conductive layer 131. The conductive layer 111c and the conductive layer 119 are electrically connected through the opening 125b, and the conductive layer 131 and the conductive layer 119 are electrically connected through the opening 125c. Specifically, for example, the conductive layer 111c and the conductive layer 119 contact each other inside the opening 125b, and the conductive layer 131 and the conductive layer 119 contact each other inside the opening 125c. As a result, the conductive layer 111c and the conductive layer 131 can be electrically connected via the conductive layer 119. By electrically connecting the conductive layer 111c and the conductive layer 131 via the conductive layer 119, it is possible to prevent the conductive layer 111c from contacting the conductive layer 111b and causing a short circuit.

[0171] The conductive layer 131 can be provided in the same layer as the conductive layer 111, and the conductive layer 119 can be provided in the same layer as the conductive layer 115. Therefore, the conductive layer 131 can have the same material as the conductive layer 111 and can be formed in the same process. Furthermore, the conductive layer 119 can have the same material as the conductive layer 115 and can be formed in the same process. For example, the conductive layer 111 and the conductive layer 131 can be formed by processing the same conductive film, and the conductive layer 115 and the conductive layer 119 can be formed by processing the same conductive film.

[0172] In Figure 12A, the shapes of openings 125a, 125b, and 125c in a plan view are circular, but one embodiment of the present invention is not limited to this and openings can have the same shape as opening 121 or opening 123.

[0173] The conductive layer 115a and the conductive layer 115c have regions extending in the X direction. The conductive layer 131 has a region extending in the Y direction. The conductive layer 115a and the conductive layer 115c have regions overlapping with the conductive layer 111a and the conductive layer 111b as well as the conductive layer 131. Specifically, a portion of the region of the conductive layer 115a extending in the X direction overlaps with a portion of the region of the conductive layer 111a, the conductive layer 111b, and the conductive layer 131 extending in the Y direction. Furthermore, a portion of the region of the conductive layer 115c extending in the X direction overlaps with a portion of the region of the conductive layer 111a, the conductive layer 111b, and the conductive layer 131 extending in the Y direction.

[0174] Here, it may be said that the region of the conductive layer 115a extending in the X direction functions as the wiring 41a, or that the entire conductive layer 115a functions as the wiring 41a. It may be said that the region of the conductive layer 115c extending in the X direction functions as the wiring 41b, or that the entire conductive layer 115c functions as the wiring 41b. It may be said that the region of the conductive layer 131 extending in the Y direction functions as the wiring 48, or that the entire conductive layer 131 functions as the wiring 48. Unless otherwise specified, the same applies to other conductive layers having a region that functions as the wiring 41a, the wiring 41b, or the wiring 48.

[0175] 12A , the conductive layer 111a, the conductive layer 111b, and the conductive layer 131 have regions that overlap with the conductive layer 115a with the insulating layer 103 and the insulating layer 105 interposed therebetween. The conductive layer 111a, the conductive layer 111b, and the conductive layer 131 also have regions that overlap with the conductive layer 115b with the insulating layer 103 and the insulating layer 105 interposed therebetween. This reduces the parasitic capacitance of the conductive layer 115a and the conductive layer 115b compared to when, for example, the insulating layer 105 is the only insulating layer provided between the conductive layer 111a, the conductive layer 111b, and the conductive layer 131 and the conductive layer 115a. This reduces the time from when the scan line driver circuit 11 outputs a signal to the conductive layer 115 a or 115 b until the signal is supplied to the pixel circuit 40 C. Therefore, the display device of one embodiment of the present invention can be driven at high speed.

[0176] FIG. 13 is a modified example of the configuration shown in FIG. 12A , showing an example in which at least a portion of a transistor 51 is provided in a region where the wiring 41a and the wiring 43 overlap. Also, an example in which at least a portion of a transistor 52 is provided in a region where the wiring 45 extends in the Y direction. Furthermore, an example in which at least a portion of a transistor 53 is provided in a region where the wiring 41b and the wiring 48 overlap. Specifically, FIG. 13 shows an example in which a semiconductor layer 113a, an opening 121a, and an opening 123a are provided in a region where the wiring 41a and the wiring 43 overlap. Also, FIG. 13 shows an example in which a semiconductor layer 113b, an opening 121b, and an opening 123b are provided in a region where the wiring 45 extends in the Y direction. Also, FIG. 13 shows an example in which a semiconductor layer 113c, an opening 121c, and an opening 123c are provided in a region where the wiring 41b and the wiring 48 overlap. 13 shows an example in which the semiconductor layer 113a, the opening 121a, and the opening 123a overlap with a region of the conductive layer 111a extending in the Y direction and a region of the conductive layer 115a extending in the X direction. Also, Fig. 13 shows an example in which the semiconductor layer 113b, the opening 121b, and the opening 123b overlap with a region of the conductive layer 111b extending in the Y direction. Furthermore, Fig. 13 shows an example in which the semiconductor layer 113c, the opening 121c, and the opening 123c overlap with a region of the conductive layer 111c extending in the Y direction and a region of the conductive layer 115c extending in the X direction.

[0177] 14A is a plan view showing a configuration example of a pixel circuit 40C, in which a conductive layer 112c functioning as the other of the source electrode and the drain electrode of the transistor 53 is provided, and at least a part of the conductive layer 112c functions as a wiring 48. Fig. 14B is a cross-sectional view taken along dashed dotted line B7-B8 shown in Fig. 14A. In the example shown in Fig. 14A, the conductive layer 112c has a region extending in the Y direction, and a part of this region overlaps with the conductive layer 115a and the conductive layer 115c.

[0178] 14B , an opening 125d reaching the conductive layer 111c is provided in the insulating layer 103, and the conductive layer 111c and the conductive layer 112b are electrically connected to each other through the opening 125d. Specifically, the conductive layer 111c and the conductive layer 112b are in contact with each other inside the opening 125d, for example.

[0179] In FIG. 14A, the shape of the opening 125d in a plan view is circular; however, one embodiment of the present invention is not limited to this, and the opening 125d can have the same shape as the opening 121 or the opening 123.

[0180] 14A , the wiring 48 is a conductive layer provided in a layer different from the wirings 43 and 45. This allows the distance between the wiring 43 and 48 and the distance between the wiring 45 and 48 to be shorter than when the wiring 48 is a conductive layer provided in the same layer as the wirings 43 and 45. Therefore, the display device of one embodiment of the present invention can be a high-resolution display device. On the other hand, as shown in FIG. 12A , by using the conductive layer 131 provided in the same layer as the conductive layer 111 as the wiring 48, the parasitic capacitance formed in the region where the wiring 41 a and the wiring 48 overlap and the parasitic capacitance formed in the region where the wiring 41 b and the wiring 48 overlap can be smaller than that in the configuration shown in FIG. 14A .

[0181] 14A , for example, the distance in a plan view between a region of conductive layer 111b extending in the Y direction and a region of conductive layer 112c extending in the Y direction can be made shorter than the width of the region of conductive layer 111b extending in the Y direction, and can also be made shorter than the width of the region of conductive layer 112c extending in the Y direction. In other words, the length in the X direction between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112c extending in the Y direction can be made shorter than the length in the X direction of the region of conductive layer 111b extending in the Y direction, and can also be made shorter than the length in the X direction of the region of conductive layer 112c extending in the Y direction.

[0182] Similarly, for example, the distance in a plan view between a region of the conductive layer 111a extending in the Y direction and a region of the conductive layer 112c extending in the Y direction can be made shorter than the width of the region of the conductive layer 111a extending in the Y direction, and can also be made shorter than the width of the region of the conductive layer 112c extending in the Y direction. In other words, the length in the X direction between the region of the conductive layer 111a extending in the Y direction and the region of the conductive layer 112c extending in the Y direction can be made shorter than the length in the X direction of the region of the conductive layer 111a extending in the Y direction, and can also be made shorter than the length in the X direction of the region of the conductive layer 112c extending in the Y direction.

[0183] Furthermore, in the example shown in FIG. 14A , for example, the distance in a planar view between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112c extending in the Y direction can be shorter than the distance between conductive layer 111a and conductive layer 111b, shorter than the distance between conductive layer 111b and conductive layer 111c, shorter than the distance between conductive layer 112a and conductive layer 112b, and further shorter than the distance between conductive layer 112b and conductive layer 112c. For example, the distance between the region of conductive layer 111b extending in the Y direction and the region of conductive layer 112c extending in the Y direction can be shorter than the shortest distance between conductive layer 111a and conductive layer 111b in the X direction or the Y direction, or shorter than the shortest distance between conductive layer 111b and conductive layer 111c in the X direction or the Y direction, or shorter than the shortest distance between conductive layer 112a and conductive layer 112b in the X direction or the Y direction, or shorter than the shortest distance between conductive layer 112b and conductive layer 112c in the X direction or the Y direction.

[0184] Similarly, for example, the distance in a planar view between a region of conductive layer 111a extending in the Y direction and a region of conductive layer 112c extending in the Y direction can be shorter than the distance between conductive layer 111a and conductive layer 111b, shorter than the distance between conductive layer 111b and conductive layer 111c, shorter than the distance between conductive layer 112a and conductive layer 112b, and further shorter than the distance between conductive layer 112b and conductive layer 112c. For example, the distance between the region of conductive layer 111a extending in the Y direction and the region of conductive layer 112c extending in the Y direction can be shorter than the shortest distance between conductive layer 111a and conductive layer 111b in the X direction or the Y direction, or shorter than the shortest distance between conductive layer 111b and conductive layer 111c in the X direction or the Y direction, or shorter than the shortest distance between conductive layer 112a and conductive layer 112b in the X direction or the Y direction, or shorter than the shortest distance between conductive layer 112b and conductive layer 112c in the X direction or the Y direction.

[0185] 14A , the conductive layer 111b and the conductive layer 112c may have an overlapping region. In this case, the distance between the conductive layer 111b and the conductive layer 112c in a planar view can be said to be zero. Similarly, the conductive layer 111a and the conductive layer 112c may have an overlapping region. In this case, the distance between the conductive layer 111a and the conductive layer 112c in a planar view can be said to be zero.

[0186] 15A is a modification of the configuration shown in Fig. 14A, and illustrates an example in which the conductive layer 112b and the conductive layer 111c are electrically connected to each other through a conductive layer 119 provided in the same layer as the conductive layer 115. Fig. 15B is a cross-sectional view taken along dashed dotted line B7-B8 in Fig. 15A, and illustrates an example configuration of the transistor 53 and the capacitor 57.

[0187] 15B , an opening 125d1 reaching the conductive layer 112b is provided in the insulating layer 105, and the conductive layer 112b and the conductive layer 119 are electrically connected by the opening 125d1. Specifically, for example, the conductive layer 112b and the conductive layer 119 are in contact with each other inside the opening 125d1. Furthermore, an opening 125d2 reaching the conductive layer 111c is provided in the insulating layer 103 and the insulating layer 105, and the conductive layer 111c and the conductive layer 119 are electrically connected by the opening 125d2. Specifically, for example, the conductive layer 111c and the conductive layer 119 are in contact with each other inside the opening 125d2.

[0188] As a result, the conductive layer 112b and the conductive layer 111c can be electrically connected to each other through the conductive layer 119. With such a structure of the display device of one embodiment of the present invention, the opening 125d (the opening 125d1 and the opening 125d2) can be formed in the same process as the opening 125a.

[0189] FIG. 16 is a modified example of the configuration shown in FIG. 14A , showing an example in which at least a portion of a transistor 51 is provided in a region where the wiring 41a and the wiring 43 overlap. Also, an example in which at least a portion of a transistor 52 is provided in a region of the wiring 45 extending in the Y direction. Furthermore, an example in which at least a portion of a transistor 53 is provided in a region of the wiring 41b extending in the X direction. Specifically, FIG. 16 shows an example in which a semiconductor layer 113a, an opening 121a, and an opening 123a are provided in a region where the wiring 41 and the wiring 43 overlap. Also, FIG. 16 shows an example in which a semiconductor layer 113b, an opening 121b, and an opening 123b are provided in a region of the wiring 45 extending in the Y direction. Also, FIG. 16 shows an example in which a semiconductor layer 113c, an opening 121c, and an opening 123c are provided in a region of the wiring 41b extending in the X direction. 16 shows an example in which the semiconductor layer 113a, the opening 121a, and the opening 123a overlap with the region of the conductive layer 111a extending in the Y direction and the region of the conductive layer 115a extending in the X direction. Also, Fig. 16 shows an example in which the semiconductor layer 113b, the opening 121b, and the opening 123b overlap with the region of the conductive layer 111b extending in the Y direction. Also, Fig. 16 shows an example in which the semiconductor layer 113c, the opening 121c, and the opening 123c overlap with the region of the conductive layer 115c extending in the X direction. Furthermore, Fig. 16 shows an example in which the opening 125d overlaps with the conductive layer 115b.

[0190] 16, the pixel circuit 40C can be miniaturized while ensuring the area of ​​the capacitor 57, compared to when the pixel circuit 40C has the configuration shown in Fig. 14A. On the other hand, when the pixel circuit 40C has the configuration shown in Fig. 14A, the degree of freedom in the layout of the pixel circuit 40C can be increased, compared to when the pixel circuit 40C has the configuration shown in Fig. 16.

[0191] 17, 18, and 19 are modifications of the configurations shown in FIGS. 14A, 15A, and 16, respectively, and show an example in which the conductive layer 112c is shared by two adjacent pixel circuits 40C. Each of FIGS. 17, 18, and 19 shows an example in which the conductive layer 112c is shared by the jth pixel circuit 40C and the j+1th pixel circuit 40C. Each of FIGS. 17, 18, and 19 also shows an example in which a region of the conductive layer 112c extending in the Y direction is provided between a region of the conductive layer 111b electrically connected to the transistor 52 provided in the jth pixel circuit 40C, which extends in the Y direction, and a region of the conductive layer 111b electrically connected to the transistor 52 provided in the j+1th pixel circuit 40C, which extends in the Y direction.

[0192] 17, 18, and 19, the number of conductive layers 112c provided in the display device of one embodiment of the present invention can be reduced compared to the examples shown in Figures 14A, 15A, and 16, thereby realizing a high-definition display device. On the other hand, in the examples shown in Figures 14A, 15A, and 16, the load of the conductive layers 112c can be reduced compared to the examples shown in Figures 17, 18, and 19. Therefore, a display device that can be driven at high speed can be realized.

[0193] 20A , 20B , 21A , and 21B are modifications of the configurations shown in FIGS. 14A , 14B , 15A , and 15B , respectively, and show an example in which the conductive layer 111b is shared by two adjacent pixel circuits 40C. FIGS. 20A and 21A show an example in which the conductive layer 111b is shared by the jth pixel circuit 40C and the j+1th pixel circuit 40C. Also, FIGS. 20A and 21A show an example in which a region of the conductive layer 111b extending in the Y direction is provided between a region of the conductive layer 112c electrically connected to the transistor 53 provided in the jth pixel circuit 40C, which extends in the Y direction, and a region of the conductive layer 112c electrically connected to the transistor 53 provided in the j+1th pixel circuit 40C, which extends in the Y direction.

[0194] 20A , 20B , 21A , and 21B , the number of conductive layers 111 b provided in the display device of one embodiment of the present invention can be reduced compared to the examples shown in FIGS. 14A , 14B , 15A , and 15B , thereby realizing a high-resolution display device. On the other hand, the examples shown in FIGS. 14A , 14B , 15A , and 15B , the load on the conductive layers 111 b can be reduced compared to the examples shown in FIGS. 20A , 20B , 21A , and 21B . Therefore, a display device that can be driven at high speed can be realized.

[0195] Fig. 22A is a modified example of the configuration shown in Fig. 6 , illustrating an example in which a conductive layer 135 is provided. Fig. 22A illustrates an example configuration of a pixel circuit 40A. Fig. 22B is a cross-sectional view taken along dashed dotted line C1-C2 in Fig. 22A , illustrating an example configuration of a transistor 52.

[0196] The conductive layer 135 has a region extending in the X direction and a region overlapping with the conductive layer 111a and the conductive layer 111b. The conductive layer 135 can be provided in the same layer as the conductive layer 112. Therefore, the conductive layer 135 can have the same material as the conductive layer 112 and can be formed in the same process. For example, the conductive layer 112 and the conductive layer 135 can be formed by processing the same conductive film.

[0197] 22B , an opening 127 reaching the conductive layer 111b is provided in the insulating layer 103, and the conductive layer 111b and the conductive layer 135 are electrically connected by the opening 127. Specifically, for example, inside the opening 127, the conductive layer 111b and the conductive layer 135 are in contact with each other.

[0198] In Figure 22A, the shape of opening 127 in a planar view is circular, but one embodiment of the present invention is not limited to this and can be the same shape as opening 121, opening 123, or opening 125.

[0199] 22A , the display device of one embodiment of the present invention can be configured such that not only the conductive layer 111b having a region extending in the Y direction but also the conductive layer 135 having a region extending in the X direction functions as the wiring 45 that functions as a power supply line. Therefore, the power supply circuit 15 shown in FIG. 1A can supply a power supply potential to the transistor 52 not only through the conductive layer 111b but also through the conductive layer 135. This can prevent the power supply potential generated by the power supply circuit 15 from dropping before it is supplied to the pixel circuit 40A. In particular, this can suitably prevent the power supply potential generated by the power supply circuit 15 from dropping before it is supplied to the pixel circuit 40A, which is located a long wiring distance from the power supply circuit 15.

[0200] Figure 23 is a modified example of the configuration shown in Figure 22A, and shows an example in which at least a part of transistor 51 is provided in the area where wiring 41 and wiring 43 overlap, and at least a part of transistor 52 is provided in the area where wiring 45 extends in the Y direction.

[0201] Fig. 24A is a modified example of the configuration shown in Fig. 12A , illustrating an example in which a conductive layer 135 is provided. Fig. 24A illustrates an example configuration of a pixel circuit 40C. Fig. 24B is a cross-sectional view taken along dashed dotted line C3-C4 in Fig. 24A , illustrating an example configuration of a transistor 53.

[0202] The conductive layer 135 has a region extending in the X direction and has regions overlapping with the conductive layer 111a, the conductive layer 111b, and the conductive layer 131. As described above, the conductive layer 135 can be provided in the same layer as the conductive layer 112.

[0203] 22B , an opening 127 reaching the conductive layer 111b is provided in the insulating layer 103, and the conductive layer 111b and the conductive layer 135 are electrically connected by the opening 127. Specifically, for example, inside the opening 127, the conductive layer 111b and the conductive layer 135 are in contact with each other.

[0204] 24A , the power supply potential generated by the power supply circuit 15 shown in FIG. 2A can be prevented from dropping before being supplied to the pixel circuit 40C. In particular, the power supply potential generated by the power supply circuit 15 can be suitably prevented from dropping before being supplied to the pixel circuit 40C, which is located a long wiring distance from the power supply circuit 15.

[0205] 25 is a modification of the configuration shown in FIG. 24A , and shows an example in which at least a part of a transistor 51 is provided in a region where a wiring 41 a overlaps with a wiring 43. Also, this example shows an example in which at least a part of a transistor 52 is provided in a region where a wiring 45 extends in the Y direction. Furthermore, this example shows an example in which at least a part of a transistor 53 is provided in a region where a wiring 41 b overlaps with a wiring 48.

[0206] 26A is a modification of the configuration shown in FIG. 22A , and illustrates an example in which the conductive layer 111 b and the conductive layer 135 are electrically connected via a conductive layer 137 that is provided in the same layer as the conductive layer 115. FIG. 26A illustrates an example configuration of a pixel circuit 40A. FIG. 26B is a cross-sectional view taken along dashed dotted line C1-C2 in FIG. 26A , and illustrates an example configuration of a transistor 52.

[0207] 26B , an opening 127a reaching the conductive layer 111b is provided in the insulating layer 103 and the insulating layer 105, and the conductive layer 111b and the conductive layer 137 are electrically connected by the opening 127a. Specifically, for example, the conductive layer 111b and the conductive layer 137 are in contact inside the opening 127a. Furthermore, an opening 127b reaching the conductive layer 135 is provided in the insulating layer 105, and the conductive layer 135 and the conductive layer 137 are electrically connected by the opening 127b. Specifically, for example, the conductive layer 135 and the conductive layer 137 are in contact inside the opening 127b.

[0208] As a result, the conductive layer 111b and the conductive layer 135 can be electrically connected to each other through the conductive layer 137. With such a structure of the display device of one embodiment of the present invention, the opening 127 (the opening 127a and the opening 127b) can be formed in the same process as the opening 125.

[0209] Figure 27 is a modified example of the configuration shown in Figure 26A, and shows an example in which at least a part of transistor 51 is provided in the region where wiring 41 and wiring 43 overlap, and at least a part of transistor 52 is provided in the region where wiring 45 extends in the Y direction.

[0210] 28A is a modification of the configuration shown in FIG. 24A , and shows an example in which conductive layer 111 b and conductive layer 135 are electrically connected via conductive layer 137 provided in the same layer as conductive layer 115. FIG. 28A shows an example of the configuration of pixel circuit 40C. FIG. 28B is a cross-sectional view taken along dashed dotted line C3-C4 shown in FIG. 28A , and shows an example of the configuration of transistor 53.

[0211] FIG. 28A shows an example in which a region of the conductive layer 115c extending in the X direction is provided between the transistor 52 and the transistor 53 to prevent contact between the conductive layer 115c and the conductive layer 137.

[0212] Figure 29 is a modified example of the configuration shown in Figure 28A, and shows an example in which at least a part of transistor 51 is provided in the region where wiring 41a and wiring 43 overlap, at least a part of transistor 52 is provided in the region where wiring 45 extends in the Y direction, and at least a part of transistor 53 is provided in the region where wiring 41b and wiring 48 overlap.

[0213] 22A , and illustrates an example in which the conductive layer 135 is provided in the same layer as the conductive layer 115. Fig. 30A illustrates an example of the configuration of a pixel circuit 40A. Fig. 30B is a cross-sectional view taken along dashed dotted line C1-C2 in Fig. 30A , and illustrates an example of the configuration of a transistor 52.

[0214] Figure 31 is a modified example of the configuration shown in Figure 30A, and shows an example in which at least a part of transistor 51 is provided in the area where wiring 41 and wiring 43 overlap, and at least a part of transistor 52 is provided in the area where wiring 45 extends in the Y direction.

[0215] Fig. 32A is a modified example of the configuration shown in Fig. 30A, and shows an example in which at least a part of the conductive layer 112a functions as a wiring 43 that functions as a signal line. Fig. 32B is a cross-sectional view taken along the dashed dotted line C1-C2 shown in Fig. 32A.

[0216] Figure 33 is a modified example of the configuration shown in Figure 32A, and shows an example in which at least a part of transistor 51 is provided in the area where wiring 41 and wiring 43 overlap, and at least a part of transistor 52 is provided in the area where wiring 45 extends in the Y direction.

[0217] 34A, 34B, 35, 36A, 36B, and 37 are modified examples of the configurations shown in FIGS. 30A, 30B, 31, 32A, 32B, and 33, respectively, and show examples in which conductive layer 111b and conductive layer 135 are electrically connected via conductive layer 137 provided in the same layer as conductive layer 112.

[0218] In the examples shown in Figures 34A, 34B, 35, 36A, 36B, and 37, an opening 127a reaching the conductive layer 111b is provided in the insulating layer 103, and the conductive layer 111b and the conductive layer 137 are electrically connected by the opening 127a. Specifically, for example, the conductive layer 111b and the conductive layer 137 are in contact inside the opening 127a. Furthermore, an opening 127b reaching the conductive layer 137 is provided in the insulating layer 105, and the conductive layer 137 and the conductive layer 135 are electrically connected by the opening 127b. Specifically, for example, the conductive layer 137 and the conductive layer 135 are in contact inside the opening 127b. As a result, the conductive layer 111b and the conductive layer 135 can be electrically connected via the conductive layer 137. 34A, 34B, 35, 36A, 36B, and 37 can also be applied to the openings 125b and 125c. Also, the structure of the conductive layer 137 shown in FIG. 34A, 34B, 35, 36A, 36B, and 37 can also be applied to the conductive layer 119.

[0219] FIG. 38A is a modified example of the structure shown in FIG. 34A , in which the layer in which the conductive layer 137 is provided is different. FIG. 38A shows a pixel electrode 311, and illustrates an example in which the conductive layer 137 is provided in the same layer as the pixel electrode 311. Therefore, in the example shown in FIG. 38A , the conductive layer 137 can be made of the same material as the pixel electrode 311 and can be formed in the same process. For example, the pixel electrode 311 and the conductive layer 137 can be formed by processing the same conductive film. FIG. 38B is a cross-sectional view taken along dashed dotted line C5-C6 in FIG. 38A , illustrating an example configuration of, for example, the transistor 52. FIG. 38B also illustrates an example configuration of, for example, layers above the transistor 52. Note that some of the reference numerals shown in FIG. 34A are omitted in FIG. 38A .

[0220] 38A illustrates an example in which the pixel electrode 311 does not overlap any of the regions of the conductive layer 111a extending in the Y direction, the regions of the conductive layer 111b extending in the Y direction, the regions of the conductive layer 115a extending in the X direction, and the regions of the conductive layer 135 extending in the X direction. However, the pixel electrode 311 may have a region that overlaps with at least one of these regions. This increases the aperture ratio of the pixel. On the other hand, by configuring the pixel electrode 311 so that it does not overlap these regions, it is possible to suppress the propagation of noise caused by the conductive layers 111a, 111b, 115a, and 135 to the pixel electrode 311. In particular, by not overlapping the region of the conductive layer 111a extending in the Y direction to which an image signal is supplied and the region of the conductive layer 115a extending in the X direction to which a scanning signal is supplied, it is possible to effectively suppress the propagation of noise to the pixel electrode 311.

[0221] An insulating layer 218 and an insulating layer 235 over the insulating layer 218 are provided to cover the transistor 51, the transistor 52, and the capacitor 57. The insulating layer 105, the insulating layer 218, and the insulating layer 235 have an opening 129 that reaches the conductive layer 112b. For a description of elements provided above the insulating layer 235 and a description of the opening 129, see, for example, the description of FIG. 8B .

[0222] 38B , an opening 127a reaching the conductive layer 111b is provided in the insulating layer 103, the insulating layer 105, the insulating layer 218, and the insulating layer 235. An opening 127b reaching the conductive layer 135 is provided in the insulating layer 218 and the insulating layer 235. Here, the openings 127a and 127b can be formed in the same process as the opening 129.

[0223] The conductive layer 137 is provided to cover the openings 127a and 127b. The conductive layer 137 has a shape that conforms to the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, the side surfaces of the insulating layer 103, the upper surface of the conductive layer 111b, and the upper surface of the conductive layer 135. The conductive layer 137 has a region that contacts the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, the side surfaces of the insulating layer 103, the upper surface of the conductive layer 111b, and the conductive layer 135. The conductive layer 137 can be electrically connected to the conductive layer 111b inside the opening 127a and can be electrically connected to the conductive layer 135 inside the opening 127b. This allows the conductive layer 111b and the conductive layer 135 to be electrically connected via the conductive layer 137.

[0224] An insulating layer 237 can be provided so as to cover the upper surface end portion of the conductive layer 137. By providing the insulating layer 237, for example, the conductive layer 137 can be prevented from coming into contact with the pixel electrode 311 and causing a short circuit.

[0225] A recess is formed in the conductive layer 137 so as to cover the opening 127a, and another recess is formed so as to cover the opening 127b. An insulating layer 237 is filled in these recesses.

[0226] The structures of the openings 127a, 127b, and conductive layer 137 shown in Figures 38A and 38B can also be applied to the openings 127a, 127b, and conductive layer 137 shown in layers other than those shown in Figures 34A and 34B. For example, the conductive layer 137 shown in layers other than those shown in Figures 34A and 34B can be provided in the same layer as the pixel electrode. Furthermore, the structures of the openings 127a and 127b shown in Figures 38A and 38B can also be applied to the openings 125b, 125c, 125d1, and 125d2. Furthermore, the structure of the conductive layer 137 shown in Figures 38A and 38B can also be applied to the conductive layer 119. For example, the conductive layer 119 can be provided in the same layer as the pixel electrode.

[0227] <Components of Display Device> Components included in the display device of this embodiment will be described below.

[0228] [Semiconductor Layer 113] The semiconductor material that can be used for the semiconductor layer 113 is not particularly limited. For example, an elemental semiconductor or a compound semiconductor can be used. Examples of elemental semiconductors that can be used include silicon or germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors that can be used include organic substances having semiconductor properties or metal oxides having semiconductor properties. Note that these semiconductor materials may contain impurities as dopants.

[0229] The crystallinity of the semiconductor material used for the semiconductor layer 113 is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a single-crystalline semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0230] Silicon can be used for the semiconductor layer 113. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0231] A transistor using amorphous silicon for the semiconductor layer 113 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 113 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layer 113 has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed.

[0232] The semiconductor layer 113 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 113 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, an element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0233] For the semiconductor layer 113, for example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), indium tin gallium oxide (In—Sn—Ga oxide), or indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, indium tin oxide containing silicon or the like can be used. Alternatively, the above oxides having an amorphous structure can be used. For example, indium oxide having an amorphous structure or indium tin oxide having an amorphous structure can be used.

[0234] The element M is preferably one or more elements selected from gallium, aluminum, yttrium, and tin, and is particularly preferably gallium.

[0235] Here, the composition of the metal oxide in the semiconductor layer 113 greatly affects the electrical characteristics and reliability of the transistor 50 .

[0236] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0237] When an In—Zn oxide is used for the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, In:Zn=10:1, or a ratio close to these can be used.

[0238] When an In—Sn oxide is used for the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, In:Sn=10:1, or a ratio close to these can be used.

[0239] When an In-M-Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 113 may have atomic ratios of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1 :6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides thereof having a similar structure can be used.

[0240] When a plurality of metal elements are contained as the element M, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned ranges.

[0241] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In—Ga—Zn oxide is used for the semiconductor layer 113, it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, the element M, and zinc be in the above-mentioned range.

[0242] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0243] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that is required to have a high on-state current, a display device with excellent electrical characteristics can be provided.

[0244] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0245] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition near there, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 to 3 and the atomic ratio of zinc is 2 to 4. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition near there, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 5 and less than 7. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition near there, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0246] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0247] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and the drain potential and the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and a NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0248] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of variation in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0249] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 113, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of fluctuation in threshold voltage in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This allows a highly reliable transistor to be realized.

[0250] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0251] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in metal oxides has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0252] More specifically, when an In—Ga—Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer 113. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layer 113.

[0253] For example, the semiconductor layer 113 has an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1 :6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof can be used.

[0254] The semiconductor layer 113 preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V Ｏ This has the effect of making oxygen vacancy less likely to occur.

[0255] A metal oxide that does not contain gallium may be used for the semiconductor layer 113. For example, In—Zn oxide may be used for the semiconductor layer 113. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Alternatively, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer 113. Using a metal oxide that does not contain gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0256] For example, an oxide containing indium and zinc can be used for the semiconductor layer 113. In this case, a metal oxide having an atomic ratio of metal elements of, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these can be used.

[0257] Although gallium has been used as a representative example in the description, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M.

[0258] A transistor having high reliability when a positive bias is applied can be obtained by using a metal oxide having a low content of the element M for the semiconductor layer 113. When the transistor is used as a transistor that is required to have high reliability when a positive bias is applied, a display device having high reliability can be obtained.

[0259] Next, the reliability of the transistor against light will be described.

[0260] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0261] Increasing the content of the element M in the metal oxide can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of the element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide in the semiconductor layer 113 is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, still more preferably 3.2 eV or more, even more preferably 3.3 eV or more, still more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0262] For example, the semiconductor layer 113 can use metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or similar ratios thereof.

[0263] The semiconductor layer 113 can suitably use a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less.

[0264] When an In—Ga—Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is equal to or less than the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a ratio close to these can be used.

[0265] The semiconductor layer 113 can suitably use a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is 20 atomic % or more and 60 atomic % or less, preferably 20 atomic % or more and 50 atomic % or less, more preferably 30 atomic % or more and 50 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less.

[0266] A transistor with high reliability to light can be obtained by using a metal oxide having a high content of element M for the semiconductor layer 113. By using the transistor as a transistor that is required to have high reliability to light, a display device with high reliability can be obtained.

[0267] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used for the semiconductor layer 113. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a display device that has both excellent electrical characteristics and high reliability can be obtained.

[0268] The semiconductor layer 113 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 113 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0269] The two or more metal oxide layers included in the semiconductor layer 113 may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto provided on the first metal oxide layer can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0270] A crystalline metal oxide layer is preferably used for the semiconductor layer 113. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 113, the density of defect states in the semiconductor layer 113 can be reduced, and a highly reliable display device can be realized.

[0271] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 113, the more the density of defect states in the semiconductor layer 113 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0272] When a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (stage temperature) during formation, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (also referred to as the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0273] The semiconductor layer 113 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer 113 may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 113 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, by using the same sputtering target and varying the oxygen flow rate, a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the two or more metal oxide layers included in the semiconductor layer 113 may have different compositions.

[0274] The thickness of the semiconductor layer 113 is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, even more preferably 10 nm or more and 100 nm or less, even more preferably 10 nm or more and 70 nm or less, even more preferably 15 nm or more and 70 nm or less, even more preferably 15 nm or more and 50 nm or less, even more preferably 20 nm or more and 50 nm or less, even more preferably 20 nm or more and 40 nm or less, even more preferably 25 nm or more and 40 nm or less.

[0275] The substrate temperature during the formation of the semiconductor layer 113 is preferably from room temperature (25° C.) to 200° C., more preferably from room temperature to 130° C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0276] Here, oxygen vacancies that can be formed in the semiconductor layer 113 will be described.

[0277] When an oxide semiconductor is used for the semiconductor layer 113, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, and oxygen vacancies (V Ｏ In addition, defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V ＯHydrogen atoms (H) may function as donors and generate electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0278] V Ｏ H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0279] From the above, when an oxide semiconductor is used for the semiconductor layer 113, V in the semiconductor layer 113 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, impurities such as water and hydrogen in the oxide semiconductor are removed (this may be referred to as dehydration or dehydrogenation treatment), and oxygen vacancies (V Ｏ It is important to repair the Ｏ By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0280] In the case where an oxide semiconductor is used for the semiconductor layer 113, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm−３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0281] [Insulating Layer 103] An inorganic insulating material or an organic insulating material can be used for the insulating layer 103. The insulating layer 103 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0282] An inorganic insulating material can be suitably used for the insulating layer 103. Examples of the inorganic insulating material that can be used include one or more of oxide, oxynitride, nitride oxide, and nitride. For example, the insulating layer 103 can include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride.

[0283] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0284] The oxygen and nitrogen contents can be analyzed using, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 1 atomic% or less, or 0.5 atomic% or less). When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0285] The insulating layer 103 may have a stacked structure of two or more layers. In the cross-sectional view illustrating the example of the structure of the transistor 50 described above, the insulating layer 103 has a stacked structure of an insulating layer 103a and an insulating layer 103b over the insulating layer 103a. The insulating layer 103a and the insulating layer 103b can each be made of the same material as that used for the insulating layer 103. Note that the insulating layer 103a and the insulating layer 103b may be made of the same material or different materials. Note that the insulating layer 103a may have a stacked structure of two or more layers. The insulating layer 103b may have a stacked structure of two or more layers.

[0286] The insulating layer 103a can be thicker than the insulating layer 103b. The deposition rate (also referred to as deposition rate) of the insulating layer 103a is preferably fast, for example, faster than the deposition rate of the insulating layer 103b. In particular, when the insulating layer 103a is thick, the deposition rate of the insulating layer 103a is preferably fast. By increasing the deposition rate of the insulating layer 103a, productivity can be increased. For example, the deposition rate can be increased by increasing the power used in forming the insulating layer 103a.

[0287] The insulating layer 103a preferably has a small stress. If the insulating layer 103a is made thick, the stress of the insulating layer 103a increases, which may cause warping of the substrate. By reducing the stress of the insulating layer 103a, it is possible to prevent problems during processing that are caused by stress, such as warping of the substrate.

[0288] The insulating layer 103b functions as a blocking layer that suppresses gas desorption from the insulating layer 103a. The insulating layer 103b is preferably made of a material that does not easily diffuse gas. The insulating layer 103b preferably has a region with a higher film density than the insulating layer 103a. Increasing the film density of the insulating layer 103b can improve the blocking property. For example, the insulating layer 103b can be made of a material that has a higher nitrogen content than the insulating layer 103a. Increasing the nitrogen content of the insulating layer 103b can improve the blocking property.

[0289] The insulating layer 103b may have any thickness that functions as a blocking layer for preventing gas from being released from the insulating layer 103a, and may be thinner than the insulating layer 103a. The deposition rate of the insulating layer 103b is preferably slow, for example, slower than the deposition rate of the insulating layer 103a. By slowing the deposition rate of the insulating layer 103b, the film density of the insulating layer 103b can be increased, thereby improving the blocking property. Furthermore, by increasing the substrate temperature during deposition of the insulating layer 103b, the film density of the insulating layer 103b can be increased, thereby improving the blocking property.

[0290] The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a darker (darker) transmission electron (TE) image, whereas a low film density results in a lighter (brighter) transmission electron (TE) image. Therefore, the insulating layer 103b may appear darker (darker) in the transmission electron (TE) image than the insulating layer 103a. Even when the insulating layer 103a and the insulating layer 103b are made of the same material, the film density is different, and therefore the boundary between them can sometimes be observed as a difference in contrast in a cross-sectional TEM image.

[0291] The insulating layer 103b may have a region where the hydrogen concentration in the film is lower than that in the insulating layer 103a. The difference in hydrogen concentration between the insulating layer 103a and the insulating layer 103b can be evaluated by, for example, secondary ion mass spectrometry (SIMS).

[0292] Here, the insulating layer 103 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 113.

[0293] When an oxide semiconductor is used for the semiconductor layer 113, an inorganic insulating material can be suitably used for each of the insulating layers 103a and 103b.

[0294] The insulating layer 103a is preferably formed using an oxide or an oxynitride. The insulating layer 103a is preferably formed using a film that releases oxygen by heating. For example, silicon oxide or silicon oxynitride can be suitably used for the insulating layer 103a.

[0295] When the insulating layer 103a releases oxygen, oxygen can be supplied from the insulating layer 103a to the semiconductor layer 113. When oxygen is supplied from the insulating layer 103a to the semiconductor layer 113, particularly to the channel formation region of the semiconductor layer 113, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability. The insulating layer 103a preferably has a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient of the insulating layer 103a, oxygen can be easily diffused in the insulating layer 103a, and oxygen can be efficiently supplied from the insulating layer 103a to the semiconductor layer 113. Other treatments for supplying oxygen to the semiconductor layer 113 include heat treatment in an atmosphere containing oxygen and plasma treatment in an atmosphere containing oxygen.

[0296] The insulating layer 103a preferably releases little impurities (for example, water and hydrogen) from itself. Reducing the release of impurities from the insulating layer 103a suppresses the impurities from diffusing into the semiconductor layer 113. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0297] For example, silicon oxide or silicon oxynitride formed by plasma enhanced chemical vapor deposition (PECVD) can be suitably used for the insulating layer 103a. In this case, a mixed gas of a silicon-containing gas and an oxygen-containing gas is preferably used as the source gas. As the silicon-containing gas, for example, one or more of silane, disilane, trisilane, and silane fluoride can be used. As the oxygen-containing gas, for example, oxygen (O ２ ), ozone (O ３ ), nitrous oxide (N ２ O), nitric oxide (NO), or nitrogen dioxide (NO ２ Note that by increasing the power used in forming the insulating layer 103a, the amount of impurities (for example, water and hydrogen) released from the insulating layer 103a can be reduced.

[0298] The insulating layer 103b is preferably impermeable to oxygen. The insulating layer 103b functions as a blocking layer that suppresses oxygen from being released from the insulating layer 103a. Furthermore, the insulating layer 103b is preferably impermeable to hydrogen. The insulating layer 103b functions as a blocking layer that suppresses hydrogen from diffusing from the outside of the transistor to the semiconductor layer 113 through the insulating layer 103. The insulating layer 103b preferably has a high film density. Increasing the film density of the insulating layer 103b can improve the blocking property of oxygen and hydrogen. The film density of the insulating layer 103b is preferably higher than that of the insulating layer 103a. When silicon oxide or silicon oxynitride is used for the insulating layer 103a, the insulating layer 103b can be preferably made of, for example, silicon nitride, silicon nitride oxide, or aluminum oxide. The insulating layer 103b preferably has a region with a higher nitrogen content than the insulating layer 103a, for example. The insulating layer 103b can be formed using, for example, a material having a higher nitrogen content than the insulating layer 103a. The insulating layer 103b is preferably formed using a nitride or a nitride oxide. For example, silicon nitride or silicon nitride oxide can be suitably used for the insulating layer 103b.

[0299] When oxygen contained in the insulating layer 103a diffuses upward from a region of the insulating layer 103a that is not in contact with the semiconductor layer 113 (for example, the upper surface of the insulating layer 103a), the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may decrease. By providing the insulating layer 103b on the insulating layer 103a, it is possible to prevent the oxygen contained in the insulating layer 103a from diffusing from a region of the insulating layer 103a that is not in contact with the semiconductor layer 113. Therefore, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0300] The conductive layer 112 may be oxidized by the oxygen contained in the insulating layer 103a, resulting in an increase in resistance. Furthermore, the conductive layer 112 may be oxidized by the oxygen contained in the insulating layer 103a, resulting in a decrease in the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113. By providing the insulating layer 103b on the insulating layer 103a, it is possible to prevent the conductive layer 112 from being oxidized and the resistance from increasing. At the same time, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 increases, resulting in an oxygen deficiency (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0301] When hydrogen diffuses into the semiconductor layer 113, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V Ｏ ) may be formed. Ｏ By providing the insulating layer 103b on the insulating layer 103a, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0302] The insulating layer 103b preferably has a thickness that functions as a blocking layer for oxygen and hydrogen. If the insulating layer 103b is too thin, its function as a blocking layer may be reduced. On the other hand, if the insulating layer 103b is too thick, the region of the semiconductor layer 113 in contact with the insulating layer 103a may be narrowed, and the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may be reduced. The insulating layer 103b may have a thickness thinner than that of the insulating layer 103a. The insulating layer 103b has a thickness preferably from 5 nm to 100 nm, more preferably from 5 nm to 70 nm, further preferably from 10 nm to 70 nm, further preferably from 10 nm to 50 nm, further preferably from 20 nm to 50 nm, and further preferably from 20 nm to 40 nm. By setting the thickness of the insulating layer 103b within the above range, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0303] The insulating layer 103b preferably releases less impurities (for example, water and hydrogen) from itself. Reducing the release of impurities from the insulating layer 103b suppresses the impurities from diffusing into the semiconductor layer 113. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0304] In the transistor 50, a region of the semiconductor layer 113 in contact with the insulating layer 103 can function as a channel formation region. That is, oxygen is selectively supplied to the channel formation region, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0305] [Conductive Layer 111, Conductive Layer 112, and Conductive Layer 115] The conductive layers 111 and 112 functioning as source and drain electrodes, and the conductive layer 115 functioning as a gate electrode can be formed using one or more of chromium, copper, aluminum, magnesium, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above metals. The conductive layers 111, 112, and 115 can be formed using a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum. Copper and aluminum are particularly preferred because of their excellent mass productivity.

[0306] A metal oxide (also referred to as an oxide conductor) can be used for the conductive layer 111, the conductive layer 112, and the conductive layer 115. Examples of the oxide conductor (OC) include In—Sn oxide (ITO), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide (ITSO), and In—Ga—Zn oxide.

[0307] Here, oxide conductors (OC) will be explained. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0308] The conductive layers 111, 112, and 115 may each have a stacked structure of a conductive layer containing the oxide conductor (metal oxide) and a conductive layer containing a metal or an alloy. By using a conductive layer containing a metal or an alloy, wiring resistance can be reduced.

[0309] A Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used for the conductive layer 111, the conductive layer 112, and the conductive layer 115. By using a Cu-X alloy, processing can be performed by a wet etching process, which makes it possible to reduce manufacturing costs.

[0310] Note that the conductive layers 111, 112, and 115 may be formed using the same material or different materials.

[0311] Here, the conductive layer 111 and the conductive layer 112 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 113 .

[0312] When an oxide semiconductor is used for the semiconductor layer 113, the conductive layers 111 and 112 are oxidized by oxygen contained in the semiconductor layer 113, which may increase the resistance. The conductive layers 111 and 112 are oxidized by oxygen contained in the insulating layer 103a, which may increase the resistance. Furthermore, the conductive layers 111 and 112 are oxidized by oxygen contained in the semiconductor layer 113, which may increase the oxygen vacancy (V Ｏ When the conductive layers 111 and 112 are oxidized by oxygen contained in the insulating layer 103a, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may decrease.

[0313] The conductive layers 111 and 112 are preferably made of a material that is resistant to oxidation. The conductive layers 111 and 112 are preferably made of an oxide conductor. For example, In—Sn oxide (ITO) or In—Sn—Si oxide (ITSO) can be suitably used. The conductive layers 111 and 112 may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layers 111 and 112 may have a stacked structure of the above-mentioned materials.

[0314] By using a material that is difficult to oxidize for the conductive layer 111 and the conductive layer 112, it is possible to prevent the conductive layer 111 and the conductive layer 112 from being oxidized by oxygen contained in the semiconductor layer 113 or oxygen contained in the insulating layer 103a, which can prevent the resistance from increasing. Ｏ ) in the semiconductor layer 113 can be suppressed, and the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 can be increased. Ｏ ) and V ＯH can be reduced. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability. Note that the conductive layers 111 and 112 may be made of the same material or different materials.

[0315] [Insulating Layer 105] The insulating layer 105 functioning as a gate insulating layer preferably has a low defect density. A low defect density in the insulating layer 105 enables the transistor to exhibit favorable electrical characteristics. Furthermore, the insulating layer 105 preferably has a high withstand voltage. A high withstand voltage of the insulating layer 105 enables the transistor 50 to have high reliability.

[0316] The insulating layer 105 can be formed using, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties. The insulating layer 105 can be formed using, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layer 105 can be formed as a single layer or a stacked layer. The insulating layer 105 can have, for example, a stacked structure of an oxide and a nitride.

[0317] In a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0318] The insulating layer 105 preferably releases little impurities (for example, water and hydrogen) from itself. The small amount of impurities released from the insulating layer 105 suppresses the impurities from diffusing into the semiconductor layer 113. Therefore, the transistor 50 can have favorable electrical characteristics and high reliability.

[0319] Since the insulating layer 105 is formed over the semiconductor layer 113, it is preferable that the insulating layer 105 be formed under conditions that cause little damage to the semiconductor layer 113. For example, it is preferable that the insulating layer 105 be formed under conditions that cause a sufficiently slow deposition rate, specifically, under conditions that cause a slower deposition rate than that of the insulating layer 103b. For example, when the insulating layer 105 is formed by a PECVD method, damage to the semiconductor layer 113 can be reduced by forming the insulating layer 105 under low power conditions.

[0320] Here, the insulating layer 105 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 113 .

[0321] In order to improve the interface characteristics with the semiconductor layer 113, it is preferable to use an oxide for the insulating layer 105. For example, one or more of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 105. It is more preferable to use a film that releases oxygen by heating for the insulating layer 105.

[0322] Note that the insulating layer 105 may have a stacked structure. The insulating layer 105 can have a stacked structure of an oxide film on a side in contact with the semiconductor layer 113 and a nitride film on a side in contact with the conductive layer 115. For example, one or more of silicon oxide and silicon oxynitride can be preferably used as the oxide film. For the nitride film, silicon nitride can be preferably used. When the insulating layer 105 has a stacked structure, it is preferable to use an oxide on at least the side of the insulating layer 105 in contact with the semiconductor layer 113 because the interface characteristics with the semiconductor layer 113 can be improved.

[0323] [Substrate 101] For example, there are no significant limitations on the material of the substrate 101, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 101. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 101. Furthermore, a printed circuit board may also be used as the substrate 101. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0324] A flexible substrate may be used as the substrate 101, and the transistor 50, for example, may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 101 and the transistor 50, etc. The peeling layer can be used to separate a display device, after a part or the whole of the display device is completed thereon, from the substrate 101 and transfer the display device to another substrate. In this case, for example, the transistor 50 can be transferred to a substrate with poor heat resistance or a flexible substrate.

[0325] [Insulating Layer 218] The insulating layer 218 is preferably made of a material that does not easily diffuse impurities. Thus, the insulating layer 218 functions as a blocking layer that prevents impurities from diffusing from the outside into the transistor. Examples of impurities include water and hydrogen. Providing the insulating layer 218 can improve the reliability of the display device.

[0326] The insulating layer 218 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as an oxide or a nitride can be suitably used for the insulating layer 218. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, silicon nitride oxide is suitable for use as the insulating layer 218 because it emits little impurities (e.g., water and hydrogen) from itself and can function as a blocking layer that suppresses impurity diffusion from above the transistor to the transistor. For example, one or more of an acrylic resin and a polyimide resin can be used as the organic material. A photosensitive material may be used as the organic material. Two or more of the above insulating films may be stacked. The insulating layer 218 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0327] [Insulating Layer 235] The insulating layer 235 has a function of reducing unevenness caused by the transistor 51, the transistor 52, the capacitor 57, and the like. In this specification and the like, the insulating layer 235 may be referred to as a planarizing layer.

[0328] An insulating layer containing an organic material can be suitably used for the insulating layer 235. As the organic material, a photosensitive organic resin is preferably used, and for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0329] The insulating layer 235 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, or precursors of these resins. The insulating layer 235 may also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. A photoresist may also be used as the photosensitive resin. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.

[0330] The insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer. For example, the insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. By providing an inorganic insulating layer on the outermost surface of the insulating layer 235, the inorganic insulating layer can function as an etching protection layer. This prevents a portion of the insulating layer 235 from being etched when the pixel electrode 311 is formed, thereby preventing the insulating layer 235 from becoming less flat.

[0331] If the top surface of the insulating layer 235, on which the light-emitting element 60 is formed, is not flat, for example, a connection failure due to a step disconnection of the common electrode 315 may occur. Furthermore, if the top surface of the insulating layer 235 is not flat, the film thickness of the common electrode 315 may become locally thin, resulting in an increase in electrical resistance. Furthermore, if the top surface of the insulating layer 235 is not flat, the processing accuracy of layers formed on the insulating layer 235 may decrease. By flattening the top surface of the insulating layer 235, for example, the processing accuracy of the light-emitting element 60 provided on the insulating layer 235 can be improved, thereby realizing a display device with high resolution. Furthermore, it is possible to suppress the occurrence of a connection failure due to a step disconnection of the common electrode 315 and the increase in electrical resistance due to a local thinning of the film thickness of the common electrode 315, thereby realizing a display device with high display quality.

[0332] Note that a part of the insulating layer 235 may be removed when forming the pixel electrode 311. The insulating layer 235 may have a recess in a region that does not overlap with the pixel electrode 311.

[0333] [Insulating Layer 237] The insulating layer 237 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. The insulating layer 237 can be made of a material that can be used for the insulating layer 218 or the insulating layer 235. The insulating layer 237 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0334] [Protective Layer 331] The protective layer 331 may have a single-layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 331 does not matter. The protective layer 331 can be made of at least one of an insulating film, a semiconductor film, and a conductive film.

[0335] The protective layer 331 having an inorganic film can prevent the common electrode 315 from being oxidized and prevent impurities (such as moisture and oxygen) from entering the light-emitting element 60. This prevents deterioration of the light-emitting element 60 and improves the reliability of the display device.

[0336] The protective layer 331 can be formed using an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an oxynitride insulating film, or an insulating nitride oxide film. The protective layer 331 can be an insulating layer containing an inorganic material. The protective layer 331 can be formed using an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an oxynitride insulating film, or an insulating nitride oxide film. The protective layer 331 can have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, the protective layer 331 preferably includes a nitride insulating film or a nitride oxide insulating film, and more preferably includes a nitride insulating film.

[0337] The protective layer 331 may be an inorganic film containing In—Sn oxide (ITO), In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, In—Ga—Zn oxide (IGZO), or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 315. The inorganic film may further contain nitrogen.

[0338] When light emitted from the light-emitting element 60 is extracted through the protective layer 331, it is preferable that the protective layer 331 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0339] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film, can be used for the protective layer 331. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0340] The protective layer 331 may be made of an organic material. For example, the protective layer 331 may be made of an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, or a precursor of any of these resins. The protective layer 331 may also be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. The protective layer 331 may also contain both inorganic and organic materials.

[0341] The protective layer 331 may have a two-layer structure formed by using different film formation methods. Specifically, the first layer of the protective layer 331 may be formed by the ALD method, and the second layer of the protective layer 331 may be formed by the sputtering method.

[0342] [Substrate 152] The substrate 152 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element 60 is extracted. Furthermore, using a flexible material for the substrate 152 can increase the flexibility of the display device. A polarizing plate may also be used as the substrate 152. Furthermore, a lamination film or a base film may also be used as the substrate 152.

[0343] The substrate 152 may be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, or the like), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, or the like. The substrate 152 may also be made of glass having a thickness sufficient to provide flexibility.

[0344] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display device. Therefore, it is preferable to use a film with low water absorption for the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0345] Various optical members can be disposed on the outside of the substrate 152. Examples of optical members include a polarizing plate (e.g., a circular polarizing plate), a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be disposed on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘThe surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ ), polyester-based materials, polycarbonate-based materials, etc. may be used for the surface protection layer. It is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0346] When a circularly polarizing plate is superimposed on a display device, it is preferable to use a substrate with high optical isotropy as the substrate of the display device. A substrate with high optical isotropy can also be said to have small birefringence (small amount of birefringence).

[0347] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0348] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0349] [Adhesive Layer 142] Various curable adhesives can be used for the adhesive layer 142, such as photo-curable adhesives such as ultraviolet curable adhesives, reactive curable adhesives, thermosetting adhesives, or anaerobic adhesives. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. Alternatively, an adhesive sheet may be used, for example.

[0350] [Light-shielding layer 317] Examples of materials that can be used for the light-shielding layer 317 include carbon black, titanium black, metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The light-shielding layer 317 can also be configured by stacking multiple layers containing the materials of the colored layers. For example, the light-shielding layer 317 can have a stacked structure of a layer containing the material used for a colored layer that transmits light of a certain color and a layer containing the material used for a colored layer that transmits light of another color.

[0351] The above is a description of the components.

[0352] <Memory Cell> One embodiment of the present invention can be applied not only to a display device but also to a memory device. FIG. 39A is a block diagram showing a configuration example of a memory device 400 to which one embodiment of the present invention can be applied. The memory device 400 includes a memory portion 410, a word line driver circuit 411, a bit line driver circuit 413, and a power supply circuit 415. The memory portion 410 includes a plurality of memory cells 420 arranged in a matrix. Note that the power supply circuit 415 may be provided outside the memory device 400.

[0353] The word line driving circuit 411 is electrically connected to the memory cells 420 via wiring 41. For example, similar to the display device 10 shown in Fig. 1, the wiring 41 extends in the row direction of the matrix. In the memory device 400, the wiring 41 functions as a word line.

[0354] The bit line driver circuit 413 is electrically connected to the memory cells 420 via wirings 43. For example, similar to the display device 10 shown in Figure 1, the wirings 43 extend in the column direction of the matrix. In the memory device 400, the wirings 41 function as bit lines.

[0355] The power supply circuit 415 is electrically connected to the memory cells 420 through a wiring 45. For example, all the memory cells 420 can be electrically connected to the power supply circuit 415 through the same wiring 45. The wiring 45 functions as a power supply line.

[0356] The word line driver circuit 411 has a function of selecting, for each row, a memory cell 420 to which data is to be written. The word line driver circuit 411 also has a function of selecting, for each row, a memory cell 420 from which data is to be read. Specifically, the word line driver circuit 411 can select a memory cell 420 to which data is to be written or a memory cell 420 from which data is to be read by outputting a signal to the wiring 41.

[0357] The bit line driver circuit 413 has a function of writing data to the memory cell 420 selected by the word line driver circuit 411 via the wiring 43. The bit line driver circuit 413 also has a function of amplifying the data output from the memory cell 420 to the wiring 43 and outputting the amplified data to, for example, the outside of the memory device 400, thereby reading out the data held in the memory cell 420. The bit line driver circuit 413 also has a function of precharging the wiring 43 before reading out data from the memory cell 420.

[0358] The power supply circuit 415 has a function of generating a power supply potential and supplying it to the wiring 45. The power supply circuit 415 has a function of generating a high potential or a low potential and supplying it to the wiring 45, for example.

[0359] 39B, 39C, 39D, 39E, and 39F are circuit diagrams showing configuration examples of the memory cell 420. Here, the memory cells 420 shown in Figures 39B, 39C, 39D, 39E, and 39F are referred to as memory cell 420A, memory cell 420B, memory cell 420C, memory cell 420D, and memory cell 420E, respectively.

[0360] The memory cell 420A includes a transistor 51 and a capacitor 57. That is, the memory cell 420A is a 1Tr1C type memory cell.

[0361] In the memory cell 420A, one of the source and the drain of the transistor 51 is electrically connected to the wiring 43. The other of the source and the drain of the transistor 51 is electrically connected to one electrode of the capacitor 57. The gate of the transistor 51 is electrically connected to the wiring 41. The other electrode of the capacitor 57 is electrically connected to the wiring 45.

[0362] In the memory cell 420A, data is written to the memory cell 420A through the wiring 43 by turning on the transistor 51, and the written data is held by turning off the transistor 51. Furthermore, by turning on the transistor 51, data held in the memory cell 420A can be output to the wiring 43, and the bit line driver circuit 413 can read the data.

[0363] The memory cell 420B includes a transistor 51, a transistor 52, and a capacitor 57. In other words, the memory cell 420B is a 2Tr1C type memory cell.

[0364] The memory cell 420B is electrically connected to wirings 41a and 41d as wirings 41, and to wirings 43a and 43b as wirings 43. Specifically, one of the source or drain of the transistor 51 is electrically connected to the wiring 43a. The other of the source or drain of the transistor 51 is electrically connected to one electrode of a capacitor 57. One electrode of the capacitor 57 is electrically connected to the gate of the transistor 52. The gate of the transistor 51 is electrically connected to the wiring 41a. The other electrode of the capacitor 57 is electrically connected to the wiring 41d. One of the source or drain of the transistor 52 is electrically connected to the wiring 43b. The other of the source or drain of the transistor 52 is electrically connected to the wiring 45.

[0365] In the memory cell 420B, data is written to the memory cell 420B through the wiring 43a by turning on the transistor 51, and the written data is retained by turning off the transistor 51. Therefore, in the memory cell 420B, the wiring 41a can be referred to as a write word line, and the wiring 43a can be referred to as a write bit line. Furthermore, by controlling the potential of the wiring 41d, the gate potential of the transistor 52 can be changed by capacitive coupling, and the potential of the wiring 43b can be set to a potential corresponding to the data retained in the memory cell 420B. This allows the bit line driver circuit 413 to read the data retained in the memory cell 420B. Thus, in the memory cell 420B, the wiring 41d can be referred to as a read word line, and the wiring 43b can be referred to as a read bit line.

[0366] The memory cell 420C is a modified example of the memory cell 420B, and shows an example in which the other of the source and the drain of the transistor 52 is electrically connected to the wiring 41d, and the other electrode of the capacitor 57 is electrically connected to the wiring 45. The word line driver circuit 411 controls the potential of the other of the source and the drain of the transistor 52, so that the memory cell 420C can output data held in the memory cell 420C to the wiring 43b.

[0367] The memory cell 420D is a modified example of the memory cell 420C, and differs from the memory cell 420C in that it includes a transistor 53. The memory cell 420D is a 3Tr1C type memory cell.

[0368] The memory cell 420D is electrically connected to wirings 41a and 41b as the wiring 41. Specifically, the gate of the transistor 53 is electrically connected to the wiring 41b. One of the source and the drain of the transistor 52 is electrically connected to the source and the drain of the transistor 53. The other of the source and the drain of the transistor 52 is electrically connected to the wiring 45. The other of the source and the drain of the transistor 53 is electrically connected to the wiring 43b.

[0369] The transistor 53 functions as a switch and controls the conduction or non-conduction state between the wiring 43b and one of the source and drain of the transistor 52 based on the potential of the wiring 41b. By turning on the transistor 53, the potential of the wiring 43b can be set to a potential corresponding to the data stored in the memory cell 420D. This allows the bit line driver circuit 413 to read the data stored in the memory cell 420D. As described above, in the memory cell 420D, the wiring 41b can be considered a read word line.

[0370] The memory cell 420E is a modification of the memory cell 420D, and differs from the memory cell 420D in that the memory cell 420E does not include the capacitor 57. In the memory cell 420E, the wiring 45 is electrically connected to the other of the source and the drain of the transistor 52.

[0371] For example, if the parasitic capacitance of the gate capacitance of the transistor 52 is sufficiently large, data can be held in the memory cell without providing the capacitor 57 .

[0372] An OS transistor is preferably used as the transistor 51 included in each of the memory cells 420A to 420E. As described above, an OS transistor has an extremely low off-state current. Therefore, by using an OS transistor as the transistor 51, charge stored in the capacitor 57 can be held for a long period of time. Furthermore, the gate potential of the transistor 52 can be held for a long period of time. As described above, data written to the memory cell 420 can be held for a long period of time, and therefore the frequency of refresh operations (rewriting data to the memory cell 420) can be reduced. Therefore, the power consumption of the memory device 400 can be reduced.

[0373] It is also preferable to use OS transistors as the transistors 52 and 53. As described above, OS transistors have higher field-effect mobility than, for example, transistors using amorphous silicon. Therefore, by using OS transistors as the transistors 51 to 53, the memory device 400 can be driven at high speed.

[0374] The memory cell 420A can be referred to as a DOSRAM (registered trademark). DOSRAM is an abbreviation for "Dynamic Oxide Semiconductor Random Access Memory." DOSRAM refers to a RAM having a 1Tr1C type memory cell. DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that utilizes the low off-state current of OS transistors.

[0375] The memory cells 420B to 420E can be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)." NOSRAM can read stored data without destroying it (nondestructive read). Therefore, NOSRAM is suitable for arithmetic processing that repeats a large number of data read operations.

[0376] <Configuration Example 2 of Semiconductor Device> Below, a description will be given of a configuration example of a transistor that is partially different from that of Figures 4A1, 4B, etc. Note that, below, descriptions of parts that overlap with Figures 4A1, 4B, etc. may be omitted.

[0377] 4A1 , in a plan view, both the Y-direction end and the −Y-direction end of the conductive layer 112 as viewed from the opening 123 have regions that overlap with the conductive layer 111. That is, the Y-direction end of the conductive layer 112 as viewed from the opening 123 is located inside the Y-direction end of the conductive layer 111 as viewed from the opening 123, and the −Y-direction end of the conductive layer 112 as viewed from the opening 123 is located inside the −Y-direction end of the conductive layer 111 as viewed from the opening 123. However, one embodiment of the present invention is not limited to this. FIG. 40A illustrates an example in which the −Y-direction end of the conductive layer 112 as viewed from the opening 123 does not overlap with the conductive layer 111 in a plan view. That is, in the example illustrated in FIG. 40A , the −Y-direction end of the conductive layer 112 as viewed from the opening 123 is located outside the −Y-direction end of the conductive layer 111 as viewed from the opening 123. For example, if the transistor 52 shown in Figure 6 has the structure shown in Figure 40A, the end of the conductive layer 112b in the region functioning as the transistor 52 can be configured to protrude toward the conductive layer 115a more than the end of the conductive layer 111b.

[0378] 40B shows an example in which, in a plan view, the end of the conductive layer 112 in the Y direction as viewed from the opening 123 does not overlap with the conductive layer 111. That is, in the example shown in Fig. 40B , the end of the conductive layer 112 in the Y direction as viewed from the opening 123 is positioned outside the end of the conductive layer 111 in the Y direction as viewed from the opening 123. For example, when the transistor 51 shown in Fig. 6 has the configuration shown in Fig. 40B , the end of the conductive layer 112a in the region functioning as the transistor 51 can be configured to protrude further than the end of the conductive layer 111a toward the region of the conductive layer 115a extending in the X direction.

[0379] 40C shows an example in which, in a plan view, neither the Y-direction end nor the −Y-direction end of conductive layer 112, as viewed from opening 123, overlaps with conductive layer 111. That is, in the example shown in Fig. 40C , the Y-direction end of conductive layer 112, as viewed from opening 123, is located outside the Y-direction end of conductive layer 111, as viewed from opening 123, and the −Y-direction end of conductive layer 112, as viewed from opening 123, is located outside the −Y-direction end of conductive layer 111, as viewed from opening 123.

[0380] Note that for a cross-sectional view of the configurations shown in FIGS. 40A, 40B, and 40C taken along the dashed dotted line A1-A2, refer to FIG. 4B.

[0381] Fig. 41A is a modified example of the configuration shown in Fig. 4A1, and Fig. 41B is a cross-sectional view taken along dashed line A1-A2 in Fig. 41A. Figs. 41A and 41B show an example in which the end of the conductive layer 115 is located inside the end of the semiconductor layer 113 in the X direction, i.e., on the opening 123 side. In the example shown in Figs. 41A and 41B, the semiconductor layer 113 has a region that does not overlap with the conductive layer 115. With this configuration, the area of ​​the region where the conductive layer 115 and the conductive layer 112 overlap can be reduced. This reduces parasitic capacitance.

[0382] Fig. 42A is a modified example of the configuration shown in Fig. 41A, and Fig. 42B is a cross-sectional view taken along dashed line A1-A2 in Fig. 42A. Figs. 42A and 42B show an example in which the end of conductive layer 115 is located more inward in the X direction than the end of conductive layer 112 on the opening 123 side. In the example shown in Figs. 42A and 42B, openings 121 and 123 have regions that do not overlap with conductive layer 115. This configuration can further reduce the area of ​​the overlapping region between conductive layer 115 and conductive layer 112. This can further reduce parasitic capacitance.

[0383] 43A is a modified example of the structure shown in FIG. 4A1 , and FIG. 43B1 is a cross-sectional view taken along dashed line A1-A2 in FIG. 43A . In FIGS. 43A and 43B1 , an example is shown in which, in the region where the conductive layer 111 and the conductive layer 112 overlap, the end of the conductive layer 115 in the X direction is positioned outside the end of the conductive layer 112. In the example shown in FIGS. 43A and 43B1 , the conductive layer 115 covers the entire region where the conductive layer 111 and the conductive layer 112 overlap. With this structure, for example, when the conductive layer 115 is formed using photolithography and etching, the alignment accuracy of the photomask can be reduced. Therefore, the transistor 50 can be easily manufactured.

[0384] 43B2 is a modified example of the configuration shown in Fig. 43B1, and shows an example in which the upper surface edge of the insulating layer 105 coincides or roughly coincides with the lower surface edge of the conductive layer 115. For example, when the conductive layer 115 is formed using a photolithography method and an etching method, if the etching selectivity between the conductive layer 115 and the insulating layer 105 is low, the configuration shown in Fig. 43B2 may be formed.

[0385] 43B3 is a modified example of the configuration shown in Fig. 43B2, and shows an example in which the bottom surface edge of conductive layer 115 is located inside the top surface edge of insulating layer 105, that is, on the conductive layer 112 side. For example, if the etching rate of conductive layer 115 in the X direction is faster than the etching rate of insulating layer 105 in the X direction, the configuration shown in Fig. 43B3 may be formed.

[0386] For a plan view of the configuration shown in Figures 43B2 and 43B3, refer to Figure 43A.

[0387] Figures 44A and 44B are modified examples of the configuration shown in Figure 4A1, and show an example in which openings 121 and 123 are rectangular with rounded corners in a plan view. Figure 44A shows an example in which the length of openings 121 and 123 in the X direction is longer than the length of openings 121 and 123 in the Y direction, and Figure 44B shows an example in which the length of openings 121 and 123 in the X direction is shorter than the length of openings 121 and 123 in the Y direction. Note that Figure 4B can be referred to for cross-sectional views of the configurations shown in Figures 44A and 44B.

[0388] In the example shown in Figures 44A and 44B, the side surface of the insulating layer 103 in the opening 121 and the side surface of the conductive layer 112 in the opening 123 have regions that are flat rather than curved. This improves the coverage of the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 inside the opening 121 and the opening 123. Note that, in a planar view, the corners of the openings 121 and 123 do not have to be rounded; for example, the planar shapes of the openings 121 and 123 may be rectangular, rhombic, or square. The planar shapes of the openings 121 and 123 may also be triangular or triangular with rounded corners. Furthermore, the planar shapes of the openings 121 and 123 may be polygonal, such as a pentagon, or polygonal shapes with rounded corners. The above is applicable to all configurations shown in this specification.

[0389] Fig. 45A1 is a modified example of the configuration shown in Fig. 4A1 , showing an example in which, in plan view, the conductive layer 112 covers part of the outer periphery of the opening 121 but does not cover the entirety. Fig. 45A2 is a modified example of the configuration shown in Fig. 45A1 , showing an example in which, in plan view, an end of the conductive layer 112 contacts the outer periphery of the opening 121 at a single point. In the example shown in Fig. 45A2, the opening 121 is circular in plan view, and one of the ends of the conductive layer 112 extending in the Y direction is a tangent to the opening 121. Fig. 45B is a cross-sectional view taken along dashed line A1-A2 shown in Figs. 45A1 and 45A2.

[0390] 45A1, 45A2, and 45B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be reduced. This reduces the parasitic capacitance. On the other hand, in the examples shown in FIG. 4A1, 4B, etc., the width of the other of the source region and the drain region can be increased.

[0391] 45A1 and 45A2, and shows an example in which, in plan view, conductive layer 112 does not cover opening 121 and conductive layer 112 is not in contact with opening 121. Fig. 46B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 46A.

[0392] 46A and 46B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be further reduced, thereby further reducing the parasitic capacitance.

[0393] Fig. 47A is a modified example of the configuration shown in Fig. 4A1, and shows an example in which conductive layer 111 does not entirely overlap opening 121 but overlaps only a portion of it. Fig. 47B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 47A. In the examples shown in Fig. 47A and 47B, semiconductor layer 113 has a region in opening 121 that does not overlap conductive layer 111.

[0394] 47A and 47B, it is possible to reduce the parasitic capacitance formed between the conductive layer 111 and the conductive layer 115. On the other hand, in the examples shown in Fig. 4A1 and 4B, it is possible to increase the width of one of the source region and the drain region.

[0395] Fig. 48A is a modified example of the configuration shown in Fig. 47A, and shows an example in which openings 121 and 123 are rectangular with rounded corners in a plan view. Fig. 48B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 48A.

[0396] 48A , the side surface of the insulating layer 103 in the opening 121 and the side surface of the insulating layer 103 in the opening 123 have regions that are flat rather than curved. This can improve the coverage of the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 inside the opening 121 and the opening 123. Note that while FIG. 48A shows an example in which the length of the opening 121 and the opening 123 in the X direction is longer than the length of the opening 121 and the opening 123 in the Y direction, the length of the opening 121 and the opening 123 in the X direction may be shorter than the length of the opening 121 and the opening 123 in the Y direction.

[0397] Fig. 49A1 is a modified example of the configuration shown in Fig. 47A , showing an example in which, in plan view, the conductive layer 112 covers part of the outer periphery of the opening 121 but does not cover the entirety. Fig. 49A2 is a modified example of the configuration shown in Fig. 49A1 , showing an example in which, in plan view, an end of the conductive layer 112 contacts the outer periphery of the opening 121 at a single point. In the example shown in Fig. 49A2 , the opening 121 is circular in plan view, and one of the ends of the conductive layer 112 extending in the Y direction is a tangent to the opening 121. Fig. 49B is a cross-sectional view taken along dashed line A1-A2 shown in Figs. 49A1 and 49A2 .

[0398] 49A1, 49A2, and 49B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be reduced. This reduces the parasitic capacitance. On the other hand, in the examples shown in FIGS. 47A and 47B, the width of the other of the source region and the drain region can be increased.

[0399] Fig. 50A is a modified example of the configuration shown in Fig. 49A1 and Fig. 49A2, and shows an example in which the conductive layer 112 does not overlap the opening 121. Fig. 50B is a cross-sectional view taken along the dashed dotted line A1-A2 shown in Fig. 50A.

[0400] 50A and 50B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be further reduced, thereby further reducing the parasitic capacitance.

[0401] Fig. 51A is a modified example of the configuration shown in Fig. 48A , and shows an example in which, in plan view, part of one side of opening 121 contacts an end of conductive layer 112 and the length of opening 121 in the X direction is shorter than the length in the Y direction. Fig. 51B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 51A .

[0402] 51A and 51B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be reduced, thereby reducing the parasitic capacitance. On the other hand, in the examples shown in FIGS. 48A and 48B, the width of the other of the source region and the drain region can be increased.

[0403] 52A is a modified example of the configuration shown in Fig. 51A, and shows an example in which the length of opening 121 in the X direction is longer than the length in the Y direction. In the example shown in Fig. 52A, it is possible to configure opening 121 so that one entire side thereof contacts the end of conductive layer 112 in plan view.

[0404] 52B is a modified example of the configuration shown in Fig. 52A, and shows an example in which, in plan view, parts of three sides of opening 121 contact the ends of conductive layer 112. In the example shown in Fig. 52B, in plan view, the entire side of opening 121 on the conductive layer 112 side extending in the Y direction and parts of the side extending in the X direction are covered by conductive layer 112.

[0405] 52B, the width of the other of the source region and the drain region can be increased. On the other hand, in the example shown in Fig. 52A, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be reduced, thereby reducing the parasitic capacitance. Note that Fig. 51B can be referred to for the cross-sectional view of the dashed dotted line A1-A2 shown in Fig. 52A and Fig. 52B.

[0406] Fig. 53A1 is a modified example of the configuration shown in Fig. 51A , showing an example in which, in a plan view, conductive layer 112 does not cover opening 121 and conductive layer 112 is not in contact with opening 121. Fig. 53A2 is a modified example of the configuration shown in Fig. 53A1 , showing an example in which the length of opening 121 in the X direction is longer than the length in the Y direction. Fig. 53B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Figs. 53A1 and 53A2.

[0407] 53A1, 53A2, and 53B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be further reduced, thereby further reducing the parasitic capacitance.

[0408] Fig. 54A is a modified example of the configuration shown in Fig. 4A1, showing an example in which the planar shape of opening 121 and the planar shape of opening 123 do not match. In the example shown in Fig. 54A, the planar shape of opening 123 is a circle with a larger radius than opening 121. Note that one or both of the planar shapes of opening 121 and opening 123 do not have to be circular. Specifically, one or both of the planar shapes of opening 121 and opening 123 can be the above-mentioned shapes, such as a rectangle with rounded corners. Fig. 54B1 is a cross-sectional view taken along dashed line A1-A2 shown in Fig. 54A.

[0409] For example, when openings 121 and 123 are formed in different processes, openings 121 and 123 may have the shapes shown in Figures 54A and 54B1. Even when openings 121 and 123 are formed in the same process, if the etching rate of conductive layer 112 in the X and Y directions is different from the etching rate of insulating layer 103 in the X and Y directions, openings 121 and 123 may have the shapes shown in Figures 54A and 54B1. For example, when the etching rate of conductive layer 112 in the X and Y directions is faster than the etching rate of insulating layer 103 in the X and Y directions, openings 121 and 123 may have the shapes shown in Figures 54A and 54B1, even when openings 121 and 123 are formed in the same process.

[0410] 54B2 is a modified example of the configuration shown in Fig. 54B1, and shows an example in which the upper surface of the semiconductor layer 113 has a region in contact with the conductive layer 112. For example, the configuration shown in Fig. 54B2 can be formed by forming an opening 121 in the insulating layer 103, then forming the semiconductor layer 113, and then depositing a film that will become the conductive layer 112 and forming an opening 123 in the film.

[0411] As described above, the channel width of the transistor 50 can be made equal to the length of the periphery of the opening 123 in a plan view. Therefore, for example, if the area of ​​the opening 123 is larger than the area of ​​the opening 121, the channel width of the transistor 50 can be increased in some cases. On the other hand, for example, if the area of ​​the opening 123 is equal to the area of ​​the opening 121, the transistor 50 can be miniaturized in some cases.

[0412] Fig. 55A is an enlarged view showing an example of the configuration of transistor 50 shown in Fig. 54B1 and its periphery, and Fig. 55B is an enlarged view showing an example of the configuration of transistor 50 shown in Fig. 54B2 and its periphery. As shown in Fig. 55A and Fig. 55B, the side surface of insulating layer 103a facing opening 121 has tapered portion 161a, and the side surface of insulating layer 103b facing opening 121 has tapered portion 161b.

[0413] 55A and 55B , the upper surface edge of insulating layer 103a on the opening 121 side and the lower surface edge of insulating layer 103b on the opening 121 side can be aligned or approximately aligned. Furthermore, the taper angle of tapered portion 161a and the taper angle of tapered portion 161b can be made equal or approximately equal. Here, the taper angle of the side surface of conductive layer 112 on the opening 123 side may be larger or smaller than the taper angles of tapered portions 161a and 161b. Furthermore, the taper angle of the side surface of conductive layer 112 on the opening 123 side may be equal or approximately equal to the taper angles of tapered portions 161a and 161b.

[0414] 56A and 56B are modified examples of the configurations shown in FIGS. 55A and 55B, respectively, showing examples in which the taper angle of tapered portion 161a is different from the taper angle of tapered portion 161b. In FIGS. 56A and 56B, the straight line extending from tapered portion 161b toward insulating layer 103a is shown by a dashed line. For example, if the materials of insulating layer 103a and insulating layer 103b are different, which results in differences in the processability of insulating layer 103a and insulating layer 103b, the taper angle of tapered portion 161a may be different from the taper angle of tapered portion 161b.

[0415] 56A and 56B show an example in which the taper angle of tapered portion 161a is smaller than the taper angle of tapered portion 161b. The taper angle of tapered portion 161a may be larger than the taper angle of tapered portion 161b. Here, the taper angle of the side surface of conductive layer 112 facing opening 123 may be larger or smaller than the taper angle of tapered portion 161a, and may also be larger or smaller than the taper angle of tapered portion 161b. Furthermore, the taper angle of the side surface of conductive layer 112 facing opening 123 may be equal to or approximately equal to the taper angle of tapered portion 161a, or may be equal to or approximately equal to the taper angle of tapered portion 161b.

[0416] 57A and 57B are modified examples of the configuration shown in Figures 55A and 55B, respectively, and show an example in which the upper surface edge of insulating layer 103a and the lower surface edge of insulating layer 103b do not coincide, specifically, an example in which the edge of insulating layer 103b on the opening 121 side is positioned outside the edge of insulating layer 103a on the opening 121 side. In Figures 57A and 57B, opening 121 provided in insulating layer 103a is referred to as opening 121a, and opening 121 provided in insulating layer 103b is referred to as opening 121b.

[0417] For example, if the etching rate of insulating layer 103a in the X direction is different from the etching rate of insulating layer 103b in the X direction, the upper surface edge of insulating layer 103a may not coincide with the lower surface edge of insulating layer 103b. Specifically, if the etching rate of insulating layer 103b in the X direction is faster than the etching rate of insulating layer 103a in the X direction, the configuration shown in Figures 57A and 57B may be formed. Here, the taper angle of tapered portion 161a and the taper angle of tapered portion 161b may be equal, approximately equal, or different. Furthermore, the taper angle of the side surface of conductive layer 112 facing opening 123 may be larger or smaller than the taper angle of tapered portion 161a, and may also be larger or smaller than the taper angle of tapered portion 161b. Furthermore, the taper angle of the side surface of the conductive layer 112 on the opening 123 side may be equal to or approximately equal to the taper angle of the tapered portion 161a, or may be equal to or approximately equal to the taper angle of the tapered portion 161b.

[0418] The taper angles of the side surfaces of the tapered portion 161a, the tapered portion 161b, and the conductive layer 112, as well as the positional relationship between the ends of the insulating layer 103a, the insulating layer 103b, and the conductive layer 112, which have been described using Figures 55A to 57B, can be applied to all configurations shown in this specification, etc.

[0419] Fig. 58A is a modified example of the configuration shown in Fig. 4A1, and shows an example in which the semiconductor layer 113 extends in the X direction beyond the end of the conductive layer 112 that does not face the opening 123. Fig. 58B is a cross-sectional view taken along the dashed dotted line A1-A2 shown in Fig. 58A.

[0420] 58B , when viewed from the XZ plane, the semiconductor layer 113 covers the end of the conductive layer 112 that does not face the opening 123. In addition, the semiconductor layer 113 can have a region in contact with the upper surface of the insulating layer 103.

[0421] 59A is a modified example of the configuration shown in Fig. 4A1, and shows an example in which, in the Y direction, the end of the semiconductor layer 113 is located outside the end of the conductive layer 112 and inside the end of the conductive layer 111. In the example shown in Fig. 59A, in the Y direction, the end of the semiconductor layer 113 overlaps with the conductive layer 111 but does not overlap with the conductive layer 112.

[0422] 59B is a modified example of the configuration shown in Fig. 4A1, and shows an example in which the end of the semiconductor layer 113 is located outside the end of the conductive layer 112 and the end of the conductive layer 111 in the Y direction. In the example shown in Fig. 59B, the end of the semiconductor layer 113 does not overlap with either the conductive layer 111 or the conductive layer 112 in the Y direction. Note that Fig. 4B can be referred to for the cross-sectional view of the dashed dotted line A1-A2 shown in Figs. 59A and 59B.

[0423] Fig. 60A is a modified example of the configuration shown in Fig. 4A1, and shows an example in which the transistor 50 has two openings 121 and two openings 123, which are arranged in the X direction. Fig. 60B is a cross-sectional view of the dashed dotted line A1-A2 shown in Fig. 60A. Here, in describing a configuration in which one transistor 50 has multiple openings 121 and multiple openings 123, the X direction may be referred to as the row direction and the Y direction may be referred to as the column direction.

[0424] 60A and 60B, the two openings 121 are distinguished by being labeled as opening 121_1 and opening 121_2, and the two openings 123 are distinguished by being labeled as opening 123_1 and opening 123_2. Also, in Fig. 60A and 60B, an example is shown in which different semiconductor layers 113 are provided inside the openings 121_1 and 123_1 and inside the openings 121_2 and 123_2, and these two semiconductor layers 113 are distinguished by being labeled as semiconductor layer 113_1 and semiconductor layer 113_2, respectively. Similar descriptions may be used in the subsequent drawings.

[0425] Fig. 61A is a modified example of the configuration shown in Fig. 60A , showing an example in which two openings 121 and openings 123 are arranged in the Y direction. Fig. 61B is a modified example of the configuration shown in Fig. 61A , showing an example in which one opening 121 and opening 123 are provided to the right of the two openings 121 and openings 123 arranged in the Y direction. Here, if the two openings 121 and openings 123 arranged in the Y direction are provided in a first row and one opening 121 and opening 123 is provided in a second row, for example, the centers of the openings 121 and openings 123 in the second row can be located between the centers of the upper openings 121 and openings 123 in the first row and the centers of the lower openings 121 and openings 123 in the first row in the Y direction.

[0426] 61C is a modified example of the configuration shown in Fig. 61A, and shows an example in which one opening 121 and one opening 123 are provided on the left and right sides of two openings 121 and 123 arranged in the Y direction. Here, if one opening 121 and one opening 123 are provided in the first row and the third row, and two openings 121 and 123 arranged in the Y direction are provided in the second row, for example, the centers of the openings 121 and 123 in the first row and the centers of the openings 121 and 123 in the third row can be located between the centers of the upper openings 121 and 123 in the second row and the centers of the lower openings 121 and 123 in the second row in the Y direction.

[0427] Fig. 62A is a modified example of the configuration shown in Fig. 4A1 , showing an example in which four openings 121 and openings 123 are arranged in a matrix of two rows and two columns. Fig. 62B is a modified example of the configuration shown in Fig. 60A , showing an example in which one opening 121 and opening 123 are provided below two openings 121 and opening 123 arranged in the X direction. Here, if two openings 121 and opening 123 arranged in the X direction are provided in the first row and one opening 121 and opening 123 is provided in the second row, for example, the centers of the openings 121 and opening 123 in the second row can be located between the centers of the openings 121 and opening 123 on the left side of the first row and the centers of the openings 121 and opening 123 on the right side of the first row in the X direction.

[0428] Fig. 62C is a modified example of the configuration shown in Fig. 62A, and shows an example in which the lower two openings 121 and opening 123 are located to the right of Fig. 62A. In the configuration shown in Fig. 62C, the four openings 121 and openings 123 are arranged in a zigzag pattern.

[0429] Fig. 63A is a modified example of the configuration shown in Fig. 4A1, showing an example in which nine apertures 121 and apertures 123 are arranged in a matrix of three rows and three columns. Fig. 63B is a modified example of the configuration shown in Fig. 63A, showing an example in which two apertures 121 and apertures 123 are provided in the center row. In the example shown in Fig. 63B, the apertures 121 and apertures 123 in the top row and the apertures 121 and apertures 123 in the center row are arranged in a zigzag pattern. In addition, in the example shown in Fig. 63B, the apertures 121 and apertures 123 in the bottom row and the apertures 121 and apertures 123 in the center row are arranged in a zigzag pattern.

[0430] Increasing the number of openings 121 and openings 123 provided in the transistor 50 may increase the total perimeter of the openings 121 and 123 in a plan view. As described above, the channel width of the transistor 50 may be equal to the perimeter of the opening 123 in a plan view. Therefore, providing the transistor 50 with a plurality of openings 121 and openings 123 may increase the channel width of the transistor 50. On the other hand, reducing the number of openings 121 and openings 123 provided in the transistor 50 may facilitate the fabrication of the transistor 50 and enable miniaturization of the transistor 50.

[0431] 64A is a modification of the configuration shown in Fig. 60A , and illustrates an example in which the semiconductor layer 113 provided inside openings 121_1 and 123_1 and the semiconductor layer 113 provided inside openings 121_2 and 123_2 are the same. That is, Fig. 64A illustrates an example in which the transistor 50 has two openings 121 and two openings 123, and one semiconductor layer 113. Fig. 64B is a cross-sectional view taken along dashed line A1-A2 shown in Fig. 64A .

[0432] 64A and 64B, for example, when the semiconductor layer 113 is formed by photolithography and etching, the alignment accuracy of the photomask can be reduced. Therefore, the transistor 50 can be easily manufactured. On the other hand, in the structures shown in FIGS. 60A and 60B, the surface area of ​​the semiconductor layer 113 can be reduced, which may prevent impurities from being mixed into the semiconductor layer 113. Note that the structures shown in FIGS. 61A to 63B can also include a single semiconductor layer 113.

[0433] Fig. 65A is a modified example of the configuration shown in Fig. 4A1, and shows an example in which conductive layer 112 extends in a direction parallel to conductive layer 115 and extends in a direction perpendicular to conductive layer 111. That is, in the example shown in Fig. 65A, conductive layer 112 and conductive layer 115 extend in the X direction, and conductive layer 111 extends in the Y direction. Fig. 65B is a cross-sectional view taken along dashed line A3-A4 shown in Fig. 65A.

[0434] Fig. 66 is a modification of the configuration shown in Fig. 6, in which the configuration of transistor 50 shown in Fig. 65A is applied to transistors 51 and 52. In the example shown in Fig. 66, conductive layer 112a has a first region overlapping with openings 121a and 123a, and a second region overlapping with opening 125a, and has a region extending in the Y direction from the first region toward the second region. On the other hand, in the example shown in Fig. 6, conductive layer 112a has a region extending in the X direction from the first region toward the second region.

[0435] 65A , in a plan view, both the Y-direction end and the −Y-direction end of the conductive layer 115 as viewed from the opening 123 have regions that overlap with the conductive layer 112. That is, the Y-direction end of the conductive layer 115 as viewed from the opening 123 is located inside the Y-direction end of the conductive layer 112 as viewed from the opening 123, and the −Y-direction end of the conductive layer 115 as viewed from the opening 123 is located inside the −Y-direction end of the conductive layer 112 as viewed from the opening 123, but this is not a limitation of one embodiment of the present invention. FIG. 67A illustrates an example in which the −Y-direction end of the conductive layer 115 as viewed from the opening 123 does not overlap with the conductive layer 112 in a plan view. That is, in the example illustrated in FIG. 67A , the −Y-direction end of the conductive layer 115 as viewed from the opening 123 is located outside the −Y-direction end of the conductive layer 112 as viewed from the opening 123.

[0436] 67B shows an example in which, in a plan view, the Y-direction end of conductive layer 115 as seen from opening 123 does not overlap with conductive layer 112. In other words, in the example shown in Fig. 67B, the Y-direction end of conductive layer 115 as seen from opening 123 is positioned outside the Y-direction end of conductive layer 112 as seen from opening 123.

[0437] 67C shows an example in which, in a plan view, neither the Y-direction end nor the −Y-direction end of conductive layer 115 as viewed from opening 123 overlaps with conductive layer 112. That is, in the example shown in Fig. 67C , the Y-direction end of conductive layer 115 as viewed from opening 123 is located outside the Y-direction end of conductive layer 112 as viewed from opening 123, and the −Y-direction end of conductive layer 115 as viewed from opening 123 is located outside the −Y-direction end of conductive layer 112 as viewed from opening 123.

[0438] Fig. 68A is a modified example of the configuration shown in Fig. 65A. Fig. 68A shows an example in which the end of the conductive layer 115 is located more inward than the end of the semiconductor layer 113 in the Y direction, that is, on the opening 123 side. In the example shown in Fig. 68A, the semiconductor layer 113 has a region that does not overlap with the conductive layer 115. With this configuration, the area of ​​the region where the conductive layer 115 and the conductive layer 112 overlap can be reduced. Therefore, the parasitic capacitance can be reduced.

[0439] Fig. 68B is a modified example of the configuration shown in Fig. 68A. Fig. 68B shows an example in which the end of conductive layer 115 is located more inward in the Y direction than the end of conductive layer 112 on the opening 123 side. In the example shown in Fig. 68B, openings 121 and 123 have areas that do not overlap with conductive layer 115. With this configuration, the area of ​​the overlapping area between conductive layer 115 and conductive layer 112 can be further reduced. Therefore, the parasitic capacitance can be further reduced.

[0440] For cross-sectional views of the dashed dotted line A3-A4 shown in Figures 67A, 67B, 67C, 68A, and 68B, refer to Figure 65B.

[0441] Fig. 69A is a modified example of the configuration shown in Fig. 65A , showing an example in which conductive layer 111 does not overlap the entirety of opening 121 but overlaps only a portion of it. Fig. 69B is a cross-sectional view taken along dashed dotted line A3-A4 shown in Fig. 69A . In the examples shown in Fig. 69A and Fig. 69B , semiconductor layer 113 has a region in opening 121 that does not overlap conductive layer 111.

[0442] 69A and 69B, it is possible to reduce the parasitic capacitance formed between the conductive layer 111 and the conductive layer 115. On the other hand, in the examples shown in Figures 65A and 65B, it is possible to increase the width of one of the source region and the drain region.

[0443] Fig. 70A1 is a modified example of the configuration shown in Fig. 69A , showing an example in which, in plan view, the conductive layer 112 covers part of the outer periphery of the opening 121 but does not cover the entirety. Fig. 70A2 is a modified example of the configuration shown in Fig. 70A1 , showing an example in which, in plan view, an end of the conductive layer 112 contacts the outer periphery of the opening 121 at a single point. In the example shown in Fig. 70A2, the opening 121 is circular in plan view, and one of the ends of the conductive layer 112 extending in the Y direction is a tangent to the opening 121. Fig. 70B is a cross-sectional view taken along dashed line A3-A4 shown in Figs. 70A1 and 70A2.

[0444] 70A1, 70A2, and 70B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be reduced, thereby reducing the parasitic capacitance. On the other hand, in the examples shown in FIGS. 69A and 69B, the width of the other of the source region and the drain region can be increased.

[0445] Fig. 71A is a modified example of the configuration shown in Fig. 70A1 and Fig. 70A2, and shows an example in which the conductive layer 112 does not overlap the opening 121. Fig. 71B is a cross-sectional view taken along the dashed dotted line A3-A4 shown in Fig. 71A.

[0446] 71A and 71B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be further reduced, thereby further reducing the parasitic capacitance.

[0447] Fig. 72A is a modified example of the configuration shown in Fig. 65A , and shows an example in which the semiconductor layer 113 extends in the X direction beyond the end of the conductive layer 112 that does not face the opening 123. Fig. 72B is a cross-sectional view taken along the dashed dotted line A3-A4 shown in Fig. 72A .

[0448] 72B , when viewed from the XZ plane, the semiconductor layer 113 covers the end of the conductive layer 112 that does not face the opening 123. In addition, the semiconductor layer 113 can have a region in contact with the upper surface of the insulating layer 103.

[0449] Fig. 73A is a modification of the configuration shown in Fig. 65A, and shows an example in which transistor 50 has two openings 121 and two openings 123, which are arranged in the X direction. Fig. 73B is a cross-sectional view taken along dashed line A3-A4 shown in Fig. 73A.

[0450] Fig. 74A is a modified example of the configuration shown in Fig. 73A , showing an example in which two openings 121 and openings 123 are arranged in the Y direction. Fig. 74B is a modified example of the configuration shown in Fig. 74A , showing an example in which one opening 121 and opening 123 are provided to the right of the two openings 121 and openings 123 arranged in the Y direction. Here, if the two openings 121 and openings 123 arranged in the Y direction are provided in a first row and one opening 121 and opening 123 is provided in a second row, for example, the centers of the openings 121 and openings 123 in the second row can be located between the centers of the upper openings 121 and openings 123 in the first row and the centers of the lower openings 121 and openings 123 in the first row in the Y direction.

[0451] 74C is a modified example of the configuration shown in Fig. 74A, and shows an example in which one opening 121 and one opening 123 are provided on the left and right sides of two openings 121 and 123 arranged in the Y direction. Here, if one opening 121 and one opening 123 are provided in the first row and the third row, and two openings 121 and 123 arranged in the Y direction are provided in the second row, for example, the centers of the openings 121 and 123 in the first row and the centers of the openings 121 and 123 in the third row can be located between the centers of the upper openings 121 and 123 in the second row and the centers of the lower openings 121 and 123 in the second row in the Y direction.

[0452] Fig. 75A is a modified example of the configuration shown in Fig. 65A , showing an example in which four openings 121 and openings 123 are arranged in a matrix of two rows and two columns. Fig. 75B is a modified example of the configuration shown in Fig. 73A , showing an example in which one opening 121 and opening 123 are provided below two openings 121 and opening 123 arranged in the X direction. Here, if two openings 121 and opening 123 arranged in the X direction are provided in the first row and one opening 121 and opening 123 is provided in the second row, for example, the centers of the openings 121 and opening 123 in the second row can be located between the centers of the openings 121 and opening 123 on the left side of the first row and the centers of the openings 121 and opening 123 on the right side of the first row in the X direction.

[0453] Fig. 75C is a modified example of the configuration shown in Fig. 75A, and shows an example in which the lower two openings 121 and opening 123 are located to the right of Fig. 75A. In the configuration shown in Fig. 75C, the four openings 121 and openings 123 are arranged in a zigzag pattern.

[0454] Fig. 76A is a modified example of the configuration shown in Fig. 65A , showing an example in which nine apertures 121 and apertures 123 are arranged in a matrix of three rows and three columns. Fig. 76B is a modified example of the configuration shown in Fig. 76A , showing an example in which two apertures 121 and apertures 123 are provided in the center row. In the example shown in Fig. 76B , the apertures 121 and apertures 123 in the top row and the apertures 121 and apertures 123 in the center row are arranged in a zigzag pattern. In addition, in the example shown in Fig. 76B , the apertures 121 and apertures 123 in the bottom row and the apertures 121 and apertures 123 in the center row are arranged in a zigzag pattern.

[0455] As described above, the total perimeter of the openings 121 and 123 in a plan view can be increased in some cases by increasing the number of the openings 121 and 123 provided in the transistor 50. As described above, the channel width of the transistor 50 can be equal to the perimeter of the opening 123 in a plan view, for example. Therefore, the channel width of the transistor 50 can be increased in some cases by providing a plurality of the openings 121 and 123 in the transistor 50. On the other hand, reducing the number of the openings 121 and 123 provided in the transistor 50 can facilitate the manufacture of the transistor 50 and enable miniaturization of the transistor 50 in some cases.

[0456] 77A is a modification of the configuration shown in Fig. 73A , and illustrates an example in which the semiconductor layer 113 provided inside the openings 121_1 and 123_1 is the same as the semiconductor layer 113 provided inside the openings 121_2 and 123_2. That is, Fig. 77A illustrates an example in which the transistor 50 has two openings 121 and two openings 123, and one semiconductor layer 113. Fig. 77B is a cross-sectional view taken along dashed line A3-A4 shown in Fig. 77A .

[0457] 77A and 77B, for example, when the semiconductor layer 113 is formed by photolithography and etching, the alignment accuracy of the photomask can be reduced. Therefore, the transistor 50 can be easily manufactured. On the other hand, in the structures shown in FIGS. 73A and 73B, the surface area of ​​the semiconductor layer 113 can be reduced, which may prevent impurities from being mixed into the semiconductor layer 113. Note that the structures shown in FIGS. 74A to 76B can also include a single semiconductor layer 113.

[0458] <Example 1 of Manufacturing Method of Display Device> A manufacturing method of a display device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the manufacturing method of a display device including the transistor 50 illustrated in FIGS. 4A1 and 4B will be described as an example.

[0459] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the display device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. CVD methods include a PECVD method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0460] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the display device may be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, or knife coating.

[0461] The thin film can be processed by, for example, forming a resist mask by photolithography and then etching the thin film according to the pattern of the resist mask. Alternatively, the thin film may be processed by nanoimprinting, sandblasting, lift-off, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask. Furthermore, a photosensitive thin film can be processed by exposure and development. In other words, a photosensitive thin film can be processed by photolithography.

[0462] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0463] The thin film can be etched by dry etching, wet etching, or the like.

[0464] 78A1 to 81B2 are diagrams illustrating a method for fabricating the configuration shown in Fig. 4A1 and Fig. 4B. A1 and B1 in each diagram are plan views, and A2 and B2 in each diagram are cross-sectional views taken along dashed line A1-A2 shown in each plan view.

[0465] [Formation of Conductive Layer 111] A conductive film that will become the conductive layer 111 is formed over the substrate 101. For example, a sputtering method can be suitably used for forming the conductive film. After a resist mask is formed on the conductive film by a photolithography process, the conductive film is processed to form an island-shaped conductive layer 111 that functions as one of a source electrode and a drain electrode (FIGS. 78A1 and 78A2). The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0466] [Formation of Insulating Layer 103a and Insulating Layer 103b] Next, the insulating layer 103a and the insulating layer 103b are formed on the substrate 101 and the conductive layer 111 (FIGS. 78B1 and 78B2). The insulating layer 103a and the insulating layer 103b can be formed, for example, by a PECVD method. After forming the insulating layer 103a, it is preferable to form the insulating layer 103b in succession in a vacuum without exposing the surface of the insulating layer 103a to the atmosphere. By successively forming the insulating layer 103a and the insulating layer 103b, it is possible to prevent impurities from the atmosphere from adhering to the surface of the insulating layer 103a. Examples of such impurities include water and organic substances.

[0467] The substrate temperature during the formation of the insulating layer 103a and the insulating layer 103b is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature within such a range during the formation of the insulating layer 103a and the insulating layer 103b, the release of impurities (e.g., water and hydrogen) from the insulating layer itself can be reduced, and the diffusion of the impurities into the semiconductor layer 113 formed in a later step can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be manufactured.

[0468] As described above, the insulating layer 103a and the insulating layer 103b are formed before the semiconductor layer 113. Therefore, there is no need to worry about oxygen being desorbed from the semiconductor layer 113 due to heat applied during the formation of the insulating layer 103a and the insulating layer 103b.

[0469] After the insulating layers 103a and 103b are formed, heat treatment may be performed. By performing the heat treatment, water and hydrogen can be released from the surfaces and the interior of the insulating layers 103a and 103b.

[0470] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being taken into the insulating layer 103a and the insulating layer 103b as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) device, etc. By using an RTA device, the heat treatment time can be shortened.

[0471] [Formation of Conductive Film 112f] Subsequently, a conductive film 112f that will become the conductive layer 112 is formed on the insulating layer 103b (FIGS. 79A1 and 79A2). The conductive film 112f can be preferably formed by, for example, sputtering.

[0472] [Formation of openings 121 and 123] Subsequently, the conductive film 112f is removed from a portion of the region overlapping with the conductive layer 111 to form a conductive layer 112A having an opening 123 (FIGS. 79B1 and 79B2). The opening 123 can be formed by, for example, either or both of a wet etching method and a dry etching method, and the wet etching method is preferably used.

[0473] Next, the insulating layer 103 (insulating layer 103a and insulating layer 103b) is removed from a portion of the region overlapping with the conductive layer 111. This forms an opening 121 in the insulating layer 103 (FIGS. 79B1 and 79B2). The opening 121 can be formed by, for example, either or both of a wet etching method and a dry etching method, with a dry etching method being preferred.

[0474] The opening 123 can be formed using, for example, the resist mask used to form the opening 121. Specifically, a resist mask is formed over the conductive film 112f, the conductive film 112f is removed using the resist mask to form the opening 123, and the insulating layer 103 is removed using the resist mask to form the opening 121. Note that by processing the width of the opening 123 to be larger than that of the resist mask, a transistor 50 in which the width of the opening 123 is larger than that of the opening 121 can be manufactured, as shown in FIG. 54A and FIG. 54B1 . Here, for example, when manufacturing a transistor 50 in which the width of the opening 123 is different from that of the opening 121, the opening 121 may be formed using a resist mask different from the resist mask used to form the opening 123.

[0475] [Formation of Conductive Layer 112] Subsequently, the conductive layer 112A is processed into a desired shape to form the conductive layer 112 (FIGS. 80A1 and 80A2). The conductive layer 112 can be formed by, for example, either a wet etching method or a dry etching method, or both, and the wet etching method is preferably used.

[0476] [Formation of Semiconductor Layer 113] Subsequently, a semiconductor film 113f that will become the semiconductor layer 113 is formed so as to cover the openings 121 and 123 (FIGS. 80B1 and 80B2). The semiconductor film 113f can be provided so as to have regions in contact with the upper surface and side surfaces of the conductive layer 112, the upper surface and side surfaces of the insulating layer 103, and the upper surface of the conductive layer 111.

[0477] The semiconductor film 113f is preferably formed by a sputtering method using a metal oxide target.

[0478] The semiconductor film 113f is preferably a dense film with as few defects as possible. Furthermore, the semiconductor film 113f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the semiconductor film 113f.

[0479] It is preferable to use oxygen gas when forming the semiconductor film 113f. By using oxygen gas when forming the semiconductor film 113f, oxygen can be suitably supplied into the insulating layer 103. For example, when an oxide is used for the insulating layer 103a, by using oxygen gas when forming the semiconductor film 113f, oxygen can be suitably supplied into the insulating layer 103a.

[0480] By supplying oxygen to the insulating layer 103a, oxygen is supplied to the semiconductor layer 113 in a later process, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0481] When forming the semiconductor film 113f, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, or xenon gas). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the semiconductor film 113f (oxygen flow ratio), the more the crystallinity of the semiconductor film 113f can be improved, resulting in a highly reliable transistor. On the other hand, the lower the oxygen flow ratio, the more the crystallinity of the semiconductor film 113f can be reduced, resulting in a transistor with a high on-state current.

[0482] The higher the substrate temperature when forming the semiconductor film 113f, the higher the crystallinity and density of the semiconductor film 113f. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the semiconductor film 113f.

[0483] The substrate temperature during the formation of the semiconductor film 113f may be set to a range from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, it is preferable to set the substrate temperature to a range from room temperature to less than 140° C., because productivity is increased. Furthermore, by setting the substrate temperature to room temperature or by forming the semiconductor film 113f without heating the substrate, the crystallinity can be reduced.

[0484] Before forming the semiconductor film 113f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 103 and a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment in an atmosphere containing oxygen may be performed. ２ Oxygen may be supplied to the insulating layer 103 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO). When plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while organic substances on the surface of the insulating layer 103 are suitably removed. After such treatment, it is preferable to form a semiconductor film 113f in succession without exposing the surface of the insulating layer 103 to the air.

[0485] In addition, when the semiconductor layer 113 has a stacked structure, it is preferable to form a metal oxide film first and then form a subsequent metal oxide film without exposing the surface of the first metal oxide film to the air.

[0486] Next, the semiconductor film 113f is processed into an island shape to form the semiconductor layer 113 (FIG. 81A1 and FIG. 81A2).

[0487] The semiconductor layer 113 can be formed by, for example, wet etching or dry etching, or both, and wet etching is preferably used. At this time, a part of the conductive layer 112 in a region that does not overlap with the semiconductor layer 113 may be etched and thinned. Similarly, a part of the insulating layer 103 in a region that does not overlap with either the semiconductor layer 113 or the conductive layer 112 may be etched and thinned. For example, the insulating layer 103b of the insulating layer 103 may be removed by etching, and the surface of the insulating layer 103a may be exposed. Note that by using a material having a high etching selectivity with respect to the semiconductor film 113f for the insulating layer 103b, the thickness of the insulating layer 103b can be prevented from being thinned.

[0488] Heat treatment is preferably performed after the semiconductor film 113f is formed or after the semiconductor film 113f is processed into the semiconductor layer 113. The heat treatment can remove hydrogen and water contained in the semiconductor film 113f or the semiconductor layer 113 or adsorbed on the surface of the semiconductor film 113f or the semiconductor layer 113. Furthermore, the heat treatment may improve the film quality of the semiconductor film 113f or the semiconductor layer 113; for example, defects in the semiconductor film 113f or the semiconductor layer 113 may be reduced and the crystallinity of the semiconductor film 113f or the semiconductor layer 113 may be improved.

[0489] By the heat treatment, oxygen can also be supplied from the insulating layer 103a to the semiconductor film 113f or the semiconductor layer 113. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 113. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0490] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be performed in a subsequent step. Furthermore, there are cases where a high-temperature treatment in a subsequent step, such as a film formation step, can also serve as the heat treatment.

[0491] [Formation of Insulating Layer 105] Subsequently, the insulating layer 105 is formed to cover the semiconductor layer 113, the conductive layer 112, and the insulating layer 103 (FIGS. 81B1 and 81B2). The insulating layer 105 can be preferably formed by PECVD.

[0492] When a metal oxide is used for the semiconductor layer 113, the insulating layer 105 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 105 has a function of suppressing oxygen diffusion, which suppresses oxygen from diffusing from above the insulating layer 105 to the conductive layer 115 formed in a later step, thereby suppressing oxidation of the conductive layer 115. As a result, a transistor with good electrical characteristics and high reliability can be manufactured.

[0493] By increasing the temperature during the formation of the insulating layer 105 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 105 is high, oxygen is released from the semiconductor layer 113, and oxygen vacancies (V Ｏ ) and V Ｏ H may increase. The substrate temperature during the formation of the insulating layer 105 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 105 within the above range, defects in the insulating layer 105 can be reduced and oxygen can be prevented from being released from the semiconductor layer 113. Therefore, a transistor with good electrical characteristics and high reliability can be manufactured.

[0494] Before forming the insulating layer 105, plasma treatment may be performed on the surface of the semiconductor layer 113. The plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 113. Therefore, impurities at the interface between the semiconductor layer 113 and the insulating layer 105 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable when the surface of the semiconductor layer 113 is exposed to the air between the formation of the semiconductor layer 113 and the formation of the insulating layer 105. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating layer 105 are preferably performed successively without exposure to the air.

[0495] [Formation of Conductive Layer 115] Subsequently, a conductive film to be the conductive layer 115 is formed over the insulating layer 105. The conductive film can be formed by, for example, a sputtering method. After a resist mask is formed over the conductive film by a photolithography process, the conductive film is processed to form the island-shaped conductive layer 115 that functions as a gate electrode.

[0496] Through the above steps, the transistor 50 shown in FIGS. 4A1 and 4B can be manufactured.

[0497] <Manufacturing Method Example 2 of Display Device> A manufacturing method different from the manufacturing method of the transistor 50 described in the above <Manufacturing Method Example 1 of Display Device> will be described. Note that descriptions of parts that overlap with the above description will be omitted, and only different parts will be described.

[0498] Figures 82A1, 82A2, 82B1, and 82B2 are diagrams illustrating a method for fabricating the configurations shown in Figures 4A1 and 4B. Figures 82A1 and 82B1 are plan views, and Figures 82A2 and 82B2 are cross-sectional views taken along dashed dotted lines A1-A2 shown in Figures 82A1 and 82B1, respectively.

[0499] First, the steps up to the formation of the conductive film 112f are performed in the same manner as in <Manufacturing method example 1 of a display device>. Since the description of the steps up to the formation of the conductive film 112f can be referred to in connection with FIGS. 78A1 to 79A2, detailed description thereof will be omitted.

[0500] Next, the conductive film 112f is processed to form the conductive layer 112B (FIGS. 82A1 and 82A2). Here, the opening 123 does not need to be formed in the conductive layer 112B. The conductive layer 112B can be formed by, for example, either or both of a wet etching method and a dry etching method, with the wet etching method being preferred.

[0501] Subsequently, the conductive layer 112B is removed from a portion of the region overlapping the conductive layer 111, thereby forming the conductive layer 112 having the opening 123.

[0502] Next, the insulating layer 103 (insulating layer 103a and insulating layer 103b) is removed from a portion of the region overlapping with the conductive layer 111. This forms an opening 121 in the insulating layer 103 (FIGS. 82B1 and 82B2).

[0503] The openings 121 and 123 can be formed by referring to the description in <Example 1 of manufacturing method of display device>, and therefore detailed description thereof will be omitted.

[0504] Subsequently, a semiconductor film 113f to be the semiconductor layer 113 is formed so as to cover the openings 121 and 123 (FIGS. 80B1 and 80B2). Since the above-described description of <Example 1 of manufacturing method of display device> can be referred to for the process after the formation of the semiconductor film 113f, detailed description thereof will be omitted.

[0505] Through the above steps, the transistor 50 having the structure shown in FIGS. 4A1 and 4B can be manufactured.

[0506] A plurality of configuration examples shown in this embodiment mode can be combined as appropriate. This embodiment mode can also be combined as appropriate with other embodiment modes.

[0507] Embodiment 2 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 83A to 83G and 84A to 84K.

[0508] The arrangement of the sub-pixels is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0509] The planar shape of the sub-pixel shown in the drawings in this embodiment corresponds to the planar shape of the light-emitting region (or light-receiving region).

[0510] The planar shape of the subpixel may be, for example, a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, a polygon with rounded corners, an ellipse, or a circle.

[0511] The layout of the circuits constituting the sub-pixels is not limited to the range of the sub-pixels shown in the figure, and may be arranged outside of the range.

[0512] An S-stripe arrangement is applied to the pixel 21 shown in Fig. 83A. The pixel 21 shown in Fig. 83A is composed of three types of sub-pixels: sub-pixel 23a, sub-pixel 23b, and sub-pixel 23c.

[0513] The pixel 21 shown in Figure 83B has sub-pixels 23a and 23b each having a substantially trapezoidal or triangular planar shape with rounded corners, and sub-pixel 23c having a substantially rectangular or hexagonal planar shape with rounded corners. Furthermore, sub-pixel 23b has a larger light-emitting area than sub-pixel 23a. In this way, the shape and size of each sub-pixel can be determined independently. For example, the more reliable the light-emitting element, the smaller the size of the sub-pixel can be.

[0514] The Pentile arrangement is applied to the pixels 21a and 21b shown in Fig. 83C. Fig. 83C shows an example in which pixels 21a having sub-pixels 23a and 23b and pixels 21b having sub-pixels 23b and 23c are arranged alternately.

[0515] The pixels 21a and 21b shown in Figures 83D to 83F are arranged in a delta arrangement. The pixel 21a has two subpixels (subpixels 23a and 23b) in the upper row (first row) and one subpixel (subpixel 23c) in the lower row (second row). The pixel 21b has one subpixel (subpixel 23c) in the upper row (first row) and two subpixels (subpixels 23a and 23b) in the lower row (second row).

[0516] Figure 83D is an example in which each sub-pixel has a roughly rectangular planar shape with rounded corners, Figure 83E is an example in which each sub-pixel has a circular planar shape, and Figure 83F is an example in which each sub-pixel has a roughly hexagonal planar shape with rounded corners.

[0517] In Figure 83F, each subpixel is arranged inside a closely packed hexagonal region. Focusing on a single subpixel, each subpixel is arranged so that it is surrounded by six other subpixels. Furthermore, subpixels that emit light of the same color are arranged so that they are not adjacent to each other. For example, focusing on subpixel 23a, three subpixels 23b and three subpixels 23c are arranged alternately to surround it.

[0518] 83G shows an example in which subpixels of each color are arranged in a zigzag pattern. Specifically, the positions of the upper sides of two subpixels aligned in the column direction (e.g., subpixels 23a and 23b, or subpixels 23b and 23c) are misaligned in a plan view.

[0519] 83A to 83G, it is preferable that, for example, subpixel 23a be subpixel R that emits red light, subpixel 23b be subpixel G that emits green light, and subpixel 23c be subpixel B that emits blue light. Note that the configuration of the subpixels is not limited to this, and the colors that the subpixels emit and their order of arrangement can be determined appropriately. For example, subpixel 23b may be subpixel R that emits red light, and subpixel 23a may be subpixel G that emits green light.

[0520] In photolithography, the finer the pattern to be processed, the more significant the effect of light diffraction becomes. This impairs the fidelity of the photomask pattern when it is transferred by exposure, making it difficult to process the resist mask into the desired shape. Therefore, even if the photomask pattern is rectangular, a pattern with rounded corners is likely to be formed. As a result, the planar shape of the subpixel may become a polygon with rounded corners, an ellipse, a circle, or the like.

[0521] In order to make the planar shape of the sub-pixel a desired shape, a technique for correcting the mask pattern in advance (OPC (Optical Proximity Correction) technique) may be used so that the design pattern and the transfer pattern coincide with each other. Specifically, with the OPC technique, a correction pattern is added to the corners of the figure on the mask pattern, for example.

[0522] As shown in Figures 84A to 84I, a pixel can be configured to have four types of sub-pixels.

[0523] The pixels 21 shown in FIGS. 84A to 84C are arranged in a stripe pattern.

[0524] Figure 84A is an example in which each subpixel has a rectangular planar shape, Figure 84B is an example in which each subpixel has a planar shape that combines two semicircles and a rectangle, and Figure 84C is an example in which each subpixel has an elliptical planar shape.

[0525] The pixels 21 shown in FIGS. 84D to 84F are arranged in a matrix.

[0526] Figure 84D is an example in which each sub-pixel has a square planar shape, Figure 84E is an example in which each sub-pixel has an approximately square planar shape with rounded corners, and Figure 84F is an example in which each sub-pixel has a circular planar shape.

[0527] 84G and 84H show an example in which one pixel 21 is configured in two rows and three columns.

[0528] The pixel 21 shown in Figure 84G has three subpixels (subpixels 23a, 23b, and 23c) in the top row (first row) and one subpixel (subpixel 23d) in the bottom row (second row). In other words, the pixel 21 has the subpixel 23a in the left column (first column), the subpixel 23b in the center column (second column), the subpixel 23c in the right column (third column), and further has the subpixels 23d across these three columns.

[0529] The pixel 21 shown in Figure 84H has three subpixels (subpixels 23a, 23b, and 23c) in the top row (first row) and three subpixels 23d in the bottom row (second row). In other words, the pixel 21 has subpixels 23a and 23d in the left column (first column), subpixels 23b and 23d in the center column (second column), and subpixels 23c and 23d in the right column (third column). By aligning the subpixels in the top and bottom rows as shown in Figure 84H, it becomes possible to efficiently remove dust that may occur during the manufacturing process. Therefore, a display device with high display quality can be provided.

[0530] FIG. 84I shows an example in which one pixel 21 is configured with three rows and two columns.

[0531] The pixel 21 shown in Figure 84I has subpixel 23a in the top row (first row), subpixel 23b in the center row (second row), subpixel 23c from the first row to the second row, and one subpixel (subpixel 23d) in the bottom row (third row). In other words, the pixel 21 has subpixels 23a and 23b in the left column (first column), subpixel 23c in the right column (second column), and subpixel 23d across these two columns.

[0532] The pixel 21 shown in FIGS. 84A to 84I is composed of four subpixels: a subpixel 23a, a subpixel 23b, a subpixel 23c, and a subpixel 23d.

[0533] The sub-pixels 23a, 23b, 23c, and 23d may each have a light-emitting element that emits light of a different color, such as sub-pixels of four colors R, G, B, and white (W), sub-pixels of four colors R, G, B, and Y, or sub-pixels of R, G, B, and infrared light (IR).

[0534] In each pixel 21 shown in Figures 84A to 84I, it is preferable that, for example, subpixel 23a be subpixel R that emits red light, subpixel 23b be subpixel G that emits green light, subpixel 23c be subpixel B that emits blue light, and subpixel 23d be any of subpixels W that emit white light, Y that emit yellow light, and IR that emit near-infrared light. With such a configuration, the pixel 21 shown in Figures 84G and 84H has a stripe layout of R, G, and B, thereby improving display quality. Furthermore, the pixel 21 shown in Figure 84I has a so-called S-stripe layout of R, G, and B, thereby improving display quality.

[0535] The pixel 21 may have a sub-pixel having a light-receiving element.

[0536] In each pixel 21 shown in FIGS. 84A to 84I, any one of the sub-pixels 23a to 23d may be a sub-pixel having a light-receiving element.

[0537] In each pixel 21 shown in Figures 84A to 84I, it is preferable that, for example, subpixel 23a is a subpixel R that emits red light, subpixel 23b is a subpixel G that emits green light, subpixel 23c is a subpixel B that emits blue light, and subpixel 23d is a subpixel S that has a light-receiving element. With this configuration, the pixel 21 shown in Figures 84G and 84H has a stripe layout of R, G, and B, which can improve display quality. Furthermore, the pixel 21 shown in Figure 84I has a so-called S-stripe layout of R, G, and B, which can improve display quality.

[0538] There are no particular limitations on the wavelength of light detected by the subpixel S having a light receiving element. The subpixel S can be configured to detect either or both of visible light and infrared light.

[0539] As shown in Figures 84J and 84K, a pixel can be configured to have five types of sub-pixels.

[0540] FIG. 84J shows an example in which one pixel 21 is configured in two rows and three columns.

[0541] The pixel 21 shown in Figure 84J has three subpixels (subpixels 23a, 23b, and 23c) in the top row (first row) and two subpixels (subpixels 23d and 23e) in the bottom row (second row). In other words, the pixel 21 has subpixels 23a and 23d in the left column (first column), subpixel 23b in the center column (second column), subpixel 23c in the right column (third column), and subpixel 23e from the second column to the third column.

[0542] FIG. 84K shows an example in which one pixel 21 is configured with three rows and two columns.

[0543] 84K has subpixel 23a in the top row (first row), subpixel 23b in the center row (second row), subpixel 23c from the first row to the second row, and two subpixels (subpixel 23d and subpixel 23e) in the bottom row (third row). In other words, pixel 21 has subpixels 23a, 23b, and 23d in the left column (first column), and subpixels 23c and 23e in the right column (second column).

[0544] In each pixel 21 shown in Figures 84J and 84K, it is preferable that, for example, subpixel 23a is a subpixel R that emits red light, subpixel 23b is a subpixel G that emits green light, and subpixel 23c is a subpixel B that emits blue light. With this configuration, the pixel 21 shown in Figure 84J has a stripe layout of R, G, and B, which can improve display quality. Furthermore, the pixel 21 shown in Figure 84K has a so-called S-stripe layout of R, G, and B, which can improve display quality.

[0545] In each pixel 21 shown in Figures 84J and 84K, for example, it is preferable to apply a subpixel S having a light receiving element to at least one of the subpixels 23d and 23e. When a light receiving element is used for both the subpixels 23d and 23e, the configurations of the light receiving elements may be different from each other. For example, the wavelength ranges of light detected may be at least partially different from each other. Specifically, one of the subpixels 23d and 23e may have a light receiving element that mainly detects visible light, and the other may have a light receiving element that mainly detects infrared light.

[0546] 84J and 84K, it is preferable that one of the subpixels 23d and 23e is a subpixel S having a light-receiving element, and the other is a subpixel having a light-emitting element that can be used as a light source. For example, it is preferable that one of the subpixels 23d and 23e is a subpixel IR that emits infrared light, and the other is a subpixel S having a light-receiving element that detects infrared light.

[0547] In a pixel having sub-pixels R, G, B, IR, and S, an image is displayed using the sub-pixels R, G, and B, and the sub-pixel IR is used as a light source, allowing the sub-pixel S to detect reflected infrared light emitted by the sub-pixel IR.

[0548] As described above, the display device of one embodiment of the present invention can employ various layouts for a pixel having a subpixel including a light-emitting element. The display device of one embodiment of the present invention can also employ a pixel having both a light-emitting element and a light-receiving element. In this case, various layouts can also be employed.

[0549] A plurality of configuration examples shown in this embodiment mode can be combined as appropriate. This embodiment mode can also be combined as appropriate with other embodiment modes.

[0550] Embodiment 3 In this embodiment, a display device according to one embodiment of the present invention will be described.

[0551] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type device for AR.

[0552] [Display Device 10A] Fig. 85 is a perspective view showing a configuration example of the display device 10A, and Fig. 86 is a cross-sectional view showing a configuration example of the display device 10A. The configuration of the display device 10 shown in the first embodiment can be applied to the display device 10A.

[0553] The display device 10A has a configuration in which a substrate 152 and a substrate 101 are bonded together. In Fig. 85, the substrate 152 is clearly indicated by a dashed line.

[0554] The display device 10A includes a display unit 20, a connection unit 140, a circuit 164, wiring 165, etc. Fig. 85 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 10A. Therefore, the configuration shown in Fig. 85 can also be said to be a display module including the display device 10A, an IC (integrated circuit), and an FPC.

[0555] In this specification and the like, a display device having a connector such as an FPC attached to a substrate, or a display device having an IC mounted on the substrate, is referred to as a display module.

[0556] The connection portion 140 is provided on the outside of the display portion 20. The connection portion 140 can be provided along one side or multiple sides of the display portion 20. The connection portion 140 may be single or multiple. Figure 85 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion. The connection portion 140 electrically connects the common electrode of the light-emitting element and the conductive layer, and a potential can be supplied to the common electrode via the conductive layer.

[0557] The circuit 164 can have at least one of the scanning line driver circuit 11, the signal line driver circuit 13, and the power supply circuit 15 shown in FIGS. 1A and 2A of Embodiment 1, and the reference potential generating circuit 17 shown in FIG. 2A.

[0558] The wiring 165 has a function of supplying signals and power to the display portion 20 and the circuit 164. The signals and power are input to the wiring 165 from the outside via the FPC 172 or input to the wiring 165 from the IC 173.

[0559] 85 shows an example in which an IC 173 is provided on a substrate 101 by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like. The IC 173 can include at least one of the scan line driver circuit 11, the signal line driver circuit 13, and the power supply circuit 15 shown in FIGS. 1A and 2A of Embodiment 1, and the reference potential generating circuit 17 shown in FIG. 2A. Note that the display device 10A and the display module may not include an IC. Alternatively, the IC may be mounted on an FPC by, for example, a COF method.

[0560] Figure 86 shows an example of a cross section of the display device 10A when cutting a portion of the area including the FPC 172, a portion of the circuit 164, a portion of the display unit 20, a portion of the connection portion 140, and a portion of the area including the end portion.

[0561] The display device 10A shown in FIG. 86 includes a transistor 201, a transistor 205R, a transistor 205G, a transistor 205B, a light-emitting element 60R, a light-emitting element 60G, and a light-emitting element 60B between a substrate 101 and a substrate 152. The light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B may have a structure similar to that of the light-emitting element 60 shown in FIG. 8B of Embodiment 1, for example. The pixel electrode 311 and the layer 313 included in the light-emitting element 60R are referred to as a pixel electrode 311R and a layer 313R, respectively. The pixel electrode 311 and the layer 313 included in the light-emitting element 60G are referred to as a pixel electrode 311G and a layer 313G, respectively. The pixel electrode 311 and the layer 313 included in the light-emitting element 60B are referred to as a pixel electrode 311B and a layer 313B, respectively. A common electrode 315 is provided on the layer 313R, the layer 313G, and the layer ...

Claims

1. A first conductive layer, A first insulating layer having a region positioned above the first conductive layer and having a first opening and a second opening that reach the first conductive layer, A second conductive layer having a region positioned above the first insulating layer, a third opening positioned such that it overlaps with the first opening in a plan view, and a fourth opening positioned such that it overlaps with the second opening in a plan view, A first oxide semiconductor layer having a region in the first opening facing the upper surface of the first conductive layer, a region in the first opening facing the side surface of the first insulating layer, a region in the third opening facing the side surface of the second conductive layer, and a region facing the upper surface of the second conductive layer, A second oxide semiconductor layer having a region in the second opening facing the upper surface of the first conductive layer, a region in the second opening facing the side surface of the first insulating layer, a region in the fourth opening facing the side surface of the second conductive layer, and a region facing the upper surface of the second conductive layer, The third conductive layer has a region facing the side surface of the first insulating layer at the first opening via the second insulating layer and the first oxide semiconductor layer, and a region facing the side surface of the first insulating layer at the second opening via the second insulating layer and the second oxide semiconductor layer, The first conductive layer functions as either the source electrode or the drain electrode of the transistor. The second conductive layer functions as either the source electrode or the drain electrode of the transistor. The third conductive layer has the function of a gate electrode of the transistor. Semiconductor equipment.

2. In Claim 1, Each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, zinc, and M (where M is one or more selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium, and hafnium).

3. A first conductive layer, A first insulating layer having a region positioned above the first conductive layer and having a first opening and a second opening that reach the first conductive layer, A second conductive layer having a region positioned above the first insulating layer, a third opening positioned such that it overlaps with the first opening in a plan view, and a fourth opening positioned such that it overlaps with the second opening in a plan view, An oxide semiconductor layer having a region in the first opening facing the upper surface of the first conductive layer, a region in the first opening facing the side surface of the first insulating layer, a region in the third opening facing the side surface of the second conductive layer, a region in the second opening facing the upper surface of the first conductive layer, a region in the second opening facing the side surface of the first insulating layer, a region in the fourth opening facing the side surface of the second conductive layer, and a region facing the upper surface of the second conductive layer, The present invention comprises a third conductive layer having a region facing the side surface of the first insulating layer at the first opening via a second insulating layer and the oxide semiconductor layer, The first conductive layer functions as either the source electrode or the drain electrode of the transistor. The second conductive layer functions as either the source electrode or the drain electrode of the transistor. The third conductive layer has the function of a gate electrode of the transistor. Semiconductor equipment.

4. In claim 3, The oxide semiconductor layer comprises indium, zinc, and M (where M is one or more selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium, and hafnium).

5. In any one of Claims 1 to 4, The pixel comprises the aforementioned transistor, a capacitive element, and a light-emitting element. The second conductive layer is electrically connected to the pixel electrode of the light-emitting element, The second conductive layer functions as the first electrode of the capacitive element. The third conductive layer functions as the second electrode of the capacitive element. Semiconductor equipment.