Light-emitting element, display device, and electronic device

Abstract

A light-emitting element according to an embodiment comprises: a semiconductor stack including a first semiconductor layer, an active layer, and a second semiconductor layer; a conductive layer disposed on a first surface of the semiconductor stack; a protective layer which is disposed on side surfaces of the conductive layer, a side surface of the semiconductor stack, and a first surface of the conductive layer, and which is spaced apart from a second surface opposite the first surface of the semiconductor stack; a contact electrode disposed on one surface of the semiconductor stack; and a selective reflective layer which is disposed, outside the protective layer, on the side surfaces of the conductive layer, the side surface of the semiconductor stack, and the first surface of the conductive layer, and which includes an opening overlapping the contact electrode. The reflective layer includes M (where M is an integer greater than or equal to 2) pairs of a first layer and a second layer, wherein the first layer of each pair is located closer to the semiconductor stack than the second layer, and the length of one end of the first layer in each pair may differ from the length of one end of the second layer.

Description

Light-emitting elements, display devices and electronic devices

[0001] The present invention relates to a light-emitting element, a display device, and an electronic device.

[0002] As the information society develops, demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel displays such as liquid crystal displays (LCDs), field emission displays (FEDs), and light emitting displays (LEDs).

[0003] The light-emitting display device may include an organic light-emitting display device including an organic light-emitting diode element as a light-emitting element, and an ultra-small light-emitting display device including a micro light-emitting diode element (hereinafter referred to as a micro light-emitting element) as a light-emitting element. Since the ultra-small light-emitting diode element is made of an inorganic material, it has the advantage of having a longer lifespan due to fewer deterioration issues compared to an organic light-emitting diode element.

[0004] The problem to be solved by the present invention is to provide a light-emitting element capable of separating the light-emitting element from a semiconductor substrate by low laser power, and a display device and electronic device using the same.

[0005] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] According to one embodiment of the present invention for solving the above problem, a light-emitting device includes a semiconductor layer stack including a first semiconductor layer, an active layer, and a second semiconductor layer, a conductive layer disposed on a first surface of the semiconductor layer stack, a protective layer disposed on side surfaces of the conductive layer, a side surface of the semiconductor stack, and the first surface of the conductive layer, and disposed away from a second surface opposite the first surface of the semiconductor stack, a contact electrode disposed on one surface of the semiconductor stack, and a selective reflective layer disposed on side surfaces of the conductive layer, a side surface of the semiconductor stack, and the first surface of the conductive layer outside the protective layer, and including an opening overlapping the contact electrode, wherein the selective reflective layer includes M pairs of first layers and second layers (M is an integer greater than or equal to 2), the first layer of each pair being disposed closer to the semiconductor stack than the second layer, and in each pair, a length of one end of the first layer is different from a length of one end of the second layer.

[0007] In one embodiment, the lengths of the first layers in different pairs of the semiconductor stacks are different from each other.

[0008] In one embodiment, the first layers of different pairs may have a shorter length closer to the light emitting element.

[0009] In one embodiment, the refractive index of the first layer may be lower than the refractive index of the second layer.

[0010] In one embodiment, the semiconductor stack may further include a third semiconductor layer disposed on the second semiconductor layer.

[0011] In one embodiment, the semiconductor stack may further include light extraction patterns formed on the upper surface of the semiconductor stack in a concave cross-sectional shape.

[0012] In one embodiment, the protective layer covers a side surface of the active layer, and a distance between the upper surface of the semiconductor stack and the protective layer in the height direction of the light emitting element may be greater than a maximum length of any one of the light extraction patterns in the height direction of the light emitting element.

[0013] In one embodiment, the protective layer and the first layer may be silicon oxide, and the second layer may be titanium oxide.

[0014] In one embodiment, the contact electrode may include a first contact electrode connected to the conductive layer that is exposed and not covered by the protective layer, and a second contact electrode connected to the second semiconductor layer that is exposed and not covered by the protective layer and the optional reflective layer.

[0015] The second contact electrode may be disposed in a hole penetrating the conductive layer and a portion of the semiconductor stack.

[0016] The above contact electrode can be connected to the conductive layer that is exposed and not covered by the protective layer.

[0017] According to one embodiment, a light-emitting device includes a substrate, a pixel electrode layer disposed on the substrate, and a light-emitting device disposed on the pixel electrode, the light-emitting device including a semiconductor layer stack including a first semiconductor layer, an active layer, and a second semiconductor layer, a conductive layer disposed on a first surface of the semiconductor layer stack, a protective layer disposed on side surfaces of the conductive layer, a side surface of the semiconductor stack, and the first surface of the conductive layer, and disposed away from a second surface opposite the first surface of the semiconductor stack, a contact electrode disposed on one surface of the semiconductor stack, and a selective reflective layer disposed on side surfaces of the conductive layer, a side surface of the semiconductor stack, and the first surface of the conductive layer outside the protective layer, and including an opening overlapping the contact electrode, wherein the selective reflective layer includes M pairs of first layers and second layers (M is an integer greater than or equal to 2), the first layer of each pair being disposed closer to the semiconductor stack than the second layer, and in each pair, a length of one end of the first layer may be different from a length of one end of the second layer.

[0018] In one embodiment, the pixel electrode layer may include a pixel electrode and a common electrode disposed spaced apart from the pixel electrode, and the contact electrode may include a first contact electrode connected to the conductive layer exposed without being covered by the protective layer, and a second contact electrode connected to the second semiconductor layer exposed without being covered by the protective layer and the selective reflective layer.

[0019] In one embodiment, the display device may further include an organic film disposed on a portion of the pixel electrode and the common electrode, a first connection electrode connecting the first contact electrode and the pixel electrode, and a second connection electrode connecting the second contact electrode and the common electrode.

[0020] In one embodiment, the pixel electrode layer includes a pixel electrode, the contact electrode is connected to the conductive layer that is exposed and not covered by the protective layer, and the display device may further include a common electrode disposed on the light-emitting element.

[0021] In one embodiment, the display device may further include an organic film disposed on the pixel electrode and a connection electrode connecting the contact electrode and the pixel electrode.

[0022] In one embodiment, a method for manufacturing a display device includes the steps of forming a second semiconductor material layer, an active material layer, a first semiconductor material layer, and a conductive material layer on a semiconductor substrate, etching the second semiconductor material layer, the active material layer, the first semiconductor material layer, and the conductive material layer to form light-emitting elements each including the second semiconductor layer, the active layer, the first semiconductor layer, and the conductive layer, forming a protective layer and a selective reflective layer surrounding each of the light-emitting elements, patterning the protective layer and the selective reflective layer by forming a mask pattern so as to cover the light-emitting elements, and dipping the light-emitting elements surrounded by the mask pattern into an etchant, wherein the dipping step can be performed until the protective layer on the side of the light-emitting elements is etched and separated from the semiconductor substrate.

[0023] In one embodiment, the step of forming the protective layer and the selective reflective layer includes the steps of forming a protective layer on the entire surface of the semiconductor substrate to cover each of the light-emitting elements, depositing a first material on the entire surface of the semiconductor substrate to cover the protective layer to form a first layer of the selective reflective layer, and depositing a second material on the entire surface of the semiconductor substrate to cover the first layer to form a second layer of the selective reflective layer, wherein the step of forming the first layer and the step of forming the second layer may be alternately repeated M times (M is an integer greater than or equal to 2).

[0024] The above dipping step can be stopped before the protective layer on the side of the light emitting element reaches the side of the active layer.

[0025] In one embodiment, the method for manufacturing a display device may further include the steps of forming a mask pattern on the protective layer and forming a contact electrode, and the steps of arranging the conductive layer of each of the light-emitting elements to face the target substrate, irradiating a laser to transfer the light-emitting elements to the target substrate, and separating the light-emitting elements from the semiconductor substrate.

[0026] Specific details of other embodiments are included in the detailed description and drawings.

[0027] According to the display device and the manufacturing method thereof according to the embodiments, the light-emitting element can be separated from the semiconductor substrate by low laser power, so that the transfer of the light-emitting element can be facilitated.

[0028] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0029] Figure 1 is a perspective view showing a display device according to one embodiment.

[0030] FIG. 2 is a layout diagram showing a display device according to one embodiment.

[0031] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0032] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0033] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0034] Fig. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5.

[0035] Figure 7 is a cross-sectional view showing in detail an example of area A of Figure 6.

[0036] Figure 8 is a cross-sectional view showing in detail an example of area B of Figure 7.

[0037] Figure 9 is a cross-sectional view showing another example of area B of Figure 7 in detail.

[0038] Figure 10 is a cross-sectional view showing another example of area A of Figure 6 in detail.

[0039] Figure 11 is a drawing showing an enlarged view of area B1 of Figure 10.

[0040] Figure 12 is another example drawing showing an enlarged view of area B of Figure 7.

[0041] Fig. 13 is a cross-sectional view showing another example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5.

[0042] Figure 14 is a cross-sectional view showing in detail an example of area A1 of Figure 13.

[0043] Figure 15 is a cross-sectional view showing another example of area A1 of Figure 13 in detail.

[0044] Figure 16 is a cross-sectional view showing another example of area A1 of Figure 13 in detail.

[0045] Fig. 17 is a cross-sectional view showing another example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5.

[0046] Figure 18 is a cross-sectional view showing in detail an example of area A1 of Figure 17.

[0047] FIG. 19 is a layout diagram showing pixels of a display area according to one embodiment.

[0048] Fig. 20 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 19.

[0049] Figure 21 is a cross-sectional view showing in detail an example of area A3 of Figure 20.

[0050] Figure 22 is a cross-sectional view showing another example of area A3 of Figure 20 in detail.

[0051] Fig. 23 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0052] FIGS. 24 to 29 and FIGS. 31 to 36 are drawings for explaining a method of manufacturing a display device according to one embodiment, and FIG. 30 is an image for explaining a protective layer and a selective reflective layer according to the dipping time of FIG. 29.

[0053] FIG. 37 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0054] FIGS. 38 and 39 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0055] FIG. 40 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment.

[0056] FIG. 41 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0057] FIG. 42 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0058] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0059] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0060] The individual features of the various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the others, or may be implemented together in a related manner.

[0061] Specific embodiments are described below with reference to the attached drawings.

[0062] Figure 1 is a perspective view showing a display device according to one embodiment.

[0063] Referring to FIG. 1, the display device (10) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT), etc.

[0064] The display device (10) may be a light-emitting display device such as an organic light-emitting display device (OLED) using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro or nano light emitting diode (micro LED or nano LED)). Hereinafter, the display device (10) is described mainly as an ultra-small light-emitting display device, but the present invention is not limited thereto. Meanwhile, for the convenience of explanation, an ultra-small light-emitting diode is described as a light-emitting element below.

[0065] The display device (10) includes a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply circuit (or power supply unit, 500).

[0066] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) intersecting the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a square, and may be formed in another polygonal, circular, or oval shape. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include a curved portion formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel (100) may be formed flexibly so as to be bent, curved, folded, or rolled.

[0067] The substrate (SUB in FIG. 6) of the display panel (100) may include a main area (MA) and a sub area (SBA).

[0068] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) that is a surrounding area of ​​the display area (DA). The display area (DA) may include a plurality of pixels that display an image. Each of the pixels may include a plurality of sub-pixels. For example, each of the pixels may include a first sub-pixel that emits light of a first color, a second sub-pixel that emits light of a second color, and a third sub-pixel that emits light of a third color, but the embodiments of the present specification are not limited thereto.

[0069] The sub-area (SBA) may protrude in a second direction (DR2) from one side of the main area (MA). In FIG. 1, the sub-area (SBA) is illustrated as being unfolded, but the sub-area (SBA) may be bent, in which case it may be disposed on the lower surface of the display panel (100). When the sub-area (SBA) is bent, it may overlap with the main area (MA) in the third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be disposed in the sub-area (SBA).

[0070] The display driving circuit (display driving unit, 250) can generate signals and voltages for driving the display panel (100). The display driving circuit (250) can be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) can be attached to a circuit board (PCB, 300) using a COF (chip on film) method.

[0071] The circuit board (300) may be attached to one end of the sub-area (SBA) of the display panel (100). As a result, the circuit board (300) may be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) may receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0072] The power supply circuit (500) can generate multiple panel driving voltages according to an external power voltage. The power supply circuit (500) can be formed as an integrated circuit (IC) and attached to a circuit board (300) using a COF method.

[0073] Fig. 2 is a layout diagram showing a display device according to one embodiment. Fig. 2 illustrates that the sub-area (SBA) is unfolded rather than bent.

[0074] Referring to FIG. 2, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0075] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may occupy most of the area of ​​the main area (MA). The display area (DA) may be positioned at the center of the main area (MA).

[0076] The display area (DA) includes a plurality of pixels (PX) for displaying an image, and each of the plurality of pixels (PX) may include a plurality of sub-pixels (SPX). A pixel (PX) may be defined as a sub-pixel group that is the smallest unit capable of expressing white gradation.

[0077] A non-display area (NDA) may be positioned adjacent to a display area (DA). The non-display area (NDA) may be an area outside the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0078] The first scan driver (SDC1) and the second scan driver (SDC2) may be disposed in a non-display area (NDA). The first scan driver (SDC1) may be disposed on one side (for example, the left side) of the display panel (100), and the second scan driver (SDC2) may be disposed on the other side (for example, the right side) of the display panel, but is not limited thereto. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to the display driver circuit (250) via scan fan-out lines. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driver circuit (250), generate scan signals according to the scan control signal, and output the scan signals to the scan lines.

[0079] The sub-area (SBA) may protrude from one side of the main area (MA) in a second direction (DR2). The length of the sub-area (SBA) in the second direction (DR2) may be shorter than the length of the main area (MA) in the second direction (DR2). The length of the sub-area (SBA) in the first direction (DR1) may be shorter than the length of the main area (MA) in the first direction (DR1) or may be substantially the same as the length of the main area (MA) in the first direction (DR1). The sub-area (SBA) may be curved and may be disposed at a lower portion of the display panel (100). In this case, the sub-area (SBA) may overlap the main area (MA) in the third direction (DR3).

[0080] The sub-area (SBA) may include a connection area (CA), a pad area (PA), and a bending area (BA).

[0081] The connection area (CA) is an area that protrudes in the second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) may be in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0082] The pad area (PA) is an area where pads (PD) and a display driving circuit (250) are arranged. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PD) of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. One side of the pad area (PA) can be in contact with the bending area (BA).

[0083] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) can be positioned below the connection area (CA) and below the main area (MA). The bending area (BA) can be positioned between the connection area (CA) and the pad area (PA). One side of the bending area (BA) can be in contact with the connection area (CA), and the other side of the bending area (BA) can be in contact with the pad area (PA).

[0084] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0085] Referring to FIG. 3, the display area (DA) includes a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of emission control lines (EL), and a plurality of data lines (DL).

[0086] A plurality of pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). For example, the plurality of pixels (PX) may be arranged in a matrix form composed of rows and columns along the first direction (DR1) and the second direction (DR2). A plurality of scan lines (SL) and a plurality of emission control lines (EL) may extend in the first direction (DR1) and be arranged in the second direction (DR2). A plurality of data lines (DL) may extend in the second direction (DR2) and be arranged in the first direction (DR1). The plurality of scan lines (SL) include a plurality of write scan lines (GWL), a plurality of initialization scan lines (GIL), and a plurality of bias scan lines (GBL).

[0087] Each of the plurality of sub-pixels (SPX) may be connected to one of the plurality of write scan lines (GWLs), one of the plurality of initialization scan lines (GILs), one of the plurality of bias scan lines (GBLs), one of the plurality of emission control lines (ELs), and one of the plurality of data lines (DLs). Each of the plurality of sub-pixels (SPX) may be supplied with a data voltage of the data line (DL) according to a write scan signal of the write scan line (GWL), and may emit light through a light-emitting element according to the data voltage.

[0088] The non-display area (NDA) includes a first scan driver (SDC1), a second scan driver (SDC2), and a display driver circuit (250).

[0089] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) may include a write scan signal output unit (611), an initialization scan signal output unit (612), a bias scan signal output unit (613), and an emission control signal output unit (614). Each of the write scan signal output unit (611), the initialization scan signal output unit (612), the bias scan signal output unit (613), and the emission control signal output unit (614) may receive a scan timing control signal (SCS) from a timing control circuit (251).

[0090] The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (251) and sequentially output them to write scan lines (GWL).

[0091] The initialization scan signal output unit (612) can generate initialization scan signals according to a scan timing control signal (SCS) and sequentially output them to initialization scan lines (GIL).

[0092] The bias scan signal output unit (613) can generate bias scan signals according to a scan timing control signal (SCS) and sequentially output them to bias scan lines (GBL).

[0093] The light emission control signal output unit (614) can generate light emission control signals according to a scan timing control signal (SCS) and sequentially output them to light emission control lines (EL).

[0094] The display driving circuit (250) includes a timing control circuit (timing control circuit section, 251) and a data driving circuit (data driving circuit section, 252).

[0095] The data driving circuit (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (251). The data driving circuit (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs the converted data voltages to the data lines (DL). In this case, the sub-pixels (SPX) are selected by the write scan signals of the first scan driving unit (SDC1) and the second scan driving unit (SDC2), and the data voltages can be supplied to the selected sub-pixels (SPX).

[0096] The timing control circuit (251) can receive digital video data (DATA) and timing signals from the outside. The timing control circuit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) for controlling the display panel (100) according to the timing signals. The timing control circuit (251) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control circuit (251) can output digital video data (DATA) and a data timing control signal (DCS) to the data driving circuit (252).

[0097] The power supply circuit (power supply circuit unit, 500) can generate a plurality of panel driving voltages according to a power voltage supplied from an external source. For example, the power supply circuit (500) can generate a first power voltage (VDD), a second power voltage (VSS), a third power voltage (VINT), and a fourth power voltage (VAINT) and supply them to the display panel (100).

[0098] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0099] Referring to FIG. 4, a sub-pixel (SPX) according to one embodiment may be connected to scan lines (GWL, GIL, GBL), an emission control line (EL), and a data line (DL). For example, the sub-pixel (SPX) may be connected to a write scan line (GWL), an initialization scan line (GIL), a bias scan line (GBL), an emission control line (EL), and a data line (DL).

[0100] A sub-pixel (SPX) according to one embodiment includes a driving transistor (DT), switch elements, a capacitor, and a light emitting element (LE). The switch elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0101] A driving transistor (DT) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls a drain-source current (Ids, hereinafter referred to as “driving current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0102] The light emitting element (LE) may be a micro light emitting diode.

[0103] The light emitting element (LE) emits light according to the driving current (Ids). The amount of light emitted by the light emitting element (LE) may be proportional to the driving current (Ids). The anode electrode of the light emitting element (LE) may be connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to the second power line (VSL) to which the second power voltage (VSS) is applied.

[0104] A capacitor (C1) is formed between a gate electrode of a driving transistor (DT) and a first power line (VDL) to which a first power voltage (VDD) is applied. The first power voltage (VDD) may be a voltage of a higher level than a second power voltage (VSS). One electrode of the capacitor (C1) may be connected to the gate electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0105] As shown in Fig. 4, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as p-type metal-oxide-semiconductor field-effect transistors (MOSFETs). In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon.

[0106] The gate electrode of the first transistor (ST1) and the gate electrode of the second transistor (ST2) may be connected to a write scan line (GWL), the gate electrode of the third transistor (ST3) may be connected to an initialization scan line (GIL), the gate electrode of the fourth transistor (ST4) may be connected to a bias scan line (GBL), and the gate electrodes of the fifth and sixth transistors (ST5, ST6) may be connected to an emission line (EL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) are formed of p-type MOSFETs, they may be turned on when a scan signal of a gate low voltage and an emission control signal are applied to the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the emission line (EL), respectively. One electrode of the third transistor (ST3) may be connected to a first initialization voltage line (VIL) to which a third power supply voltage (VINT of FIG. 3) is applied, and one electrode of the fourth transistor (ST4) may be connected to a second initialization voltage line (VIL, VAIL) to which a fourth power supply voltage (VAINT of FIG. 3) is applied. The third power supply voltage (VINT of FIG. 3) and the fourth power supply voltage (VAINT of FIG. 3) may be different voltages. In addition, the third power supply voltage (VINT of FIG. 3) and the fourth power supply voltage (VAINT of FIG. 3) may be a voltage at a lower level than the first power supply voltage (VDD) and a voltage at a higher level than the second power supply voltage (VSS).

[0107] Alternatively, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. In this case, the active layers of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as p-type MOSFETs may be formed of polysilicon, and the active layers of each of the first transistor (ST1) and the third transistor (ST3) formed as n-type MOSFETs may be formed of oxide semiconductors. In addition, since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) may be turned on when a scan signal of a gate high voltage is applied, and the third transistor (ST3) may be turned on when an initialization scan signal of a gate high voltage is applied. In comparison, the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, and thus can be turned on when a scan signal of a gate low voltage and a light emission control signal are applied.

[0108] Alternatively, when the fourth transistor (ST4) is formed as an n-type MOSFET and the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) are formed as p-type MOSFETs, the active layer of the fourth transistor (ST4) may be formed of an oxide semiconductor, and the active layers of each of the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be formed of polysilicon. In addition, the fourth transistor (ST4) may be turned on when a scan signal of a gate high voltage is applied, whereas the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be turned on when a scan signal of a gate low voltage and a light emission control signal are applied.

[0109] Alternatively, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) are formed of an oxide semiconductor and can be turned on when a scan signal of a gate high voltage and a light emission control signal are applied.

[0110] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0111] Referring to FIG. 5, each of the plurality of pixels (PX) of the display area (DA) may include three sub-pixels (SPX1, SPX2, SPX3), but the embodiment of the present specification is not limited thereto and may include four sub-pixels. When each of the plurality of pixels (PX) includes three sub-pixels, the three sub-pixels may include a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3).

[0112] A plurality of pixels (PX) can be arranged in a matrix form. In each of the plurality of pixels (PX), a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3) can be arranged in a first direction (DR1).

[0113] When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), the first sub-pixel (SPX1) can emit light of a first color, the second sub-pixel (SPX2) can emit light of a second color, and the third sub-pixel (SPX3) can emit light of a third color. Here, the light of the first color may be light in a red wavelength band, the light of the second color may be light in a green wavelength band, and the light of the third color may be light in a blue wavelength band. For example, the blue wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 370 nm to 460 nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 480 nm to 560 nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 600 nm to 750 nm.

[0114] Alternatively, when each of the plurality of pixels (PX) includes four sub-pixels, the first sub-pixel may emit light of a first color, the second and fourth sub-pixels may emit light of a second color, and the third sub-pixel may emit light of a third color. Alternatively, the first sub-pixel may emit light of a first color, the second sub-pixel may emit light of a second color, the third sub-pixel may emit light of a third color, and the fourth sub-pixel may emit light of a fourth color. In this case, the light of the fourth color may be white light.

[0115] A first sub-pixel (SPX1) includes a first pixel electrode (PXE1), a first common electrode (CE1), a plurality of light-emitting elements (LEs), and a first light conversion layer (QDL1). A second sub-pixel (SPX2) includes a second pixel electrode (PXE2), a second common electrode (CE2), a plurality of light-emitting elements (LEs), and a second light conversion layer (QDL2). A third sub-pixel (SPX3) includes a third pixel electrode (PXE3), a third common electrode (CE3), a plurality of light-emitting elements (LEs), and a light-transmitting layer (TPL).

[0116] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). The area of ​​the first sub-pixel (SPX1), the area of ​​the second sub-pixel (SPX2), and the area of ​​the third sub-pixel (SPX3) may be set according to the light conversion efficiency of the first light conversion layer (QDL1) and the light conversion efficiency of the second light conversion layer (QDL2). That is, the lower the light conversion efficiency, the larger the area of ​​the sub-pixel.

[0117] For example, as shown in FIG. 5, when the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1), and the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3).

[0118] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to a second electrode of a fourth transistor (ST4 of FIG. 4) and a second electrode of a sixth transistor (ST6 of FIG. 4) of the corresponding sub-pixel.

[0119] Each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) may have a rectangular planar shape. The area of ​​the first pixel electrode (PXE1) may be the same as the area of ​​the first common electrode (CE1), the area of ​​the second pixel electrode (PXE2) may be the same as the area of ​​the second common electrode (CE2), and the area of ​​the third pixel electrode (PXE3) may be the same as the area of ​​the third common electrode (CE3), but the embodiments of the present specification are not limited thereto.

[0120] In the first sub-pixel (SPX1), the first pixel electrode (PXE1) and the first common electrode (CE1) may be arranged to be spaced apart from each other in the second direction (DR2). In the second sub-pixel (SPX2), the second pixel electrode (PXE2) and the second common electrode (CE2) may be arranged to be spaced apart from each other in the second direction (DR2). In the third sub-pixel (SPX3), the third pixel electrode (PXE3) and the third common electrode (CE3) may be arranged to be spaced apart from each other in the second direction (DR2).

[0121] The first common electrode (CE1) can be connected to a second power line (VSL in FIG. 4) to which a second power voltage (VSS in FIG. 3) is applied through a first common connection hole (CT4). The second common electrode (CE2) can be connected to the second power line (VSL) through a second common connection hole (CT5). The third common electrode (CE3) can be connected to the second power line (VSL) through a third common connection hole (CT6). Therefore, the second power voltage (VSS) can be applied to each of the common electrodes (CE1, CE2, and CE3).

[0122] A plurality of light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3). At least a portion of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) may be exposed without the light emitting elements (LEs) being arranged thereon. The same number of light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). The plurality of light emitting elements (LEs) may emit light of a third color, i.e., light in a blue wavelength band, but the embodiments of the present specification are not limited thereto. When the light-emitting element (LE) of the first sub-pixel (SPX1) emits light of a first color, the light-emitting element (LE) of the second sub-pixel (SPX2) emits light of a second color, and the light-emitting element (LE) of the third sub-pixel (SPX3) emits light of a third color, the light conversion layers (QDL1, QDL2) and the light transmitting layer (TPL) may be omitted.

[0123] The first light conversion layer (QDL1) can completely overlap the first pixel electrode (PXE1), the first common electrode (CE1), and the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1) into first light.

[0124] The second light conversion layer (QDL2) can completely overlap the second pixel electrode (PXE2), the second common electrode (CE2), and the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the second light conversion layer (QDL2) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2) into second light.

[0125] The light transmitting layer (TPL) can completely overlap the third pixel electrode (PXE3), the third common electrode (CE3), and the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3). The light transmitting layer (TPL) can directly transmit incident light. For example, the light transmitting layer (TPL) can directly transmit third light emitted from the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3).

[0126] Fig. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5. Fig. 7 is a cross-sectional view showing in detail an example of area A of Fig. 6. Fig. 8 is a cross-sectional view showing in detail an example of area B of Fig. 7. Fig. 9 is a cross-sectional view showing in detail another example of area B of Fig. 7.

[0127] Referring to FIGS. 6 and 7, the substrate (SUB) may be made of an insulating material such as glass or a polymer resin. If the substrate (SUB) is made of a polymer resin, it may be a flexible substrate that can be stretched. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0128] A barrier film (BR) may be disposed on the substrate (SUB). The barrier film (BR) is a film that protects the transistors of the thin film transistor layer (TFTL) and the light emitting element layer (EML) from moisture penetrating through the substrate (SUB), which is vulnerable to moisture permeation. The barrier film (BR) may be composed of a plurality of inorganic films that are alternately laminated.

[0129] A thin film transistor (TFT1) may be arranged on the barrier film (BR). The thin film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) illustrated in FIG. 4. The thin film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0130] A first active layer (ACT1) of a thin film transistor (TFT1) may be disposed on the barrier film (BR). The first active layer (ACT1) of the thin film transistor (TFT1) may include polycrystalline silicon, single-crystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the first active layer (ACT1) of the thin film transistor (TFT1) may be formed of an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0131] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region overlapping the first gate electrode (G1) in a third direction (DR3) that is a thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions in which ions are doped into a semiconductor material to have conductivity.

[0132] A first gate insulating film (131) may be disposed on the first channel region (CHA1), the first source region (S1), the first drain region (D1) and the barrier film (BR) of the thin film transistor (TFT1).

[0133] A first gate metal layer may be disposed on the first gate insulating film (131). The first gate metal layer may include a first gate electrode (G1) of a thin film transistor (TFT1) and a first capacitor electrode (CAE1). The first gate electrode (G1) may overlap the first active layer (ACT1) in the third direction (DR3). Although FIG. 6 illustrates that the first gate electrode (G1) and the first capacitor electrode (CAE1) are disposed apart from each other, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be connected to each other.

[0134] A second gate insulating film (132) may be disposed on the first gate electrode (G1) and the first capacitor electrode (CAE1) of the thin film transistor (TFT1) and the first gate insulating film (131).

[0135] A second gate metal layer may be disposed on the second gate insulating film (132). The second gate metal layer may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap the first capacitor electrode (CAE1) of the thin film transistor (TFT1) in the third direction (DR3). Since the second gate insulating film (132) has a predetermined dielectric constant, a capacitor (C1 in FIG. 4) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating film (132) disposed therebetween.

[0136] A first interlayer insulating film (141) may be placed on the second capacitor electrode (CAE2) and the second gate insulating film (132).

[0137] A first data metal layer may be disposed on an interlayer insulating film (141). The first data metal layer may include a first source connection electrode (PCE1). The first source connection electrode (PCE1) may be connected to a first drain region (D) of a first active layer (ACT1) through a first source contact hole (PCT1) penetrating the first gate insulating film (131), the second gate insulating film (132), and the interlayer insulating film (141).

[0138] A first planarization organic film (160) may be placed on the first source connection electrode (PCE1) and the interlayer insulating film (141) to planarize the step caused by the thin film transistor (TFT1).

[0139] A second data metal layer may be disposed on the first planarization organic film (160). The second data metal layer may include a second source connection electrode (PCE2). The second source connection electrode (PCE2) may be connected to the first source connection electrode (PCE1) through a second pixel contact hole (PCT2) penetrating the first planarization organic film (160).

[0140] A second planarization organic film (180) may be placed on the second source connection electrode (PCE2) and the first planarization organic film (160).

[0141] The barrier film (BR), the first gate insulating film (131), the second gate insulating film (132), and the interlayer insulating film (141) are inorganic films, for example, silicon nitride (SiN). x ), silicon oxide nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed.

[0142] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0143] The first planarization organic film (160) and the second planarization organic film (180) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0144] A light-emitting element layer may be arranged on the second planarizing organic film (180). The light-emitting element layer may include pixel electrodes (PXE1, PXE2, PXE3), light-emitting elements (LE), common electrodes (CE1, CE2, CE3), and a first organic layer (210).

[0145] A pixel electrode layer may be arranged on the second planarizing organic film (180). The pixel electrode layer may include pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (CE1, CE2, CE3).

[0146] The pixel electrode layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, in order to lower the resistance of each of the pixel electrodes (PXE1, PXE2, PXE3), the pixel electrode layer may be made of copper (Cu) having a low surface resistance.

[0147] The first organic layer (210) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3). The first organic layer (210) may be disposed on some or all of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3). The first organic layer (210) serves to temporarily fix or adhere the plurality of light emitting elements (LEs) to prevent the plurality of light emitting elements (LEs) from tilting and falling over or falling over during the process of transferring the plurality of light emitting elements (LEs) to the display panel (100). That is, the first organic layer (210) may be a film for temporarily adhering the plurality of light emitting elements (LEs) onto each of the pixel electrodes (PXE1, PXE2, PXE3). To facilitate adhesion, the thickness of the first organic layer (210) may be greater than the thickness of each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3).

[0148] The first organic layer (210) may be a photosensitive organic film such as a photoresist. Alternatively, the first organic layer (210) may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0149] A plurality of light emitting elements (LEs) may be arranged on the first organic layer (210). In FIG. 6, it is exemplified that each of the plurality of light emitting elements (LEs) is a flip-type micro LED. A flip-type micro LED refers to an LED in which contact electrodes (CTE1, CTE2) are formed on one surface (e.g., the lower surface) of the light emitting element (LE).

[0150] Each of the plurality of light emitting elements (LEs) can be grown and formed on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light emitting elements (LEs) can be transferred directly from the semiconductor substrate onto the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) of the display panel (100). Alternatively, the plurality of light emitting elements (LEs) can be transferred onto the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) of the display panel (100) through an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0151] A light emitting element (LE) may include a conductive layer (E1), a semiconductor stack (STC), contact electrodes (CTE1, CTE2), a protective layer (INS), and a selective reflective layer (SRF). The semiconductor stack (STC) may include a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), and a third semiconductor layer (SEM3) sequentially arranged in a third direction (DR3).

[0152] The conductive layer (E1) may be disposed on the lower surface of the first semiconductor layer (SEM1). In Fig. 7, the conductive layer (E1) covers the entire lower surface of the first semiconductor layer (SEM1), but the embodiment of the present specification is not limited thereto. For example, the conductive layer (E1) may be disposed on a portion of the lower surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0153] A first semiconductor layer (SEM1) may be disposed on a conductive layer (E1) (or on a first contact electrode (CTE1) if the conductive layer (E1) is omitted), an active layer (MQW) may be disposed on the first semiconductor layer (SEM1), a second semiconductor layer (SEM2) may be disposed on the active layer (MQW), and a third semiconductor layer (SEM3) may be disposed on the second semiconductor layer (SEM2).

[0154] The first semiconductor layer (SEM1) may be formed of GaN doped with a first conductivity type dopant (e.g., a p-type dopant) such as Mg, Zn, Ca, Sr, or Ba.

[0155] The first semiconductor layer (SEM1) may be electrically connected to the pixel electrode (PXE) of each sub-pixel (SPX). For example, the first semiconductor layer (SEM1) may be electrically connected to the pixel electrode (PXE) of each sub-pixel (SPX) through the conductive layer (E1) and the first contact electrode (CTE1).

[0156] The active layer (MQW) can be disposed on the first semiconductor layer (SEM1). The active layer (MQW) can emit light by the combination of electron-hole pairs in response to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0157] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the active layer (MQW) may have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked, or may include different group III to group V semiconductor materials depending on the wavelength of the emitted light.

[0158] When the active layer (MQW) includes InGaN, the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer may shift toward a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer may shift toward a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of the light-emitting element (LE) that emits the third light (light in the blue wavelength band) may be approximately 10 wt% to 20 wt%.

[0159] The second semiconductor layer (SEM2) may be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be doped with a second conductivity type dopant, such as Si, Ge, Sn, etc. For example, the second semiconductor layer (SEM2) may be n-GaN doped with n-type Si.

[0160] The third semiconductor layer (SEM3) can be disposed on the second semiconductor layer (SEM2).

[0161] The third semiconductor layer (SEM3) is a semiconductor material layer having an n-type dopant lower than a predetermined threshold value, and may be referred to as an undoped semiconductor layer. For example, the third semiconductor layer (SEM3) may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN), having an n-type dopant lower than a predetermined threshold value.

[0162] An electron blocking layer may be positioned between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer that suppresses or prevents excessive electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0163] The superlattice layer may be positioned between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0164] Light extraction patterns (LEPs) can be formed on the upper surface of the semiconductor stack (STC). For example, the light extraction patterns (LEPs) can be formed on the upper surface of the third semiconductor layer (SEM3).

[0165] Light extraction patterns (LEPs) may be patterns for increasing the efficiency of light emitted from the upper surface of the light emitting element (LE). The light extraction patterns (LEPs) may be concave patterns formed in a hemisphere or a semi-ellipse. The light extraction patterns (LEPs) may be concave patterns having a cross-sectional shape of a semicircle or a semi-ellipse. The maximum length (Lmax) of the light extraction patterns (LEPs) in the third direction (DR3) may be approximately 100 nm. In addition, the distance between adjacent light extraction patterns (LEPs) may be approximately 100 nm or less.

[0166] The protective layer (INS) may be a film for protecting the light emitting element (LE) by being disposed on at least one side of the semiconductor stack (STC) and at least one side and a lower surface of the conductive layer (E1). Specifically, the protective layer (INS) is exemplified as being disposed on the lower surface and the side surfaces of the conductive layer (E1), the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), and the side surfaces of the second semiconductor layer (SEM2), and not disposed on the side surfaces of the third semiconductor layer (SEM3), but the embodiment of the present specification is not limited thereto. For example, the protective layer (INS) may be disposed on the side surfaces of the first semiconductor layer (SEM1) of the semiconductor stack (STC), the side surfaces of the active layer (MQW), and a portion of the side surface of the second semiconductor layer (SEM2).

[0167] A hole (LEH) can be formed that penetrates the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the light emitting element (LE) to expose the second semiconductor layer (SEM2). The hole (LEH) may have a circular planar shape, but the embodiments of the present specification are not limited thereto. For example, the hole (LEH) may have a polygonal planar shape, such as an ellipse or a square.

[0168] Additionally, the protective layer (INS) may be disposed on a sidewall of the conductive layer (E1) exposed in the hole (LEH), a sidewall of the first semiconductor layer (SEM1), a sidewall of the active layer (MQW) exposed by the hole (LEH), and a portion of the sidewall of the second semiconductor layer (SEM2) exposed in the hole (LEH). The protective layer (INS) may not cover the second semiconductor layer (SEM2) in the hole (LEH). Therefore, the second semiconductor layer (SEM2) may be exposed without being covered by the protective layer (INS).

[0169] The protective layer (INS) may have two openings (OP1, OP2). The two openings (OP1, OP2) may be spaced apart from each other. The first opening (OP1) may be disposed on the first surface of the light emitting element (LE), and the second opening (OP2) may be disposed to overlap the bottom of the hole (LEH). For example, the protective layer (INS) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), and the sidewall of the active layer (MQW). The protective layer (INS) may not cover the second semiconductor layer (SEM2) in the hole (LEH). Therefore, the second semiconductor layer (SEM2) may be exposed without being covered by the protective layer (INS).

[0170] The protective layer (INS) may be disposed on one side and a portion of a side surface of the light emitting element (LE). For example, the protective layer (INS) may be disposed on at least one side surface of the semiconductor stack (STC) and at least one side surface and a lower surface of the conductive layer (E1).

[0171] The protective layer (INS) may expose an area adjacent to the upper surface of the semiconductor stack (STC) among the side surfaces of the semiconductor stack (STC). For example, a distance (DS1) between the upper surface of the semiconductor stack (STC) and the protective layer (INS) in the third direction (DR3) may be greater than approximately 100 nm. In addition, the distance (DS1) between the upper surface of the semiconductor stack (STC) and the protective layer (INS) in the third direction (DR3) may be greater than a maximum length (Lmax) of the light extraction pattern in the third direction (DR3). Here, the third direction (DR3) may be substantially the same as the height direction (or thickness direction) of the light emitting element (LE). In this way, when the protective layer (INS) is spaced apart from the upper surface of the semiconductor stack (STC), the light emitting element (LE) can be easily separated from the base substrate on which the light emitting element (LE) is grown in a manufacturing process.

[0172] The protective layer (INS) is an inorganic film, for example, silicon nitride (SiN). x), silicon oxide nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed. In one embodiment, the protective layer (INS) is silicon oxide (SiO x ) may be.

[0173] The first contact electrode (CTE1) may be disposed on at least one side of the semiconductor stack (STC) and on at least one side and the lower surface of the conductive layer (E1). The first contact electrode (CTE1) may be disposed on the lower surface of the conductive layer (E1) that is exposed and not covered by the protective layer (INS). Therefore, the first contact electrode (CTE1) may be electrically connected to the conductive layer (E1) through the first opening (OP1).

[0174] The second contact electrode (CTE2) may be disposed on at least one side of the semiconductor stack (STC) and on at least one side and the lower surface of the conductive layer (E1). In this case, the first contact electrode (CTE1) may be disposed on the first side of the semiconductor stack (STC) and the first side of the conductive layer (E1), while the second contact electrode (CTE2) may be disposed on the second side of the semiconductor stack (STC) and the second side of the conductive layer (E1).

[0175] The second contact electrode (CTE2) can be disposed on the protective layer (INS) disposed in the hole (LEH) and the second semiconductor layer (SEM2) exposed in the hole (LEH) without being covered by the protective layer (INS). Therefore, the second contact electrode (CTE2) can be electrically connected to the hole (LEH) of the protective layer (INS) and the second semiconductor layer (SEM2) located in the second opening (OP2).

[0176] The first contact electrode (CTE1) and the second contact electrode (CTE2) are positioned spaced apart from each other on the lower surface of the conductive layer (E1) and do not contact each other. Therefore, the first contact electrode (CTE1) and the second contact electrode (CTE2) are not electrically connected to each other.

[0177] The first contact electrode (CTE1) and the second contact electrode (CTE2) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, the plurality of contact electrodes (CTEs) may be formed in a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to increase reflectivity.

[0178] A selective reflection layer (SRF) is disposed on the protective layer (INS), surrounds the side surfaces of the conductive layer (E1) and the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3), and can be disposed on one surface of the conductive layer (E1).

[0179] A selective reflection layer (SRF) may be disposed on the lower surface and side surfaces of the conductive layer (E1) and on the side surfaces of the semiconductor stack (STC). The selective reflection layer (SRF) may reflect light emitted from the active layer (MQW) of the light emitting element (LE) toward the upper portion of the light emitting element (LE). For example, the selective reflection layer (SRF) may be designed to primarily reflect light (λ1) of a first wavelength. The light (λ1) of the first wavelength may be light with a wavelength of 310 nm or less, but is not limited thereto.

[0180] The selective reflection layer (SRF) may extend from the side surface of the light emitting element (LE) on the protective layer (INS) and protrude outward from the upper surface of the light emitting element (LE). The protrusion direction may be a first direction (DR1) that is perpendicular to the third direction (DR3) that is the extension direction. For example, the selective reflection layer (SRF) may protrude outwardly perpendicular to the side surface of the light emitting element (LE).

[0181] The selective reflection layer (SRF) can be positioned higher than the height of the protective layer (INS).

[0182] A detailed description of the selective reflective layer (SRF) is provided below with reference to FIGS. 8 and 9.

[0183] The connection electrode (BE) includes a first connection electrode (BE1) and a second connection electrode (BE2), and connects the contact electrode (CTE) of the light emitting element (LE) and the pixel electrodes (PXE1 / PXE2 / PXE3) and the common electrodes (CE1, CE2, CE3). The first connection electrode (BE1) may be connected to the pixel electrode (PXE1 / PXE2 / PXE3) exposed through a connection hole (BH) penetrating the first organic layer (210). The second connection electrode (BE2) may be connected to the common electrodes (CE1, CE2, CE3) exposed in the first organic layer (210). In addition, the connection electrode (BE) may be disposed on the upper surface of the first organic layer (210) and the contact electrode (CTE).

[0184] The connecting electrode (BE) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the connecting electrode (BE) may be made of a transparent conductive material (TCO), such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0185] The connection electrode (BE) may be arranged on a side surface of the semiconductor stack (STC). Among the side surfaces of the semiconductor stack (STC), a region adjacent to a top surface of the semiconductor stack (STC) may be exposed without being covered by the connection electrode (BE). For example, a separation distance (DS2) between the top surface of the semiconductor stack (STC) and the connection electrode (BE) in the third direction (DR3) may be greater than approximately 100 nm. In addition, the separation distance (DS2) between the top surface of the semiconductor stack (STC) and the connection electrode (BE) in the third direction (DR3) may be greater than a maximum length (Lmax) of the light extraction pattern in the third direction (DR3).

[0186] The separation distance (DS2) between the top surface of the semiconductor stack (STC) and the connection electrode (BE) in the third direction (DR3) may be greater than the separation distance (DS1) between the top surface of the semiconductor stack (STC) and the contact electrode (CTE) in the third direction (DR3), but the embodiment of the present specification is not limited thereto. For example, the separation distance (DS2) between the top surface of the semiconductor stack (STC) and the connection electrode (BE) in the third direction (DR3) may be smaller than the separation distance (DS1) between the top surface of the semiconductor stack (STC) and the contact electrode (CTE) in the third direction (DR3). In this case, the connection electrode (BE) may cover at least a portion of the protective layer (INS) that is exposed and not covered by the contact electrode (CTE). Alternatively, the connection electrode (BE) may be arranged to cover the entirety of the protective layer (INS) that is exposed and not covered by the contact electrode (CTE). As another example, the separation distance (DS2) between the top surface of the semiconductor stack (STC) and the connecting electrode (BE) in the third direction (DR3) may be substantially equal to the separation distance (DS1) between the top surface of the semiconductor stack (STC) and the contact electrode (CTE) in the third direction (DR3).

[0187] The second organic film (211) may be arranged to cover a portion of a side surface of a plurality of light-emitting elements (LE). In addition, the second organic film (211) may be arranged to cover a connection electrode (BE).

[0188] The third organic film (212) may be disposed on the second organic film (211). The third organic film (212) may be disposed to cover another portion of a side surface of each of the plurality of light-emitting elements (LE). The third organic film (212) may be disposed on the protective layer (INS), the contact electrode (CTE), and the connection electrode (BE) that are not covered by the second organic film (211) and are exposed as shown in FIG. 7, but the embodiment of the present specification is not limited thereto. For example, the entire connection electrode (BE) may be covered by the second organic film (211). The upper surface of each of the plurality of light-emitting elements (LE) may be exposed and not covered by the third organic film (212).

[0189] The second organic film (211) and the third organic film (212) are layers for leveling the steps caused by the plurality of light-emitting elements (LE). If the height of the second organic film (211) is arranged to cover most of the side surfaces of each of the plurality of light-emitting elements (LE), the third organic film (212) may be omitted.

[0190] The second organic film (211) and the third organic film (212) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0191] The common electrodes (CE1, CE2, CE3) may be made of a transparent metal material (TCO, Transparent Conductive Material) such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide) that can transmit light.

[0192] The pixel electrodes (PXE1, PXE2, PXE3) may be referred to as anode electrodes or first electrodes, and the common electrodes (CE1, CE2, CE3) may be referred to as cathode electrodes or second electrodes.

[0193] The first capping layer (CAP1) can be disposed on the light emitting element (LE) and the third organic film (212).

[0194] A light-shielding layer (BM), a first light conversion layer (QDL1), a second light conversion layer (QDL2), and a light-transmitting layer (TPL) may be disposed on a first capping layer (CAP1). The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light-transmitting layer (TPL) may be formed by the partitioning of the light-shielding layer (BM). Therefore, in the first sub-pixel (SPX1), the first light conversion layer (QDL1) may be disposed on the first capping layer (CAP1), in the second sub-pixel (SPX2), the second light conversion layer (QDL2) may be disposed on the first capping layer (CAP1), and in the third sub-pixel (SPX3), the light-transmitting layer (TPL) may be disposed on the first capping layer (CAP1). The light-shielding layer (BM) may not overlap with a plurality of light-emitting elements (LE) in the third direction (DR3).

[0195] The first light conversion layer (QDL1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band). The first light conversion layer (QDL1) can include a first base resin (BRS1) and a first wavelength conversion particle (WCP1). The first base resin (BRS1) can include a light-transmitting organic material. The first wavelength conversion particle (WCP1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band).

[0196] The second light conversion layer (QDL2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band). It can include a second base resin (BRS2) and second wavelength conversion particles (WCP2). The second base resin (BRS2) can include a light-transmitting organic material. The second wavelength conversion particles (WCP2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band).

[0197] The optically transparent layer (TPL) may include a light-transmitting organic material.

[0198] For example, the first base resin (BRS1), the second base resin (BRS2), and the light transmitting layer (TPL) may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first and second wavelength conversion particles (WCP1, WCP2) may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials.

[0199] The light-blocking layer (BM) may include a first light-blocking layer (BM1) and a second light-blocking layer (BM2) that are sequentially laminated. The length of the first light-blocking layer (BM1) in the first direction (DR1) or the length of the second direction (DR2) may be wider than the length of the second light-blocking layer (BM2) in the first direction (DR1) or the length of the second light-blocking layer (BM2) in the second direction (DR2). The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may include a light-blocking material to prevent light from a light-emitting element (LE) of a sub-pixel from propagating to an adjacent sub-pixel. For example, the first shading layer (BM1) and the second shading layer (BM2) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0200] The second capping layer (CAP2) may be disposed on the first capping layer (CAP1) and the light-shielding layer (BM). The second capping layer (CAP2) may be disposed on the side surface and the upper surface of the light-shielding layer (BM). That is, the second capping layer (CAP2) may be disposed on the side surface of the first light-shielding layer (BM1) and the side surface and the upper surface of the second light-shielding layer (BM2).

[0201] A reflective film (RF) may be disposed between a light-shielding layer (BM) and a first light conversion layer (QDL1), between a light-shielding layer (BM) and a second light conversion layer (QDL2), and between a light-shielding layer (BM) and a light-transmitting layer (TPL). The reflective film (RF) may be disposed on a second capping layer (CAP2) disposed on a side surface of the first light-shielding layer (BM1) and a side surface of the second light-shielding layer (BM2). The reflective film (RF) serves to reflect light that propagates in a lateral direction in the first light-conversion layer (QDL1), the second light-conversion layer (QDL2), and the light-transmitting layer (TPL).

[0202] The reflective film (RF) may include a highly reflective metal material, such as aluminum (Al). The thickness of the reflective film (RF) may be approximately 0.1 μm.

[0203] Alternatively, the reflective film (RF) may include M pairs of first and second layers having different refractive indices (M is an integer greater than or equal to 2) to function as distributed Bragg reflectors (DBRs). In this case, the M first layers and the M second layers may be arranged alternately. Within the same pair, the first layer may be arranged further inward of the light emitting element than the second layer, and the refractive index of the first layer may be lower than the refractive index of the second layer. The difference between the refractive index of the first layer and the refractive index of the second layer may be greater than or equal to 0.55.

[0204] The first and second layers are inorganic films, for example, silicon nitride (SiN). x ), silicon oxide nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed.

[0205] The third capping layer (CAP3) can be disposed on the second capping layer (CAP2), the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL).

[0206] The first capping layer (CAP1), the second capping layer (CAP2), and the light transmitting layer (TPL) are inorganic films, for example, silicon nitride (SiN). x ), silicon oxide nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x) can be formed. The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL) can be encapsulated by the first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3).

[0207] A fourth organic film (213) may be disposed on the third capping layer (CAP3). A plurality of color filters (CF1, CF2, CF3) may be disposed on the fourth organic film (213). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0208] The first color filter (CF1) arranged in the first sub-pixel (SPX1) can transmit the first light (light in the red wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the first color filter (CF1) can transmit the first light (light in the red wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer (QDL1). Therefore, the first sub-pixel (SPX1) can emit the first light (light in the red wavelength band).

[0209] The second color filter (CF2) arranged in the second sub-pixel (SPX2) can transmit the second light (light in the green wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the second color filter (CF2) can transmit the second light (light in the green wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer (QDL1). Therefore, the second sub-pixel (SPX2) can emit the second light (light in the green wavelength band).

[0210] The third color filter (CF3) arranged in the third sub-pixel (SPX3) can transmit the third light (light in the blue wavelength band). Therefore, the third color filter (CF3) can transmit the third light (light in the blue wavelength band) emitted from the light-emitting element (LE) passing through the light-transmitting layer (TPL). Therefore, the third sub-pixel (SPX3) can emit the third light (light in the blue wavelength band).

[0211] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) overlapping in the third direction (DR3) can overlap with the light-shielding layer (BM) and the light-shielding layer (BM) in the third direction (DR3).

[0212] A fifth organic film (214) for planarization may be placed on multiple color filters (CF1, CF2, CF3).

[0213] The fourth organic film (213) and the fifth organic film (214) can be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0214] Fig. 8 is a drawing showing an enlarged view of area B of Fig. 7. Fig. 9 is a drawing showing an enlarged view of area B of Fig. 7 according to another example.

[0215] Referring to FIGS. 8 and 9, an example of a selective reflective layer (SRF) can be seen in detail.

[0216] Referring to FIGS. 8 and 9, the selective reflection layer (SRF) can function as a distributed Bragg reflector. That is, the selective reflection layer (SRF) can reflect light of a first wavelength and transmit light of other wavelengths. The first wavelength may be a target reflection wavelength that the selective reflection layer (SRF) is intended to reflect.

[0217] In order for the selective reflection layer (SRF) to function as a distributed Bragg reflector, it includes M pairs of first layers (LL1) and second layers (LL2) (M is an integer greater than or equal to 2). The M first layers (LL1) and M second layers (LL2) may be arranged alternately. In each of the M pairs, the first layer (LL1) may be arranged closer to the light emitting element (LE) than the second layer (LL2). For example, the three pairs of first layers (LL1) and second layers (LL2) of the selective reflection layer (SRF) may be arranged in the following order: semiconductor stack (STC), protective layer (INS), first layer (LL1), second layer (LL2), first layer (LL1), second layer (LL2).

[0218] The selective reflection layer (SRF) may include M pairs of first and second layers having different refractive indices (M is an integer greater than or equal to 2) to function as distributed Bragg reflectors (DBR). In this case, the M first layers and the M second layers may be arranged alternately. The first and second layers may be formed of an inorganic film, for example, silicon nitride (SiN x ), silicon oxide nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed.

[0219] In each of the M pairs, the first layer (LL1) may include a material such as a protective layer (INS). The first layer (LL1) and the protective layer (INS) may be etched by the first etchant, while the second layer (LL2) may not be etched by the first etchant. For example, the first layer (LL1) and the protective layer (INS) may be silicon oxide (SiO x ) is formed, and the second layer (LL2) is titanium oxide (TiO x ) can be formed.

[0220] In each M pair, the first layer (LL1) can be formed shorter than the second layer (LL2).

[0221] In each of the M pairs, the first layer (LL1) may be arranged spaced apart from one end of the light emitting element (LE).

[0222] The first layers (LL1) of the M pair may have different lengths. For example, the first layers (LL1) may be formed to be longer as they move away from the light emitting element (LE), but this is not limited thereto.

[0223] For example, referring to Fig. 8, a first pair, a second pair, and a third pair are arranged in an outward direction from the light emitting element (LE). The first layer (LL1) of the first pair may have the same height as the protective layer (INS). On the other hand, the first layer (LL1) of the second pair may be longer than the first layer (LL1) of the first pair, and the first layer (LL1) of the third pair may be longer than the first layer (LL1) of the second pair.

[0224] Additionally, the second layer (LL2) may protrude outwardly from the upper surface of the light emitting element (LE). The protrusion direction may be a first direction (DR1) that is perpendicular to the third direction (DR3), which is the extension direction. For example, the second layer (LL2) may protrude outwardly perpendicular to the side surface of the light emitting element (LE). On the other hand, the first layer (LL1) may not protrude outwardly perpendicular to the side surface of the light emitting element (LE).

[0225] Referring to FIG. 9, the first layer (LL1) positioned closest to the light-emitting element (LE) may have the same height as the protective layer (INS). On the other hand, the first layer (LL1) positioned farthest from the light-emitting element (LE) is longer than the first layer (LL1) positioned closest to the light-emitting element (LE). On the other hand, the length of the first layer (LL1) positioned in the middle may be the longest.

[0226] When a light-emitting element (LE) includes a light extraction pattern (LEP) on the upper surface, a selective reflection layer (SRF) adjacent to the upper surface of the light-emitting element (LE) may also follow the shape of the light extraction pattern (LEP). In one embodiment, the selective reflection layer (SRF) may include a portion of a concave pattern having a cross-sectional shape of a semicircle or a semi-ellipse.

[0227] Figure 10 is a cross-sectional view showing another example of area A of Figure 6 in detail.

[0228] The embodiment of Fig. 10 differs from the embodiment of Fig. 7 in that the light emitting element (LE) does not include a light extraction pattern (LEP). In Fig. 10, descriptions that overlap with the embodiment of Fig. 7 are omitted, and descriptions are focused on differences from the embodiment of Fig. 7.

[0229] Referring to Fig. 10, the upper portion of the semiconductor stack (STC) does not include a light extraction pattern (LEP). In the example of Fig. 10, the semiconductor stack (STC) includes, but is not limited to, a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), and a third semiconductor layer (SEM3). The semiconductor stack (STC) may include the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2), and may not include the third semiconductor layer (SEM3).

[0230] Fig. 11 is a drawing showing an enlarged view of area B1 of Fig. 10. Fig. 12 is a drawing showing another example showing an enlarged view of area B of Fig. 7.

[0231] FIGS. 11 and 12 differ from the embodiments of FIGS. 8 and 9 in that the light emitting element (LE) does not include a light extraction pattern (LEP). In FIGS. 11 and 12, descriptions that overlap with the embodiments of FIGS. 8 and 9 will be omitted, and differences from the embodiments of FIGS. 8 and 9 will be mainly described.

[0232] Since the light emitting element (LE) does not include a light extraction pattern (LEP), the selective reflection layer (SRF) adjacent to the upper surface of the light emitting element (LE) also does not include a concave pattern and can be formed parallel to one end of the light emitting element (LE).

[0233] Fig. 13 is a cross-sectional view showing another example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5. Fig. 14 is a cross-sectional view showing in detail an example of area A1 of Fig. 13.

[0234] The embodiments of FIGS. 13 and 14 differ from the embodiments of FIGS. 6 and 7 in that the first organic layer (210) and the connection electrode (BE) are omitted, and the contact electrode (CTE1), the pixel electrodes (PXE1, PXE2, PXE3), and the common electrodes (CE1, CE2, CE3) are directly connected. In FIGS. 13 and 14, descriptions overlapping with those of the embodiments of FIGS. 6 and 7 are omitted, and descriptions are focused on differences from the embodiments of FIGS. 6 and 7.

[0235] Referring to FIGS. 13 and 14, the contact electrodes (CTE1, CTE2) may have a columnar shape.

[0236] The first contact electrode (CTE1) may be disposed on the conductive layer (E1) exposed through the first opening (OP1) of the protective layer (INS). The first contact electrode (CTE1) may be formed to protrude outward from the conductive layer (E1).

[0237] The first contact electrode (CTE1) is disposed on the pixel electrodes (PXE1, PXE2, PXE3) and can be electrically connected to each other.

[0238] The second contact electrode (CTE2) may be disposed on the second semiconductor layer (SEM2) exposed through the second opening (OP2) of the protective layer (INS) provided in the hole (LEH). The first contact electrode (CTE1) may be formed to protrude outward from the conductive layer (E1).

[0239] The second contact electrode (CTE2) is disposed on the common electrodes (CE1, CE2, CE3) and can be electrically connected to each other.

[0240] The protrusion length (WCTE1) of the first contact electrode (CTE1) and the protrusion length (WCTE2) of the second contact electrode (CTE2) may be the same, but are not limited thereto. If the protrusion length (WCTE1) of the first contact electrode (CTE1) and the protrusion length (WCTE2) of the second contact electrode (CTE2) are the same, the light emitting element (LE) can be stably placed on the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) without tilting.

[0241] Figure 15 is a cross-sectional view showing another example of area A1 of Figure 13 in detail.

[0242] The embodiment of Fig. 15 differs from the embodiment of Fig. 14 in that the light emitting element (LE) does not include a light extraction pattern (LEP). In Fig. 15, descriptions that overlap with the embodiment of Fig. 14 are omitted, and descriptions are focused on differences from the embodiment of Fig. 14.

[0243] Referring to Fig. 15, the upper portion of the semiconductor stack (STC) does not include a light extraction pattern (LEP). In the example of Fig. 15, the semiconductor stack (STC) includes, but is not limited to, a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), and a third semiconductor layer (SEM3). The semiconductor stack (STC) may include the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2), and may not include the third semiconductor layer (SEM3).

[0244] Figure 16 is a cross-sectional view showing another example of area A1 of Figure 13 in detail.

[0245] The embodiment of Fig. 16 differs from the embodiment of Fig. 14 in the shape of the semiconductor stack (STC) of the light emitting element (LE). In Fig. 16, descriptions that overlap with the embodiment of Fig. 14 are omitted, and descriptions are focused on differences from the embodiment of Fig. 14.

[0246] Referring to FIG. 16, the light emitting element (LE) may include a conductive layer (E1), a semiconductor stack (STC), a first electrode (CT1), a second electrode (CT2), a protective layer (INS), and a selective reflective layer (SRF). The semiconductor stack (STC) may include a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), and a third semiconductor layer (SEM3) sequentially arranged in a third direction (DR3).

[0247] The conductive layer (E1) can be disposed on the lower surface of the first semiconductor layer (SEM1).

[0248] The first semiconductor layer (SEM1) may be formed of GaN doped with a first conductivity type dopant (e.g., a p-type dopant) such as Mg, Zn, Ca, Sr, or Ba.

[0249] The first semiconductor layer (SEM1) can be electrically connected to the pixel electrode (PXE1) through the conductive layer (E1) and the first electrode (CT1).

[0250] The active layer (MQW) can be disposed on the first semiconductor layer (SEM1). The active layer (MQW) can emit light by the combination of electron-hole pairs in response to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0251] The second semiconductor layer (SEM2) may be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be doped with a second conductivity type dopant such as Si, Ge, Sn, etc. For example, the second semiconductor layer (SEM2) may be n-GaN doped with n-type Si. The second semiconductor layer (SEM2) may include a first portion (SEM2_1) having a first thickness (T1) and a second portion (SEM2_2) having a second thickness (T2) less than the first thickness (T1).

[0252] The first part (SEM2_1) of the second semiconductor layer (SEM2) can be disposed on the active layer (MQW).

[0253] The third semiconductor layer (SEM3) may be disposed on the second semiconductor layer (SEM2). The third semiconductor layer (SEM3) may be disposed on the first portion (SEM2_1) and the second portion (SEM2_2).

[0254] The third semiconductor layer (SEM3) may be formed as a semiconductor layer that is not doped with an n-type dopant or a p-type dopant, i.e., an undoped semiconductor layer. For example, the third semiconductor layer (SEM3) may be any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN that is not doped with a dopant. For example, the third semiconductor layer (SEM3) may be GaN that is not doped with a dopant.

[0255] Light extraction patterns (LEPs) can be formed on the upper surface of the semiconductor stack (STC). For example, the light extraction patterns (LEPs) can be formed on the upper surface of the third semiconductor layer (SEM3).

[0256] An electron blocking layer may be positioned between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer that suppresses or prevents excessive electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0257] The superlattice layer may be positioned between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0258] The protective layer (INS) may be a film for protecting the light emitting element (LE) by being disposed on at least one side of the semiconductor stack (STC) and at least one side and a lower surface of the conductive layer (E1). Specifically, the protective layer (INS) is exemplified as being disposed on the lower surface and the side surfaces of the conductive layer (E1), the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), and the side surfaces of the second semiconductor layer (SEM2), and not disposed on the side surfaces of the third semiconductor layer (SEM3), but the embodiment of the present specification is not limited thereto. For example, the protective layer (INS) may be disposed on the side surfaces of the first semiconductor layer (SEM1) of the semiconductor stack (STC), the side surfaces of the active layer (MQW), and a portion of the side surface of the second semiconductor layer (SEM2).

[0259] The protective layer (INS) may have two openings (OP1, OP2). The two openings (OP1, OP2) may be spaced apart from each other. The first opening (OP1) may be disposed on the first semiconductor layer (SEM1) to expose the first conductive layer (E1). The second opening (OP2) may be disposed on the second semiconductor layer (SEM2). For example, the second opening (OP2) may be disposed on the second portion (SEM2_2) to expose the second semiconductor layer (SEM2).

[0260] The protective layer (INS) may be exposed without covering the area adjacent to the upper surface of the semiconductor stack (STC) among the sides of the semiconductor stack (STC).

[0261] The protective layer (INS) is an inorganic film, for example, silicon nitride (SiN). x), silicon oxide nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed. In one embodiment, the protective layer (INS) is silicon oxide (SiO x ) may be.

[0262] A first electrode (CT1) may be disposed on at least a portion of a conductive layer (E1). The first electrode (CT1) is connected to the first conductive layer (E1) through a first opening (OP1).

[0263] The first electrode (CT1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0264] The second electrode (CT2) may be disposed on at least a portion of the second portion (SEM2_2) of the second semiconductor layer (SEM2). The second electrode (CT2) may be connected to the second semiconductor layer (SEM2) through the second opening (OP2).

[0265] Not only is the active layer (MQW) and the first semiconductor layer (SEM1) not disposed on the second part (SEM2_2) of the second semiconductor layer (SEM2), but the thickness (T2) of the second part (SEM2_2) of the second semiconductor layer (SEM2) is smaller than the thickness (T1) of the first part (SEM2_1). Therefore, in order to compensate for the thickness difference between the first part (SEM2_1) and the second part (SEM2_2) of the second semiconductor layer (SEM2), the thickness of the active layer (MQW), and the thickness of the first semiconductor layer (SEM1), the thickness of the second electrode (CT2) may be larger than the thickness of the first electrode (CT1). For example, the thickness of the second electrode (CT2) may be greater than or equal to the sum of the thickness difference between the first portion (SEM2_1) and the second portion (SEM2_2) of the second semiconductor layer (SEM2), the thickness of the active layer (MQW), and the thickness of the first semiconductor layer (SEM1) and the conductive layer (E1).

[0266] Fig. 17 is a cross-sectional view showing another example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5. Fig. 18 is a cross-sectional view showing in detail an example of area A1 of Fig. 17.

[0267] The embodiments of FIGS. 17 and 18 differ from the embodiments of FIGS. 6 and 7 in that the third semiconductor layer (SEM3) has a first portion (SEM3_1) and a second portion (SEM3_2) having different widths, and a protective layer (INS) and a selective reflective layer (SRF) are not disposed on the side surface of the second portion (SEM3_2) of the third semiconductor layer (SEM3). In FIGS. 17 and 18, descriptions overlapping with those of the embodiments of FIGS. 6 and 7 will be omitted, and descriptions will be focused on differences from the embodiments of FIGS. 6 and 7.

[0268] Referring to FIGS. 17 and 18, the third semiconductor layer (SEM3) may be disposed on the second semiconductor layer (SEM2). The third semiconductor layer (SEM3) may be formed as a semiconductor layer that is not doped with an n-type dopant or a p-type dopant, i.e., an undoped semiconductor layer. The third semiconductor layer (SEM3) may include a first portion (SEM3_1) having a first width (W1) and a second portion (SEM3_2) having a second width (W2). The second width (W2) may be wider than the first width (W1). The first portion (SEM3_1) of the third semiconductor layer (SEM3) may be disposed on the second semiconductor layer (SEM2), and the second portion (SEM3_2) may be disposed on the first portion (SEM3_2).

[0269] The side surfaces of the second semiconductor layer (SEM2), the active layer (MQW), the first semiconductor layer (SEM1) and the first portion (SEM3_1) of the third semiconductor layer (SEM3) can be mutually aligned and matched.

[0270] The second portion (SEM3_2) of the third semiconductor layer (SEM3) can protrude outward from the first portion (SEM3_1).

[0271] The protective layer (INS) is disposed on the lower surface and side surfaces of the conductive layer (E1), the side surface of the first semiconductor layer (SEM1), the side surface of the active layer (MQW), the side surface of the second semiconductor layer (SEM2), and the side surface of the first part (SEM3_1) of the third semiconductor layer (SEM3), and may be disposed on a part of one surface of the second part (SEM3_2) of the third semiconductor layer (SEM3). A part of the second part (SEM3_2) may be a part that does not overlap with the first part (SEM3_1). The protective layer (INS) may expose the side surface of the second part (SEM3_2) of the third semiconductor layer (SEM3) without covering it. In this way, when the side surface of the second part (SEM3_2) of the third semiconductor layer (SEM3) is not covered, the light emitting element (LE) can be easily separated from the base substrate on which the light emitting element (LE) is grown during the manufacturing process.

[0272] The protective layer (INS) may have two openings (OP1, OP2). The two openings (OP1, OP2) may be spaced apart from each other. The first opening (OP1) may be disposed on the first surface of the light emitting element (LE), and the second opening (OP2) may be disposed to overlap the bottom of the hole (LEH). For example, the protective layer (INS) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), and the sidewall of the active layer (MQW). The protective layer (INS) may not cover the second semiconductor layer (SEM2) in the hole (LEH). Therefore, the second semiconductor layer (SEM2) may be exposed without being covered by the protective layer (INS).

[0273] A selective reflection layer (SRF) may be disposed on the protective layer (INS), surround side surfaces of the conductive layer (E1) and the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3_1), and be disposed on one surface of the conductive layer (E1). In addition, the selective reflection layer (SRF) may be disposed on a portion of one surface of a second portion (SEM3_2) of the third semiconductor layer (SEM3). A portion of the second portion (SEM3_2) may be a portion that does not overlap with the first portion (SEM3_1).

[0274] A selective reflection layer (SRF) may be disposed on the protective layer (INS), surround side surfaces of the conductive layer (E1) and the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3_1), and be disposed on one surface of the conductive layer (E1). In addition, the selective reflection layer (SRF) may be disposed on a portion of one surface of a second portion (SEM3_2) of the third semiconductor layer (SEM3). A portion of the second portion (SEM3_2) may be a portion that does not overlap with the first portion (SEM3_1).

[0275] FIG. 19 is a layout diagram showing pixels of a display area according to one embodiment.

[0276] The embodiment of FIG. 19 differs from the embodiment of FIG. 5 in that the light emitting elements (LEs) overlap the pixel electrodes (PXE1 / PXE2 / PXE3) in each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). In the embodiment of FIG. 19, descriptions overlapping with the embodiment of FIG. 5 are omitted.

[0277] Referring to FIG. 19, a first sub-pixel (SPX1) includes a first pixel electrode (PXE1), a plurality of light-emitting elements (LEs), and a first light conversion layer (QDL1). A second sub-pixel (SPX2) includes a second pixel electrode (PXE2), a plurality of light-emitting elements (LEs), and a second light conversion layer (QDL2). A third sub-pixel (SPX3) includes a third pixel electrode (PXE3), a plurality of light-emitting elements (LEs), and a light-transmitting layer (or third light conversion layer) (TPL).

[0278] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). The area of ​​the first sub-pixel (SPX1), the area of ​​the second sub-pixel (SPX2), and the area of ​​the third sub-pixel (SPX3) may be set according to the light conversion efficiency of the first light conversion layer (QDL1) and the light conversion efficiency of the second light conversion layer (QDL2). For example, the lower the light conversion efficiency, the larger the area of ​​the sub-pixel.

[0279] For example, as in FIG. 19, when the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1). In addition, since the first light conversion layer (QDL1) must convert the light while the light transmitting layer (TPL) directly transmits the light of the light emitting element (LE), the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3).

[0280] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to a second electrode of a fourth transistor (ST4 of FIG. 4) and a second electrode of a sixth transistor (ST6 of FIG. 4) of the corresponding sub-pixel.

[0281] A plurality of light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). The same number of light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). For example, two light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3).

[0282] The first light conversion layer (QDL1) can completely overlap the first pixel electrode (PXE1) and the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1). The area of ​​the first light conversion layer (QDL1) can be larger than the area of ​​the first pixel electrode (PXE1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1) into first light.

[0283] The second light conversion layer (QDL2) can completely overlap the second pixel electrode (PXE2) and the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2). The area of ​​the second light conversion layer (QDL2) can be larger than the area of ​​the second pixel electrode (PXE2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the second light conversion layer (QDL2) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2) into second light.

[0284] The light transmitting layer (TPL) can completely overlap the third pixel electrode (PXE3) and the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3). The light transmitting layer (TPL) can directly transmit incident light. For example, the light transmitting layer (TPL) can directly transmit third light emitted from the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3).

[0285] Fig. 20 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 19. Fig. 21 is a cross-sectional view showing in detail an example of area A3 of Fig. 20.

[0286] The embodiments of FIGS. 20 and 21 differ from the embodiments of FIGS. 6 and 7 in that the light emitting elements (LE) are vertical type micro LEDs in which each of the plurality of light emitting elements (LE) extends in a third direction (DR3). The vertical type micro LED refers to an LED having a structure in which a conductive layer (E1), a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) are sequentially arranged in the third direction (DR3), which is a vertical direction. Each of the plurality of light emitting elements (LE) may have a cross-sectional shape of a reverse taper. For example, each of the plurality of light emitting elements (LE) may have a cross-sectional shape of a trapezoid in which the width of the upper surface is wider than the width of the lower surface. The shape of the light emitting elements (LE) may vary depending on the embodiments. For example, each of the plurality of light emitting elements (LE) may include a substantially vertical side surface. The light emitting element (LE) can be patterned by vertical etching and can have a rectangular or square cross-sectional shape with the width of the upper surface and the width of the lower surface being substantially the same.

[0287] In the embodiments of FIGS. 20 and 21, descriptions that overlap with those of the embodiments of FIGS. 6 and 7 are omitted.

[0288] Referring to FIGS. 20 and 21, a pixel electrode layer including pixel electrodes (PXE1, PXE2, PXE3) may be disposed on a second planarizing organic film (180). A common electrode (CE) may be disposed on an upper surface of each of a plurality of light emitting elements (LE) and an upper surface of a third organic layer (212). The common electrode (CE) may be a common layer formed commonly on the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3).

[0289] A pixel electrode layer may be arranged on the second flattening organic film (180). The pixel electrode layer may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3).

[0290] A first organic layer (210) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3).

[0291] A plurality of light emitting elements (LEs) can be arranged on the first organic layer (210).

[0292] Each of the plurality of light emitting elements (LE) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3) of several to several hundred μm, respectively. For example, each of the plurality of light emitting elements (LE) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3) of approximately 100 μm or less, respectively.

[0293] A light emitting element (LE) may include a conductive layer (E1), a semiconductor stack (STC), a contact electrode (CTE), and a passivation layer (INS). The semiconductor stack (STC) may include a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), and a third semiconductor layer (SEM3) sequentially arranged in a third direction (DR3).

[0294] The protective layer (INS) may be a film for protecting the light emitting element (LE) by being disposed on at least one side of the semiconductor stack (STC) and at least one side and a lower surface of the conductive layer (E1). Specifically, the protective layer (INS) is exemplified as being disposed on the lower surface and the side surfaces of the conductive layer (E1), the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), and the side surfaces of the second semiconductor layer (SEM2), and not disposed on the side surfaces of the third semiconductor layer (SEM3), but the embodiment of the present specification is not limited thereto. For example, the protective layer (INS) may be disposed on the side surfaces of the first semiconductor layer (SEM1) of the semiconductor stack (STC), the side surfaces of the active layer (MQW), and a portion of the side surface of the second semiconductor layer (SEM2).

[0295] The protective layer (INS) may expose an area adjacent to the upper surface of the semiconductor stack (STC) among the side surfaces of the semiconductor stack (STC). For example, a distance (DS1) between the upper surface of the semiconductor stack (STC) and the protective layer (INS) in the third direction (DR3) may be greater than approximately 100 nm. In addition, the distance (DS1) between the upper surface of the semiconductor stack (STC) and the protective layer (INS) in the third direction (DR3) may be greater than a maximum length (Lmax) of the light extraction pattern in the third direction (DR3). Here, the third direction (DR3) may be substantially the same as the height direction (or thickness direction) of the light emitting element (LE). In this way, when the protective layer (INS) is spaced apart from the upper surface of the semiconductor stack (STC), the light emitting element (LE) can be easily separated from the base substrate on which the light emitting element (LE) is grown in a manufacturing process.

[0296] The protective layer (INS) is an inorganic film, for example, silicon nitride (SiN). x ), silicon oxide nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x) can be formed. In one embodiment, the protective layer (INS) is silicon oxide (SiO x ) may be.

[0297] The contact electrode (CTE) may be disposed on the protective layer (INS). The contact electrode (CTE) may be disposed between the first organic layer (210) and the protective layer (INS). The contact electrode (CTE) may be in contact with the first organic layer (210).

[0298] The contact electrode (CTE) can be connected to the exposed conductive layer (E1) that is not covered by the protective layer (INS).

[0299] The contact electrode (CTE) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, the contact electrode (CTE) may be formed as a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to increase reflectivity.

[0300] The connecting electrode (BE) is disposed between the contact electrode (CTE) and the first organic layer (210) and can extend along the first organic layer (210) onto the pixel electrode (PXE1 / PXE2 / PXE3). The connecting electrode (BE) connects the contact electrode (CTE) of the light emitting element (LE) and one of the pixel electrodes (PXE1, PXE2, PXE3).

[0301] A common electrode (CE) may be disposed on the upper surface of each of the plurality of light emitting elements (LE) and the upper surface of the third organic film (212). The common electrode (CE) may be a common layer formed in common on the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). The common electrode (CE) may be made of a transparent metal material (TCO, Transparent Conductive Material), such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), which can transmit light.

[0302] The pixel electrodes (PXE1, PXE2, PXE3) may be referred to as anode electrodes or first electrodes, and the common electrode (CE) may be referred to as cathode electrodes or second electrodes.

[0303] The first capping layer (CAP1) can be disposed on the common electrode (CE).

[0304] Figure 22 is a cross-sectional view showing another example of area A3 of Figure 20 in detail.

[0305] The embodiment of Fig. 22 differs from the embodiment of Fig. 21 in that the light emitting element (LE) does not include a light extraction pattern (LEP). In Fig. 22, descriptions that overlap with the embodiment of Fig. 21 are omitted, and descriptions are focused on differences from the embodiment of Fig. 21.

[0306] Referring to Fig. 22, the upper portion of the semiconductor stack (STC) does not include a light extraction pattern (LEP). In the example of Fig. 22, the semiconductor stack (STC) includes, but is not limited to, a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), and a third semiconductor layer (SEM3). The semiconductor stack (STC) may include the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2), and may not include the third semiconductor layer (SEM3).

[0307] Fig. 23 is a flowchart illustrating a method for manufacturing a display device according to one embodiment. Figs. 24 to 29 and Figs. 31 to 36 are drawings for explaining a method for manufacturing a display device according to one embodiment. Fig. 30 is an image for showing a protective layer and a selective reflective layer according to the dipping time of Fig. 29.

[0308] Figures 24 to 32 illustrate the formation of a light-emitting element.

[0309] Below, a method for manufacturing the display device illustrated in FIGS. 24 to 29 and FIGS. 31 to 36 will be described in connection with FIG. 23.

[0310] First, as shown in Fig. 24, a third semiconductor material layer (SEML3), a second semiconductor material layer (SEML2), an active material layer (MQWL), a first semiconductor material layer (SEML1), and a conductive material layer (EL1) are formed on a semiconductor substrate (SSUB). (S110 of Fig. 23)

[0311] The semiconductor substrate (SSUB) may be a silicon wafer substrate or a sapphire substrate. A light extraction pattern layer (LEPL) is formed on one surface of the semiconductor substrate (SSUB). The light extraction pattern layer (LEPL) may include convex patterns formed in a hemisphere or a semi-ellipse. The light extraction pattern layer (LEPL) may include convex patterns having a cross-sectional shape of a semicircle or a semi-ellipse. The light extraction pattern layer (LEPL) may be formed of a semiconductor material layer, an organic film, or an inorganic film.

[0312] Then, a third semiconductor material layer (SEML3) is formed on the light extraction pattern layer (LEPL). Due to the light extraction pattern layer (LEPL), light extraction patterns (LEP in FIG. 7) can be formed on one surface of the third semiconductor material layer (SEML3).

[0313] The third semiconductor material layer (SEML3) may be arranged to reduce the difference in lattice constants between the second semiconductor material layer (SEML2) and the semiconductor substrate (SSUB). For example, the third semiconductor material layer (SEML3) may include an undoped semiconductor and may be an n-type or p-type undoped material. In an exemplary embodiment, the third semiconductor material layer (SEML3) may be at least one of, but is not limited to, undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN.

[0314] A second semiconductor material layer (SEML2) is formed on a third semiconductor material layer (SEML3). The second semiconductor material layer (SEML2) may be a semiconductor material layer doped with a second conductive dopant such as silicon (Si), germanium (Ge), or tin (Sn).

[0315] Then, an active material layer (MQWL) is formed on the second semiconductor material layer (SEML2), and a first semiconductor material layer (SEML1) is formed on the active material layer (MQWL). The active material layer (MQWL) may include the same semiconductor material layer as the first semiconductor material layer (SEML1) and the second semiconductor material layer (SEML2). For example, when the first semiconductor material layer (SEML1) and the second semiconductor material layer (SEML2) include gallium nitride (GaN), the active material layer (MQWL) may also include gallium nitride (GaN). For example, the active material layer (MQWL) may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The first semiconductor material layer (SEML1) may be a semiconductor material layer doped with a first conductive dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc.

[0316] The light extraction pattern layer (LEPL), the third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), and the first semiconductor material layer (SEML1) can be formed on a semiconductor substrate (SSUB) through an epitaxial growth process. As the epitaxial growth process, a method for forming the light extraction pattern layer (LEPL), the second semiconductor material layer (SEML2), the active material layer (MQWL), and the first semiconductor material layer (SEML1) can include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), etc. Preferably, metal-organic chemical vapor deposition (MOCVD) may be used, but the embodiments of the present disclosure are not limited thereto.

[0317] Then, a conductive material layer (EL1) is formed on the first semiconductor material layer (SEML1). The conductive material layer (EL1) can be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0318] Secondly, as shown in Fig. 25, the third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), the first semiconductor material layer (SEML1), and the conductive material layer (EL1) are etched to form light emitting elements (LE). (S120 of Fig. 23)

[0319] After forming a mask pattern on the conductive material layer (EL1), the third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), the first semiconductor material layer (SEML1), and the conductive material layer (EL1) are etched according to the mask pattern. The mask pattern can be removed after forming the light emitting elements (LE).

[0320] The second semiconductor material layer (SEML2), the active material layer (MQWL), the first semiconductor material layer (SEML1), and the conductive material layer (EL1) can be etched by a dry etching method, a wet etching method, a reactive ion etching (RIE), a deep reactive ion etching (DRIE), an inductively coupled plasma reactive ion etching (ICP-RIE), or the like. In the case of the dry etching method, anisotropic etching is possible, so it may be suitable for vertical etching. When the dry etching method is used, the etching gas may be, but is not limited to, chlorine (Cl2) or oxygen (O2) gas.

[0321] Then, a hole (LEH) is formed in each of the light emitting elements (LE) to penetrate the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) and expose the second semiconductor layer (SEM2).

[0322] Thirdly, a protective layer (INS) and a selective reflective layer (SRF) having a first opening (OP1) and a second opening (OP2 in FIG. 7) can be formed on the entire surface of the semiconductor substrate (SSUB). (S130 in FIG. 23)

[0323] Referring to FIG. 26, a protective material layer (INSL) can be fully deposited on one surface of a semiconductor substrate (SSUB). The protective material layer (INSL) can be formed to cover one surface and side surfaces of the light emitting elements (LE). The protective material layer (INSL) can be formed on one surface of the semiconductor substrate (SSUB) exposed between the light emitting elements (LE).

[0324] The next selective reflection layer (SRF) can be formed on the entire surface of the protective material layer (INSL).

[0325] A selective reflection layer (SRF) can be formed by alternately depositing a first layer and a second layer on one surface of a semiconductor substrate (SSUB). The first layer can be etched by the same etchant as the protective layer (INSL). The second layer may not be etched by the etchant that etches the protective layer (INSL). For example, the protective layer (INSL) and the first layer may be formed of silicon oxide (SiO). x ) can be. The second layer is titanium oxide (TiO x ) may be. The etchant may be a silicon oxide film etchant, and may be BOE (Buffered Oxide Etch).

[0326] A portion of the protective layer (INS) and selective reflection layer (SRF) are etched to expose a portion of the conductive layer (E1) and a portion of the second semiconductor layer (SEM2).

[0327] To this end, a first mask pattern is formed on a selective reflective layer (SRF).

[0328] Referring to FIG. 27, the first mask pattern (MP1) may be formed to expose a portion of the hole (LEH) of each of the light-emitting elements (LE). For example, the first mask pattern (MP1) may form a first opening (OP1) by etching a portion of the selective reflection layer (SRF) and the protective layer (INS) disposed on one surface of each of the light-emitting elements (LE). In addition, the first mask pattern (MP1) may form a second opening (OP2) so as not to cover the selective reflection layer (SRF) and the protective layer (INS) disposed on the bottom surface of the hole (LEH) of each of the light-emitting elements (LE). The conductive layer (E1) may be exposed by the first opening (OP1), and the second semiconductor layer (SEM2) may be exposed by the second opening (OP2).

[0329] Fourth, the selective reflection layer (SRF) and the protective layer (INS) that do not overlap with the light emitting element (LE) are etched (S140 in Fig. 23).

[0330] Referring to FIG. 28, a photoresist pattern (PR) covering a light emitting element (LE) is formed. The photoresist pattern (PR) can protect the light emitting element (LE) during an etching process. Thereafter, a portion of the selective reflection layer (SRF) and the protective layer (INS) can be etched using a photo process. The photo process is a process for forming a desired structure by applying photoresist (PR) on a substrate and then passing light through a mask formed in a desired pattern. In this way, a photo process tolerance may occur due to the mask and the passage of light in the photo process. For example, the photoresist (PR) may be formed to surround the light emitting element (LE). The selective reflection layer (SRF) and the protective layer (INS) can be etched using the photoresist (PR) as a mask. In this way, when the photoresist (PR) is used as a mask, a portion protruding outward from the bottom of the semiconductor stack occurs due to the photo process tolerance. The photo process tolerance may vary depending on the photo equipment, but may be approximately 0.5 ㎛ to 2 ㎛. Accordingly, the protrusion length of the selective reflection layer (SRF) and the protective layer (INS) can be formed within a range of 0.6 ㎛ to 2.4 ㎛, which includes a margin of approximately 20% in the photo process tolerance.

[0331] Fifth, a portion of the protective layer (INS) is etched by dipping in an etchant (EF). (S150 in Fig. 23)

[0332] For example, referring to Figure 29, the etchant (EF) forms a silicon oxide (SiO) that forms a protective layer (INS). x ) and titanium oxide (TiO ) which forms the second layer of the selective reflection layer (SRF). x ) may not respond.

[0333] Referring to Figure 30, it can be seen that as the dipping time increases, the length of the protective layer (INS) decreases. It can also be seen that along with the length of the protective layer (INS), the length of the first layers of the selective reflection layer (SRF) also changes.

[0334] For example, after 3 minutes, it can be confirmed that the protective layer (INS) that does not overlap with the light emitting element (LE) is completely etched, and the first layers of the selective reflection layer (SRF) are also shorter than the second layers of each pair. After 5 minutes, it can be confirmed that the protective layer (INS) is etched and removed up to the side of the light emitting element (LE). At this time, the time must be adjusted carefully because if the time is too long, the protective layer (INS) on the side of the active layer (MQW) may also be removed. In addition, it can be confirmed that the first layers of the selective reflection layer (SRF) are also removed from the part that does not overlap with the light emitting element (LE). The etching time may vary depending on the concentration of the etchant, the thickness of the protective layer (INS) and the selective reflection layer (SRF), etc.

[0335] As shown in Fig. 31, when the protective layer (INS) that does not overlap the light emitting element (LE) is etched, the light emitting element (LE) can be easily separated from the semiconductor substrate (SSUB) in a subsequent transfer process. Here, easy separation means that, for example, when the light emitting element (LE) is separated from the semiconductor substrate (SSUB) by laser irradiation, the semiconductor substrate (SSUB) can be separated even with a relatively low laser power. If the separation is not easy in the separation process of the light emitting element (LE) and the semiconductor substrate (SSUB), and a high laser power is required, the dispersion of the current-voltage curve of the light emitting element (LE) increases, and delayed lighting may occur. In addition, the problem of the protective layer of the light emitting element (LE) being peeled off may also occur. Conversely, in a case where the protective layer (INS) that does not overlap the light emitting element (LE) is etched to separate the protective layer (INS) and the semiconductor substrate (SSUB), when transferring the light emitting element (LE) to the target substrate, the light emitting element (LE) can be easily separated from the semiconductor substrate (SSUB) with a relatively low laser power.

[0336] After the dipping process is complete, the photoresist (PR) can be removed by an ashing process.

[0337] Sixth, as shown in FIGS. 32 and 33, contact electrodes (CTE1, CTE2) are formed. (S160 of FIG. 23)

[0338] The mask pattern (MP) can be formed with a first thickness (T1) between the light emitting elements (LE) as shown in FIG. 32.

[0339] Thereafter, a contact electrode layer (CTEL) is deposited on one surface of the semiconductor substrate (SSUB) to cover the light emitting elements (LE) and the mask pattern (MP). The contact electrode layer (CTEL) can be formed on one surface of the semiconductor substrate (SSUB) exposed between the light emitting elements (LE).

[0340] The mask pattern (MP) is removed by a lift-off process, and first contact electrodes (CTE1) and second contact electrodes (CTE2) are formed.

[0341] To remove a mask pattern (MP) through a lift-off process, the mask pattern (MP) may be formed using a negative photoresist. In this case, the mask pattern (MP) and the contact electrode layer (CTE) disposed on the mask pattern (MP) may be removed through a solvent ashing process using alcohol.

[0342] When the mask pattern (MP) is removed, the first contact electrode (CTE1) connected to the conductive layer (E1) and the second contact electrode (CTE2) connected to the second semiconductor layer (SEM2) are positioned apart from each other, and thus can be electrically isolated from each other. In addition, the first contact electrode (CTE1) and the second contact electrode (CTE2) can be exposed without covering the protective layer (INS) positioned on the side of the third semiconductor layer (SEML3).

[0343] Seventh, as shown in Fig. 34, the light emitting elements (LE) are transferred to the first organic film (210) disposed on the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3), and the semiconductor substrate (SSUB) is removed. (S170 of Fig. 23)

[0344] The light emitting elements (LEs) may be moved onto the first organic layer (210) disposed on the pixel electrodes (PXE). At this time, the light emitting elements (LEs) may be temporarily fixed by being embedded in the first organic layer (210). In FIG. 34, it is exemplified that the first contact electrode (CTE1) and the second contact electrode (CTE2) of each of the light emitting elements (LEs) are disposed on the first organic layer (210), but the embodiment of the present specification is not limited thereto. For example, the first organic layer (210) may be disposed on a lower surface and a part of a side surface of the first contact electrode (CTE1) of each of the light emitting elements (LEs) and a part of a lower surface and a part of a side surface of the second contact electrode (CTE2) of each of the light emitting elements (LEs). Alternatively, the first organic layer (210) may be disposed on the side surfaces of the conductive layer (E1) of each of the light emitting elements (LEs). Alternatively, the first organic layer (210) may be disposed on the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), and the side surfaces of the second semiconductor layer (SEM2) of each of the light emitting elements (LE). In this case, the first organic layer (210) may be disposed on a portion of each of the side surfaces of the second semiconductor layer (SEM2).

[0345] When the fluidity of the first organic layer (210) is low or the first organic layer (210) is solid, the depth at which the light-emitting element (LE) is inserted or embedded in the first organic layer (210) may be very small, or the light-emitting element (LE) may be placed on the first organic layer (210) without being inserted or embedded in the first organic layer (210).

[0346] When the first organic layer (210) is a photosensitive organic film such as a photoresist, after the first organic layer (210) is cured (soft baked) at a first temperature, at least a portion of each of the plurality of light-emitting elements (LE) is inserted into the first organic layer (210). Then, the first organic layer (210) can be completely cured at a second temperature higher than the first temperature. The first temperature may be approximately 100 degrees, and the second temperature may be approximately 230 degrees, but the embodiments of the present specification are not limited thereto. In addition, the process of completely curing the first organic layer (210) at the second temperature may be performed for approximately 30 minutes.

[0347] Then, the semiconductor substrate (SSUB) is removed by a laser lift-off process. Alternatively, if the light-emitting elements (LEs) are transferred to a separate transfer substrate rather than the semiconductor substrate (SSUB), the transfer substrate may be removed instead of the semiconductor substrate (SSUB).

[0348] Eighth, as shown in Fig. 35, first connection electrodes (BE1) and second connection electrodes (BE2) are formed, and a second organic film (211) and a third organic film (212) are formed. (S180 of Fig. 23)

[0349] First connection electrodes (BE1) for connecting the first contact electrode (CTE1) and pixel electrodes (PXE1, PXE2, PXE3) of the light emitting element (LE) disposed on the first organic film (210) and second connection electrodes (BE2) for connecting the second contact electrode (CTE2) and the common electrodes (CE1, CE2, CE3) are formed.

[0350] Then, a second organic film (211) and a third organic film (212) are formed to fix the light emitting elements (LEs) and to level the steps caused by the light emitting elements (LEs).

[0351] Ninth, as shown in Fig. 36, a light-shielding layer, a wavelength conversion layer, a light-transmitting layer, and a color filter layer are formed sequentially. (S190 of Fig. 23)

[0352] A first capping layer (CPL1) is formed on the third organic film (212) and the light-emitting elements (LE), and a first light-blocking layer (BM1) and a second light-blocking layer (BM2) are formed on the first capping layer (CPL1) so as not to overlap with the light-emitting elements (LE) in the third direction (DR). Then, a second capping layer (CPL2) covering the first light-blocking layer (BM1), the second light-blocking layer (BM2), and the first capping layer (CPL1) is formed. Then, a reflective film (RF) is formed covering the second capping layer (CPL2) disposed on the first light-blocking layer (BM1) and the second light-blocking layer (BM2).

[0353] Then, a first light conversion layer (QDL1) is formed on each of the first sub-pixels (SPX1), a second light conversion layer (QDL2) is formed on each of the second sub-pixels (SPX2), and a light transmitting layer (TPL) is formed on each of the third sub-pixels (SPX3). Then, a third capping layer (CPL3) is formed to cover the first light conversion layers (QDL1), the second light conversion layers (QDL2), and the light transmitting layers (TPL). Then, a fourth organic film (213) is formed on the third capping layer (CPL3).

[0354] Then, a fourth organic film (213) is formed on the third capping layer (CPL3), a first color filter (CF1) is formed on the fourth organic film (213) to overlap the first light conversion layers (QDL1) in the third direction (DR3), a second color filter (CF2) is formed to overlap the second light conversion layers (QDL2) in the third direction (DR3), and a third color filter (CF3) is formed to overlap the light transmitting layers (TPL) in the third direction (DR3). The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) can all be formed in the region overlapping the first light-blocking layer (BM1) and the second light-blocking layer (BM2) in the third direction (DR3).

[0355] Then, a fifth organic film (214) is formed on the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3).

[0356] FIG. 37 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0357] Referring to FIG. 37, a display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of smart devices.

[0358] FIGS. 38 and 39 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0359] Referring to FIGS. 38 and 39, a head-mounted display device (1000_2) according to one embodiment includes a first display device (10_2), a second display device (10_3), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece lens (1210), a second eyepiece lens (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0360] The first display device (10_2) provides an image to the user's left eye, and the second display device (10_3) provides an image to the user's right eye. Since each of the first display device (10_2) and the second display device (10_3) is substantially the same as the display device (10) described in conjunction with FIGS. 1 and 2, descriptions of the first display device (10_2) and the second display device (10_3) are omitted.

[0361] The first optical member (1510) may be positioned between the first display device (10_2) and the first eyepiece lens (1210). The second optical member (1520) may be positioned between the second display device (10_3) and the second eyepiece lens (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0362] The middle frame (1400) is disposed between the first display device (10_2) and the control circuit board (1600), and may be disposed between the second display device (10_3) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (10_2), the second display device (10_3), and the control circuit board (1600).

[0363] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (10_2) and the second display device (10_3) via connectors. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (10_2) and the second display device (10_3) via the connectors.

[0364] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (10_2) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (10_3). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (10_2) and the second display device (10_3).

[0365] The display device storage unit (1100) serves to store the first display device (10_2), the second display device (10_3), the middle frame (1400), the first optical member (1510), the second optical member (1520), and the control circuit board (1600). The storage unit cover (1200) is arranged to cover an open surface of the display device storage unit (1100). The storage unit cover (1200) may include a first eyepiece (1210) for placing the user's left eye and a second eyepiece (1220) for placing the user's right eye. In FIGS. 38 and 39, the first eyepiece (1210) and the second eyepiece (1220) are exemplified as being separately arranged, but the embodiments of the present specification are not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0366] The first eyepiece (1210) can be aligned with the first display device (10_2) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (10_3) and the second optical member (1520). Accordingly, the user can view the image of the first display device (10_2) enlarged into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view the image of the second display device (10_3) enlarged into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0367] The head-mounted band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be positioned respectively for the user's left and right eyes. If the display device storage unit (1200) is implemented in a lightweight and compact form, the head-mounted display device (1000) may be equipped with a glasses frame as shown in FIG. 40 instead of the head-mounted band (800).

[0368] In addition, the head-mounted display device (1000) may further include a battery for supplying power, an external memory slot for storing external memory, and an external connection port and wireless communication module for receiving a video source. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0369] Fig. 40 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment. Fig. 40 shows a virtual reality device (1000_3) to which a display device (10_4) according to one embodiment is applied.

[0370] Referring to FIG. 40, a virtual reality device (1000_3) according to one embodiment may be a device in the form of glasses. The virtual reality device (1000_3) according to one embodiment may include a display device (10_4), a left-eye lens (10a), a right-eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device storage unit (50).

[0371] In Fig. 40, it is exemplified that the virtual reality device (1000_3) is a glasses-type display device including glasses frame legs (30a, 30b). That is, the virtual reality device (1000_3) according to one embodiment is not limited to that illustrated in Fig. 40, and can be applied in various forms in various other electronic devices.

[0372] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user may view a virtual reality image displayed on the display device (10_4) through the right eye.

[0373] In FIG. 40, the display device housing (50) is exemplified as being arranged at the right end of the support frame (20), but the embodiment of the present specification is not limited thereto. For example, the display device housing (50) may be arranged at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user may view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be arranged at both the left end and the right end of the support frame (20), in which case the user may view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0374] FIG. 41 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment. FIG. 41 shows an automobile to which display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment are applied.

[0375] Referring to FIG. 41, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to a dashboard of a vehicle, a center fascia of a vehicle, or a CID (Center Information Display) placed on a dashboard of a vehicle. In addition, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0376] FIG. 42 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0377] Referring to FIG. 42, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light at the same time. Therefore, a user positioned at the front of the transparent display device can not only view the image (IM) displayed on the display device (10_5), but also view an object (RS) or background positioned at the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) can include a light-transmitting portion that can transmit light or can be formed of a material that can transmit light.

[0378] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. A semiconductor stack including a first semiconductor layer, an active layer, and a second semiconductor layer; A conductive layer disposed on the first surface of the semiconductor stack; A protective layer disposed on the side surfaces of the conductive layer and the side surface of the semiconductor stack and the first surface of the conductive layer, and disposed away from the second surface facing the first surface of the semiconductor stack; A contact electrode arranged on one surface of the semiconductor stack; A selective reflective layer is disposed on the side surfaces of the conductive layer and the side surfaces of the semiconductor stack and the first surface of the conductive layer outside the protective layer, and includes an opening overlapping the contact electrode, A light emitting device in which the selective reflective layer comprises M pairs of first and second layers (M is an integer greater than or equal to 2), the first layer of each pair being positioned closer to the semiconductor stack than the second layer, and a length of one end of the first layer in each pair being different from a length of one end of the second layer.

2. In the first paragraph, a light emitting element in which the lengths of the first layers in different pairs of the semiconductor stacks are different from each other.

3. In the first paragraph, a light emitting element having a length of one end of a different pair of the first layer that is shorter the closer it is to the light emitting element of the corresponding layer.

4. A light emitting element in the first paragraph, wherein the refractive index of the first layer is lower than the refractive index of the second layer.

5. In paragraph 1, A light emitting device wherein the semiconductor stack further comprises a third semiconductor layer disposed on the second semiconductor layer.

6. A light emitting device according to claim 1, wherein the semiconductor stack further includes light extraction patterns formed on the upper surface of the semiconductor stack in a concave cross-sectional shape.

7. In paragraph 6, the protective layer covers the side surface of the active layer, A light emitting element in which a distance between the upper surface of the semiconductor stack and the protective layer in the height direction of the light emitting element is greater than the maximum length of any one of the light extraction patterns in the height direction of the light emitting element.

8. In paragraph 1, A light emitting element in which the protective layer and the first layer are silicon oxide and the second layer is titanium oxide.

9. In paragraph 1, A light emitting element comprising a first contact electrode connected to the conductive layer exposed without being covered by the protective layer and a second contact electrode connected to the second semiconductor layer exposed without being covered by the protective layer and the selective reflective layer.

10. In paragraph 9, A light emitting element in which the second contact electrode is disposed in a hole penetrating the conductive layer and a portion of the semiconductor stack.

11. In paragraph 1, The above contact electrode is a light emitting element connected to the exposed conductive layer that is not covered by the protective layer.

12. Substrate; A pixel electrode layer disposed on the above substrate; It has a light emitting element arranged on the pixel electrode, The above light emitting element, A semiconductor stack comprising a first semiconductor layer, an active layer, and a second semiconductor layer; A conductive layer disposed on the first surface of the semiconductor stack; A protective layer disposed on the side surfaces of the conductive layer and the side surfaces of the semiconductor stack and the first surface of the conductive layer, and disposed away from the second surface facing the first surface of the semiconductor stack; a contact electrode arranged on one surface of the semiconductor stack; and A selective reflective layer is disposed on the side surfaces of the conductive layer and the side surfaces of the semiconductor stack and the first surface of the conductive layer outside the protective layer, and includes an opening overlapping the contact electrode, A display device in which the selective reflective layer comprises M pairs of first and second layers (M is an integer greater than or equal to 2), the first layer of each pair being positioned closer to the semiconductor stack than the second layer, and a length of one end of the first layer in each pair being different from a length of one end of the second layer.

13. In paragraph 12, The pixel electrode layer includes a pixel electrode and a common electrode disposed spaced apart from the pixel electrode, A display device comprising a first contact electrode connected to the conductive layer exposed without being covered by the protective layer and a second contact electrode connected to the second semiconductor layer exposed without being covered by the protective layer and the selective reflective layer.

14. In paragraph 13, An organic film disposed on the pixel electrode and a portion of the common electrode; a first connection electrode connecting the first contact electrode and the pixel electrode; and A display device further comprising a second connection electrode connecting the second contact electrode and the common electrode.

15. In paragraph 12, The above pixel electrode layer includes a pixel electrode, The above contact electrode is connected to the conductive layer which is exposed and not covered by the protective layer, The display device further includes a common electrode disposed on the light emitting element.

16. In paragraph 15, An organic film disposed on the pixel electrode; and A display device further comprising a connecting electrode connecting the contact electrode and the pixel electrode.

17. Includes a display panel that displays the image, The above display panel, A semiconductor stack comprising a first semiconductor layer, an active layer, and a second semiconductor layer; A conductive layer disposed on the first surface of the semiconductor stack; A protective layer disposed on the side surfaces of the conductive layer and the side surface of the semiconductor stack and the first surface of the conductive layer, and disposed away from the second surface facing the first surface of the semiconductor stack; A contact electrode arranged on one surface of the semiconductor stack; A selective reflective layer is disposed on the side surfaces of the conductive layer and the side surfaces of the semiconductor stack and the first surface of the conductive layer outside the protective layer, and includes an opening overlapping the contact electrode, An electronic device wherein the selective reflective layer comprises M pairs of first and second layers (M is an integer greater than or equal to 2), wherein the first layer of each pair is disposed closer to the semiconductor stack than the second layer, and wherein a length of one end of the first layer in each pair is different from a length of one end of the second layer.

18. In paragraph 17, The pixel electrode layer includes a pixel electrode and a common electrode disposed spaced apart from the pixel electrode, An electronic device comprising a first contact electrode connected to the conductive layer exposed without being covered by the protective layer and a second contact electrode connected to the second semiconductor layer exposed without being covered by the protective layer and the selective reflective layer.

19. In paragraph 18, An organic film disposed on the pixel electrode and a portion of the common electrode; a first connection electrode connecting the first contact electrode and the pixel electrode; and An electronic device further comprising a second connection electrode connecting the second contact electrode and the common electrode.

20. In paragraph 17, The above pixel electrode layer includes a pixel electrode, The above contact electrode is connected to the conductive layer which is exposed and not covered by the protective layer, An electronic device wherein the display device further includes a common electrode disposed on a light-emitting element.

Images