Vertically stacked pixel circuit
The vertically stacked pixel circuit with dual gate TFTs and backside driving architecture addresses short channel effects in OLED displays, achieving high pixel density and resolution by improving switching speed and reducing power consumption.
Patent Information
- Application Number
- PCT/CA2025/051415
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-10-25
- Filing Date
- 2025-10-24
- Publication Date
- 2026-04-30
AI Technical Summary
Existing pixel driver circuits in OLED displays face challenges with short channel effects due to miniaturization, leading to issues such as high electric fields, drain-source leakage currents, and poor performance in high-resolution displays.
A vertically stacked pixel circuit design with a capacitor layer and transistor layer positioned on top of one another, incorporating dual gate TFTs and a backside driving architecture to fit multiple transistors and capacitors within a small footprint, utilizing amorphous-oxide semiconductors like a-IGZO and Molybdenum gate electrodes.
The design addresses short channel effects, enabling high pixel density and resolution in OLED displays by reducing parasitic capacitance and improving switching speed, thus enhancing image quality and reducing power consumption.