Shared work queue configuration for a memory device
A shared work queue interface addresses synchronization issues in NVMe systems by enabling direct command communication, enhancing SSD performance and reducing overhead in GPU applications.
WO2026111938A1PCT designated stage Publication Date: 2026-05-28MICRON TECHNOLOGY INC
Patent Information
- Application Number
- PCT/US2025/055153
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-07-22
- Filing Date
- 2025-11-12
- Publication Date
- 2026-05-28
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Figure US2025055153_28052026_PF_FP_ABST
Abstract
Systems, methods, and apparatus related to shared work queue interfaces for memory systems. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes NVMe commands to the SSD using a PCIe transaction layer packet. The host system can selectively configure a shared work queue interface of the SSD. A host / processor sends a get feature command to determine whether an SWQ interface is supported by the SSD. If the SSD supports the SWQ interface, then the SSD provides a response that identifies the resources provided by an NVMe controller in the SSD for use of the SWQ feature. The host / processor can send a command to enable / disable the SWQ feature using a set feature command. A queue pair can also be used whether the SWQ feature is enabled or disabled.
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Citation Information
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