System-on-chip, clock gating components, multiplexer components, and frequency division components

Abstract

The present invention provides a system on chip, a clock gating component, a clock multiplexer component and a clock frequency division component. The system on chip includes a plurality of intellectual property blocks and a clock management unit, and the clock management unit is configured to perform clock gating on at least one of the intellectual property blocks. The intellectual property blocks and the clock management unit are connected to each other using a full handshake method. The full handshake method may include at least one of the following items: the intellectual property block sends a request signal to the clock management unit to start providing a clock signal or stop providing a clock signal; and in response to receiving the request signal, the clock management unit sends a confirmation signal to the corresponding intellectual property block. The system on chip of the present invention consumes low power, and the method of driving the system on chip of the present invention can prevent the system on chip from consuming too much power.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2017-0010945 filed in the Korean Intellectual Property Office on January 24, 2017, and U.S. Patent Application No. 15 / 414,969 filed in the U.S. Patent and Trademark Office on January 25, 2017, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a semiconductor device. Background Art

[0004] As computers, communications, and broadcasting gradually merge, the demand for application specific integrated circuits (ASICs) and application specific standard products (ASSPs) has changed due to the demand for system-on-chip (SoC). In addition, the trend toward lighter, thinner, more compact, and higher performance information technology (IT) devices is a factor driving the development of SoC.

[0005] The SoC is a single chip on which functional blocks (eg, intellectual property (IP) blocks) having various functions are integrated by means of the development of semiconductor process technology.

[0006] As the integration density, size, and operating speed of SoCs increase, power consumption becomes a design factor to a greater extent. When the SoC consumes a lot of power, the temperature of the SoC may increase. If the temperature rises too much, the SoC may malfunction or may be damaged.

[0007] Therefore, a need exists for a SoC and a method of driving the SoC that can prevent the SoC from consuming too much power. Summary of the invention

[0008] According to an exemplary embodiment of the inventive concept, a system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU), wherein the clock management unit is configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU are connected to each other using a full handshake method.

[0009] According to an exemplary embodiment of the inventive concept, a clock gating component includes a clock control circuit configured to generate an operation clock signal; and a channel management (CM) circuit configured to receive a request signal across a communication channel from an external device and forward the request signal to the clock control circuit. The clock control circuit is configured to selectively provide the operation clock signal to the external device according to the request signal and provide an acknowledgment (Ack) signal to the CM circuit.

[0010] According to an exemplary embodiment of the inventive concept, a clock multiplexer component includes a clock control circuit, which is configured to select one of a first clock signal and a second clock signal based on a first selection signal, generate an operation clock signal based on the selected clock signal, and selectively output the operation clock signal in response to a request signal; and a channel management (CM) circuit, which is configured to receive a request signal across a communication channel from an external device and forward the request signal to the clock control circuit.

[0011] According to an exemplary embodiment of the inventive concept, a clock division component includes a clock control circuit, which is configured to perform a division operation on an input clock signal to generate a divided clock signal, generate an operating clock signal based on the divided clock signal, and selectively output the operating clock signal to an external device in response to a request signal; and a channel management (CM) circuit, which is configured to receive a request signal across a communication channel from an external device and forward the request signal to the clock control circuit.

[0012] According to an exemplary embodiment of the inventive concept, a method of operating a clock management unit (CMU) includes: the CMU determines whether a request signal received from an intellectual property (IP) block indicates that the IP block needs to enter a selected one of an active mode and a sleep mode; when the request signal indicates that the IP block needs to enter the active mode, the CMU outputs an acknowledgment (Ack) signal and a clock signal at an activation layer to the IP block; and when the clock request signal indicates that the IP block needs to enter the sleep mode, the CMU outputs an Ack signal at a deactivation layer to the IP block and stops outputting the clock signal to the IP block.

[0013] According to an exemplary embodiment of the inventive concept, a clock management unit (CMU) includes a controller circuit, the controller circuit being configured to output a first clock signal based on an output generated from a phase-locked loop or an oscillator; a multiplexing circuit, the multiplexing circuit being configured to output one of the first clock signal and a second clock signal; a first clock frequency division circuit, the first clock frequency division circuit being configured to perform a first frequency division operation on the output of the multiplexing circuit to generate a third clock signal; a quick stop circuit, the quick stop circuit being configured to selectively stop a pulse of the third clock signal to generate a fourth clock signal; a second clock frequency division circuit, the second clock frequency division circuit being configured to perform a second frequency division operation on the output of the quick stop circuit to generate a fifth clock signal; and a first clock gating circuit, the first clock gating circuit being configured to selectively output the fifth clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The concept of the present invention will become more apparent and easier to understand through the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a block diagram of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0016] Figure 2 is a block diagram of a clock management unit (CMU) included in a semiconductor device according to an exemplary embodiment of the inventive concept.

[0017] Figure 3 is a block diagram of an intellectual property (IP) block included in a semiconductor device according to an embodiment of the inventive concept.

[0018] Figure 4 Signal transmission paths between a plurality of clock control circuits of a CMU according to an exemplary embodiment of the inventive concept are described.

[0019] Figure 5A A clock request signal and a clock confirmation signal that may be used in a CMU according to an exemplary embodiment of the inventive concept are described.

[0020] Figure 5B Clock level transitions for clock request signals and clock acknowledgement signals that may occur in a CMU according to an exemplary embodiment of the inventive concept are illustrated.

[0021] Figure 6 An implementation of a clock gating component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0022] Figure 7 A structure of a clock gating component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0023] Figure 8 is a timing diagram illustrating behaviors of a clock gating component included in a semiconductor device according to an exemplary embodiment of the inventive concept.

[0024] Fig.9A An implementation of a clock multiplexer (MUX) component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0025] Fig. 9B A finite state machine (FSM) of a clock MUX component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0026] Fig.10 A structure of a clock MUX component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0027] Figures 11 to 20 is a timing diagram illustrating behavior of a clock MUX component included in a semiconductor device according to an exemplary embodiment of the inventive concept.

[0028] Fig.21A A clock frequency dividing component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0029] Fig.21B A FSM of a clock division component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0030] Fig. 22 A clock frequency dividing component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0031] Fig.23 is a timing diagram illustrating behavior of a clock division component included in a semiconductor device according to an embodiment of the inventive concept.

[0032] Fig.24 A phase locked loop (PLL) controller included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0033] Fig.25 A multiplexer of a PLL controller circuit included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0034] Fig.26 and 27 is a timing diagram illustrating behavior of a PLL controller included in a semiconductor device according to an exemplary embodiment of the inventive concept.

[0035] Fig.28 A PLL user controller included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0036] Fig.29 An adapter assembly included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0037] Fig.30 A structure of a lag filter included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0038] Figures 31 to 33 is a timing diagram illustrating the behavior of a lag filter included in a semiconductor device according to an exemplary embodiment of the inventive concept.

[0039] Fig.34 is a block diagram of a power management unit (PMU) included in a semiconductor device according to an exemplary embodiment of the inventive concept.

[0040] Figures 35 to 39 is a timing diagram illustrating an example of clock on / off operation of the PMU. and

[0041] Fig.40 is a block diagram of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0042] Description of Figure Numbers

[0043] CLK, CLK0, CLK1, CLK2, CLK3, CLK_IN, CLK_OUT, CLK_RF: clock signals;

[0044] REQ1, REQ2, REQ3, PARENT_CLK_REQ, CHILD_CLK_REQ PARENT_CLK_REQ 0, PARENT_CLK_REQ 1, PARENT_CLK_REQ 2, PARENT_CLK_REQ 3, CLK_REQ: clock request signal;

[0045] ACK1, ACK2, ACK3, PARENT_CLK_ACK, CHILD_CLK_ACK, CLK_ACK: clock confirmation signal;

[0046] CH: communication channel;

[0047] 100, 730: clock management unit;

[0048] 101: Input / Output pad;

[0049] 110: CMU controller;

[0050] 120a, 120b, 120c, 120d, 120e, 120f, 120g: clock components;

[0051] 122a, 122b, 122c, 122d, 122e, 122f, 122g: clock control circuit;

[0052] 124a, 124b, 124c, 124d, 124e, 124f, 124g: clock source;

[0053] 124c: frequency division circuit;

[0054] 124d: clock gating circuit;

[0055] 130, 132: channel management circuit;

[0056] 150, 300: Power management unit;

[0057] 151: CMU interface circuit;

[0058] 152: power supply sequence management circuit;

[0059] 153: scan dump sequence management circuit;

[0060] 200: First intellectual property block;

[0061] 210: Second intellectual property block;

[0062] 220: The third intellectual property block;

[0063] 202: channel adapter;

[0064] 204: IP core;

[0065] 700: Semiconductor devices;

[0066] 710: Central processing unit;

[0067] 720: clock generator;

[0068] 740: Random Access Memory;

[0069] 750: read-only memory;

[0070] 760: memory control unit;

[0071] Adapter_CLKGATE: adapter;

[0072] ADAPTER_HYSTERESISFILTER: adapter hysteresis filter;

[0073] CLKGATE_CLK_REQ: clock request;

[0074] CLKDIV_DIVCHG_REQ: clock division ratio change request;

[0075] DIVRATIO: clock division ratio;

[0076] DIVCHG_REQ: request to change the division ratio;

[0077] DIVCHG_ACK: confirmation of change;

[0078] EN: Enable signal;

[0079] EN_FB: feedback signal;

[0080] OSC: oscillator;

[0081] FSM_CLK_REQ: additional clock request;

[0082] H-CH: H channel;

[0083] I, II, III: Partial;

[0084] MUXSEL: multiplexer selection signal;

[0085] MUX: multiplexer;

[0086] MERGE_MUXSEL: Multiplexer.

[0087] PLL: phase-locked loop;

[0088] PREICG: Second logic circuit;

[0089] PARENT_CLK_REQ: clock stop request signal;

[0090] S0, S1, S2, S3, a1, a2, a3, a4, a5, a6, a7, b1, b2, b3, b4, c1, c2, c3, c4, c5: status;

[0091] SEC_AP_RTL_CLKGATE: clock gating unit;

[0092] SYNC_EN: synchronization enable signal;

[0093] SYNC: first logic circuit;

[0094] S-CH: S channel;

[0095] SEL, SEL_OUT: selection signal;

[0096] SEC_AP_RTL_GFMUX: MUX circuit;

[0097] STATUS: signal;

[0098] SEC_AP_RTL_CLKDIV_SKEWLESS: clock division circuit;

[0099] STOPREQ: stop request signal;

[0100] synchronized_CLKDIV_DIVCHG_ACK:input;

[0101] SFR: Special Function Register;

[0102] SYSCLK_OSC: system clock oscillator;

[0103] T1, T2, T3, T4: time;

[0104] Active_PARENT_CLK_REQ, Active_PARENT_CLK_ACK, ADAPTER_CLKDIV, OSCCLK, PLL_FOUT, SEL_REQ0, SEL_REQ1, SEL_ACK0, SEL_ACK1, M UXSEL_ACK[1], synchronized_MUXSEL_REQ[0], synchronized_MUXSEL_REQ[1], MUX_SEL, MUX_STATUS, MUX_SEL_sequential, MUXSEL_ REQ0, MUXSEL_ACK0, RefClk, Hch / Data, Hch / Request_lock, Hch / Acknowledge, CHILD_CLK_ACK[c;0], CHILD_CLK_REQ[c;0], FILTER_R EQ / ACK, FILTERED_REQ, ENABLE_FILTER, EXPIRE_VALU, increase_counter, clear_counter, RefClk, FORCE_AUTOMATIC_CLKGATING: signal;

[0105] SEC_AP_RTL_GFCLKMUX, ADAPTER_CLKMUX, SEC_AP_, SFR I / F, ADAPTER_NULL: module. DETAILED DESCRIPTION

[0106] Figure 1 is a block diagram of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0107] refer to Figure 1 , a semiconductor device according to an exemplary embodiment of the inventive concept includes an input / output (I / O) pad 101, a clock management unit (CMU) 100, a power management unit (PMU) 300, and a logic block (e.g., one or more logic circuits). For example, the logic block can be implemented as one or more intellectual property (IP) blocks 200 to 220. In an embodiment, an IP block is an IP core or a reusable unit of logic or chip layout of a party's intellectual property. In an embodiment, the semiconductor device is or includes a system-on-chip (SoC).

[0108] The CMU 100 generates an operation clock signal to be provided to each of the first to third IP blocks 200 to 220. For example, the CMU 100 may generate first to third clock signals CLK1 to CLK3.

[0109] The first to third IP blocks 200 to 220 may be connected to a system bus and communicate with each other through the system bus. In an embodiment, each of the first to third IP blocks 200 to 220 includes a processor, a graphics processor, a memory controller, an input and output interface block, and the like.

[0110] The CMU 100 may provide a first clock signal CLK1 to the first IP block 200. The CMU 100 may provide a second clock signal CLK2 to the second IP block 210. The CMU 100 may provide a third clock signal CLK3 to the third IP block 220.

[0111] Any of the first to third IP blocks 200 to 220 may transmit a clock request signal to the CMU 100 according to a full handshake method (e.g., synchronous handshake). The clock request signal may indicate that the corresponding IP block requires the CMU 100 to provide a clock signal thereto or requires the CMU 100 to stop providing the clock signal thereto. In an embodiment, in the full handshake method, the CMU 100 responds to the clock request signal with a clock confirmation signal, the clock confirmation signal indicating that the CMU is currently providing or will provide the requested clock signal, or that the CMU has stopped or will stop providing the requested clock signal. In an embodiment, the CMU 100 responds to the clock confirmation signal, the clock confirmation signal only indicating that the CMU confirms receiving the clock request signal, without providing information about the state of the clock signal.

[0112] For example, the first IP block 200 may transmit the first clock request signal REQ1 to the CMU 100 according to the full handshake method. The CMU 100 may transmit the first clock confirmation signal ACK1 to the first IP block 200 in response to the reception of the first clock request signal REQ1. Simultaneously or before transmitting the first clock confirmation signal ACK1, the CMU 100 may transmit the first clock signal CLK1 to the first IP block 200.

[0113] In an embodiment, the interface between the CMU 100 and the first to third IP blocks 200 to 220 has a format of a complete handshake method. In an embodiment, the interface may be implemented to comply with, but not limited to, the Low Power Interface (LPI) of ARM Limited, a Q channel interface, or a P channel interface.

[0114] Clock gating can be used to divide a computer system into small functional blocks and then cut off power to the unused parts. Since not all parts of the computer are always running, blocks in the unused parts can be stopped to reduce power consumption and heat generation in the stopped blocks.

[0115] The CMU 100 according to an exemplary embodiment of the inventive concept performs clock gating on some of the first to third IP blocks 200 to 220 that do not require an operation clock signal. The CMU 100 can reduce power consumption by automatically performing clock gating without generating errors in IP block operations.

[0116] The PMU 300 controls the power supply of the semiconductor device. For example, when the semiconductor device enters the standby mode, the PMU 300 cuts off the power supply of the SoC by cutting off the power control circuit. Here, the PMU 300 continuously consumes power. However, since the power consumed by the PMU 300 is much less than the power consumed by the entire semiconductor device, the power consumption of the semiconductor device in the standby mode is significantly reduced.

[0117] Specifically, when the SoC is in the standby mode, the PMU 300 may cut off the power supply of the CMU 100. This may correspond to a case where there is no clock request from the first to third IP blocks 200 to 220. For example, if none of the IP blocks makes a request for a clock signal within a predefined time period, the PMU 300 may cut off the power supply of the CMU 100.

[0118] Figure 2 is a block diagram of a CMU 100 included in a semiconductor device according to an exemplary embodiment of the inventive concept.

[0119] refer to Figure 2 , the CMU 100 includes clock components 120a to 120g (e.g., clock gating circuits), channel management circuits (CM) 130 and 132, and a CMU controller 110. The clock components 120a to 120g are configured to generate clock signals to be provided to the IP blocks 200 and 210, and the channel management circuits 130 and 132 are disposed between the clock components 120f and 120g and the IP blocks 200 and 210 to provide a communication channel CH between the CMU 100 and the IP blocks 200 and 210. The CMU controller 110 provides the clock signals to the IP blocks 200 and 210 using the clock components 120a to 120g. In an alternative embodiment, the channel management circuits 130 and 132 are omitted, and the last clock component provides the communication channel CH between the CMU 100 and the IP blocks 200 and 210.

[0120] In some embodiments, the communication channel CH provided by the channel management circuits 130 and 132 may be implemented to comply with, but not limited to, LPI, Q-channel interface or P-channel interface of ARM Ltd. The communication channel CH may also be implemented to comply with different communication protocols.

[0121] The clock components 120a to 120g include clock sources (CS) 124a to 124g (e.g., clock signal generators) and clock control circuits (CC) 122a to 122g that respectively control the clock sources 124a to 124g. The clock sources 124a to 124g may include, for example, a multiplexer (MUX) circuit, a clock frequency division circuit, a fast stop circuit, and a clock gating circuit.

[0122] The clock components 120a to 120g form a parent-child relationship with each other. In the present embodiment, the clock component 120a is the parent of the clock component 120b, and the clock component 120b is the child of the clock component 120a and the parent of the clock component 120c. In addition, the clock component 120e is the parent of two clock components 120f and 120g, and the clock components 120f and 120g are the children of the clock component 120e. In the present embodiment, the clock component 120a located closest to the phase locked loop (PLL) is called the root clock component, and the clock components 120f and 120g located closest to the IP blocks 200 and 210 can be called leaf clock components. According to the parent-child relationship between the clock components 120a to 120g, the parent-child relationship must also be formed between the clock control circuits 122a to 122g and the clock sources 124a to 124g.

[0123] The clock control circuits 122 a to 122 g exchange a clock request REQ and an acknowledgement ACK of the clock request REQ between a parent and a child, and provide a clock signal to the IP blocks 200 and 210 .

[0124] If the IP block 200 does not need a clock signal, for example, if the IP block 200 needs to be in a sleep state, the CMU 100 stops providing the clock signal to the IP block 200 .

[0125] Specifically, the channel management circuit 130 transmits a first signal to the IP block 200, the first signal indicating that the channel management circuit will stop providing the clock signal under the control of the CMU 100 or the CMU controller 110. The IP block 200 receiving the first signal transmits a second signal to the channel management circuit 130, the second signal indicating that the clock signal can be stopped after the processed operation is completed. The channel management circuit 130 receiving the second signal from the IP block 200 requests the clock component 120f, that is, its parent, to stop providing the clock signal.

[0126] In an example, if the communication channel CH provided by the channel management circuit 130 complies with the Q channel interface, the channel management circuit 130 transmits a QREQn signal having a first logic value (e.g., logic low, hereinafter indicated by reference character “L”) to the IP block 200 as a first signal. Subsequently, when receiving a QACCEPTn signal having a first logic value as a second signal from the IP block 200, the channel management circuit 130 transmits a clock request REQ (e.g., signal) having a first logic value to the clock component 120f. In this case, the clock request REQ having the first logic value refers to a “clock supply stop request”.

[0127] The clock control circuit 122f receiving the clock request REQ (i.e., the clock supply stop request) having the first logic value from the channel management circuit 130 stops providing the clock signal by deactivating the clock source 124f. For example, the clock control circuit 122f may deactivate the clock source 124f by providing a deactivation signal to the clock source 124f. Therefore, the IP block 200 may enter the sleep mode. In this process, the clock control circuit 122f may provide an acknowledgment ACK having the first logic value to the channel management circuit 130. However, it should be noted that although the channel management circuit 130 receives the acknowledgment ACK having the first logic value after transmitting the clock supply stop request having the first logic value, it does not ensure that the clock supply from the clock source 124f is stopped. In an embodiment, the acknowledgment ACK only means that the clock control circuit 122f recognizes that the clock component 120f (i.e., the parent of the channel management circuit 130) no longer needs to provide the clock signal to the channel management circuit 130.

[0128] At the same time, the clock control circuit 122f of the clock component 120f transmits a clock request REQ having a first logic value to the clock control circuit 122e of the clock component 120e as its parent. If the IP block 210 also does not need a clock signal, for example, if the clock control circuit 122e receives a clock supply stop request from the clock control circuit 122g, the clock control circuit 122e stops supplying the clock signal by deactivating the clock source 124e (for example, a clock frequency dividing circuit). Therefore, the IP blocks 200 and 210 can enter a sleep mode.

[0129] For the other clock control circuits 122a to 122d, the above operation can be performed in the same manner.

[0130] Although the clock control circuit 122f of the clock component 120f transmits the clock request REQ having the first logic value to the clock control circuit 122e of the clock component 120e as its parent, the clock control circuit 122e cannot deactivate the clock source 124e if the IP block 210 is running. The clock control circuit 122e can deactivate the clock source 124e and transmit the clock request REQ having the first logic value to the clock control circuit 120d as its parent only when the IP block 210 no longer needs the clock signal. That is, the clock control circuit 122e can deactivate the clock source 124e only when receiving the clock supply stop request from both the clock control circuits 122f and 122g.

[0131] When the IP blocks 200 and 210 are in the sleep state, all clock sources 124a to 124f may be disabled. Subsequently, when the IP block 200 enters the run state, the CMU 100 resumes providing clock signals to the IP blocks 200 and 210.

[0132] The channel management circuit 130 transmits a clock request REQ having a second logic value (e.g., logic high, hereinafter indicated by reference character "H") to the clock control circuit 122f of the clock component 120f as its parent, and waits for an acknowledgement ACK from the clock control circuit 122f. Here, the clock request REQ having the second logic value is a "clock supply request", and the acknowledgement ACK of the clock supply request indicates that the clock supply through the clock source 124f has been resumed. The clock control circuit 122f cannot immediately enable the clock source 124f (e.g., a clock gating circuit), but waits for the clock signal to be provided through its parent.

[0133] Subsequently, the clock control circuit 122f transmits a clock request REQ (i.e., a clock supply request) having a second logic value to the clock control circuit 122e as its parent, and waits for an acknowledgement ACK from the clock control circuit 122e. This operation can be performed in the same manner for the clock control circuits 122a to 122d. For example, each clock control circuit in the cascade except the first clock control circuit transmits a clock supply request to its parent.

[0134] The first clock control circuit 122a (i.e., the root clock component) receiving the clock request REQ having the second logic value from the clock control circuit 122b enables the first clock source 124a (e.g., the MUX circuit) and transmits the confirmation ACK to the second clock control circuit 122b. The second clock control circuit 122b enables the second clock source 124b in response to receiving the ACK from the first clock control circuit 122a, and transmits the ACK to the third clock control circuit 122c. The process is repeated by the third, fourth, and fifth clock control circuits 122c-122e. After sequentially enabling the clock sources 124b to 124e in this manner, the fifth clock control circuit 122e finally transmits the confirmation ACK to the first leaf clock control circuit 122f, and the confirmation ACK notifies the leaf clock control circuit that the clock has been restored by the clock source 124e. The first leaf clock control circuit 122f receiving the confirmation ACK provides the clock signal to the IP block 200 by enabling the clock source 124f, and provides the confirmation ACK to the channel management circuit 130.

[0135] As described above, the clock control circuits 122a to 122g operate according to a complete handshake method (e.g., synchronous handshake), in which a clock request REQ and an acknowledgement ACK of the clock request REQ are exchanged between a parent and a child. Therefore, the clock control circuits 122a to 122g can control the clock signals provided to the IP blocks 200 and 210 by controlling the hardware aspects of the clock sources 124a to 124g.

[0136] The clock control circuits 122a to 122g may transmit the clock request REQ to their parents, or control the clock sources 124a to 124g by operating independently or under the control of the CMU controller 110. In some embodiments, the clock control circuits 122a to 122g may respectively include finite state machines (FSM) that control the clock sources 124a to 124g according to the clock request REQ exchanged between the parent and the child.

[0137] although Figure 2 A cascaded clock component tree including five clock components and two leaf clock components is shown, but the inventive concept is not limited thereto. In alternative embodiments, one or more of these clock components may be omitted. In a first embodiment, only the first clock component 120a and the first leaf clock component 120f are present, the second to fifth clock components 120b-120e are omitted, and the second leaf clock component 120g is omitted. In a second embodiment, only the second clock component 120b and the first leaf clock component 120f are present, the first clock component 120a is omitted, the third to fifth clock components 120c-120e are omitted, and the second leaf clock component 120g is omitted. In a third embodiment, only the third clock component 120c and the first leaf clock component 120f are present, the first to second clock components 120a-120b are omitted, the fourth to fifth clock components 120d-e are omitted, and the second leaf clock component 120g is omitted. In the fourth embodiment, only the fourth clock component 120d and the first leaf clock component 120f are present, the first to third clock components 120a-120c are omitted, the fifth clock component 120e is omitted, and the second leaf component 120g is omitted. In the fifth embodiment, only the fifth clock component 120e and the first leaf clock component 120f are present, the first to fourth clock components 120a-120d are omitted, and the second leaf clock component 120g is omitted. These embodiments can be further changed by various other combinations. For example, in the sixth embodiment, the first to second clock components 120a-120b are present, the first leaf clock component 120f is present, the third to fifth clock components 120b-120e are omitted, and the second leaf clock component 120g is omitted.

[0138] In an exemplary embodiment, the first clock component 120a is a phase-locked loop (PLL) controller.

[0139] In an exemplary embodiment, the PLL controller receives a constant or variable frequency signal oscillated by an oscillator OSC and a PLL signal output by a PLL from an oscillator OSC, and outputs one of the two received signals based on a specific condition. When a component needs a PLL signal, the PLL controller outputs the PLL signal. When a component needs an oscillator signal, the PLL controller outputs an oscillator signal. When there is no component using the output of the PLL, in an embodiment of the inventive concept, the PLL controller turns off the PLL. In an alternative embodiment, when there is no component using the output of the PLL, the PLL controller automatically controls the PLL to enter a bypass mode. In another alternative embodiment, when there is no component using the output of the PLL, the PLL controller does not affect the operation of the PLL at all.

[0140] The PLL controller can be replaced with any component that generates a clock signal. For example, the PLL controller can be implemented using a ring oscillator or a crystal oscillator.

[0141] In an exemplary embodiment of the inventive concept, the clock component 120 b is a clock multiplexer (MUX) unit.

[0142] In an embodiment, the clock MUX unit includes a clock control circuit 122b and a MUX circuit 124b. The clock control circuit 122b of the clock MUX unit can be operated by sequential behavior. The clock control circuit 122b can control the opening or closing of the clock signal. In order to change the MUX selection of the clock MUX unit in a state where the clock signal is turned off, the clock control circuit 122b generates a clock request signal. The clock request signal generated by the clock control circuit 122b for changing the MUX selection can be provided only to the previous parent clock component and the next parent clock component, or can be provided to all possible parent clock components. In an alternative embodiment, the clock control circuit 122b does not generate a clock request signal for changing the MUX selection in a state where the clock signal is turned off. For example, in this embodiment, the clock control circuit 122b only changes the MUX selection when the clock signal is turned on.

[0143] The clock control circuit 122b of the clock MUX unit can transmit the clock request signal only to the parent clock component used. The clock MUX unit can have two or more than two input clock signals. For example, Figure 2 A MUX circuit 124b is shown that receives a first clock signal CLK1 output from the first clock control circuit 122a and a second clock signal CLK2 that may be received from an external CMU or other external device. The MUX circuit 124b may then select one of the first clock signal CLK1 and the second clock signal CLK2 for output based on certain conditions.

[0144] In an exemplary embodiment of the inventive concept, the clock component 120c is a clock frequency division unit, for example, a clock frequency divider circuit (e.g., a frequency division circuit). The clock frequency divider circuit obtains an input signal having an input frequency and generates an output signal by dividing the input frequency by an output frequency generated by a clock frequency division ratio. For example, the frequency division ratio can be an integer greater than 1.

[0145] In an embodiment, the clock frequency division unit includes a clock control circuit 122c and a frequency division circuit 124c. The clock control circuit 122c of the clock frequency division unit can be operated by sequential behavior. The clock control circuit 122c can control the opening or closing of the clock signal output by the frequency division circuit 124c. In order to change the clock frequency division ratio of the frequency division circuit 124c in a state where the clock signal is turned off, the clock control circuit 122c can generate a clock request signal. For example, the clock control circuit 122c can output the clock request signal to the root clock component, and the root clock component causes the frequency division circuit 124c to start receiving the clock signal so that the frequency division circuit can perform a frequency division operation on the received clock signal. In an alternative embodiment, the clock control circuit 122c does not generate a clock request signal for changing the clock frequency division ratio of the frequency division circuit 124c in a state where the clock signal is turned off. For example, in this embodiment, the clock control circuit 122c changes the clock frequency division ratio only when the clock signal is turned on.

[0146] In an exemplary embodiment, the clock component 120d is a shortstop unit. In an embodiment, the shortstop unit provides a plurality of pulses to the clock signal during a first cycle, stops the pulses during a second cycle after the first cycle, and resumes the pulses during a third cycle after the second cycle.

[0147] The quick stop unit includes a clock control circuit 122d and a clock gating circuit 124d. In an embodiment, the clock gating circuit 124d selectively outputs a clock signal based on a specific condition. The clock control circuit 122d of the quick stop unit can operate by sequential behavior. The clock control circuit 122d can control the turning on or off of the clock signal. When the clock request signal from the child clock component is inactive, the clock control circuit 122d can activate the clock gating circuit 124d. For example, even if the clock control circuit 122d has been notified to stop providing the clock signal through the child clock component, the clock control circuit 122d can also activate the clock gating circuit 124d when a specific condition occurs.

[0148] In an exemplary embodiment of the inventive concept, each of the leaf clock components 120f and 120g is a clock gating unit. In the embodiment where the leaf clock components 120f and 120g are clock gating units, each component includes a clock gating circuit.

[0149] The clock gating unit may communicate with at least one of the channel management circuits 130 and 132 according to a full handshaking method.

[0150] refer to Figure 1 and 2 In an exemplary embodiment of the inventive concept, the PMU 300 transmits a power control signal to the oscillator OSC in response to a wake-up signal received in the standby mode. The oscillator OSC is an oscillation circuit that generates a specific frequency signal and supplies an operation clock signal to a logic block (e.g., the clock component 120a). The crystal oscillator generates a signal at an accurate and stable oscillation frequency using piezoelectric oscillation of a crystal XTAL.

[0151] When power is input to the oscillator OSC, the oscillator OSC starts to oscillate. The oscillator OSC initially outputs an accurate and unstable signal, and then gradually starts to output a stable crystal clock signal. After the crystal clock signal output from the oscillator OSC is stabilized, the CMU 100 can supply an operation clock signal to the logic block.

[0152] Figure 3 is a block diagram of an IP block included in a semiconductor device according to an exemplary embodiment of the inventive concept.

[0153] refer to Figure 3 , the first IP block 200 includes a channel adapter 202 and an IP core 204. Figure 3 , the first IP block 200 is illustrated as an example. However, the second IP block 210 and the third IP block 220 may include substantially the same elements as the first IP block 200.

[0154] In an embodiment, the channel adapter 202 communicates with the first channel management circuit 130 according to a full handshake method. Through the channel adapter 202, the first IP block 200 can transmit the first clock request signal REQ1 and receive the first clock signal CLK1. For example, the first IP block 200 can transmit REQ1 to the first channel management circuit 130, and receive the clock signal CLK output by the leaf clock component 120f as CLK1 in response to transmitting REQ1. Alternatively, through the channel adapter 202, the first IP block 200 can transmit the first clock request signal REQ1, receive a confirmation signal indicating the presence of the clock signal, and directly receive the first clock signal CLK1 from the clock component controlled by the channel adapter 202.

[0155] IP core 204 may include, for example, a processor, a graphics processor, a memory controller, input and output interface blocks, and the like.

[0156] Figure 4 The signal transmission paths between multiple clock control circuits are described.

[0157] refer to Figure 4 , the clock control circuit can operate using a handshake signal, the handshake signal including a clock request signal REQ and an acknowledgement (or clock acknowledgement signal) ACK as a response signal to the clock request signal REQ. The clock request signal REQ and the clock acknowledgement signal ACK can have, for example, a first logic value (e.g., logic low) or a second logic value (e.g., logic high). However, the clock request signal REQ and the clock acknowledgement signal ACK can also be implemented by other methods.

[0158] In an exemplary embodiment of the inventive concept, the clock consumer transmits a clock request signal REQ having a second logic value to the clock provider, thereby notifying the clock provider that a clock signal is needed. Conversely, the clock consumer may transmit a clock request signal REQ having a first logic value to the clock provider, thereby notifying the clock provider that a clock signal is no longer needed.

[0159] At the same time, the clock provider may transmit a clock confirmation signal ACK having a second logic value to the clock consumer. The clock confirmation signal ACK having the second logic value indicates that the clock signal is stably provided to the clock consumer by the clock provider. On the contrary, the clock provider may transmit a clock confirmation signal ACK having a first logic value to the clock consumer. In an embodiment, the clock confirmation signal ACK having a first logic value indicates that the clock provider cannot notify the clock consumer to provide the clock signal. For example, the clock provider providing an ACK having a first logic level may indicate that the clock provider only understands the clock consumer's demand for the clock signal, but is unable to notify the clock consumer when the clock signal is stably provided.

[0160] In an example, the clock control circuit 122b as a clock consumer may transmit a clock request signal PARENT_CLK_REQ having a second logic value, for example, to the clock control circuit 122a as a clock provider, thereby notifying the clock control circuit 122a that a clock signal is required. Therefore, the clock component (i.e., the clock provider) including the clock control circuit 122a may transmit a clock signal to the clock component (i.e., the clock consumer) including the clock control circuit 122b. Subsequently, the clock control circuit 122b may receive a clock confirmation signal PARENT_CLK_ACK having a second logic value, for example, from the clock control circuit 122a.

[0161] At the same time, the clock control circuit 122b as a clock provider can receive, for example, a clock request signal CHILD_CLK_REQ having a second logic value from the clock control circuit 122f. By receiving the clock request signal CHILD_CLK_REQ having a second logic value, the clock control circuit 122b can understand that the clock control circuit 122f as a clock consumer needs a clock signal. Therefore, the clock component (i.e., the clock provider) including the clock control circuit 122b can provide the clock signal to the clock component (i.e., the clock consumer) including the clock control circuit 122f. At the same time, the clock control circuit 122b as a clock provider can transmit, for example, a clock confirmation signal CHILD_CLK_ACK having a second logic value to the clock control circuit 122f.

[0162] In another example, the clock control circuit 122b as a clock consumer may transmit a clock request signal PARENT_CLK_REQ having a first logic value, for example, to the clock control circuit 122a as a clock provider, thereby notifying the clock control circuit 122a that the clock signal is no longer needed. Therefore, the clock control circuit 122b may receive a clock confirmation signal PARENT_CLK_ACK having a first logic value, for example, from the clock control circuit 122a. The clock confirmation signal PARENT_CLK_ACK having a first logic value indicates that the clock is not guaranteed to be provided by the clock provider.

[0163] At the same time, the clock control circuit 122b as a clock provider can receive a clock request signal CHILD_CLK_REQ having a first logic value, for example, from the clock control circuit 122f. The clock request signal CHILD_CLK_REQ having the first logic value indicates that the clock control circuit 122f as a clock consumer no longer needs the clock signal. Therefore, the clock control circuit 122b can transmit a clock confirmation signal CHILD_CLK_ACK having a second logic value, for example, to the clock control circuit 122f. The clock confirmation signal CHILD_CLK_ACK having the second logic value indicates that the clock is not guaranteed to be provided by the clock provider.

[0164] It should be noted that the combination path between these clock control circuits may include a first path (e.g., a first conductor or a communication channel) through which the clock control circuit 122b transmits a clock request signal PARENT_CLK_REQ to the clock control circuit 122a as its parent and then receives a clock confirmation signal PARENT_CLK_ACK from the clock control circuit 122a as its parent; and a second path (e.g., a second conductor or a communication channel) through which the clock control circuit 122b receives a clock request signal CHILD_CLK_REQ from the clock control circuit 122f as its child and then transmits a clock confirmation signal CHILD_CLK_ACK to the clock control circuit 122f as its child, but the combination path does not include a path (in Figure 4 For example, if path X exists, the clock confirmation signal PARENT_CLK_ACK received from the clock control circuit 122 a may pass through path X or the clock request signal PARENT_CLK_REQ may pass through path X.

[0165] The clock request signal REQ and the clock confirmation signal ACK are implemented according to the full handshake method, and the clock provider and the clock consumer may belong to a single clock domain or different clock domains. When the clock provider and the clock consumer belong to a single clock domain, the clock provider and the clock consumer operate in response to the same reference clock signal. When the clock provider and the clock consumer belong to different clock domains, the clock provider and the clock consumer operate in response to different reference clock signals.

[0166] In an exemplary embodiment, a clock MUX circuit, a clock frequency division circuit, a clock gating circuit, etc., which are respectively connected to the clock control circuit for communication, use different clock domains from the clock control circuit. That is, the clock frequency in the signal line transmitting the clock request signal may be different from the clock frequency of the operating clock signal actually provided.

[0167] Figure 5A The clock request signal REQ and the clock confirmation signal ACK used in this article are explained. Figure 5B Clock level transitions for a clock request signal REQ and a clock acknowledgement signal ACK used herein are described.

[0168] refer to Figure 5A , the clock request signal REQ transitions to the second logic value at time T1. This may indicate that the clock consumer notifies the clock provider that the clock consumer needs the clock signal CLK. After time T1, the clock provider may provide the clock signal CLK to the clock consumer.

[0169] At time T2, the clock provider transmits a clock confirmation signal ACK having a second logic value to the clock consumer. This indicates that the clock signal CLK is stably provided to the clock consumer by the clock provider (see Part I).

[0170] At time T3, the clock request signal REQ transitions to a first logic value. This may indicate that the clock consumer notifies the clock provider that the clock signal CLK is no longer needed. At time T3, the clock provider may stop providing the clock signal CLK to the clock consumer, or may continue to provide the clock signal CLK.

[0171] At time T4, the clock provider may transmit a clock confirmation signal ACK having a first logic value to the clock consumer, which indicates that the clock provider cannot notify the clock consumer to provide the clock signal CLK.

[0172] That is to say, Figure 5A Among them, the part in which it is guaranteed that the clock signal CLK is stably provided to the clock consumer by the clock supplier is only part I. In the other part II, it is impossible to know whether the clock signal CLK is provided to the clock consumer by the clock supplier.

[0173] exist Figure 5B In FIG. 1 , possible combinations of the clock request signal REQ and the clock confirmation signal ACK and possible transitions therebetween are described when the second logic value is expressed as “1” and the first logic value is expressed as “0”.

[0174] In addition, state S2 is from time T2 to time T3, and state S3 is from time T3 to time T4. The combination of the values ​​of the clock request signal REQ and the clock confirmation signal ACK sequentially changes from state S0 to state S1, state S2, state S3, and then changes to state S0 (see the solid arrow).

[0175] If the circuit is implemented so that at time T1, the clock request signal REQ and the clock confirmation signal ACK are simultaneously transferred to the second logic value, the combination of the values ​​of the clock request signal REQ and the clock confirmation signal ACK can directly switch from state S0 to state S2. Similarly, if the circuit is implemented so that at time T3, the clock request signal REQ and the clock confirmation signal ACK simultaneously transition to the first logic value, the combination of the values ​​of the clock request signal REQ and the clock confirmation signal ACK can directly switch from state S2 to state S0 (see the dotted arrow).

[0176] Will refer to it again Figure 1 , 2 and 4 describe the full handshake method.

[0177] According to the full handshake method, when the first IP block 200 needs a clock signal, the first IP block activates the first clock request signal REQ1. For example, the first IP block 200 sets the first clock request signal REQ1 to a high state.

[0178] The CMU 100 activates the first clock confirmation signal ACK1 for the first clock request signal REQ1 in response to the activation of the first clock request signal REQ1. That is, the CMU 100 sets the first clock confirmation signal ACK1 to a high state.

[0179] The CMU 100 may transmit the first clock signal CLK1 to the first IP block 200 before activating the first clock confirmation signal ACK1. Alternatively, the CMU 100 may transmit the first clock signal CLK1 to the first IP block 200 while activating the first clock confirmation signal ACK1.

[0180] When the first IP block 200 does not need a clock signal, the first clock request signal REQ1 is deactivated. That is, the first IP block 200 sets the first clock request signal REQ1 to a low state.

[0181] When the first clock request signal REQ1 is in a low state, the CMU 100 sets the first clock confirmation signal ACK1 to a low state. At the same time, the CMU 100 may deactivate the first clock signal CLK1.

[0182] When the first clock confirmation signal ACK1 is active, the first IP block 200 can operate normally. For example, when the first clock confirmation ACK1 is in a high state, the first IP block 200 can operate normally. When the first IP block 200 senses that the first clock confirmation signal ACK1 has reached a low state, the first IP block can switch to a sleep mode.

[0183] Now refer to Figure 1 and 2 A full handshake method of the CMU 100 according to an exemplary embodiment of the inventive concept is described. The full handshake method will be described based on the following assumptions: Figure 2The clock components 120a to 120f are respectively a PLL controller, a clock MUX unit, a first clock frequency division unit, a quick stop unit, a second clock frequency division unit and a first clock gating unit. However, this is merely an example in which the inventive concept can be implemented, and the scope of the present invention is not limited thereto. In an embodiment, the PLL controller deactivates the PLL in response to a request signal from a daughter clock component, and then relies on the OSC. In an embodiment, the quick stop unit includes a quick stop circuit, which is configured to temporarily stop the clock signal within a certain time period. For example, the quick stop circuit maintains the pulse of the clock signal during the first cycle, sets the clock signal to a constant low (e.g., deactivates the pulse) during the second cycle, and restores the pulse of the clock signal during the third cycle.

[0184] The PLL controller, the clock MUX unit, the first clock frequency dividing unit, the fast stop unit, the second clock frequency dividing unit and the first clock gating unit may include clock sources 124 a to 124 f , respectively.

[0185] Specifically, the PLL controller may include a clock MUX circuit, which receives signals from the oscillator OSC and the PLL. The clock MUX unit may include a clock MUX circuit, which receives multiple clock signals. The first clock frequency division unit may include a first clock frequency division circuit. The fast stop circuit may include a first clock gating circuit. The second clock frequency division unit may include a second clock frequency division circuit. The first clock gating unit may include a second clock gating circuit.

[0186] In addition, the PLL controller may include a clock control circuit 122a. The clock MUX unit may include a clock control circuit 122b. The first clock frequency division unit may include a clock control circuit 122c. The fast stop circuit may include a clock control circuit 122d. The second clock frequency division unit may include a clock control circuit 122e. The first clock gating unit may include a clock control circuit 122f.

[0187] Each of the clock control circuits 122a to 122f may communicate according to a full handshake method. For example, each of the clock control circuits 122a and 122b may support a full handshake method between a PLL controller and a clock MUX unit.

[0188] Each of the clock control circuits 122 b and 122 c may support a full handshake method between the clock MUX unit and the first clock frequency dividing unit.

[0189] Each of the clock control circuits 122c and 122d may support a full handshake method between the first clock frequency dividing unit and the faststop circuit.

[0190] Each of the clock control circuits 122d and 122e may support a full handshake method between the faststop circuit and the second clock dividing unit.

[0191] Each of the clock control circuits 122e and 122f may support a full handshake method between the second clock dividing unit and the first clock gating unit.

[0192] Likewise, each of the clock control circuit 122 f and the channel management circuit 130 may support a full handshake method between the first clock gating unit and the channel management unit 130 .

[0193] The first IP block 200 may request the CMU 100 to provide an operation clock signal according to the full handshake method. For example, when the first IP block 200 needs an operation clock signal, the first IP block may activate a clock request signal. That is, when the first IP block 200 needs an operation clock signal, the first IP block may transmit the activated clock request signal to the CMU 100.

[0194] The channel management circuit 130 receives the activated clock request signal. The channel management circuit 130 transmits the activated clock request signal to the first clock gating unit (e.g., clock component 120f). The first clock gating unit transmits the activated clock request signal to the second clock dividing unit (e.g., clock component 120e). The second clock dividing unit transmits the activated clock request signal to the fast stop circuit (e.g., clock component 120d). The fast stop circuit transmits the activated clock request signal to the first clock dividing unit (e.g., clock component 120c). The first clock dividing unit transmits the activated clock request signal to the clock MUX unit (e.g., clock component 120b). The clock MUX unit transmits the activated clock request signal to the PLL controller (e.g., clock component 120a).

[0195] In an exemplary embodiment, each of the PLL controller, the clock MUX unit, the first clock frequency division unit, the fast stop unit, the second clock frequency division unit, the first clock gating unit, and the first channel management circuit 130 is implemented as a combinational circuit. Therefore, the activated clock request signal can be transmitted to the first channel management circuit 130 through the PLL controller at any time.

[0196] The PLL controller activates a clock confirmation signal for the activated clock request signal. That is, the PLL controller transmits the activated clock confirmation signal generated in response to the activated clock request signal to the clock MUX unit. At the same time, the PLL controller transmits the clock signal CLK to the clock MUX unit. For example, the PLL controller can transmit the clock signal CLK to the clock MUX unit, and the PLL controller transmits the activated clock confirmation signal at the same time.

[0197] The clock MUX unit transmits the activated clock confirmation signal to the first clock frequency division unit. At the same time, the clock MUX unit transmits the clock signal CLK to the first clock frequency division unit. For example, the clock MUX unit can transmit the clock signal CLK to the first clock frequency division unit, and at the same time, the clock MUX unit transmits the activated clock confirmation signal.

[0198] The first clock frequency division unit transmits the activated clock confirmation signal to the quick stop circuit. At the same time, the first clock frequency division unit transmits the clock signal CLK to the quick stop circuit. For example, the first clock frequency division unit can transmit the clock signal CLK to the quick stop circuit, and at the same time, the first clock frequency division unit transmits the activated clock confirmation signal.

[0199] The quick stop unit transmits the activated clock confirmation signal to the second clock frequency division unit. At the same time, the quick stop unit transmits the clock signal CLK to the second clock frequency division unit. For example, the quick stop unit can transmit the clock signal CLK to the second clock frequency division unit, and at the same time, the quick stop unit transmits the activated clock confirmation signal.

[0200] The second clock frequency division unit transmits the activated clock confirmation signal to the first clock gating unit. At the same time, the second clock frequency division unit transmits the clock signal CLK to the first clock gating unit. For example, the second clock frequency division unit can transmit the clock signal CLK to the second clock frequency division unit, and at the same time, the second clock frequency division unit transmits the activated clock confirmation signal.

[0201] The first clock gating unit transmits the activated clock confirmation signal to the first channel management circuit 130. At the same time, the first clock gating unit provides the clock signal CLK to the first IP block 200. For example, the first clock gating unit may transmit the clock signal CLK to the first channel management circuit 130 while the first clock gating unit transmits the activated clock confirmation signal.

[0202] In the current embodiment, the clock confirmation signal may be transmitted to the PLL controller through the first channel management circuit 130 at a time.

[0203] When the first IP block 200 does not need a clock signal, the first IP block may deactivate the clock request signal. That is, when the first IP block 200 does not need a clock signal, the first IP block may transmit a deactivated clock request signal to the CMU 100.

[0204] The channel management circuit 130 receives the deactivated clock request signal. The channel management circuit 130 may transmit the deactivated clock request signal to the first clock gating unit. The first clock gating unit transmits the deactivated clock request signal to the second clock frequency division unit. The second clock frequency division unit transmits the deactivated clock request signal to the quick stop circuit. The quick stop circuit may transmit the deactivated clock request signal to the first clock frequency division unit. The first clock frequency division unit may transmit the deactivated clock request signal to the clock MUX unit. The clock MUX unit may transmit the deactivated clock request signal to the PLL controller.

[0205] Each of the PLL controller, the clock MUX unit, the first clock frequency division unit, the fast stop unit, the second clock frequency division unit, the first clock gating unit, and the first channel management circuit 130 can be implemented as a combination circuit. Therefore, the deactivated clock request signal can be transmitted to the channel management circuit 130 by the PLL controller at any time.

[0206] In response to the deactivated clock request signal, the PLL controller deactivates the clock confirmation signal. That is, the PLL controller can transmit the deactivated clock confirmation signal to the clock MUX unit. At the same time, the PLL controller can deactivate the clock signal CLK or can continue to transmit the clock signal CLK to the clock MUX unit.

[0207] The clock MUX unit transmits the deactivated clock confirmation signal to the first clock frequency dividing unit. Meanwhile, the clock MUX unit may transmit the deactivated clock signal CLK or may still transmit the clock signal CLK to the first clock frequency dividing unit.

[0208] The first clock frequency dividing unit transmits the deactivated clock confirmation signal to the fast stop circuit. Meanwhile, the first clock frequency dividing unit can deactivate the clock signal CLK or can still transmit the clock signal CLK to the fast stop unit.

[0209] The quick stop circuit transmits the deactivated clock confirmation signal to the second clock frequency division unit. At the same time, the quick stop circuit can deactivate the clock signal CLK or can still transmit the clock signal CLK to the second clock frequency division unit.

[0210] The second clock frequency dividing unit transmits the deactivated clock confirmation signal to the first clock gating unit. Meanwhile, the second clock frequency dividing unit can deactivate the clock signal CLK or can still transmit the clock signal CLK to the first clock gating unit.

[0211] The first clock gating unit transmits the deactivated clock confirmation signal to the channel management circuit 130. At the same time, the first clock gating unit deactivates the clock signal CLK.

[0212] Likewise, the clock confirmation signal may be transmitted to the PLL controller via the first channel management circuit 130 at each time.

[0213] Various types of clock components included in a semiconductor device according to embodiments will now be described.

[0214] Figure 6 An implementation of a clock gating component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described. Figure 7 A structure of a clock gating component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described. Figure 8 is a timing diagram illustrating the behavior of a clock gating component included in a semiconductor device according to an embodiment of the present invention. Figure 6 or Figure 7 The clock gating component implements the clock component 120f or the clock component 120g.

[0215] refer to Figure 6 According to an embodiment of the present invention, a clock gating component included in a semiconductor device includes a finite state machine (FSM) and a clock gating unit SEC_AP_RTL_CLKGATE. Here, FSM refers to a computing model or machine consisting of a finite number of states and transitions between states. The FSM and / or the clock gating unit SEC_AP_RTL_CLKGATE can be implemented using one or more logic gates. In an embodiment, the clock control circuit 122f or the clock control circuit 122g is implemented by the FSM, and the clock source 124f or the clock source 124g is implemented by the clock gating unit SEC_AP_RTL_CLKGATE. Figure 6 The FSM and clock gating unit SEC_AP_RTL_CLKGATE correspond to Figure 7 Here, the FSM or adapter can operate with a reference clock signal CLK_RF belonging to a different clock domain from the clock signal CLK generated by the clock component and perform a full handshake with the clock gating unit SEC_AP_RTL_CLKGATE.

[0216] The FSM may receive a clock request signal CHILD_CLK_REQ from a child clock component and transmit the clock request signal PARENT_CLK_REQ to a parent clock component or output an enable signal EN to control a clock gating unit SEC_AP_RTL_CLKGATE according to a state of the FSM. For example, based on the state of the clock request signal CHILD_CLK_REQ and its corresponding confirmation received in response to sending the parent clock request signal PARENT_CLK_REQ, the FSM may determine that it is time to activate a clock source (e.g., a clock gating unit SEC_AP_RTL_CLKGATE), and thus output an enable signal EN to enable the clock source to output a clock signal CLK_OUT based on an input clock signal CLK_IN. The clock gating unit SEC_AP_RTL_CLKGATE sends an enable feedback signal EN_FB to the FSM in response to the received enable signal EN or after it starts outputting the clock signal CLK_OUT in response to the received enable signal.

[0217] The clock gating unit SEC_AP_RTL_CLKGATE receives the clock signal CLK_IN according to the enable signal EN output from the FSM and outputs a clock signal CLK_OUT obtained by gating or bypassing the clock signal CLK_IN.

[0218] Also refer to Figure 8 , the FSM of the clock gating component can contain the following states.

[0219] The first state a1 is a state in which the clock gating component provides the clock signal CLK to the child clock component according to the clock request signal CHILD_CLK_REQ having the second logic value received from the child clock component without performing a clock gating operation. Assume that the clock request signal CHILD_CLK_REQ received from the child clock component transitions to the first logic value later.

[0220] The second state a2 is a state in which the clock gating component performs a clock gating operation. Therefore, after a local handshake delay period required for the clock gating operation of the clock gating component, the clock gating component transmits a clock confirmation signal CHILD_CLK_ACK having a first logic value to the child clock component. In addition, the clock gating component transmits a clock request signal PARENT_CLK_REQ having a first logic value to the parent clock component.

[0221] In the third state a3, the clock gating component requests the parent clock component to stop providing the clock by transmitting the clock request signal PARENT_CLK_REQ having a first logic value to the parent clock component. In the fourth state a4, the clock gating component waits until the clock gating component receives the clock confirmation signal PARENT_CLK_ACK having a first logic value from the parent clock component. This indicates that since the gating operation of the clock gating component has been completed, the clock gating operation of the parent component can be performed when necessary.

[0222] After receiving the clock acknowledgement signal PARENT_CLK_ACK having the first logic value from the parent clock component, the child clock component that supplies the clock to the clock gating component is completely stopped in the fifth state a5.

[0223] Here, when receiving the clock request signal CHILD_CLK_REQ having the second logic value from the child clock component, the clock gating component transmits the clock request signal PARENT_CLK_REQ having the second logic value to the parent clock component and then stops the clock gating operation in a sixth state a6.

[0224] After the local handshake delay period required to stop the clock gating operation, if the clock gating component receives the clock confirmation signal PARENT_CLK_ACK having the second logic value from the parent clock component, the clock gating component switches to the seventh state a7. Here, the seventh state a7 is the same as the first state a1.

[0225] The clock gating unit SEC_AP_RTL_CLKGATE includes a first logic circuit SYNC and a second logic circuit PREICG. The first logic circuit SYNC provides an enable feedback signal EN_FB to the FSM in response to receiving an enable signal EN, and provides a synchronization enable signal SYNC_EN to the second logic circuit PREICG based on the input clock signal CLK_IN after receiving the enable signal EN. The second logic circuit PREICG outputs an output clock output signal CLK_OUT based on the input clock signal CLK_IN in response to the synchronization enable signal SYNC_EN. The second logic circuit PREICG can be used to ensure that a stable clock signal is output.

[0226] Fig.9A The implementation of a clock MUX component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described. In the embodiment, the clock component 120b is connected by Fig.9A Circuit implementation. Fig. 9B A FSM of a clock MUX component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described. Fig.10A structure of a clock MUX component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described. Figures 11 to 20 is a timing diagram illustrating behavior of a clock MUX component included in a semiconductor device according to an exemplary embodiment of the inventive concept.

[0227] refer to Fig.9A , a clock MUX component included in a semiconductor device according to an exemplary embodiment of the inventive concept includes a FSM and a MUX circuit SEC_AP_RTL_GFMUX. The MUX circuit SEC_AP_RTL_GFMUX includes first and second logic circuits SEC_AP_RTL_CLKGATE for receiving a first clock signal CLK0 and a second clock signal CLK1, and a multiplexer MUX that can provide a STATUS signal to the FSM, the STATUS signal indicating whether the multiplexer MUX is currently outputting one of the clock signals or has received an output selection signal SEL_OUT from the FSM. The FSM receives a clock request signal CHILD_CLK_REQ from a child clock component through an adapter gate Adapter_CLKGATE (e.g., a logic circuit), and transmits clock request signals PARENT_CLK_REQ 0 and PARENT_CLK_REQ 1 to a parent clock component. For example, the first parent clock request signal PARENT_CLK_REQ 0 may be transmitted to the clock component 120 a , and the second parent clock request signal PARENT_CLK_REQ 1 may be transmitted to the external clock component.

[0228] Here, the clock MUX component may include a non-interference MUX. Interference refers to a temporary malfunction of a computer due to noise.

[0229] The FSM receives the select signal SEL. When the FSM determines that the value of the select signal SEL has changed, the FSM compares the select signal SEL and the multiplexer select signal MUXSEL and determines whether these signals have the same value.

[0230] When the selection signal SEL and the multiplexer selection signal do not have the same value, the FSM generates a detection change signal. Here, the detection change signal can be generated by switching the value of the detection change signal having a low state to a high state or by switching the value of the detection change signal having a high state to a low state.

[0231] In response to the selection signal SEL_OUT output from the FSM to the multiplexer, the clock MUX component outputs the first clock signal CLK0 or the second clock signal CLK1 as the clock signal CLK_OUT. The sub-generation clock component receives the clock output from the clock MUX component. The first clock signal CLK0 can be output by the clock component 120a, and the second clock signal CLK1 can be output by the external clock component.

[0232] Also refer to Fig. 9B , the FSM contained in the Clock MUX component can contain the following states.

[0233] The first state b1 is a state in which clock gating is performed by hardware. This is a state in which both the parent clock component (of the clock MUX component) that stops providing the clock to the child clock component and the parent clock component (of the clock MUX component) that still provides the clock signal exist. However, in this state, it is not guaranteed that all parent clock components of the clock MUX component are in operation. That is, since the operation of unnecessary parent clock components is stopped in this state, power consumption may be the lowest. Therefore, the clock MUX component cannot change its selection according to the selection signal SEL. Unlike the clock gating component, the clock MUX component can maintain the optimal state even when receiving a clock request signal from the child clock component.

[0234] In the second state b2, all parent clock components of the clock MUX component are awakened because the clock MUX component needs to change its selection according to the selection signal SEL.

[0235] The third state b3 is a state in which clock gating by hardware is not performed. That is, all awakened parent clock components are providing clock signals to the clock MUX component. In this state, the clock MUX component can change its selection according to the selection signal SEL.

[0236] In the fourth state b4, the clock gating by hardware is restored after the clock MUX component changes its selection according to the selection signal SEL. Therefore, the operation of the parent clock component that does not need the clock signal starts to stop in the fourth state b4. That is, in the fourth state b4, the clock stop request signal PARENT_CLK_REQ is transmitted to the parent clock component that does not need the clock signal.

[0237] After receiving the clock acknowledgement signal PARENT_CLK_ACK from the parent clock component that does not require a clock signal, the clock MUX component returns to the first state b1. Figures 11 to 20 The fifth state b5 described in is the same as the first state b1.

[0238] refer to Fig.10A clock MUX component included in a semiconductor device according to an exemplary embodiment of the inventive concept includes a gasket (e.g., a register), an arbitrator (e.g., an arbitration circuit), a MUX converter, an adapter (e.g., an adapter circuit), and a clock MUX. The gasket, the arbitrator, the MUX converter, and the adapter perform signal transmission and reception using a reference clock signal CLK_RF, and the adapter controls the clock MUX according to a full handshake method.

[0239] The gasket may receive a request for selecting an input to the clock MUX via an S-channel (S-CH). The request may include a multiplexer select signal. In this case, the multiplexer select signal may be encoded and passed to the adapter via a four-phase synchronous full handshake performed between the gasket and the arbitrator.

[0240] At the same time, the arbiter may also receive a request for selecting an input to the clock MUX through the H channel (H-CH). In this case, the arbiter receives the request through the H channel (H-CH) according to a four-phase asynchronous full double handshake. The four-phase asynchronous full double handshake may include a lock request, a release request, a multiplexer selection signal input to the arbiter; and a confirmation output from the arbiter. In this case, the multiplexer selection signal may be encoded and passed to the adapter through a four-phase synchronous full handshake performed between the arbiter and the MUX converter.

[0241] The adapter contains the Fig.9A and 9B The FSM described, and the multiplexer selection signal can be decoded by a two-phase asynchronous full handshake performed between the adapter and the clock MUX and input to the clock MUX.

[0242] refer to Fig.11 , the clock signal change occurs in the b3 section through the clock MUX component. Here, if the child's clock request signal is in a low state and the child's clock confirmation signal is in a low state between the b1 section and the b2 section, when the parent's clock confirmation signal becomes high, the child's clock request signal becomes high. Fig.11 In the embodiment, the clock request signal transmitted to all parents becomes a high state between the b2 and b3 parts. However, the clock request signal in a high state can also be transmitted only to the previous parent or the next parent. Fig.11Four parent clock requests PARENT_CLK_REQ 0, PARENT_CLK_REQ 1, PARENT_CLK_REQ 2, and PARENT_CLK_REQ 3 are illustrated to illustrate an example of a clock MUX unit capable of receiving four different clock signals and communicating with four different parent clock components that provide these clock signals. However, embodiments of the clock MUX unit are not limited thereto, as fewer or additional parent clock components may be supported in alternative embodiments.

[0243] refer to Fig.12 If the child's clock request signal is in a low state and the child's clock confirmation signal is in a low state between the b1 part and the b2 part, the child's clock request signal becomes a high state before the parent's clock confirmation signal becomes a high state.

[0244] refer to Fig.13 , between the b1 section and the b2 section, the clock request signal of the child is in a high state, and the clock confirmation signal of the child is in a low state.

[0245] refer to Fig.14 , between the b1 section and the b2 section, the clock request signal of the child is in a high state, and the clock confirmation signal of the child is in a high state.

[0246] refer to Fig.15 , between the b3 portion and the b4 portion, the clock request signal of the child is in a low state, the clock confirmation signal of the child is in a low state, and the clock request signal of the child remains in a low state.

[0247] refer to Fig.16 , between the b3 portion and the b4 portion, the clock request signal of the child is in a low state, the clock confirmation signal of the child is in a low state, and the clock request signal of the child is switched from a low state to a high state.

[0248] See also Fig.17 , between the b3 portion and the b4 portion, the clock request signal of the child is in a low state, the clock confirmation signal of the child is in a high state, and the clock request signal of the child remains in a low state.

[0249] refer to Fig.18 , between the b3 portion and the b4 portion, the clock request signal of the child is in a high state, the clock confirmation signal of the child is in a low state, and the clock request signal of the child remains in a high state.

[0250] refer to Fig.19 , between the b3 portion and the b4 portion, the clock request signal of the child is in a high state, the clock confirmation signal of the child is in a high state, and the clock request signal of the child is switched from a high state to a low state.

[0251] refer to Fig. 20 , between the b3 portion and the b4 portion, the clock request signal of the child is in a high state, the clock confirmation signal of the child is in a high state, and the clock request signal of the child remains in a high state.

[0252] Figures 11 to 20 Contains signals Active_PARENT_CLK_REQ and Active_PARENT_CLK_ACK.

[0253] Fig.21A The clock component 120c or the clock component 120e may be implemented by Fig.21A The clock division component is implemented. Fig.21B A FSM of a clock division component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described. Fig. 22 A structure of a clock frequency dividing component included in a semiconductor device according to an exemplary embodiment of the inventive concept is described. Fig.23 is a timing diagram illustrating the behavior of a clock division component included in a semiconductor device according to an embodiment of the present invention.

[0254] refer to Fig.21A, a clock division component included in a semiconductor device according to an embodiment of the inventive concept includes an adapter Adapter_CLKGATE (e.g., a logic gate), a FSM, and a clock division circuit SEC_AP_RTL_CLKDIV_SKEWLESS. The adapter Adapter_CLKGATE receives a clock request signal CHILD_CLK_REQ from a child clock component and transmits a clock request signal PARENT_CLK_REQ to a parent clock component. The adapter Adapter_CLKGATE may also receive a merged clock request CLKGATE_CLK_REQ from the FSM, the merged clock request CLKGATE_CLK_REQ being a merge of the CHILD_CLK_REQ and the additional clock request FSM_CLK_REQ. The merged clock request CLKGATE_CLK_REQ may be generated by performing an OR operation on the CHILD_CLK_REQ and the FSM_CLK_REQ. The FSM determines a clock division ratio DIVRATIO and provides the determined clock division ratio DIVRATIO to the adapter Adapter_CLKGATE. The FSM may control the clock frequency division circuit according to a full handshake method. For example, Adapter_CLKGATE (e.g., one or more logic circuits) may send a stop request signal STOPREQ to the clock frequency division circuit SEC_AP_RTL_CLKDIV_SKEWLESS. In an embodiment, the clock frequency division circuit SEC_AP_RTL_CLKDIV_SKEWLESS performs a frequency division operation on the input clock signal CLK_IN using the clock frequency division ratio DIVRATIO to generate an output clock signal CLK_OUT after receiving the clock frequency division ratio DIVRATIO from the FSM and provide a confirmation signal to the FSM.

[0255] Also refer to Fig.21B , the FSM contained in the clock divider component can contain the following states.

[0256] The first state c1 is a state in which clock gating is performed by hardware. This is a state in which both the parent clock component (of the clock division component) that stops providing the clock signal to the child clock component and the parent clock component (of the clock division component) that still provides the clock signal can exist. However, in this state, it is not guaranteed that all parent clock components of the clock division component are in operation. That is, since the operation of unnecessary parent clock components is stopped in this state, the power consumption may be the lowest. Therefore, the clock division component cannot change the clock division ratio DIVRATIO. For example, in state c1, even if a request DIVCHG_REQ to change the division ratio is input, the clock division component cannot change the clock division ratio DIVRATIO.

[0257] In the second state c2, all parent clock components of the clock division component are awakened because the clock division component needs to change the clock division ratio DIVRATIO. The awakening of the parent clock component can be caused by outputting a clock request CLK_REQ to the parent clock component.

[0258] The third state c3 is a state in which clock gating by hardware is not performed. That is, all awakened parent clock components are providing clock signals to the clock division component. In this state, the clock division component can change the clock division ratio. For example, a clock division ratio change request CLKDIV_DIVCHG_REQ can be output to cause a change. After the change and after receiving the input synchronized_CLKDIV_DIVCHG_ACK, a confirmation DIVCHG_ACK of the change is output.

[0259] In the fourth state c4, the clock gating by the hardware is restored after the clock frequency division component changes the clock frequency division ratio. Therefore, the operation of the parent clock component that does not need the clock signal begins to stop. That is, in the fourth state c4, the clock stop request signal PARENT_CLK_REQ is transmitted to the parent clock component that does not need the clock signal.

[0260] After receiving the clock acknowledgement signal PARENT_CLK_ACK from the parent clock component that does not require a clock signal, the clock division component returns to the first state c1. Fig.23 The fifth state c5 described in is the same as the first state c1.

[0261] refer to Fig. 22 According to an embodiment of the present invention, a clock frequency division component included in a semiconductor device includes a gasket, an arbitrator, and an adapter. The gasket, the arbitrator, and the adapter perform signal transmission and reception using a reference clock signal CLK_RF, and the adapter controls the clock frequency divider according to a full handshake method.

[0262] The gasket may receive a request signal for changing the clock division ratio via an S-channel (S-CH). The request may include DIVRATIO as a division ratio signal. In this case, the request signal may be encoded and delivered to the adapter via a synchronous full handshake performed between the gasket and the arbitrator.

[0263] At the same time, the arbitrator may also receive a request signal for changing the clock division ratio through the H channel (H-CH). In this case, the arbitrator receives the request signal through the H channel (H-CH) according to the asynchronous full double handshake. The four-phase asynchronous full double handshake may include a lock request, a release request, and a division ratio signal input to the arbitrator; and a confirmation output from the arbitrator. In this case, the request signal may be encoded and transmitted to the adapter through a synchronous full handshake performed between the arbitrator and the adapter.

[0264] The adapter contains the Fig.21A and 21B The FSM described, and the request signal can be decoded by an asynchronous full handshake performed between the adapter and the clock divider and input to the clock divider.

[0265] refer to Fig.23 , the change of the clock division ratio DIVRATIO occurs in the c3 section. The clock divider operates in response to the clock division ratio change request CLKDIV_DIVCHG_REQ transmitted to the clock divider. Fig.23 Contains the signal ADAPTER_CLKDIV.

[0266] Fig.24 An implementation of a PLL controller included in a semiconductor device according to an exemplary embodiment of the inventive concept is described. Fig.25 The structure of the multiplexer MERGE_MUXSEL of the PLL controller circuit included in the semiconductor device according to the embodiment of the present invention is described. Fig.26 and 27 is a timing diagram illustrating behavior of a PLL controller included in a semiconductor device according to an exemplary embodiment of the inventive concept.

[0267] refer to Fig.24 , a PLL controller included in a semiconductor device according to an exemplary embodiment of the inventive concept includes an adapter, a multiplexer, etc. The adapter is used as a control circuit for transmitting a request signal and an acknowledgement signal. The adapter can send REQ / ACK to a parent clock component and receive REQ / ACK from the parent clock component when the parent clock component exists, and the adapter can bypass when the parent clock component does not exist. Fig.24 Contains signals OSCCLK and PLL_FOUT, Fig.24 Contains modules SEC_AP_RTL_GFCLKMUX, ADAPTER_CLKMUX and SEC_AP_.

[0268] refer to Fig.25, the multiplexer MERGE_MUXSEL communicates with a special function register (SFR) and a system clock oscillator (SYSCLK_OSC) according to a full handshake method and outputs a selection signal SEL. Fig.25 Contains signals SEL_REQ0, SEL_REQ1, SEL_ACK0 and SEL_ACK1, Fig.25 Contains module SFR I / F.

[0269] exist Fig.26 and 27 In the embodiment of the present invention, a timing diagram is provided to illustrate the operation of the PLL controller circuit. Specifically, Fig.26 is a timing diagram illustrating the operation of the multiplexer MERGE_MUXSEL, and Fig. 27 is a timing diagram illustrating the operation of TRANS_HCH2PH. Fig.26 Contains signals MUXSEL_ACK[1], synchronized_MUXSEL_REQ[0], synchronized_MUXSEL_REQ[1], MUX_SEL, MUX_STATUS and MUX_SEL_sequential. Fig. 27 Contains signals MUXSEL_REQ0, MUXSEL_ACK0, RefClk, Hch / Data, Hch / Request_lock and Hch / Acknowledge.

[0270] Fig.28 An implementation of a PLL user controller included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0271] refer to Fig.28 , the PLL user controller includes an adapter, a multiplexer, etc. The adapter is used as a control circuit for transmitting request signals and confirmation signals. The adapter can send REQ / ACK to the parent clock component when the parent clock component exists and receive REQ / ACK from the parent clock component, and the adapter can bypass when the parent clock component does not exist. Fig.28 Contains signals OSCCLK and PLL_FOUT, Fig.28 Contains modules SEC_AP_RTL_GFCLKMUX, ADAPTER_CLKMUX and SEC_AP_.

[0272] Fig.29 An implementation of an adapter assembly included in a semiconductor device according to an exemplary embodiment of the inventive concept is described.

[0273] refer to Fig.29, the adapter component merges multiple request channels into one channel. The adapter component communicates according to a full handshake method. The adapter component receives a clock request signal from the child and transmits the clock request signal to the parent. In addition, the adapter component receives a clock confirmation signal from the parent and transmits the clock confirmation signal to the child.

[0274] exist Fig.29 In , the path between CHILD_CLK_REQ and PARENT_CLK_REQ can be implemented using only combinational cells. This path can be used to minimize the cycle delay of the request path. Fig.29 In , the path between PARENT_CLK_ACK and CHILD_CLK_ACK can be implemented using only combinational cells. This path can be used to minimize the cycle delay of the confirmation path. Fig.29 In , the path from CHILD_CLK_REQ to CHILD_CLK_ACK can be implemented using only combinational cells. This path can be used to minimize the cycle delay of the request to acknowledge path. Fig.29 In the example, the path from PARENT_CLK_ACK to PARENT_CLK_REQ can be implemented using only combinational cells. This path can be used to minimize the cycle delay of the confirmation to request path. Some of the above four paths can be intentionally separated by sequential cells to prevent combinational loops.

[0275] Fig.30 The structure of a lag filter included in a semiconductor device according to an exemplary embodiment of the inventive concept is described. Fig.30 The lag filter implementation Fig.24 The adapter hysteresis filter ADAPTER_HYSTERESISFILTER. Figures 31 to 33 is a timing diagram illustrating the behavior of a lag filter included in a semiconductor device according to an embodiment of the present invention.

[0276] refer to Fig.30 , the hysteresis filter is included in the adapter. Figures 31 to 33 , the lag filter generates a request signal that is filtered using a counter. Fig.30 Contains signals CHILD_CLK_ACK[c;0], CHILD_CLK_REQ[c;0], FILTER_REQ / ACK, FILTERED_REQ, ENABLE_FILTER, and EXPIRE_VALUE, Fig.30 Includes the module ADAPTER_NULL. Fig.31 Contains the signals EXPIRE_VALUE, FILTERED_REQ, increase_counter, and clear_counter. Fig.32Contains the signals EXPIRE_VALUE, FILTERED_REQ, and increase_counter. Fig.33 Contains the signals EXPIRE_VALUE and FILTERED_REQ.

[0277] Fig.34 is an exemplary embodiment according to the inventive concept. Figure 1 A block diagram of an embodiment of a PMU 300 is illustrated in FIG. Figure 35 to Figure 39 is a timing diagram illustrating an example of clock on / off operation of PMU 150 .

[0278] refer to Fig.34 The PMU 300 may communicate with the CMU 100 through a CMU interface circuit (CMU I / F) 151 according to a full handshake method. In addition, the PMU 300 may further include a power supply sequence management circuit 152 and a scan dump sequence management circuit 153.

[0279] Fig.35 Describing the operation of the PMU 300 during the startup sequence, Fig.36 Describing the operation of the PMU 300 in a power down sequence w / hold for the CMU 100, Fig.37 Describing the operation of the PMU 300 in a power-on sequence w / hold for the CMU 100, Fig.38 describes the operation of the PMU 300 in a power down sequence w / o retention for the CMU 100, and Fig.39 The operation of the PMU 300 in a power-on sequence for the CMU 100 w / o retention is described.

[0280] refer to Fig.35 In a power-on state following a startup sequence, the PLL operates. After the operation of the PLL, clock gating by hardware according to various embodiments is performed as necessary in an environment for minimizing unnecessary power consumption. Fig.35 Contains the signal RefClk.

[0281] refer to Fig.36 and Figure 1 , the power-off sequence is as follows.

[0282] First, the bus interaction between the CMU 100 and the IP blocks 200 to 220 is terminated, and the clock signals CLK1 to CLK3 provided by the CMU 100 are stopped. Subsequently, the use of the PLL is stopped by switching the use of the PLL to the oscillator, and the CMU 100 obtains control of the clock source on which the clock gating by hardware has not been performed. After the hold operation, the oscillator is stopped. The CMU 100 may temporarily generate a clock signal for the hold operation.

[0283] refer to Fig.37 , the power-on sequence is as follows.

[0284] First, the oscillator is operated to perform a hold operation. For the hold operation, the CMU 100 may temporarily generate a clock signal. Next, the control of the clock source on which the clock gating by hardware has not been performed is removed, and the PLL is operated. Subsequently, bus interactions between the CMU 100 and the IP blocks 200 to 220 are prepared to be performed. Thus, the power-on sequence is completed.

[0285] refer to Fig.38 , the power-off sequence is as follows.

[0286] First, bus interactions between the CMU 100 and the IP blocks 200 to 220 are terminated, and the clock signal is stopped from being provided by the CMU 100. Next, the use of the PLL is stopped by switching from the use of the PLL to the use of the oscillator, and the CMU 100 acquires control of the clock source on which clock gating by hardware has not been performed. Subsequently, the oscillator is stopped.

[0287] refer to Fig.39 , the power-on sequence is as follows.

[0288] First, the oscillator is operated, control of the clock source on which clock gating by hardware has not been performed is removed, and the PLL is operated. Subsequently, bus interactions between the CMU 100 and the IP blocks 200 to 220 are ready to be performed. Thus, the power-on sequence is completed. Figure 36 to Figure 39 Contains signals RefClk and FORCE_AUTOMATIC_CLKGATING.

[0289] Fig.40 is a block diagram of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0290] refer to Fig.40 The semiconductor device 700 includes a central processing unit (CPU) 710, a clock generator 720, a CMU 730, a random access memory (RAM) 740, a read only memory (ROM) 750, and a memory control unit 760. An oscillator OSC may be provided outside the semiconductor device 700 to provide an oscillation signal. The CMU 730 may be used Figure 1However, this is merely an embodiment, and the semiconductor device 700 according to the embodiment may include various other functional blocks. In addition, an oscillator OSC may also be included in the semiconductor device 700. Fig.40 The semiconductor device 700 may be included in a semiconductor system as an application processor.

[0291] The clock generator 720 generates a reference clock signal CLK_IN having a reference frequency using a signal generated from an oscillator OSC. The CMU 730 may receive the reference clock signal CLK_IN, generate an operation clock signal CLK_OUT having a specific frequency, and provide the operation clock signal CLK_OUT to each functional block. The CMU 730 may include one or more master clock controllers and one or more slave clock controllers. Each of the clock controllers may generate an operation clock signal CLK_OUT using the reference clock signal CLK_IN.

[0292] In addition, since the clock controller included in the CMU 730 is connected through a channel, management of the clock signal can be performed in hardware. In addition, since the clock controller included in the CMU 730 is connected to the functional block through a channel, clock request and confirmation can be performed in hardware.

[0293] The CPU 710 may process or execute code and / or data stored in the RAM 740. For example, the CPU 710 may process or execute code and / or data in response to an operation clock signal output from the CMU 730. The CPU 710 may be implemented as a multi-core processor. A multi-core processor is a computing component having two or more independent and large processors, and each of the processors may read and execute program instructions. Since a multi-core processor may run multiple accelerators simultaneously, a data processing system including a multi-core processor may perform multiple accelerations.

[0294] RAM 740 can temporarily store program code, data or instructions. For example, program code and / or data stored in an internal or external memory (not illustrated) can be temporarily stored in RAM 740 under the control of CPU 710 or according to a boot code stored in ROM 750. Memory control module 760 is a block for connecting to an internal or external memory. Memory control module 760 controls the overall operation of the memory and controls data exchange between the host and the memory.

[0295] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A system on chip, comprising: multiple intellectual property blocks; as well as a clock management unit configured to perform clock gating on at least one of the intellectual property blocks, wherein the intellectual property block and the clock management unit are connected to each other using a full handshake method, and The clock management unit comprises: a first clock component configured to provide a first request signal indicating that a first one of the intellectual property blocks needs to enter one of a sleep mode and an active mode; a second clock component configured to provide a second request signal indicating that a second one of the intellectual property blocks needs to enter one of a sleep mode and an active mode; a third clock component configured to receive the first request signal and the second request signal, provide a clock signal to the first clock component and the second clock component based on the first request signal and the second request signal, start providing the clock signal to both components when one of the request signals indicates a need to enter the active mode, provide the clock signal to both components when one of the request signals indicates a need to enter the sleep mode and one of the first clock component and the second clock component is operating, and stop providing the clock signal when both of the request signals indicate a need to enter the sleep mode; a first channel management circuit configured to, when a first one of the intellectual property blocks needs to enter the sleep mode, send a signal indicating that the first channel management circuit will stop providing the clock signal to the first one of the intellectual property blocks, and in response to receiving a signal indicating that the clock signal can be stopped after the first one of the intellectual property blocks completes the operation processed, request the first clock component to stop providing the clock signal; and The second channel management circuit is configured to send a signal indicating that the second channel management circuit will stop providing the clock signal to the second one of the intellectual property blocks when the second one of the intellectual property blocks needs to enter the sleep mode, and in response to receiving a signal indicating that the clock signal can be stopped after the second one of the intellectual property blocks completes the processing operation, request the second clock component to stop providing the clock signal.

2. The system on chip according to claim 1, characterized in that: One of the intellectual property blocks is configured to provide a request signal to the clock management unit, the request signal indicating that the one intellectual property block needs to enter a selected one of a sleep mode and an active mode.

3. The system on chip according to claim 2, characterized in that: The clock management unit is configured to provide a confirmation signal to the one intellectual property block in response to the request signal.

4. The system on chip according to claim 3, characterized in that: In response to the confirmation signal, the one intellectual property block enters the selected mode.

5. The system on chip according to claim 3, characterized in that: The clock management unit is configured to provide an output clock signal to the one intellectual property block in response to the request signal indicating that the one intellectual property block needs to enter the active mode, and then activate the confirmation signal to indicate that the clock management unit is outputting the output clock signal after determining that the output clock signal is stable.

6. The system on chip according to claim 5, characterized in that: The clock management unit is configured to deactivate the confirmation signal to indicate that the clock management unit has stopped outputting the output clock signal in response to the request signal indicating that the one intellectual property block needs to enter the sleep mode, and then stop providing the output clock signal to the one intellectual property block.

7. The system on chip according to claim 1, characterized in that: Further included is a power management unit configured to cut off power to the clock management unit when a request signal has not been sent through the intellectual property block during a given cycle.

8. The system on chip according to claim 5, characterized in that: The clock management unit includes a controller configured to receive a first signal from a crystal oscillator and a second signal from a phase locked loop, and provide one of the received signals as the output clock signal and an acknowledgement signal in response to the request signal.

9. The system on chip according to claim 5, characterized in that: The clock management unit comprises: a multiplexer configured to receive an internal clock signal and an external clock signal and to provide one of the received clock signals as the output clock signal; and A controller is configured to provide the confirmation signal in response to the request signal.

10. The system on chip according to claim 5, characterized in that: The clock management unit comprises: a frequency dividing circuit configured to divide the frequency of an input clock signal to generate a frequency-divided clock signal, and provide the frequency-divided clock signal as the output clock signal; and A controller is configured to provide the confirmation signal in response to the request signal.

11. The system on chip according to claim 5, characterized in that: The clock management unit comprises: a shortstop circuit configured to operate on an input clock signal to generate a resulting clock signal including a plurality of pulses during a first period and a constant level during a second period, and to provide the resulting clock signal as the output clock signal; and A controller is configured to provide the confirmation signal in response to the request signal.

12. The system on chip according to claim 5, characterized in that: The clock management unit comprises: a control circuit configured to output a control signal and the confirmation signal in response to the request signal; A clock source is configured to output the clock signal in response to the control signal.

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