Reconfiguring a processor without system reset

Abstract

Reconfiguring a processor without system reset is disclosed. Embodiments of a processor, method, and system for reconfiguring a processor without system reset are described. In an embodiment, the processor includes a configuration store, a shadow configuration store, a trigger store, and a trigger circuit. The trigger circuit is used to cause the contents of the shadow configuration store to be copied to the configuration store based on the contents of the trigger store.

Description

Technical Field

[0001] This invention relates generally to computer architecture, and more specifically to multiprocessor systems. Background Technology

[0002] Generally, systems comprising multiple processors and / or other resources can be configured in various ways. For example, the Basic Input / Output System (BIOS) or other system-level code can configure the system and its processors based on different capabilities provided and expected from any number and / or type of processors, processor cores, memory channels, input / output (I / O) devices, interconnect ports and / or topologies, workload preferences, and other resources within the system. Typically, any such configuration and / or reconfiguration of the system and processors involves a system reset, resulting in no transactions being in progress among multiple components while configuration settings are being changed. Attached Figure Description

[0003] The invention is illustrated by way of example and not limitation in the accompanying drawings, in which similar reference numerals indicate similar elements, wherein:

[0004] Figure 1 This is a block diagram illustrating a processor according to an embodiment of the present invention;

[0005] Figure 2 This is a block diagram illustrating a system according to an embodiment of the present invention;

[0006] Figure 3 This is a flowchart illustrating a method for reconfiguring a processor according to an embodiment of the present invention;

[0007] Figure 4 and Figure 5 This is a block diagram illustrating a system according to an embodiment of the present invention;

[0008] Figure 6A This is a block diagram illustrating both an exemplary ordered pipeline and an exemplary out-of-order release / execution pipeline for register renaming, according to embodiments of the present invention.

[0009] Figure 6B This is a block diagram illustrating an exemplary embodiment of an ordered architecture core to be included in a processor according to an embodiment of the present invention and an out-of-order release / execution architecture core with exemplary register renaming;

[0010] Figure 7 This is a block diagram of a processor according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have an integrated graphics device;

[0011] Figure 8This is a block diagram of a system according to an embodiment of the present invention;

[0012] Figure 9 This is a block diagram of a first, more specific, exemplary system according to an embodiment of the present invention;

[0013] Figure 10 This is a block diagram of a second, more specific, exemplary system according to an embodiment of the present invention; and

[0014] Figure 11 This is a block diagram of a SoC according to an embodiment of the present invention. Detailed Implementation

[0015] In the following description, numerous specific details, such as components and system configurations, may be set forth to provide a more thorough understanding of the invention. However, those skilled in the art will appreciate that the invention can be practiced without such specific details. Furthermore, some well-known structures, circuits, and other features have not been shown in detail to avoid unnecessarily obscuring the invention.

[0016] References to "an embodiment," "an embodiment," "an exemplary embodiment," "various embodiments," etc., indicate that the embodiments(s) of the invention described herein may include a particular feature, structure, or characteristic, but more than one embodiment may include that particular feature, structure, or characteristic, and not every embodiment necessarily includes that particular feature, structure, or characteristic. Some embodiments may have some or all of the features described with respect to other embodiments, or may not have any of those features. Furthermore, such phrases do not necessarily refer to the same embodiment. When a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed that implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge of those skilled in the art.

[0017] As used in this specification and claims, unless otherwise specified, the ordinal numbers “first,” “second,” “third,” etc., used to describe elements merely indicate a particular instance of the element being referenced or a different instance of a similar element, and are not intended to imply that the elements so described must be in a particular sequence in time, space, hierarchy, or any other way.

[0018] Furthermore, the terms “bit,” “flag,” “field,” “entry,” “indicator,” etc., can be used to describe storage locations, tables, databases, or other data structures in registers of any type or content, whether implemented in hardware or software, and these terms are not intended to limit embodiments of the invention to any particular type of storage location or the number of bits or other elements within any particular storage location. The term “clear” can be used to indicate storing a logical value of 0 in a storage location, or otherwise storing a logical value of 0 in a storage location; and the term “set” can be used to indicate storing a logical value of 1, all 1s, or some other specified value in a storage location, or otherwise storing a logical value of 1, all 1s, or some other specified value in a storage location; however, these terms are not intended to limit embodiments of the invention to any particular logical convention, as any logical convention can be used in embodiments of the invention.

[0019] Furthermore, as used in the description of embodiments of the invention, the " / " character between multiple items may mean that the embodiment may include a first item and / or a second item (and / or any other additional item), or may be implemented using, utilizing, and / or based on the first item and / or the second item (and / or any other additional item).

[0020] When a system comprises multiple processors and / or other resources, various configurations may be desired at different times. Using embodiments of the present invention, it is desirable to provide reconfiguration of processors within the system without a system reset, as reconfiguring the system would take significantly longer than reconfiguring one or more processors without reconfiguring the system. Using embodiments of the present invention, it is desirable to provide various system states for power management and / or other reasons, wherein, without a system reset, by cyclically traversing multiple states, one or more processors and / or multiple portions of these processors can be reset and / or reconfigured, thereby improving performance. Using embodiments of the present invention, dynamic system reconfigurability can be provided, which offers better reliability, availability, and suitability.

[0021] Figure 1 This is a block diagram illustrating a processor according to an embodiment of the present invention. Processor 100 may represent all or part of a hardware component including multiple processors or execution cores integrated on a single substrate and / or packaged within a single package. Processor 100 can be any type of processor, including: general-purpose microprocessors, such as... Processors in the processor family, or from Other processor families of the company or another company; dedicated processors or microcontrollers; or any other device or component in an information processing system in which embodiments of the present invention may be implemented. Processor 100 may be architected and designed to operate according to any instruction set architecture (ISA) with or without microcode. Processor 100 may represent a processor in any system embodiment of the present invention. For example, processor 100 may represent any of processors 700, 810, 970, 980, or 1110, each of which is described below.

[0022] Processor 100 is shown as including a configuration unit 110 and a system agent 140. Configuration unit 110 includes configuration storage 120 and configuration shadow storage 130. Configuration storage 120 may represent any number of configuration registers and / or other storage locations, the contents of which may be configured and / or programmed by firmware and / or software, and can be used to configure any configurable capabilities and / or features of processor 100. Configuration shadow storage 130 may represent any number of configuration registers and / or other storage locations, the contents of which may be configured and / or programmed by firmware and / or software, and in embodiments, this content may include: registers and / or other storage locations; and / or bits and / or fields of such registers and / or storage locations corresponding to each register and / or storage location; and / or bits and / or fields of such registers and / or storage locations within configuration storage 120.

[0023] Configuration shadow storage 130 may include trigger circuitry 132 and trigger bit 134. Trigger circuitry 132 may represent any circuitry or other hardware used to copy the contents of configuration shadow storage 130 to configuration storage 120 in response to a trigger, as further described below. In embodiments, triggering may be setting trigger bit 134 and / or detecting that trigger bit 134 has been set by trigger circuitry 132. Although in Figure 1 While shown as multiple individual elements, multiple portions of each of the configuration storage 120, configuration storage 130, and configuration trigger circuit 132 may be separated and / or distributed within the processor 100 in any desired manner.

[0024] System agent 140 may represent a system agent, an uncore, or other portion of the processor 100 that is not a core part (for convenience, any of the system agent, uncore, or other portion of the processor 100 that is not a core part may be referred to as a system agent), and / or this system agent, uncore, or other portion of the processor 100 that is not a core part includes microcontrollers, microengines, or other hardware agents 142 for executing firmware (pCode) 144 within the processor 100 without generating any transactions or other activities on a processor interconnect or system interconnect outside the processor 100, such as... Figure 2 The first interconnect 250 in the system interconnects such as Figure 2 The second interconnect 260 in the process. However, execution of firmware 144 may cause messages to be sent between the processor and a PCH (as defined and described below) via a sideband link or interconnect, such as PCH 230 and / or 240, such as the sideband link or interconnect. Figure 2 The third interconnect 260 in.

[0025] Figure 2 This is a block diagram illustrating a system according to an embodiment of the present invention. System 200 can represent any type of information processing system or platform, such as a server, desktop computer, portable computer, set-top box, handheld device, or embedded control system, such as a tablet or smartphone. System 200 includes processors 210, 212, 214, 216, 220, 222, 224, and 226, and platform controller hubs (PCH) 230 and 240. Each or any one of processors 210, 212, 214, 216, 220, 222, 224, and / or 226 can represent as described by... Figure 1 The processor represented by processor 100. Each of PCHs 230 and 240 may represent any one or more processors that can be connected to any one or more I / O devices or other components, including other processors and / or PCHs. The PCH may include circuitry and / or logic for performing any function of the chipset in the computer system.

[0026] The systems and / or platforms embodying this invention may include any number of processors, PCHs, and any other components or elements, such as peripherals and / or I / O devices. Unless otherwise specified, any or all of the components or other elements in this system embodiment or any system embodiment may be connected, coupled, or otherwise communicate with each other via any number of buses, point-to-point, or other wired or wireless interfaces or connections. Regardless of whether in Figure 2As shown, any component or other part of system 200 may be integrated or otherwise included on a single chip (system-on-chip or SOC), die, substrate or package, or may be integrated or otherwise included in a single chip (system-on-chip or SOC), die, substrate or package.

[0027] In system 200, each processor can be connected to each other via a first interconnect 250, such as Hyper Path Interconnect (UPI), Quick Path Interconnect (QPI), HyperTransport, or any other point-to-point or other processor bus or interconnect. One of the processors, such as processor 210, can be designated as a traditional processor (CPU-L), while the other processors are designated as non-traditional processors (CPU-NL). The traditional processor can be connected to the PCH via a second interconnect 260, and thus that PCH can be referred to as a traditional PCH (PCH-L), such as Direct Media Interconnect (DMI), Peripheral Component Interconnect Fast (PCIe), or any other system bus or interconnect, such as PCH 230. One of the non-traditional processors can be connected to another PCH, and thus that PCH can be referred to as a non-traditional PCH, such as processor 220, and the other PCH is such as PCH 240. Processors connected to the second interconnect 260 may be referred to as firmware agents (FW-S) because they also act as interfaces for other processors to access firmware storage, such as Serial Peripheral Interface (SPI) flash memory, via the PCH. Furthermore, each processor can be connected to the PCH via a third interconnect 270, such as a three-wire, bidirectional, low-speed, low-bandwidth link or any other bus or interconnect through which messages are transmitted between the processor and the PCH according to embodiments of the invention. PCHs, such as PCH 230 and PCH 240, can also be connected to each other via the third interconnect 270.

[0028] Figure 3 This is a flowchart illustrating a method 300 for reconfiguring a processor according to an embodiment of the present invention. Method 300 may be performed by the hardware, firmware, and / or software of a computer system. For illustrative purposes, the description of method 300 may refer to the elements of processor 100 and / or system 200; however, the method embodiments of the present invention are not limited to these illustrative details.

[0029] In block 310 of method 300, an event occurs, and in response to the event, the processor is configured or reconfigured. Such an event can be a transition to or from any power management or other state of system 200.

[0030] In block 320 of method 300, the BIOS or other system-level code selects a thread from a legacy processor (e.g., processor 210) to act as the System Bootstrap Processor (SBSP) for the reconfiguration process. In block 322, the BIOS places all threads in the system except the SBSP thread into a state in which these threads do not execute instructions and do not generate bus or interconnect transactions or messages; this state is, for example, a wait-for-SIPI state. In block 324, the BIOS running on the SBSP thread determines the desired configuration for each processor in the processors to be reconfigured, including the desired settings for each configuration register (e.g., configuration store 120) in each processor. For example, the BIOS may use algorithms to compute or attempt to compute the optimal settings for the system. In block 326, the BIOS running on the SBSP thread may load the settings into the shadow configuration register (e.g., shadow configuration store 130) in each processor. In box 328, the BIOS running on the SBSP thread (e.g., via the BIOS2Pcode (BIOS to Pcode) mailbox command) sends the first message to the pCode in the legacy processor and puts the legacy processor into a halted state.

[0031] In block 330, in response to the first message, pCode running on the legacy processor causes the legacy processor to send a second message to the legacy PCH (e.g., PCH 230) to request a multi-socket (i.e., multi-processor) configuration update. The second message can be sent via a sideband link (e.g., a third interconnect 270). In block 332, in response to the second message, the legacy PCH sends a third message to a non-legacy PCH (e.g., PCH 240) to request a socket (i.e., processor) configuration update. In block 334, the legacy PCH sends a fourth message to each processor (e.g., processors 210, 212, 214, and 216) to which the legacy PCH is connected via a sideband link, and in response to the third message, the non-legacy PCH sends the fourth message to each processor (e.g., processors 220, 222, 224, and 226) to which the non-legacy processor is connected via a sideband link, each fourth message being for requesting a socket configuration update.

[0032] In block 340, in response to the fourth message, the pCode running on each processor acknowledges that the processor has been stopped and sets a trigger (e.g., trigger bit 134) in each processor that loads and / or copies shadow configuration settings (e.g., from shadow configuration store 130) into a configuration register (e.g., configuration store 120). In block 342, each processor sends a fifth message to the PCH to which it is connected via a sideband link, each fifth message acknowledging completion of the configuration request (e.g., the updated configuration settings have been loaded into the configuration register). In block 344, in response to receiving the fifth message from each processor to which it is connected via a sideband link, the non-traditional PCH sends a sixth message via the sideband link to the traditional PCH to acknowledge completion of the configuration request. In block 346, in response to receiving the fifth message from each processor (in this embodiment, other than the traditional processor) to which the traditional PCH is connected via a sideband link and the sixth message from the non-traditional PCH, the traditional PCH sends a seventh message via the sideband link to the traditional processor to acknowledge completion of the configuration request.

[0033] In box 350, in response to the seventh message, the pCode running on the traditional processor (e.g., via a Direct2Core(PCU_TRIGGERED) command with a special mailbox code as described below) sends an eighth message to the microcode on the processor core including the SBSP thread (SBSP microcode). In box 352, in response to the eighth message, the SBSP microcode executes a trap handler to restart the BIOS on the SBSP thread. The trap handler increments the instruction pointer in response to the special mailbox code, causing the BIOS to restart at the instruction following the stop instruction associated with box 328. At box 354, the BIOS continues to run on the SBSP thread (e.g., to continue system initialization).

[0034] Therefore, method embodiments of the present invention (such as method 300) provide reconfiguration of the processor without requiring a system reset. For example, during blocks 330 to 352, when no BIOS is running in the system, the processor in system 200 is reconfigured, there is no in-flight traffic using configuration settings, all processor threads are stopped, and no system reset is performed. The actions associated with each of these blocks can occur before I / O devices are enumerated in the system, thereby ensuring that no processor sees any I / O traffic during these blocks.

[0035] Figure 4 This is a block diagram illustrating a system according to an embodiment of the present invention. Figure 4 In this embodiment, system 400 includes an embedded multi-die interconnect bridge (EMID) 410 for mesh connectivity of processors, for example, in a server. In an embodiment, the EMID 410 can be trained with a BIOS-based layer (e.g., a PHY layer) to provide operation at optimal speed and low bit error rate, for example, by applying different voltage and / or frequency operating conditions to account for process and temperature variations. The EMID 410 can be trained under basic operating conditions before BIOS code fetching begins. Since these basic operating conditions are not at the optimal performance point, embodiments of the invention can be used to apply configuration settings when mesh traffic is silent prior to training. For example, the BIOS can reconfigure the EMID with a new set of parameters based on system characteristics and (via mailbox) instruct the Pcode to trigger retraining, all without requiring a system reset.

[0036] Figure 5 This is a block diagram illustrating a system according to an embodiment of the present invention. Figure 5 In this system 500, a mesh 510 is included, to which one or more accelerators, such as IPx 520 and IPy 530, may be connected, for example, via a consistent (MESH-2-IDI) gasket 522 or a non-consistent (MESH-2-IOSF) gasket 532. These accelerators may be dynamically enabled and disabled, for example, in a cloud computing environment, based on system workload. Embodiments of the invention provide workload-based dynamic redistribution of credits. For example, if IPx 520 or IPy 520 is disabled, the optimal configuration may not allocate any credits to take IPx or IPy into account and reuse those credits for operating accelerators, other IP blocks, or cores, potentially achieving higher bandwidth and performance. In this embodiment, accelerators may be kept in a software-visible silent state during credit redistribution.

[0037] Exemplary core architectures, processors, and computer architectures

[0038] The following figures detail exemplary architectures and systems used to implement the embodiments described above.

[0039] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores can include: 1) general-purpose ordered cores intended for general-purpose computing; 2) high-performance general-purpose out-of-order cores intended for general-purpose computing; and 3) dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors can include: 1) CPUs, which include one or more general-purpose ordered cores and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) coprocessors, which include one or more dedicated cores intended primarily for graphics and / or scientific (throughput) computing. These different processors result in different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic or a dedicated core, such as integrated graphics and / or scientific (throughput) logic); and 4) a system-on-a-chip that may include the described CPU (sometimes referred to as application cores or application processors), the coprocessors described above, and additional functionality on the same die. Exemplary core architectures are then described, followed by exemplary processors and computer architectures.

[0040] Exemplary core architecture

[0041] Ordered and disordered kernel diagrams

[0042] Figure 6A This is a block diagram illustrating an exemplary ordered pipeline and an exemplary out-of-order release / execution pipeline for register renaming according to various embodiments of the present invention. Figure 6B This is a block diagram illustrating exemplary embodiments of ordered architecture cores to be included in a processor according to various embodiments of the present invention, and exemplary out-of-order release / execution architecture cores with register renaming. Figures 6A-6B Solid boxes in the diagram represent ordered pipelines and ordered cores, while optional dashed boxes represent register-renaming, out-of-order release / execution pipelines and cores. Since the ordered aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0043] exist Figure 6A In the processor pipeline 600, there are fetch stage 602, length decoding stage 604, decoding stage 606, allocation stage 608, renaming stage 610, scheduling (also known as dispatch or issue) stage 612, register read / memory read stage 614, execution stage 616, write-back / memory write stage 618, exception handling stage 622 and commit stage 624.

[0044] Figure 6BA processor core 690 is shown, which includes a front-end unit 630 coupled to an execution engine unit 650, and both the front-end unit 630 and the execution engine unit 650 are coupled to a memory unit 670. Core 690 can be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. Alternatively, core 690 can be a dedicated core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0045] Front-end unit 630 includes branch prediction unit 632 coupled to instruction cache unit 634 coupled to instruction translation lookup buffer (TLB) 636 coupled to instruction fetch unit 638 coupled to decoding unit 640. Decoding unit 640 (or decoder) decodes instructions and generates one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as output, which are decoded from, or otherwise reflect, the original instructions or derived from them. Decoding unit 640 can be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. In one embodiment, core 690 includes microcode ROM or other media (e.g., in decoding unit 640, or otherwise within front-end unit 630) storing microcode for certain macro instructions. The decoding unit 640 is coupled to the rename / allocator unit 652 in the execution engine unit 650.

[0046] Execution engine unit 650 includes a rename / allocator unit 652 coupled to a retirement unit 654 and a set 656 of one or more scheduler units. The scheduler units 656 represent any number of different schedulers, including reservation stations, central instruction windows, etc. The scheduler units 656 are coupled to physical register file units 658. Each physical register file unit in the physical register file units 658 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating-point numbers, compressed integers, compressed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer as the address of the next instruction to be executed), etc. In one embodiment, the physical register file units 658 include vector register units, write mask register units, and scalar register units. These register units can provide architectural vector registers, vector mask registers, and general-purpose registers. Multiple physical register file units 658 are overlapped by retirement units 654 to illustrate various ways to implement register renaming and out-of-order execution (e.g., using multiple reorder buffers and multiple retirement register files; using multiple future files, multiple history buffers, and multiple retirement register files; using register maps and register pools, etc.). Retirement units 654 and multiple physical register file units 658 are coupled to multiple execution clusters 660. Multiple execution clusters 660 include a set 662 of one or more execution units and a set 664 of one or more memory access units. Execution units 662 can perform various operations (e.g., shift, addition, subtraction, multiplication) and can perform operations on various data types (e.g., scalar floating-point, compressed integer, compressed floating-point, vector integer, vector floating-point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. Multiple scheduler units 656, multiple physical register file units 658, and multiple execution clusters 660 are shown as possibly multiple because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / compact integer / compact floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines each having their own scheduler unit, multiple physical register file units, and / or execution clusters—and in the case of separate memory access pipelines, some embodiments are implemented where only the execution cluster of that pipeline has multiple memory access units 664). It should also be understood that, in the case of using separate pipelines, one or more of these pipelines may be out-of-order deployment / execution, and the remaining pipelines may be ordered.

[0047] A set of memory access units 664 is coupled to a memory unit 670, which includes a data TLB unit 672, which is coupled to a data cache unit 674, which is coupled to a Level 2 (L2) cache unit 676. In one exemplary embodiment, the memory access unit 664 may include a load unit, a memory address unit, and a memory data unit, each of which is coupled to the data TLB unit 672 in the memory unit 670. An instruction cache unit 634 is also coupled to the Level 2 (L2) cache unit 676 in the memory unit 670. The L2 cache unit 676 is coupled to one or more other levels of cache and ultimately to main memory.

[0048] As an example, the exemplary out-of-order release / execution core architecture for register renaming can implement pipeline 600 as follows: 1) Instruction fetch 638 executes fetch stage 1602 and length decoding stage 604; 2) Decoding unit 640 executes decoding stage 606; 3) Rename / allocator unit 652 executes allocation stage 608 and rename stage 610; 4) (multiple) scheduler units 656 execute scheduling stage 612; 5) (multiple) physical register file units 658 and memory unit 670 execute register read / memory read stage 614; execution cluster 660 executes execution stage 616; 6) memory unit 670 and (multiple) physical register file units 658 execute write-back / memory write stage 618; 7) each unit may involve exception handling stage 622; and 8) retirement unit 654 and (multiple) physical register file units 658 execute commit stage 624.

[0049] Core 690 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with newer versions); the MIPS instruction set of MIPS Technologies, Inc., Sunnyvale, California; the ARM instruction set of ARM Holdings, Inc., Sunnyvale, California (with optional additional extensions such as NEON)), including the instructions described herein. In one embodiment, Core 690 includes logic for supporting compressed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing the use of compressed data to perform operations used by many multimedia applications.

[0050] It should be understood that a core can support multithreading (execution of two or more parallel operations or a set of threads), and this multithreading can be accomplished in various ways, including time-division multithreading, simultaneous multithreading (where a single physical core provides a logical core for each thread in the simultaneous multithreading of the physical core), or combinations thereof (e.g., time-division fetching and decoding, and subsequent operations such as...). Simultaneous multithreading in hyper-threading technology.

[0051] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can also be used in ordered architectures. While the illustrated processor embodiment also includes separate instruction and data cache units 634 / 674 and a shared L2 cache unit 676, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache or multiple levels of internal caches. In some embodiments, the system may include a combination of internal caches and external caches located outside the core and / or processor. Alternatively, all caches may be located outside the core and / or processor.

[0052] Figure 7 This is a block diagram of a processor 700 according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have an integrated graphics device. Figure 7 The solid box in the diagram shows a processor 700 having a single core 702A, a system agent 710, and a collection 716 of one or more bus controller units, while the optional addition of the dashed box shows an alternative processor 700 having multiple cores 702A-N, a collection 714 of one or more integrated memory controller units from the system agent units 710, and dedicated logic 708.

[0053] Therefore, different implementations of processor 700 may include: 1) a CPU, wherein dedicated logic 708 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 702A-N are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, wherein cores 702A-N are a large number of dedicated cores designed primarily for graphics and / or scientific (throughput); and 3) a coprocessor, wherein cores 702A-N are a large number of general-purpose ordered cores. Thus, processor 700 may be a general-purpose processor, coprocessor, or dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 700 may be part of one or more substrates, and / or may be implemented on one or more substrates using any of a variety of process technologies (e.g., BiCMOS, CMOS, or NMOS).

[0054] The memory hierarchy includes one or more cache levels within the core, a set 706 of one or more shared cache units, and external memory (not shown) coupled to a set 714 of integrated memory controller units. The set 706 of shared cache units may include one or more intermediate-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, Last Level Cache (LLC), and / or combinations thereof. While in one embodiment, ring-based interconnect units 712 interconnect integrated graphics logic 708 (integrated graphics logic 708 is an example and is also referred to herein as dedicated logic), the set 706 of shared cache units, and system proxy units 710 / (multiple) of integrated memory controller units 714, alternative embodiments may use any number of known techniques to interconnect such units. In one embodiment, consistency is maintained between one or more cache units 706 and cores 702A-N.

[0055] In some embodiments, one or more cores 702A-N can be multithreaded. System agent 710 includes those components that coordinate and operate core 702A-N. System agent unit 710 may include, for example, a power control unit (PCU) and a display unit. The PCU may be, or may include, the logic and components required to regulate the power state of core 702A-N and integrated graphics logic 708. The display unit is used to drive one or more externally connected displays.

[0056] The 702A-N cores can be homogeneous or heterogeneous in terms of their instruction set architecture; that is, two or more cores in the 702A-N cores may be able to execute the same instruction set, while other cores may be able to execute only a subset of that instruction set or a different instruction set.

[0057] Exemplary computer architecture

[0058] Figure 8-11 This is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, a wide variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are generally suitable.

[0059] Now for reference Figure 8The diagram illustrates a block diagram of a system 800 according to an embodiment of the present invention. System 800 may include one or more processors 810, 815 coupled to a controller hub 820. In one embodiment, the controller hub 820 includes a graphics memory controller hub (GMCH) 890 and an input / output hub (IOH) 850 (which may be on separate chips); the GMCH 890 includes memory and a graphics controller, to which a memory 840 and a coprocessor 845 are coupled; the IOH 850 couples an input / output (I / O) device 860 to the GMCH 890. Alternatively, one or both of the memory and the graphics controller may be integrated within a processor (as described herein), with the memory 840 and the coprocessor 845 directly coupled to the processor 810, and the controller hub 820 and the IOH 850 residing on a single chip.

[0060] The optionality of the additional 815 processor Figure 8 The numbers are indicated by dashed lines. Each processor 810, 815 may include one or more of the processing cores described herein, and may be a version of processor 1000.

[0061] The memory 840 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of both. In at least one embodiment, the controller hub 820 communicates with the processors(s) 810, 815 via a multi-branch bus such as a front-side bus (FSB), a point-to-point interface such as a fast path interconnect (QPI), or a similar connection 895.

[0062] In one embodiment, the coprocessor 845 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and so on. In one embodiment, the controller hub 820 may include an integrated graphics accelerator.

[0063] There can be various differences between physical resources 810 and 815 in terms of a range of quality metrics, including architecture, microarchitecture, thermal and power consumption characteristics.

[0064] In one embodiment, processor 810 executes instructions that control general-type data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 810 recognizes these coprocessor instructions as having a type that should be executed by an attached coprocessor 845. Therefore, processor 810 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 845 on a coprocessor bus or other interconnect. Coprocessors 845(a) receive and execute the received coprocessor instructions.

[0065] See now Figure 9 The diagram shown is a block diagram of a first, more specific, exemplary system 900 according to an embodiment of the present invention. Figure 9 As shown, the multiprocessor system 900 is a point-to-point interconnect system and includes a first processor 970 and a second processor 980 coupled via a point-to-point interconnect 950. Each of processors 970 and 980 may be a version of processor 1000. In one embodiment of the invention, processors 970 and 980 are processors 810 and 815, respectively, and coprocessor 938 is coprocessor 845. In another embodiment, processors 970 and 980 are processor 810 and coprocessor 845, respectively.

[0066] Processors 970 and 980 are shown as including integrated memory controller (IMC) units 972 and 982, respectively. Processor 970 also includes point-to-point (PP) interfaces 976 and 978 as part of its bus controller unit; similarly, the second processor 980 includes PP interfaces 986 and 988. Processors 970 and 980 can exchange information via a PP interface 950 using point-to-point (PP) interface circuits 978 and 988. Figure 9 As shown, IMC 972 and 982 couple the processor to the corresponding memory, namely memory 932 and memory 934, which may be portions of the main memory locally attached to the corresponding processor.

[0067] Processors 970 and 980 can exchange information with chipset 990 via respective PP interfaces 952 and 954 using point-to-point interface circuits 976, 994, 986, and 998. Chipset 990 can optionally exchange information with coprocessor 938 via high-performance interface 992. In one embodiment, coprocessor 938 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc.

[0068] A shared cache (not shown) may be included in either processor or external to both processors but connected to them via a PP interconnect, such that if the processors are in a low-power mode, the local cache information of either or both processors may be stored in the shared cache.

[0069] Chipset 990 can be coupled to first bus 916 via interface 996. In one embodiment, first bus 916 may be a peripheral component interconnect (PCI) bus or a bus such as PCI Fast bus or another third-generation I / O interconnect bus, but the scope of the invention is not limited thereto.

[0070] like Figure 9 As shown, various I / O devices 914 may be coupled to a first bus 916 together with a bus bridge 918, which couples the first bus 916 to a second bus 920. In one embodiment, one or more additional processors 915, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array, or any other processor, are coupled to the first bus 916. In one embodiment, the second bus 920 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 920, including, for example, a keyboard and / or mouse 922, a communication device 927, and a storage unit 928, such as a disk drive that may include instruction / code and data 930, or other mass storage devices. Additionally, audio I / O 924 may be coupled to the second bus 920. Note that other architectures are possible. For example, instead of… Figure 9 The point-to-point architecture allows the system to implement multi-branch buses or other similar architectures.

[0071] Now for reference Figure 10 The diagram shown is a block diagram of a second, more specific, exemplary system 1000 according to an embodiment of the present invention. Figure 9 and 10 Similar elements in the figure use similar reference numerals, and from Figure 10 The middle part is omitted Figure 9 certain aspects to avoid confusion Figure 10 Other aspects.

[0072] Figure 10 The processors 970 and 980 are shown to include integrated memory and I / O control logic (“CL”) 972 and 982, respectively. Therefore, CL 972 and 982 include an integrated memory controller unit and I / O control logic. Figure 10 The demonstration shows that not only are the memories 932 and 934 coupled to CLs 972 and 982, but the I / O device 1014 is also coupled to the control logic 972 and 982. The conventional I / O device 1015 is coupled to the chipset 990.

[0073] Now for reference Figure 11 The diagram shown is a block diagram of a SoC 1100 according to an embodiment of the present invention. Figure 10 Similar elements in the figure use similar reference numerals. Additionally, dashed boxes are optional features on more advanced SoCs. Figure 11In this configuration, multiple interconnect units 1102 are coupled to: an application processor 1110, which includes a set of one or more cores 1002A-N and multiple shared cache units 1006, the set of one or more cores 1002A-N including cache units 1004A-N; a system proxy unit 1010; multiple bus controller units 1016; multiple integrated memory controller units 1014; a set of one or more coprocessors 1120, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1130; a direct memory access (DMA) unit 1132; and a display unit 1140 for coupling to one or more external displays. In one embodiment, the multiple coprocessors 1120 include dedicated processors, such as, for example, network or communication processors, compression engines, GPGPUs, high-throughput MIC processors, or embedded processors, etc.

[0074] The various embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention can be implemented as computer programs or program code executable on a programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0075] Program code (such as, Figure 9 The code 930 shown is applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0076] The program code can be implemented using a high-level procedural or object-oriented programming language to communicate with the processing system. Assembly or machine language can also be used if needed. In fact, the mechanisms described herein are not limited to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0077] One or more aspects of at least one embodiment can be implemented by representational instructions stored on a machine-readable medium, which represent various logics in a processor, and which, when read by a machine, cause the machine to manufacture logic for performing the techniques described herein. Such representations, referred to as “IP cores,” can be stored on tangible machine-readable media and can be supplied to various customers or production facilities for loading into manufacturing machines that actually manufacture the logic or processor.

[0078] Such machine-readable storage media can include, but are not limited to, non-transitory, tangible arrangements of articles made or formed by a machine or device, including storage media such as hard disks; any other type of disk, including floppy disks, optical disks, compact disc read-only memory (CD-ROM), rewritable compact discs (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM); phase-change memory (PCM); magnetic cards or optical cards; or any other type of medium suitable for storing electronic instructions.

[0079] Therefore, embodiments of the invention also include a non-transitory tangible machine-readable medium containing instructions or design data, such as a hardware description language (HDL), that defines the architectures, circuits, devices, processors, and / or system features described herein. These embodiments are also referred to as program products.

[0080] In one embodiment, the processor includes configuration storage, shadow configuration storage, trigger storage, and trigger circuitry. The trigger circuitry is used to copy the shadow configuration storage content to the configuration storage based on the content of the trigger storage.

[0081] In an embodiment, a method may include: loading a first configuration setting into a first shadow configuration store in a first processor; setting a first trigger in the first processor to cause the first configuration setting to be copied from the first shadow configuration to the first configuration store in the first processor; and copying the first configuration setting from the first shadow configuration to the first configuration store based on the first trigger. Loading the first configuration setting into the first shadow configuration store is performed by the BIOS. The method may further include: selecting a thread in the first processor to act as an SBSP by the BIOS. The method may further include: causing one or more other threads to enter a waiting state by the BIOS. The method may further include: sending a first message to first firmware on the first processor by the BIOS; and causing the first processor to enter a stopped state by the BIOS. The method may further include: the first firmware, in response to the first message, causing the first processor to send a second message via a sideband link to a first PCH to request a configuration update. The method may further include: the first PCH, in response to the second message, sending a third message via a sideband link to a second PCH to request a configuration update. The method may further include: the first PCH, in response to the second message, sending a fourth message via a sideband link to a second processor connected to the first PCH to request a configuration update by the first PCH. The method may further include: a second PCH sending a fourth message via a sideband link to a third processor in response to a third message to request a configuration update, the third processor being connected to the second PCH. The method may further include: a second firmware on the third processor setting a second trigger in the third processor in response to the fourth message, causing a second configuration setting to be copied from a second shadow configuration store in the third processor to a second configuration store in the third processor. The method may further include: a third processor sending a fifth message via a sideband link to the second PCH in response to the fourth message to acknowledge completion of the configuration request. The method may further include: a second PCH sending a sixth message via a sideband link to the first PCH in response to the fifth message to acknowledge completion of the configuration request. The method may further include: a first PCH sending a seventh message via a sideband link to the first processor in response to the sixth message to acknowledge completion of the configuration request. The method may further include: a first firmware sending an eighth message to microcode on the first processor in response to the seventh message; and the microcode executing a trap handler to reboot the BIOS on the SBSP thread. The method may further include: incrementing the instruction pointer for the SBSP thread in response to the seventh message.

[0082] In one embodiment, a device may include means for performing any of the methods described above. In another embodiment, a machine-readable tangible medium may store instructions that, when executed by a machine, cause the machine to perform any of the methods described above.

[0083] In an embodiment, a system may include a first PCH and a first processor connected to the PCH via a system interconnect and a sideband link. The first processor includes: firmware for sending a configuration update request to the first PCH via the sideband link when the first processor is in a stopped state, wherein the first processor does not generate transactions on the system interconnect in the stopped state; a first configuration store; a first shadow configuration store; a first trigger store; and a first trigger circuit for copying the contents of the first shadow configuration store to the first configuration store based on the contents of the first trigger store. The system may also include a second processor connected to the first processor via a processor interconnect, wherein the first processor is configured to send a configuration update request to the first PCH via the sideband link when the first processor is in a stopped state, wherein the first processor does not generate transactions on the processor interconnect in the stopped state. The system may also include a second PCH connected to the first PCH and the second processor via a sideband link, wherein the first PCH is configured to forward the configuration update request to the second PCH via the sideband link, and the second PCH is configured to forward the configuration update request to the second processor via the sideband link. The second processor can be used to send configuration update acknowledgments to the second PCH via a sideband link, and the second PCH can be used to forward configuration update acknowledgments to the first PCH via a sideband link, and the first PCH can be used to forward configuration update acknowledgments to the first processor via a sideband link.

Claims

1. A method for reconfiguring without system reset, the method comprising: The BIOS loads the first configuration settings into the first shadow configuration register in the first processor, the first processor including the first configuration register, the first shadow configuration register including the first trigger bit and the first trigger circuit; The BIOS selects a thread from the first processor to act as the system boot processor (SBSP). The BIOS causes one or more other threads to enter a waiting state; The BIOS sends the first message to the first firmware on the first processor; The BIOS causes the first processor to enter a stop state; In response to the first message, the first firmware causes the first processor to send a second message to the first platform controller hub (PCH) via a sideband link to request a configuration update. In response to the second message, the first PCH sends a third message to the second PCH via the sideband link to request the configuration update; The first PCH responds to the second message by sending a fourth message to the second processor via the sideband link to request the configuration update, and the second processor is connected to the first PCH; The code running on the first processor responds to the fourth message by setting the first trigger bit; The second PCH, in response to the third message, sends the fourth message to the third processor via the sideband link to request the configuration update; the third processor is connected to the second PCH. In response to detecting that the first trigger bit is set, the first trigger circuit copies the first configuration settings from the first shadow configuration register to the first configuration register so as to reconfigure the first processor without system reset; The second firmware on the third processor responds to the fourth message by setting a second trigger in the third processor, so that the second configuration settings are copied from the second shadow configuration store in the third processor to the second configuration store in the third processor; In response to the fourth message, the third processor sends a fifth message to the second PCH via the sideband link to confirm the completion of the configuration request; In response to the fifth message, the second PCH sends a sixth message to the first PCH via the sideband link to confirm the completion of the configuration request; The first PCH responds to the sixth message by sending a seventh message to the first processor via the sideband link to confirm the completion of the configuration request; The trap handler is executed by microcode to restart the BIOS on the SBSP thread.

2. The method of claim 1, further comprising: The microcode by which the first firmware sends an eighth message to the first processor in response to the seventh message.

3. The method of claim 2, further comprising: In response to the seventh message, the instruction pointer for the SBSP thread is incremented.

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