Storage system and method of selecting an operating mode of a storage device

Abstract

Disclosed are a storage system and a method of selecting an operation mode of a storage device. A system includes a storage device; a storage device controller; a first interface configured to connect the storage device controller to the storage device; and a second interface configured to connect the storage device controller to a host device, wherein the storage device is configured to operate in a first mode or a second mode based on a state of a signal at the second interface according to an instruction received from the host device.

Description

[0001] This application claims priority and benefit to U.S. Patent Application No. 62 / 701,494, filed July 20, 2018, entitled “Multimode Protocol FPGA + Solid State Device Based on SFF-TA-100X,” the entire contents of which are expressly incorporated herein by reference. Technical Field

[0002] One or more aspects of embodiments of this disclosure relate to a multimode protocol solid-state device based on Small Form Factor (SFF)-Technology Affiliate (TA)-100X. Background Technology

[0003] Non-Volatile Memory (NVM) Fast Standard (NVMe) is a standard that defines a register-level interface for host software to communicate with non-volatile memory subsystems (e.g., solid-state drives (SSDs)) via the Peripheral Component Interconnect Fast (PCIe) bus. NVMe is an alternative to the Small Computer System Interface (SCSI) standard, which is used to connect and transfer data between a host and peripheral target storage devices or systems. NVMe SSDs with PCIe connectivity allow applications to communicate directly with the storage device.

[0004] The information disclosed in this background section is only for enhancing the understanding of the background technology of the present invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] This summary is provided to introduce the selection of features and concepts of embodiments of this disclosure, which are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. One or more described features may be combined with one or more other described features to provide a feasible apparatus.

[0006] Some exemplary embodiments of this disclosure relate to a multimode protocol solid-state device based on SFF-TA-100X.

[0007] In some embodiments, a system includes: a storage device; a storage device controller; a first interface configured to connect the storage device controller to the storage device; and a second interface configured to connect the storage device controller to a host device, wherein the storage device is configured to operate in a first mode or a second mode based on the state of a signal at the second interface according to an instruction received from the host device.

[0008] In some embodiments, the storage device is one of a new form factor 1 (NF1) solid-state drive (SSD), an Ethernet SSD (eSSD), or an embedded SSD, and the storage device controller is a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In some embodiments, the first interface is a peripheral component interconnect fast (PCIe) interface or a U.2 connector, and the second interface is a small form factor (SFF)-Technology Alliance (TA)-100X connector, where X is one of 2, 6, 7, 8, or 9, wherein the storage device has one of an SFF-8201 2.5″ drive form factor, an SFF-8223 2.5″ drive form factor with serial connector, an SFF-8301 3.5″ drive form factor, or an SFF-8323 3.5″ drive form factor with serial connector.

[0009] In some embodiments, the first and second operating modes of the storage device are Non-Volatile Memory Fast (NVMe) mode and Non-Volatile Memory Fast Over Network (NVMe-oF) mode, respectively. In some embodiments, the second interface is a (SFF)-Technology Alliance (TA)-1008 connector, and the state of the signal at the second interface is the state of the signal at the Reserved for Future Use (RFU) pin of the SFF-TA-1008 connector, wherein the storage device operates in NVMe mode when the signal at the RFU pin of the SFF-TA-1008 connector is high, and the storage device operates in NVMe-oF mode when the signal at the RFU pin of the SFF-TA-1008 connector is low, wherein in each of the NVMe and NVMe-oF modes, the SFF-TA-1008 connector operates in X4 single-port, X4 dual-port, X8 single-port, X8 dual-port, X16 single-port, and X16 dual-port modes.

[0010] In some embodiments, when the storage device and the SFF-TA-1008 connector operate in NVMe-oF and X4 single-port modes respectively, the PCIe signals PERp2, PERn2, PETp2, and PETn2 of the SFF-TA-1008 connector are configured to control host A and Ethernet port 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector are configured to control host A and Ethernet port 1. In some embodiments, when the storage device and the SFF-TA-1008 connector operate in NVMe-oF and X4 dual-port modes respectively, the PCIe signals PERp1, PERn1, PETp1, and PETn1 of the SFF-TA-1008 connector are configured to control host A and Ethernet port 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector are configured to control host B and Ethernet port 1. In some embodiments, when the storage device and the SFF-TA-1008 connector operate in NVMe-oF and X8 single-port modes respectively, the PCIe signals PERp4, PERn4, PETp4, and PETn4 of the SFF-TA-1008 connector are configured as host A and Ethernet port 0, the PCIe signals PERp5, PERn5, PETp5, and PETn5 of the SFF-TA-1008 connector are configured as host A and Ethernet port 1, the PCIe signals PERp6, PERn6, PETp6, and PETn6 of the SFF-TA-1008 connector are configured as host A and Ethernet port 2, and the PCIe signals PERp7, PERn7, PETp7, and PETn7 of the SFF-TA-1008 connector are configured as host A and Ethernet port 3.

[0011] In some embodiments, when the storage device and the SFF-TA-1008 connector operate in NVMe-oF and X8 single-port modes respectively, the PCIe signals PERp2, PERn2, PETp2, and PETn2 of the SFF-TA-1008 connector are configured as host A and Ethernet port 0, the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector are configured as host A and Ethernet port 1, the PCIe signals PERp6, PERn6, PETp6, and PETn6 of the SFF-TA-1008 connector are configured as host B and Ethernet port 2, and the PCIe signals PERp7, PERn7, PETp7, and PETn7 of the SFF-TA-1008 connector are configured as host B and Ethernet port 3.

[0012] In some embodiments, when the storage device and the SFF-TA-1008 connector operate in NVMe-oF and X16 single-port modes, respectively, the PCIe signals PERp8, PERn8, PETp8, and PETn8 of the SFF-TA-1008 connector are configured as Host A and Ethernet Port 0; the PCIe signals PERp9, PERn9, PETp9, and PETn9 of the SFF-TA-1008 connector are configured as Host A and Ethernet Port 1; the PCIe signals PERp10, PERn10, PETp10, and PETn10 of the SFF-TA-1008 connector are configured as Host A and Ethernet Port 2; and the PCIe signals PERp11, PERn11, and PETp11 of the SFF-TA-1008 connector are configured as Host A and Ethernet Port 2. PETn11 is configured as host A and Ethernet port 3; PCIe signals PERp12, PERn12, PETp12, and PETn12 of the SFF-TA-1008 connector are configured as host A and Ethernet port 4; PCIe signals PERp13, PERn13, PETp13, and PETn13 of the SFF-TA-1008 connector are configured as host A and Ethernet port 5; PCIe signals PERp14, PERn14, PETp14, and PETn14 of the SFF-TA-1008 connector are configured as host A and Ethernet port 6; and PCIe signals PERp15, PERn15, PETp15, and PETn15 of the SFF-TA-1008 connector are configured as host A and Ethernet port 7.

[0013] In some embodiments, when the storage device and the SFF-TA-1008 connector operate in NVMe-oF and X16 dual-port modes, respectively, the PCIe signals PERp8, PERn8, PETp8, and PETn8 of the SFF-TA-1008 connector are configured as host A and Ethernet port 0, the PCIe signals PERp9, PERn9, PETp9, and PETn9 of the SFF-TA-1008 connector are configured as host A and Ethernet port 1, the PCIe signals PERp10, PERn10, PETp10, and PETn10 of the SFF-TA-1008 connector are configured as host B and Ethernet port 0, and the PCIe signals PERp11, PERn11, and PETp11 of the SFF-TA-1008 connector are configured as host B and Ethernet port 0. PETn11 is configured as host B and Ethernet port 1; PCIe signals PERp12, PERn12, PETp12, and PETn12 of the SFF-TA-1008 connector are configured as host A and Ethernet port 2; PCIe signals PERp13, PERn13, PETp13, and PETn13 of the SFF-TA-1008 connector are configured as host A and Ethernet port 3; PCIe signals PERp14, PERn14, PETp14, and PETn14 of the SFF-TA-1008 connector are configured as host B and Ethernet port 2; and PCIe signals PERp15, PERn15, PETp15, and PETn15 of the SFF-TA-1008 connector are configured as host B and Ethernet port 3.

[0014] In some embodiments, a system includes: a computing device; and a storage device connected to the computing device via a first interface, wherein the computing device is configured to operate as a controller of the storage device, and wherein the computing device is connected to a host device via a second interface.

[0015] In some embodiments, the storage device is one of a New Form Factor 1 (NF1) solid-state drive (SSD), an Ethernet solid-state drive (eSSD), or an embedded SSD; the computing device is a Field Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC); the first interface is a Peripheral Component Interconnect Fast (PCIe) interface or a U.2 connector; the second interface is a Small Form Factor (SFF)-Technology Alliance (TA)-1008 connector; and the storage device is configured to: based on the state of the signal at the Reserved for Future Use (RFU) pin of the SFF-TA-1008 connector, in Non-Volatile Memory Fast (NVMe) mode or over a network of Non-Volatile Memory Fast (NVMe) mode. Operating in (NVMe-oF) mode, the signal is based on instructions received from the host device via a general-purpose input / output (GPIO) connected to the RFU, and the storage device operates in NVMe mode when the signal at the RFU pin of the SFF-TA-1008 connector is high, and in NVMe-oF mode when the signal at the RFU pin of the SFF-TA-1008 connector is low, wherein in each of the NVMe and NVMe-oF modes, the SFF-TA-1008 connector operates in X4 single-port, X4 dual-port, X8 single-port, X8 dual-port, X16 single-port, and X16 dual-port modes.

[0016] In some embodiments, in X4 single-port mode, when the RFU pin of the SFF-TA-1008 connector transitions from a low state to a high state, the SFF-TA-1008 connector's PCIe signals PERp2, PERn2, PETp2, and PETn2 transition from being configured as Host A, PCIe path 2 to Host A, Ethernet port 0, and the SFF-TA-1008 connector's PCIe signals PERp3, PERn3, PETp3, and PETn3 transition from being configured as Host A, PCIe path 3 to Host A, Ethernet port 0. Port 1, wherein, in X4 dual-port mode, when the RFU pin of the SFF-TA-1008 connector transitions from a low state to a high state, the PCIe signals PERp1, PERn1, PETp1, and PETn1 of the SFF-TA-1008 connector transition from being configured as Host A, PCIe path 1 to Host A, Ethernet port 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector transition from being configured as Host B, PCIe path 1 to Host B, Ethernet port 1.

[0017] In some embodiments, in X8 single-port mode, when the RFU pin of the SFF-TA-1008 connector transitions from a low state to a high state, the SFF-TA-1008 connector's PCIe signals PERp4, PERn4, PETp4, and PETn4 transition from being configured as Host A, PCIe path 4 to Host A, Ethernet port 0; the SFF-TA-1008 connector's PCIe signals PERp5, PERn5, PETp5, and PETn5 transition from being configured as Host A, PCIe path 5 to Host A, Ethernet port 1; the SFF-TA-1008 connector's PCIe signals PERp6, PERn6, PETp6, and PETn6 transition from being configured as Host A, PCIe path 6 to Host A, Ethernet port 2; and the SFF-TA-1008 connector's PCIe signals PERp7, PERn7, PETp7, and PETn7 transition from being configured as Host A, PCIe path 7 to Host A, Ethernet port 0. Ethernet port 3, wherein, in X8 dual-port mode, when the RFU pin of the SFF-TA-1008 connector transitions from a low state to a high state, the SFF-TA-1008 connector's PCIe signals PERp2, PERn2, PETp2, and PETn2 transition from being configured as host B, PCIe path 0 to host A, Ethernet port 0; the SFF-TA-1008 connector's PCIe signals PERp3, PERn3, PETp3, and PETn3 transition from being configured as host B, PCIe path 1 to host A, Ethernet port 1; the SFF-TA-1008 connector's PCIe signals PERp6, PERn6, PETp6, and PETn6 transition from being configured as host B, PCIe path 2 to host B, Ethernet port 2; and the SFF-TA-1008 connector's PCIe signals PERp7, PERn7, PETp7, and PETn7 transition from being configured as host B, path 3 to host B, Ethernet port 3.

[0018] In some embodiments, in X16 single-port mode, when the RFU pin of the SFF-TA-1008 connector transitions from a low state to a high state, the SFF-TA-1008 connector's PCIe signals PERp8, PERn8, PETp8, and PETn8 transition from being configured as Host A, PCIe path 8 to Host A, Ethernet port 0; the SFF-TA-1008 connector's PCIe signals PERp9, PERn9, PETp9, and PETn9 transition from being configured as Host A, PCIe path 9 to Host A, Ethernet port 1; the SFF-TA-1008 connector's PCIe signals PERp10, PERn10, PETp10, and PETn10 transition from being configured as Host A, PCIe path 10 to Host A, Ethernet port 2; and the SFF-TA-1008 connector's PCIe signals PERp11, PERn11, PETp11, and PETn11 transition from being configured as Host A, PCIe path 10 to Host A, Ethernet port 2. The PCIe path 11 of the SFF-TA-1008 connector is switched to host A and Ethernet port 3. The PCIe signals PERp12, PERn12, PETp12, and PETn12 of the SFF-TA-1008 connector are switched from host A and PCIe path 12 to host A and Ethernet port 4. The PCIe signals PERp13, PERn13, PETp13, and PETn13 of the SFF-TA-1008 connector are switched from host A and PCIe path 13 to host A and Ethernet port 5. The PCIe signals PERp14, PERn14, PETp14, and PETn14 of the SFF-TA-1008 connector are switched from host A and path 14 to host A and Ethernet port 6. The PCIe signals PERp15, PERn15, PETp15, and PETn15 of the SFF-TA-1008 connector are switched from host A and path 15 to host A and Ethernet port 7.

[0019] In some embodiments, in X16 dual-port mode, when the RFU pin of the SFF-TA-1008 connector transitions from a low state to a high state, the SFF-TA-1008 connector's PCIe signals PERp8, PERn8, PETp8, and PETn8 transition from being configured as Host A, PCIe path 4 to Host A, Ethernet port 0; the SFF-TA-1008 connector's PCIe signals PERp9, PERn9, PETp9, and PETn9 transition from being configured as Host A, PCIe path 5 to Host A, Ethernet port 1; the SFF-TA-1008 connector's PCIe signals PERp10, PERn10, PETp10, and PETn10 transition from being configured as Host B, PCIe path 4 to Host B, Ethernet port 0; and the SFF-TA-1008 connector's PCIe signals PERp11, PERn11, PETp11, and PETn11 transition from being configured as Host B... PCIe path 5 is switched to host B, Ethernet port 1; PCIe signals PERp12, PERn12, PETp12, and PETn12 of the SFF-TA-1008 connector are switched from host A, PCIe path 6 is switched to host A, Ethernet port 2; PCIe signals PERp13, PERn13, PETp13, and PETn13 of the SFF-TA-1008 connector are switched from host A, PCIe path 7 is switched to host A, Ethernet port 3; PCIe signals PERp14, PERn14, PETp14, and PETn14 of the SFF-TA-1008 connector are switched from host B, PCIe path 6 is switched to host B, Ethernet port 2; PCIe signals PERp15, PERn15, PETp15, and PETn15 of the SFF-TA-1008 connector are switched from host B, PCIe path 7 is switched to host B, Ethernet port 3.

[0020] In some embodiments, a method for selecting an operating mode of a storage device, the storage device being connected to a storage device controller via a first interface, wherein the storage device controller is connected to a host device via a second interface, the method comprising: determining the state of a signal at the second interface; determining an operating mode of the storage device based on the state of the signal at the second interface; and determining the state of a dual-port pin of the host device to determine whether the storage device is operating in single-port mode or dual-port mode.

[0021] In some embodiments, the storage device is one of a New Form Factor 1 (NF1) solid-state drive (SSD), an Ethernet solid-state drive (eSSD), or an embedded SSD; the storage device controller is a Field Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC); the first interface is a Peripheral Component Interconnect Fast (PCIe) interface or a U.2 connector; the second interface is a Small Form Factor (SFF) Technology Alliance (TA)-1008 connector; and the operating mode of the storage device is Non-Volatile Memory Fast (NVMe) mode or Non-Volatile Memory Fast (NVMe-O) mode over a network. In F) mode, the signal state at the second interface is the same as the signal state at the reserved future use (RFU) pin of the SFF-TA-1008 connector. When the signal state at the RFU pin of the SFF-TA-1008 connector is high, the storage device operates in NVMe mode, and when the signal state at the RFU pin of the SFF-TA-1008 connector is low, the storage device operates in NVMe-oF mode. When the dual-port pin is low, the storage device operates in dual-port mode, and when the dual-port pin is high, the storage device operates in single-port mode.

[0022] In some embodiments, the method further includes: downloading an NVMe-oF image or microcode for dual-port NVMe-oF mode to the storage device when the storage device is operating in dual-port NVMe-oF mode; downloading an NVMe-oF image or microcode for single-port NVMe-oF mode to the storage device when the storage device is operating in single-port NVMe-oF mode; downloading an NVMe image or microcode for dual-port NVMe mode to the storage device when the storage device is operating in dual-port NVMe mode; and downloading an NVMe image or microcode for single-port NVMe mode to the storage device when the storage device is operating in single-port NVMe mode. Attached Figure Description

[0023] These and other features of some exemplary embodiments of this disclosure will be appreciated and understood by referring to the specification, claims and drawings, wherein:

[0024] Figure 1 The SFF-TA-1008 connector is shown according to some embodiments of the present disclosure;

[0025] Figure 2A A block diagram illustrating an example SSD device according to some embodiments of the present disclosure is shown;

[0026] Figure 2B Some embodiments according to this disclosure are shown. Figure 2A Another embodiment of the example SSD device;

[0027] Figure 3An SSD device according to some embodiments of the present disclosure is shown, wherein the SSD and the SSD controller are embedded together in the SSD device; and

[0028] Figure 4 Example methods for selecting the mode or protocol of an SSD device according to some embodiments of this disclosure are shown. Detailed Implementation

[0029] The specific embodiments described below with reference to the accompanying drawings are intended as examples of implementations of a multimode protocol solid-state device based on the SFF-TA-100X provided by the present invention, and are not intended to represent the only form in which the invention can be constructed or utilized. These embodiments illustrate the features of the invention in conjunction with the illustrated examples. However, it will be understood that the same or equivalent functions and structures can be implemented by different embodiments that are also intended to be included within the scope of the invention. As indicated elsewhere herein, the same element numbers are intended to indicate the same elements or features.

[0030] Non-Volatile Memory (NVM) Fast Standard (NVMe) is a standard that defines a register-level interface for host software to communicate with non-volatile memory subsystems (e.g., solid-state drives (SSDs)) via the Peripheral Component Interconnect Fast (PCIe) bus. NVMe is an alternative to the Small Computer System Interface (SCSI) standard, which is used to connect and transfer data between a host and peripheral target storage devices or systems. NVMe SSDs with PCIe connectivity allow applications to communicate directly with the storage device.

[0031] Ethernet SSDs (eSSDs) can be connected to the system via a midplane on the PCIe bus using an SSD connector (e.g., U.2). U.2 (SFF-8639) is a computer interface used to connect SSDs to a computer. The U.2 connector supports either two Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) ports and up to four parallel I / O paths (x4) in a PCIe SSD. If not used, the two PCIe paths 1 and 2 can optionally be used as additional SAS ports if needed. The U.2 connector is standardized for NVMe and supports PCIe 3.0 x4, providing speeds, for example, five times faster than SATA SSDs.

[0032] NVMe over Fabrics (NVMe-oF) is an extension of the NVMe standard that operates over various networks (or interconnects) other than PCIe. Here, the term "fabric" refers to a network topology in which network nodes can exchange data with each other via various interconnect protocols, ports, and switches. For example, an Ethernet-attached SSD can be directly attached to a network, in which case the network is Ethernet.

[0033] NVMe-oF enables the use of PCIe alternatives, which extend the distance that NVMe host devices and NVMe storage drives or subsystems can connect to. Therefore, NVMe-oF is a technology specification designed to implement commands based on the NVMe Fast Standard for messages to directly transfer data between a host computer and a target solid-state storage device (e.g., an eSSD or NVMe-oF device) or system over a network (such as Ethernet, Fibre Channel (FC), or InfiniBand). When configured to support the NVMe-oF standard, a system can support a variety of networks, including not only Ethernet but also Fibre Channel, InfiniBand, and others. For example, an eSSD can be directly attached to a network, in this case, Ethernet. An eSSD can refer to an SSD that supports the NVMe-oF protocol.

[0034] Various SSD connectors can be used to exchange data with SSDs, including, for example, U.2 connectors (for SAS4 and PCIe Gen4 protocols, 24 gigabits per second (Gbps) may be the maximum speed) or SFF-TA-100X, where X can be 2, 6, 7, 8 or 9, etc.

[0035] With the advent of 50G and / or 100G Ethernet SSDs (eSSDs) and PCIe Gen 5, the U2 connector may not be expandable. The SFF-TA-100X can support higher data transaction volumes (such as PCIe Gen 5 and others). However, the SFF-TA-100X may not support multi-mode or protocol support (such as NVMe or NVMe-oF). Therefore, some example embodiments may include a single, general-purpose SFF-TA-100X (e.g., SFF-TA-1008) device capable of supporting multiple protocols (such as NVMe or NVMe-oF) and usable in a variety of products. SSD devices may include FPGA+SSDs, network-attached SSDs or eSSDs, and SSDs.

[0036] Some embodiments of this disclosure include an SFF-TA-100X (e.g., SFF-TA-1008) device capable of supporting multiple protocols (such as NVMe or NVMe-oF). The proposed multimode device is capable of supporting NVMe or NVMe-oF by detecting information from a known location or "chassis type" or "protocol selector" pin in the SFF-TA-100X (e.g., SFF-TA-1008) connector.

[0037] For example, the SFF-TA-1006SSD can be used in data centers (e.g., optimized for scalable primary storage and acceleration in server and storage systems). The SFF-TA-1006SSD measures 31.5mm × 111.5mm × 5.75mm or 7.55mm and supports up to 12W caseless. The SFF-TA-1006SSD also supports SFF-TA-1002 1C (e.g., PCIe x4). The SFF-TA-1006SSD supports up to 32GT / s PCIe. The SFF-TA-1006SSD features a high-capacity or high-density NVMe form factor (e.g., up to 36 modules and / or up to 12 14×18mm packages per module in a 1U rack space (e.g., 432 packages / U)). The SFF-TA-1006SSD also supports integrated data-centric computing and offers both case and case-less options.

[0038] In some embodiments, the SSD may be an SFF-8201 2.5″ drive form factor, an SFF-8223 2.5″ drive form factor with a serial connector, an SFF-8301 3.5″ drive form factor, or an SFF-8323 3.5″ drive form factor with a serial connector. SFF-100x is a series of form factors that all use the SFF-1002 connector.

[0039] As another example, Figure 1 The SFF-TA-1008 connector is shown. (As in...) Figure 1As shown, the SFF-TA-1008 connector 100 can be attached to an FPGA+SSD device, and this combination can be used in data centers (e.g., 1U and 2U optimized server and storage enclosures). The SFF-TA-1008-SSD (e.g., an FPGA+SSD connected to the SFF-TA-1008 connector) comes in different sizes: 7.5×76×104.9mm (up to 25W), 7.5×76×142.2mm (up to 35W), 16.8×76×104.9mm (up to 70W), and 16.8×76×142.2mm (up to 70W). The SFF-TA-1008-SSD supports SFF-TA-10021C, 2C, and / or 4C (e.g., PCIe x4-x16). The SFF-TA-1008SSD supports PCIe Gen 5 up to 32GT / s and 802.3 up to 112GT / s. The SFF-TA-1008SSD features high capacity and / or high density NVMe form factor. For example, a 7.5mm form factor SFF-TA-1008SSD (e.g., supporting up to 25W with a 7.5×76×104.9mm form factor and up to 35W with a 7.5×76×142.2mm form factor) supports up to 48 modules. For example, the 104.9mm form factor supports up to 24 14×18mm packages per module (576 / U), or the 142.2mm form factor supports up to 48 14×18mm packages per module (960 / U). For example, the 16.8mm form factor SFF-TA-1008-SSD (e.g., supporting up to 70W in 16.8×76×104.9mm and 16.8×76×142.2mm sizes) supports up to 24 modules or up to 48 14×18mm flash memory packages per module (960 / U). The SFF-TA-1008-SSD supports data-centric computing; for example, its reduced package size frees up space for integrated accelerators. The SFF-TA-1008SSD may include a housing for electrostatic discharge (ESD) protection and hot-plug support, and is aligned with ZSFF 223 and ZSFF 224 (Gen-Z scalable form factor). The housing can also function as a heatsink or spreader for heat management.

[0040] In some embodiments, the Reserved for Future Use (RFU) pin in the SFF-TA-1008 connector can be used as a "chassis type or protocol selector". For example, when the RFU pin of the SFF-TA-1008 connector is low, it indicates the NVMe protocol or chassis. Optionally, when the RFU pin is high, a device (e.g., an FPGA+SSD connected to the SFF-TA-1008 connector) can detect the presence of the device in an NVMe-oF chassis and operate accordingly, or vice versa. For example, in some embodiments according to this disclosure, the RFU pin can be redefined by RFU=NVMe-oF mode to enable the SFF-TA-100X device (e.g., an FPGA+SSD connected to the SFF-TA-1008 connector) to support both NVMe and NVMe-oF protocols. For example, the device (e.g., an FPGA+SSD connected to the SFF-TA-1008 connector) can operate at different Ethernet speeds from 50G to 100G or higher without any changes to its hardware. For each of the NVMe and NVMe-oF modes of operation of the FPGA+SSD connected to the SFF-TA-1008 connector, the SFF-TA-1008 connector operates in X4 single-port, X4 dual-port, X8 single-port, X8 dual-port, X16 single-port, and X16 dual-port modes, respectively.

[0041] In some embodiments, if the device is located within an NVMe chassis, the device (e.g., an FPGA+SSD connected to an SFF-TA-1008 connector) will conform to Table 2 of the Enterprise Data Center Small Form Factor Specification Revision 0.9, as shown in Table 1 below. If the RFU pin is low, or if the device (e.g., an FPGA+SSD connected to an SFF-TA-1008 connector) is located within an NVMe chassis, the following table (Table 1) shows the standard SFF-TA-1008 PCI path connectivity in single-port and dual-port implementations.

[0042]

[0043]

[0044]

[0045] Table 1: Standard SFF-TA-1008PCI Path Connectivity in Single-Port and Dual-Port Implementations

[0046] In some embodiments, if the device (e.g., an FPGA+SSD connected to an SFF-TA-1008 connector) is located within an NVMe-oF chassis (e.g., when the RFU pin is high), the Ethernet port of the SFF-TA-1008 connector will only use PCIe as defined in Table 2 below. Currently, there is no standard implementation specified by NVMe.Org. In some embodiments, the choice of protocol (e.g., NVMe or NVMe-oF) can be determined before downloading the FPGA image. Gigabit transceivers can be used with either PCIe or Ethernet protocols.

[0047] In this configuration, all PCIe ports are capable of communicating with the motherboard's local central processing unit (CPU) and / or the switch's baseboard management controller (BMC), or the motherboard's local central processing unit (CPU) and / or the switch's baseboard management controller (BMC) are capable of communicating with all PCIe ports. All PCIe ports serve as a control plane to perform any normal PCIe transactions, device initialization, and / or firmware upgrades between the BMC or CPU and a device (e.g., an SSD). For example, when the RFU pin is high, a device (e.g., an FPGA+SSD connected to an SFF-TA-1008 connector) exists in an NVMe-oF chassis. The table below (Table 2) shows the SFF-TA-1008 PCIe path connectivity in single-port, dual-port, and NVMe-oF modes.

[0048]

[0049]

[0050] Table 2: SFF-TA-1008PCIe connectivity in single-port, dual-port, and NVMe-oF modes by redefining the RFU pins.

[0051] As discussed above, when the RFU pin of the SFF-TA-1008 connector is high, the FPGA+SSD connected to the SFF-TA-1008 connector operates in NVMe-oF mode, and when the RFU pin of the SFF-TA-1008 connector is low, the FPGA+SSD connected to the SFF-TA-1008 connector operates in NVMe mode. As shown in Table 2 above, in some embodiments, when the device (e.g., an FPGA+SSD connected to the SFF-TA-1008 connector) and the SFF-TA-1008 connector operate in NVMe-oF and X4 single-port modes respectively (e.g., X2 single-port and 1×50G Ethernet port), the PCIe signals PERp2, PERn2, PETp2, and PETn2 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector can be configured as Ethernet port 1 of host A. Host A is used to indicate or describe the first port of the dual-port configuration, and host B is used to indicate the second port.

[0052] As can be seen from Table 1 (NVMe mode) and Table 2 (NVMe-oF mode), in some embodiments, in X4 single-port mode, when the RFU pin of the SFF-TA-1008 connector transitions from low (NVMe mode) to high (NVMe-oF mode) (e.g., when the FPGA+SSD connected to the SFF-TA-1008 connector transitions from NVMe mode to NVMe-oF mode), the PCIe signals PERp2, PERn2, PETp2, and PETn2 of the SFF-TA-1008 connector transition from being configured as Host A, PCIe path 2 to Host A, Ethernet port 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector transition from being configured as Host A, PCIe path 3 to Host A, Ethernet port 1.

[0053] In some embodiments, when the device (e.g., an FPGA+SSD connected to the SFF-TA-1008 connector) and the SFF-TA-1008 connector are operating in NVMe-oF and X4 dual-port modes (e.g., (2 ports × 1) + (2 × 25G Ethernet ports) respectively), the PCIe signals PERp1, PERn1, PETp1, and PETn1 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector can be configured as host B and Ethernet port 1.

[0054] As can be seen from Table 1 (NVMe mode) and Table 2 (NVMe-oF mode), in some embodiments, in X4 dual-port mode, when the RFU pin of the SFF-TA-1008 connector transitions from low (NVMe mode) to high (NVMe-oF mode) (e.g., when the FPGA+SSD connected to the SFF-TA-1008 connector transitions from NVMe mode to NVMe-oF mode), the PCIe signals PERp1, PERn1, PETp1, and PETn1 of the SFF-TA-1008 connector transition from being configured as Host A, PCIe path 1 to Host A, Ethernet port 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector transition from being configured as Host B, PCIe path 1 to Host B, Ethernet port 1.

[0055] In some embodiments, when the device (e.g., an FPGA+SSD connected to the SFF-TA-1008 connector) and the SFF-TA-1008 connector are operating in NVMe-oF and X8 single-port modes (e.g., (1 port × 4) + (1 × 100G Ethernet) respectively), the PCIe signals PERp4, PERn4, PETp4, and PETn4 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 0, the PCIe signals PERp5, PERn5, PETp5, and PETn5 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 1, the PCIe signals PERp6, PERn6, PETp6, and PETn6 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 2, and the PCIe signals PERp7, PERn7, PETp7, and PETn7 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 3.

[0056] As can be seen from Tables 1 (NVMe mode) and 2 (NVMe-oF mode), in some embodiments, in X8 single-port mode, when the RFU pin of the SFF-TA-1008 connector changes from low (NVMe mode) to high (NVMe-oF mode) (e.g., when the FPGA+SSD connected to the SFF-TA-1008 connector transitions from NVMe mode to NVMe-oF mode), the PCIe signals PERp4, PERn4, PETp4, and PETn4 of the SFF-TA-1008 connector change from being configured as Host A, PCIe path 4 to Host A, Ethernet port 0, S The PCIe signals PERp5, PERn5, PETp5, and PETn5 of the FF-TA-1008 connector are switched from being configured as host A, PCIe path 5 to host A, Ethernet port 1. The PCIe signals PERp6, PERn6, PETp6, and PETn6 of the SFF-TA-1008 connector are switched from being configured as host A, PCIe path 6 to host A, Ethernet port 2. The PCIe signals PERp7, PERn7, PETp7, and PETn7 of the SFF-TA-1008 connector are switched from being configured as host A, PCIe path 7 to host A, Ethernet port 3.

[0057] In some embodiments, when the device (e.g., an FPGA+SSD connected to the SFF-TA-1008 connector) and the SFF-TA-1008 connector are operating in NVMe-oF mode and X8 dual-port mode (e.g., (1 port × 4) + (1 × 100G Ethernet) respectively), the PCIe signals PERp2, PERn2, PETp2, and PETn2 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 0, the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 1, the PCIe signals PERp6, PERn6, PETp6, and PETn6 of the SFF-TA-1008 connector can be configured as host B and Ethernet port 2, and the PCIe signals PERp7, PERn7, PETp7, and PETn7 of the SFF-TA-1008 connector can be configured as host B and Ethernet port 3.

[0058] As can be seen from Tables 1 (NVMe mode) and 2 (NVMe-oF mode), in some embodiments, in X8 dual-port mode, when the RFU pin of the SFF-TA-1008 connector changes from low (NVMe mode) to high (NVMe-oF mode) (e.g., when the FPGA+SSD connected to the SFF-TA-1008 connector transitions from NVMe mode to NVMe-oF mode), the PCIe signals PERp2, PERn2, PETp2, and PETn2 of the SFF-TA-1008 connector change from being configured as Host B, PCIe path 0 to Host A, Ethernet port 0. The PCIe signals PERp3, PERn3, PETp3, and PETn3 of the FF-TA-1008 connector are switched from being configured as Host B, PCIe path 1 to Host A, Ethernet port 1. The PCIe signals PERp6, PERn6, PETp6, and PETn6 of the SFF-TA-1008 connector are switched from being configured as Host B, PCIe path 2 to Host B, Ethernet port 2. The PCIe signals PERp7, PERn7, PETp7, and PETn7 of the SFF-TA-1008 connector are switched from being configured as Host B, PCIe path 3 to Host B, Ethernet port 3.

[0059] In some embodiments, when the device (e.g., an FPGA+SSD connected to the SFF-TA-1008 connector) and the SFF-TA-1008 connector are operating in NVMe-oF mode and X16 single-port mode (e.g., (1 port × 8) + (2 × 100G Ethernet) respectively), the PCIe signals PERp8, PERn8, PETp8, and PETn8 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 0; the PCIe signals PERp9, PERn9, PETp9, and PETn9 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 1; and the PCIe signals PERp10, PERn10, PETp10, and PETn10 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 2. The PCIe signals PERp11, PERn11, PETp11, and PETn11 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 3. The PCIe signals PERp12, PERn12, PETp12, and PETn12 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 4. The PCIe signals PERp13, PERn13, PETp13, and PETn13 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 5. The PCIe signals PERp14, PERn14, PETp14, and PETn14 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 6. The PCIe signals PERp15, PERn15, PETp15, and PETn15 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 7.

[0060] As can be seen from Tables 1 (NVMe mode) and 2 (NVMe-oF mode), in some embodiments, in X16 single-port mode, when the RFU pin of the SFF-TA-1008 connector transitions from low (NVMe mode) to high (NVMe-oF mode) (e.g., when an FPGA+SSD connected to the SFF-TA-1008 connector transitions from NVMe mode to NVMe-oF mode), the PCIe signals PERp8, PERn8, PETp8, and PETn8 of the SFF-TA-1008 connector transition from low (NVMe mode) to high (NVMe-oF mode)... The SFF-TA-1008 connector's PCIe signals PERp9, PERn9, PETp9, and PETn9 are switched from host A, PCIe path 9 to host A, Ethernet port 1. The SFF-TA-1008 connector's PCIe signals PERp10, PERn10, PETp10, and PETn10 are switched from host A, PCIe path 10 to host A, Ethernet port 2. The PCIe signals PERp11, PERn11, PETp11, and PETn11 of the SFF-TA-1008 connector are switched from being configured as Host A, PCIe path 11 to Host A, Ethernet port 3. The PCIe signals PERp12, PERn12, PETp12, and PETn12 of the SFF-TA-1008 connector are switched from being configured as Host A, PCIe path 12 to Host A, Ethernet port 4. The PCIe signals PERp13, PERn13, PETp13, and PE of the SFF-TA-1008 connector are also switched. Tn13 is switched from being configured as Host A, PCIe path 13 to Host A, Ethernet port 5; PCIe signals PERp14, PERn14, PETp14 and PETn14 of the SFF-TA-1008 connector are switched from being configured as Host A, PCIe path 14 to Host A, Ethernet port 6; PCIe signals PERp15, PERn15, PETp15 and PETn15 of the SFF-TA-1008 connector are switched from being configured as Host A, PCIe path 15 to Host A, Ethernet port 7.

[0061] In some embodiments, when the device (e.g., an FPGA+SSD connected to the SFF-TA-1008 connector) and the SFF-TA-1008 connector are operating in NVMe-oF mode and X16 dual-port mode (e.g., (2 ports × 4) + (2 × 100G Ethernet) respectively), the PCIe signals PERp8, PERn8, PETp8, and PETn8 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 0; the PCIe signals PERp9, PERn9, PETp9, and PETn9 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 1; and the PCIe signals PERp10, PERn10, PETp10, and PETn10 of the SFF-TA-1008 connector can be configured as host B and Ethernet port 0. The PCIe signals PERp11, PERn11, PETp11, and PETn11 of the SFF-TA-1008 connector can be configured as host B and Ethernet port 1. The PCIe signals PERp12, PERn12, PETp12, and PETn12 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 2. The PCIe signals PERp13, PERn13, PETp13, and PETn13 of the SFF-TA-1008 connector can be configured as host A and Ethernet port 3. The PCIe signals PERp14, PERn14, PETp14, and PETn14 of the SFF-TA-1008 connector can be configured as host B and Ethernet port 2. The PCIe signals PERp15, PERn15, PETp15, and PETn15 of the SFF-TA-1008 connector can be configured as host B and Ethernet port 3.

[0062] As can be seen from Tables 1 (NVMe mode) and 2 (NVMe-oF mode), in some embodiments, in X16 dual-port mode, when the RFU pin of the SFF-TA-1008 connector transitions from low (NVMe mode) to high (NVMe-oF mode), the PCIe signals PERp8, PERn8, PETp8, and PETn8 of the SFF-TA-1008 connector change from being configured as Host A, PCIe path 4 to Host A, Ethernet port 0. The PCIe signals PERp9, PERn9, PETp9, and PETn9 of the SFF-TA-1008 connector are switched from being configured as Host A, PCIe path 5 to Host A, Ethernet port 1. The PCIe signals PERp10, PERn10, PETp10, and PETn10 of the SFF-TA-1008 connector are switched from being configured as Host B, PCIe path 4 to Host B, Ethernet port 0. The PCIe signals PERp11 and PERn10 of the SFF-TA-1008 connector are also switched. 1. PETp11 and PETn11 are switched from being configured as Host B, PCIe path 5 to Host B, Ethernet port 1. The SFF-TA-1008 connector's PCIe signals PERp12, PERn12, PETp12, and PETn12 are switched from being configured as Host A, PCIe path 6 to Host A, Ethernet port 2. The SFF-TA-1008 connector's PCIe signals PERp13, PERn13, PETp13, and PETn13 are switched from being configured as Host B, PCIe path 6 to Host A, Ethernet port 2. A. PCIe path 7 is switched to host A, Ethernet port 3. The PCIe signals PERp14, PERn14, PETp14 and PETn14 of the SFF-TA-1008 connector are switched from host B, PCIe path 6 to host B, Ethernet port 2. The PCIe signals PERp15, PERn15, PETp15 and PETn15 of the SFF-TA-1008 connector are switched from host B, PCIe path 7 to host B, Ethernet port 3.

[0063] The table below (Table 3) shows the PCIe connectivity of the SFF-TA-1008 connector in single-port, dual-port, and NVMe (when the RFU pin is low) or NVMe-oF (e.g., when the RFU pin is high) modes by redefining the RFU pin.

[0064]

[0065] Table 3: SFF-TA-1008 connector PCIe path connection by redefining single-port and dual-port implementations of RFU pins and NVMe (when RFU pin is low) or NVMe-oF (e.g., when RFU pin is high) modes.

[0066] Figure 2A A block diagram illustrating an example SSD device 200 according to some embodiments of the present disclosure is shown. The SSD device 200 may include a computing device (e.g., a field-programmable gate array (FPGA) 201 connected to an SSD 202 (e.g., a new form factor 1 (NF1) SSD, eSSD, or embedded SSD). The FPGA 201 may operate as a controller for the SSD 202 and may provide an interface between an SFF-TA-100X connector or interface (e.g., an SFF-TA-1008 connector 206 and the SSD 202) and multiple flash drives (e.g., 203A and 203B). The SFF-TA-1008 connector 206 may connect to the motherboard and / or BMC of a host device's switch.

[0067] FPGA 201 can be connected to SSD 202 via PCIe interface 209 (e.g., PCIe x8 interface) through ports 207 (e.g., PCIe RP x8 port) and 208 (e.g., PCIe RP x4 port) and multiplexers 218A and 218B. For example, port 207 of FPGA 201 is connected to multiplexer 218A via PCIe x4 bus 216A and 216B. Port 207 of FPGA 201 is connected to multiplexer 218B via PCIe x4 bus 216E. Port 208 of FPGA 201 is connected to multiplexer 218A via PCIe x4 bus 216C, and port 208 of FPGA 201 is connected to multiplexer 218B via PCIe x4 bus 216F.

[0068] Multiplexer 218A is connected to SSD 202 via PCIe x8 interface 209 through a PCIe x8 transmit bus, and multiplexer 218B is connected to SSD 202 via PCIe x8 interface 209 through a PCIe x8 receive bus. Therefore, FPGA 201 can use PCIe x4 transmit buses 216A, 216B, and 216C to send data to SSD 202 via transmit multiplexer 218A through ports 207 and 208, and FPGA 201 can use PCIe x4 receive buses 216D, 216E, and 216F to receive data from SSD 202 via receive multiplexer 218B through ports 207 and 208. Furthermore, port 207 is connected to high-bandwidth memory (HBM) 220A, and port 208 is connected to another HBM 220B. Each of HBM 220A and HBM 220B is connected to HBM controller 222. In some embodiments, FPGA 701 is also connected to flash drives 203A-203B and clock circuit 214.

[0069] SFF-TA-1008 connector 206 can be connected to FPGA 201 via two PCIe x4 ports 204 and 205 through two multiplexers 210 and 212. PCIe x4 port 204 can use the PCIe x4 bus to send signals or packets to the motherboard in the midplane via multiplexer 210 and SFF-TA-1008 connector 206 using the PCIe x4 bus, and can use another PCIe x4 bus to receive signals or packets from the motherboard in the midplane via multiplexer 212 and SFF-TA-1008 connector 206 using the same PCIe x4 bus. PCIe x4 port 205 can use the PCIe x1 bus to send signals or packets to the motherboard in the midplane via multiplexer 210 and SFF-TA-1008 connector 206 using the same PCIe x1 bus, and can use another PCIe x1 bus to receive signals or packets from the motherboard in the midplane via multiplexer 212 and SFF-TA-1008 connector 206 using the same PCIe x1 bus. Multiplexer 210 can send signals to SFF-TA-1008 connector 206 via PCIe X4 bus, and multiplexer 212 can receive signals from SFF-TA-1008 connector 206 via another PCIe X4 bus.

[0070] In some embodiments, the reserved RFU pin 224 of the SFF-TA-1008 connector for future use is redefined by RFU=NVMe-oF mode to enable the SSD 202 to support both NVMe and NVMe-oF protocols. For example, the SSD 202 can operate at different Ethernet speeds from 50G to 100G or higher without requiring any hardware changes based on the state (high or low) of the RFU pin 224. When the RFU pin 224 is high, for example, based on an instruction received from the motherboard or BMC of the host device via the SFF-TA-1008 connector 206 (via a general purpose input / output (GPIO) connected to the RFU), the SSD 202 operates in NVMe-oF mode, and the FPGA 201 can connect to the SFF-TA-1008 connector using Ethernet port 0 and Ethernet port 1. However, when RFU pin 224 is low, for example based on an instruction received from the BMC of the motherboard or host device via SFF-TA-1008 connector 206 (via GPIO connected to RFU), SSD 202 operates in NVMe mode, and FPGA 201 can be connected to SFF-TA-1008 connector using PCIe ports 204, 205 and multiplexers 210 and 212.

[0071] Figure 2B Show Figure 2A Another embodiment of the example SSD device 200. Besides in Figure 2BIn this embodiment, the PCIe x8 interface 209 between the FPGA and the SSD 202 is replaced by a U.2 connector. Figure 2B The embodiments include Figure 2A All components of the embodiment. Figure 2B The embodiment also does not include HBM 220A and HBM 220B connected to ports 207 and 208, nor the HBM controller 222 connected to each of HBM 220A and HBM 220B. Figure 2B In one embodiment, when RFU pin 224 is high (i.e., when SSD 202 is operating in NVMe-oF mode), FPGA 201 can connect to the SFF-TA-1008 connector using Ethernet port 1 and Ethernet port 2.

[0072] Figure 3 An SSD device 300 is shown, in which an SSD 301 and an SSD controller 302 are embedded together. The SSD controller 302 may be an FPGA device or an application-specific integrated circuit (ASIC). In the SSD device 300, an SFF-TA-1008 connector 304 can be connected to the SSD controller 302 via a PCIe x2 port 306 and an Ethernet port 310 (e.g., Ethernet port 0 and Ethernet port 1). The SSD controller 302 can send signals or packets to or receive signals or packets from the motherboard in the midplane via the SFF-TA-1008 connector 304 through the PCIe x2 port 306 and the Ethernet port 310. In some embodiments, the reserved RFU pin 308 of the SFF-TA-1008 connector 304 for future use is redefined in RFU=NVMe-oF mode to enable the SSD 301 to support both NVMe and NVMe-oF protocols. For example, SSD 301 can operate at different Ethernet speeds (NVMe-oF mode) from 50G to 100G or higher without requiring any hardware changes based on the state (high) of RFU pin 308. When RFU pin 308 is high (i.e., when SSD 301 is operating in NVMe-oF mode), SSD controller 302 can connect to SFF-TA-1008 connector 304 using Ethernet port 310 (e.g., Ethernet port 0 and Ethernet port 1) and can operate at different Ethernet speeds from 50G to up to 100G or higher.

[0073] Figure 4 This illustrates an example method for selecting the mode or protocol (NVMe or NVMe-oF) of an SSD device. The SSD device can be... Figure 2A SSD device 200.

[0074] In method 400, the device (e.g., SSD device 200) is reset in step 401.

[0075] In step 402, the SSD controller (e.g., FPGA 201) of the SSD device (e.g., SSD device 200) checks the status of the RFU pin (e.g., RFU pin 224) of the SFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206) connected to the front end of the SSD device (e.g., SSD device 200).

[0076] If the state of the RFU pin (e.g., RFU pin 224) is determined to be high in step 402, then in step 404, the SSD (e.g., SSD 202) connected to the SSD controller (e.g., FPGA 201) begins to operate in NVMe-oF mode.

[0077] Once the SSD (e.g., SSD 202) begins operating in NVMe-oF mode in step 404, in step 406, the SSD controller (e.g., FPGA 201) of the SSD device (e.g., SSD device 200) checks the status of the dual-port pins of the host device connected to the SSD device (e.g., SSD device 200) via the front-end SFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206).

[0078] If, in step 406, the state of the dual-port pin of the host device connected to the SSD device (e.g., SSD device 200) is determined to be low, then in step 408, the SSD (e.g., SSD 202) begins to operate in dual-port NVMe-oF mode, and in step 410, the SSD controller (e.g., FPGA 201) downloads an NVMe-oF image or microcode for dual-port mode from the host device connected to the SSD device (e.g., SSD device 200) via the front-end SFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206) to the SSD (e.g., SSD 202) operating in dual-port NVMe-oF mode.

[0079] However, if in step 406, the state of the dual-port pin of the host device connected to the SSD device (e.g., SSD device 200) is determined to be high, then in step 412, the SSD (e.g., SSD 202) begins to operate in single-port NVMe-oF mode, and in step 414, the SSD controller (e.g., FPGA 201) downloads an NVMe-oF image or microcode for single-port mode from the host device connected to the SSD device (e.g., SSD device 200) via the front-end SFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206) to the SSD (e.g., SSD 202) operating in single-port NVMe-oF mode.

[0080] If the state of the RFU pin (e.g., RFU pin 224) is determined to be low in step 402, then in step 416, the SSD (e.g., SSD 202) connected to the SSD controller (e.g., FPGA 201) begins to operate in NVMe mode.

[0081] Once the SSD (e.g., SSD 202) begins operating in NVMe mode in step 416, in step 418, the SSD controller (e.g., FPGA 201) of the SSD device (e.g., SSD device 200) checks the status of the dual-port pins of the host device connected to the SSD device (e.g., SSD device 200) via the front-end SFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206).

[0082] If, in step 418, the state of the dual-port pin of the host device connected to the SSD device (e.g., SSD device 200) is determined to be low, then in step 420, the SSD (e.g., SSD 202) begins to operate in dual-port NVMe mode, and in step 422, the SSD controller (e.g., FPGA 201) downloads an NVMe image or microcode for dual-port mode from the host device connected to the SSD device (e.g., SSD device 200) via the front-end SFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206) to the SSD (e.g., SSD 202) operating in dual-port NVMe-oF mode.

[0083] However, if in step 418, the state of the dual-port pin of the host device connected to the SSD device (e.g., SSD device 200) is determined to be high, then in step 424, the SSD (e.g., SSD 202) begins to operate in single-port NVMe mode, and in step 426, the SSD controller (e.g., FPGA 201) downloads NVMe images or microcode for single-port mode from the host device connected to the SSD device (e.g., SSD device 200) via the front-end SFF-TA-1008 connector (e.g., SFF-TA-1008 connector 206) to the SSD (e.g., SSD device 200) operating in single-port NVMe mode.

[0084] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of the inventive concept, the first element, first component, first region, first layer, or first portion discussed herein may be referred to as a second element, second component, second region, second layer, or second portion.

[0085] For ease of description, spatial relative terms (such as "below," "under," "below," "above," "over," etc.) are used herein to describe the relationship of an element or feature shown in the accompanying drawings to other elements or features. It will be understood that spatial relative terms are intended to encompass different orientations of the device in use or operation, other than those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as "below," "under," or "below" other elements or features will subsequently be positioned "above" other elements or features. Thus, the example terms "below" and "below" can encompass both above and below orientations. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as "between" two layers, it can be the only layer between those two layers, or there may be one or more intermediate layers.

[0086] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to indicate inherent deviations in measurements or calculations that will be recognized by one of ordinary skill in the art.

[0087] As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When a statement such as “at least one of…” is placed after a list of elements, it modifies the entire list of elements, not individual elements within the list. Furthermore, the use of “may” when describing embodiments of the inventive concept means “one or more embodiments of this disclosure.” Additionally, the term “exemplary” is intended to indicate an example or illustration. As used herein, the term “use” may be considered synonymous with the term “utilize.”

[0088] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to", "bonded to", or "adjacent to" another element or layer, the element or layer may be directly on, directly connected to, directly bonded to, or directly adjacent to the other element or layer, or one or more intermediate elements or layers may be present. Conversely, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to", "directly bonded to", or "immediately adjacent to" another element or layer, no intermediate elements or layers may be present.

[0089] Any numerical range described herein is intended to include all subranges with the same numerical precision contained within the listed range. For example, the range “1.0 to 10.0” is intended to include all subranges between (and including) the listed minimum value of 1.0 and the listed maximum value of 10.0, i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0 (e.g., 2.4 to 7.6). Any maximum numerical limit listed herein is intended to include all lower numerical limits contained therein, while any minimum numerical limit listed herein is intended to include all higher numerical limits contained therein.

[0090] Electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of these devices may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate. Additionally, various components of these devices may be processes or threads executing computer program instructions and interacting with other system components to perform the various functions described herein, running on one or more processors in one or more computing devices. The computer program instructions are stored in memory, which may be implemented in the computing device using standard memory devices (e.g., random access memory (RAM)). The computer program instructions may also be stored on other non-transitory computer-readable media (e.g., CD-ROM, flash memory drive, etc.). Furthermore, those skilled in the art will recognize that, without departing from the spirit and scope of exemplary embodiments of the present disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0091] Although exemplary embodiments of multimode protocol solid-state devices based on the SFF-TA-100X have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that multimode protocol solid-state devices based on the SFF-TA-100X constructed in accordance with the principles of this disclosure can be implemented in ways other than those specifically described herein. The inventive concept is further defined in the appended claims and their equivalents.

Claims

1. A storage system, comprising: Storage device; Storage device controller; The first interface is configured to connect the storage device controller to the storage device. as well as The second interface is configured to connect the storage device controller to the host device. The storage device controller is configured to: check the status of signals at reserved pins for future use on a second interface connected to the storage device controller, and check the status of dual-port pins of a host device connected via the second interface, wherein the signals at the reserved pins for future use on the second interface are based on instructions received from the host device. The storage device is configured to operate in either a first mode or a second mode based on the state of signals at a reserved pin of the second interface for future use. The first mode and the second mode are respectively a non-volatile memory fast mode and a non-volatile memory fast mode via a network. The storage device is also configured to operate in either single-port or dual-port mode based on the status of the host device's dual-port pins. The second interface is a small form factor SFF-Technology Alliance TA-1008 connector. The SFF-TA-1008 connector is attached to the storage device controller and also connects to the motherboard and / or board management controller of the host device's switch. Specifically, when the reserved future use pin of the SFF-TA-1008 connector is high based on an instruction received from the motherboard or baseboard management controller of the host device via the SFF-TA-1008 connector, the storage device operates in non-volatile memory fast mode via network, and the storage device controller is connected to the SFF-TA-1008 connector using Ethernet port 0 and Ethernet port 1; when the reserved future use pin of the SFF-TA-1008 connector is low based on an instruction received from the motherboard or baseboard management controller of the host device via the SFF-TA-1008 connector, the storage device operates in non-volatile memory fast mode, and the storage device controller is connected to the SFF-TA-1008 connector using a PCIe port and a multiplexer.

2. The storage system according to claim 1, wherein, The storage device is one of a new form factor 1 (NF1) solid-state drive, an Ethernet solid-state drive, and an embedded solid-state drive, and the storage device controller is a field-programmable gate array or an application-specific integrated circuit.

3. The storage system according to claim 1, wherein, The first interface is a Peripheral Component Interconnect Fast PCIe interface or a U.2 connector, wherein the storage device has one of the following form factor dimensions: SFF-8201 2.5″ drive form factor, SFF-8223 2.5″ drive form factor with serial connector, SFF-8301 3.5″ drive form factor, and SFF-8323 3.5″ drive form factor with serial connector.

4. The storage system according to claim 1, wherein, In each of the non-volatile memory fast mode and the non-volatile memory fast mode over the network, the SFF-TA-1008 connector operates in one of the following modes: X4 single-port mode, X4 dual-port mode, X8 single-port mode, X8 dual-port mode, X16 single-port mode, and X16 dual-port mode.

5. The storage system according to claim 4, wherein, When the storage device and the SFF-TA-1008 connector are operating in network-connected non-volatile memory fast mode and X4 single-port mode, respectively, the PCIe signals PERp2, PERn2, PETp2, and PETn2 of the SFF-TA-1008 connector are configured as host A and Ethernet port 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector are configured as host A and Ethernet port 1.

6. The storage system according to claim 4, wherein, When the storage device and the SFF-TA-1008 connector are operating in network-connected non-volatile memory fast mode and X4 dual-port mode, respectively, the PCIe signals PERp1, PERn1, PETp1, and PETn1 of the SFF-TA-1008 connector are configured as host A and Ethernet port 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector are configured as host B and Ethernet port 1.

7. The storage system according to claim 4, wherein, When the storage device and the SFF-TA-1008 connector are operating in network-connected non-volatile memory fast mode and X8 single-port mode respectively, the PCIe signals PERp4, PERn4, PETp4, and PETn4 of the SFF-TA-1008 connector are configured as host A and Ethernet port 0, the PCIe signals PERp5, PERn5, PETp5, and PETn5 of the SFF-TA-1008 connector are configured as host A and Ethernet port 1, the PCIe signals PERp6, PERn6, PETp6, and PETn6 of the SFF-TA-1008 connector are configured as host A and Ethernet port 2, and the PCIe signals PERp7, PERn7, PETp7, and PETn7 of the SFF-TA-1008 connector are configured as host A and Ethernet port 3.

8. The storage system according to claim 4, wherein, When the storage device and the SFF-TA-1008 connector are operating in network-connected non-volatile memory fast mode and X8 dual-port mode, respectively, the PCIe signals PERp2, PERn2, PETp2, and PETn2 of the SFF-TA-1008 connector are configured as host A and Ethernet port 0, the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector are configured as host A and Ethernet port 1, the PCIe signals PERp6, PERn6, PETp6, and PETn6 of the SFF-TA-1008 connector are configured as host B and Ethernet port 2, and the PCIe signals PERp7, PERn7, PETp7, and PETn7 of the SFF-TA-1008 connector are configured as host B and Ethernet port 3.

9. The storage system according to claim 4, wherein, When the storage device and the SFF-TA-1008 connector operate in network-connected non-volatile memory fast mode and x16 single-port mode, respectively, the SFF-TA-1008 connector's PCIe signals PERp8, PERn8, PETp8, and PETn8 are configured as host A and Ethernet port 0; the SFF-TA-1008 connector's PCIe signals PERp9, PERn9, PETp9, and PETn9 are configured as host A and Ethernet port 1; the SFF-TA-1008 connector's PCIe signals PERp10, PERn10, PETp10, and PETn10 are configured as host A and Ethernet port 2; and the SFF-TA-1008 connector's PCIe signals PERp11, PERn11, and PETp1... 1 and PETn11 are configured as host A and Ethernet port 3. PCIe signals PERp12, PERn12, PETp12 and PETn12 of the SFF-TA-1008 connector are configured as host A and Ethernet port 4. PCIe signals PERp13, PERn13, PETp13 and PETn13 of the SFF-TA-1008 connector are configured as host A and Ethernet port 5. PCIe signals PERp14, PERn14, PETp14 and PETn14 of the SFF-TA-1008 connector are configured as host A and Ethernet port 6. PCIe signals PERp15, PERn15, PETp15 and PETn15 of the SFF-TA-1008 connector are configured as host A and Ethernet port 7.

10. The storage system according to claim 4, wherein, When the storage device and the SFF-TA-1008 connector operate in network-connected non-volatile memory fast mode and x16 dual-port mode, respectively, the SFF-TA-1008 connector's PCIe signals PERp8, PERn8, PETp8, and PETn8 are configured as host A and Ethernet port 0; the SFF-TA-1008 connector's PCIe signals PERp9, PERn9, PETp9, and PETn9 are configured as host A and Ethernet port 1; the SFF-TA-1008 connector's PCIe signals PERp10, PERn10, PETp10, and PETn10 are configured as host B and Ethernet port 0; and the SFF-TA-1008 connector's PCIe signals PERp11, PERn11, and PETp1... 1 and PETn11 are configured as host B and Ethernet port 1. The PCIe signals PERp12, PERn12, PETp12 and PETn12 of the SFF-TA-1008 connector are configured as host A and Ethernet port 2. The PCIe signals PERp13, PERn13, PETp13 and PETn13 of the SFF-TA-1008 connector are configured as host A and Ethernet port 3. The PCIe signals PERp14, PERn14, PETp14 and PETn14 of the SFF-TA-1008 connector are configured as host B and Ethernet port 2. The PCIe signals PERp15, PERn15, PETp15 and PETn15 of the SFF-TA-1008 connector are configured as host B and Ethernet port 3.

11. A storage system, comprising: Computing device; as well as The storage device is connected to the computing device via a first interface. The computing device is configured to operate as a controller for the storage device. The computing device is connected to the host device via a second interface. The computing device is further configured to: check the status of signals at reserved pins for future use on a second interface connected to the computing device, and check the status of dual-port pins on a host device connected via the second interface, wherein the signals at the reserved pins for future use on the second interface are based on instructions received from the host device. The storage device is configured to operate in either a first mode or a second mode based on the state of signals at a reserved pin of the second interface for future use. The first mode and the second mode are respectively a non-volatile memory fast mode and a non-volatile memory fast mode via a network. The storage device is also configured to operate in either single-port or dual-port mode based on the status of the host device's dual-port pins. The second interface is a small form factor SFF-Technology Alliance TA-1008 connector. The SFF-TA-1008 connector is attached to the computing device and also connects to the motherboard and / or board management controller of the host device's switch. Specifically, when the reserved future use pin of the SFF-TA-1008 connector is high based on an instruction received from the motherboard or baseboard management controller of the host device via the SFF-TA-1008 connector, the storage device operates in non-volatile memory fast mode via network, and the computing device connects to the SFF-TA-1008 connector using Ethernet port 0 and Ethernet port 1; when the reserved future use pin of the SFF-TA-1008 connector is low based on an instruction received from the motherboard or baseboard management controller of the host device via the SFF-TA-1008 connector, the storage device operates in non-volatile memory fast mode, and the computing device connects to the SFF-TA-1008 connector using a PCIe port and a multiplexer.

12. The storage system according to claim 11, wherein: The storage device is one of the following: a new form factor 1 solid-state drive, an Ethernet solid-state drive, and an embedded solid-state drive; the computing device is a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The first interface is either a peripheral component interconnection fast PCIe interface or a U.2 connector. The signal is based on instructions received from the host device via general purpose inputs / outputs connected to reserved pins for future use, and In both the non-volatile memory fast mode and the non-volatile memory fast mode over the network, the SFF-TA-1008 connector operates in one of the following modes: X4 single-port mode, X4 dual-port mode, X8 single-port mode, X8 dual-port mode, X16 single-port mode, and X16 dual-port mode.

13. The storage system according to claim 12, wherein, In X4 single-port mode, when the reserved pin for future use of the SFF-TA-1008 connector transitions from a low state to a high state, the SFF-TA-1008 connector's PCIe signals PERp2, PERn2, PETp2, and PETn2 transition from being configured as Host A, PCIe path 2 to Host A, Ethernet port 0; and the SFF-TA-1008 connector's PCIe signals PERp3, PERn3, PETp3, and PETn3 transition from being configured as Host A, PCIe path 3 to Host A, Ethernet port 1. In X4 dual-port mode, when the reserved pins of the SFF-TA-1008 connector transition from low to high, the PCIe signals PERp1, PERn1, PETp1, and PETn1 of the SFF-TA-1008 connector transition from being configured as Host A, PCIe path 1 to Host A, Ethernet port 0, and the PCIe signals PERp3, PERn3, PETp3, and PETn3 of the SFF-TA-1008 connector transition from being configured as Host B, PCIe path 1 to Host B, Ethernet port 1.

14. The storage system according to claim 12, wherein, In X8 single-port mode, when the reserved pin for future use of the SFF-TA-1008 connector transitions from a low state to a high state, the SFF-TA-1008 connector's PCIe signals PERp4, PERn4, PETp4, and PETn4 transition from being configured as Host A, PCIe path 4 to Host A, Ethernet port 0; the SFF-TA-1008 connector's PCIe signals PERp5, PERn5, PETp5, and PETn5 transition from being configured as Host A, PCIe path 5 to Host A, Ethernet port 1; the SFF-TA-1008 connector's PCIe signals PERp6, PERn6, PETp6, and PETn6 transition from being configured as Host A, PCIe path 6 to Host A, Ethernet port 2; and the SFF-TA-1008 connector's PCIe signals PERp7, PERn7, PETp7, and PETn7 transition from being configured as Host A, PCIe path 7 to Host A, Ethernet port 3. In X8 dual-port mode, when the reserved pins of the SFF-TA-1008 connector transition from low to high, the SFF-TA-1008 connector's PCIe signals PERp2, PERn2, PETp2, and PETn2 transition from being configured as Host B, PCIe path 0 to Host A, Ethernet port 0; the SFF-TA-1008 connector's PCIe signals PERp3, PERn3, PETp3, and PETn3 transition from being configured as Host B, PCIe path 1 to Host A, Ethernet port 1; the SFF-TA-1008 connector's PCIe signals PERp6, PERn6, PETp6, and PETn6 transition from being configured as Host B, PCIe path 2 to Host B, Ethernet port 2; and the SFF-TA-1008 connector's PCIe signals PERp7, PERn7, PETp7, and PETn7 transition from being configured as Host B, PCIe path 3 to Host B, Ethernet port 3.

15. The storage system according to claim 12, wherein, In X16 single-port mode, when the reserved pin for future use of the SFF-TA-1008 connector transitions from low to high, the SFF-TA-1008 connector's PCIe signals PERp8, PERn8, PETp8, and PETn8 transition from being configured as Host A, PCIe path 8 to Host A, Ethernet port 0; the SFF-TA-1008 connector's PCIe signals PERp9, PERn9, PETp9, and PETn9 transition from being configured as Host A, PCIe path 9 to Host A, Ethernet port 1; the SFF-TA-1008 connector's PCIe signals PERp10, PERn10, PETp10, and PETn10 transition from being configured as Host A, PCIe path 10 to Host A, Ethernet port 2; and the SFF-TA-1008 connector's PCIe signals PERp11, PERn11, PETp11, and PETn11 transition from being configured as Host A, PCIe path 8 to Host A, Ethernet port 2. The SFF-TA-1008 connector's PCIe signals PERp12, PERn12, PETp12, and PETn12 are switched from being configured as Host A, PCIe path 12 to Host A, Ethernet port 4. The SFF-TA-1008 connector's PCIe signals PERp13, PERn13, PETp13, and PETn13 are switched from being configured as Host A, PCIe path 13 to Host A, Ethernet port 5. The SFF-TA-1008 connector's PCIe signals PERp14, PERn14, PETp14, and PETn14 are switched from being configured as Host A, PCIe path 14 to Host A, Ethernet port 6. The SFF-TA-1008 connector's PCIe signals PERp15, PERn15, PETp15, and PETn15 are switched from being configured as Host A, PCIe path 15 to Host A, Ethernet port 7.

16. The storage system according to claim 12, wherein, In X16 dual-port mode, when the reserved pins for future use of the SFF-TA-1008 connector transition from low to high, the SFF-TA-1008 connector's PCIe signals PERp8, PERn8, PETp8, and PETn8 change from being configured as Host A, PCIe path 4 to Host A, Ethernet port 0; the SFF-TA-1008 connector's PCIe signals PERp9, PERn9, PETp9, and PETn9 change from being configured as Host A, PCIe path 5 to Host A, Ethernet port 1; the SFF-TA-1008 connector's PCIe signals PERp10, PERn10, PETp10, and PETn10 change from being configured as Host B, PCIe path 4 to Host B, Ethernet port 0; and the SFF-TA-1008 connector's PCIe signals PERp11, PERn11, PETp11, and PETn11 change from being configured as Host B, PCIe path 4 to Host B, Ethernet port 0. PCIe path 5 is switched to host B, Ethernet port 1; PCIe signals PERp12, PERn12, PETp12, and PETn12 of the SFF-TA-1008 connector are switched from host A, PCIe path 6 to host A, Ethernet port 2; PCIe signals PERp13, PERn13, PETp13, and PETn13 of the SFF-TA-1008 connector are switched from host A, PCIe path 7 to host A, Ethernet port 3; PCIe signals PERp14, PERn14, PETp14, and PETn14 of the SFF-TA-1008 connector are switched from host B, PCIe path 6 to host B, Ethernet port 2; PCIe signals PERp15, PERn15, PETp15, and PETn15 of the SFF-TA-1008 connector are switched from host B, PCIe path 7 to host B, Ethernet port 3.

17. A method for selecting an operating mode of a storage device, wherein the storage device is connected to a storage device controller via a first interface, wherein... The method includes connecting the storage device controller to the host device via a second interface: Check the status of the signals at the reserved pins for future use on the second interface connected to the storage device controller; The operating mode of the storage device is determined by the state of the signals at the reserved pins of the second interface for future use. Check the status of the dual-port pins of the host device connected via the second interface; and The status of the host device's dual-port pins determines whether the storage device is operating in single-port or dual-port mode. The signals at the pins reserved for future use in the second interface are based on instructions received from the host device, and the operating mode of the storage device is either non-volatile memory fast mode or non-volatile memory fast mode via network. The second interface is a small form factor SFF-Technology Alliance TA-1008 connector. The SFF-TA-1008 connector is attached to the storage device controller and also connects to the motherboard and / or board management controller of the host device's switch. Specifically, when the reserved future use pin of the SFF-TA-1008 connector is high based on an instruction received from the motherboard or baseboard management controller of the host device via the SFF-TA-1008 connector, the storage device operates in non-volatile memory fast mode via network, and the storage device controller is connected to the SFF-TA-1008 connector using Ethernet port 0 and Ethernet port 1; when the reserved future use pin of the SFF-TA-1008 connector is low based on an instruction received from the motherboard or baseboard management controller of the host device via the SFF-TA-1008 connector, the storage device operates in non-volatile memory fast mode, and the storage device controller is connected to the SFF-TA-1008 connector using a PCIe port and a multiplexer.

18. The method of claim 17, wherein: The storage device is one of the following: a new form factor 1 solid-state drive, an Ethernet solid-state drive, and an embedded solid-state drive. The storage device controller is a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The first interface is a peripheral component interconnect fast PCIe interface or a U.2 connector, and When the dual-port pin is low, the memory device operates in dual-port mode; when the dual-port pin is high, the memory device operates in single-port mode.

19. The method according to claim 18, wherein, The method further includes: When the storage device is operating in dual-port mode and network-connected non-volatile memory fast mode, the network-connected non-volatile memory fast image or microcode for dual-port mode is downloaded to the storage device. When the storage device is operating in single-port mode and network-connected non-volatile memory fast mode, the network-connected non-volatile memory fast image or microcode for single-port mode is downloaded to the storage device. When the storage device is operating in dual-port mode and non-volatile memory fast mode, a non-volatile memory fast image or microcode for dual-port mode is downloaded to the storage device, and When the storage device is operating in single-port mode and non-volatile memory fast mode, non-volatile memory fast images or microcode for single-port mode are downloaded to the storage device.

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