A high performance charge pump for phase-locked loops

Abstract

The present invention discloses a high-performance charge pump for a phase-locked loop, belonging to the technical field of integrated circuits, and solving the technical problem that the charge pump in the charge pump type phase-locked loop in the prior art is difficult to achieve high current matching and low current noise output. The charge pump comprises: a charging circuit (10) for charging a charge pump output node; a discharging circuit (20) for discharging the charge pump output node; a charge-discharge voltage balancing circuit (30) for controlling the charging circuit and the discharging circuit during the process of charging and discharging the charge pump output node, so that the charge pump output node voltage is consistent with the reference node voltage, so as to eliminate the charge sharing effect; and a charge-discharge current matching circuit (40) for controlling the charging circuit and the discharging circuit during the process of charging and discharging the charge pump output node, so that the current matching degree between the charging circuit and the discharging circuit is maintained within a preset range, thereby reducing the PLL reference spurious.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-performance charge pump used in a phase-locked loop. Background Art

[0002] With the development of the integrated circuit industry, transceiver chips compatible with multiple protocols have become a research hotspot in the current wireless communication field. As a key module of the RF front end, the frequency synthesizer mainly provides a programmable frequency local carrier signal to the frequency conversion circuit in the transceiver.

[0003] Most of the current mainstream integrated frequency synthesizers are phase-locked loop frequency synthesizers, and the commonly used architecture in phase-locked loop frequency synthesizers is the charge pump phase-locked loop (CPPLL). Phase-locked loop systems are widely used, from global positioning systems to clock recovery circuits to wireless receiver circuits, etc. Different application fields have different requirements for their performance. The important point is that the quality of their performance directly affects the quality of the communication system. Therefore, high-speed, low phase noise, low power jitter, low power consumption and low chip area CPPLL systems are increasingly gaining attention from engineers.

[0004] like Figure 1 As shown in the figure, it is a basic structural diagram of integer-division CPPLL. CPPLL is mainly composed of phase frequency detector PFD (Phase Frequency Detector), charge pump CP (Charge Pump), loop filter LPF (Low Pass Filter), one-to-N divider (Divider) and voltage-controlled oscillator VCO (Voltage Controlled Oscillator). When a very small frequency step output is required, fractional CPPLL with modulator is also widely used. As the requirements for CPPLL are increasingly tending towards broadband, low phase noise, and low spurious, the design of charge pump CP, a key module in CPPLL, also needs to meet the requirements of high current matching and low current noise.

[0005] At present, in addition to using the simplest current mirror and MOS switches to form charging and discharging current branches, the industry can also achieve CP current matching through the following solutions in engineering. Figure 2As shown, the charge pump circuit includes: a charging branch 1, a discharging branch 2, a bias circuit 3 and a switch output circuit 4. The charge pump adopts a common source and common gate mirror structure to generate precise pull-up current Iup0 and sink current Idn0, reduce the channel length modulation effect and increase the output resistance of the charge pump, and realize a current matching CP structure, but its current mismatch is usually greater than 3%, and it has high requirements on the symmetry of the layout. At the same time, the drain end (CP_OUT0 node) of the MOS switch tube connected to the UP end and the DN end in the switch output circuit 4 will produce a charge sharing effect, causing the output voltage of the loop filter to change, introducing a steady-state phase error in the loop, which will cause ripples on the output voltage of the loop filter. These ripples will frequency modulate the voltage-controlled oscillator, so that the output signal of the voltage-controlled oscillator is no longer an ideal sine wave, and deteriorate the phase noise performance of the loop.

[0006] That is to say, it is difficult for the charge pump in the CPPLL in the prior art to achieve the technical problem of high current matching and low current noise output. Summary of the invention

[0007] The present invention aims at the technical problem in the prior art that the charge pump in a charge pump type phase-locked loop is difficult to achieve high current matching and low current noise output, and provides a high-performance charge pump structure that can reduce the charge sharing effect, improve the CP output current matching performance, and reduce the PLL reference spurious.

[0008] The present invention provides a high-performance charge pump used in a phase-locked loop, comprising:

[0009] A charging circuit, used to charge the charge pump output node under the action of a charging control signal;

[0010] A discharge circuit, used for discharging the charge pump output node under the action of a discharge control signal;

[0011] A charge-discharge voltage balancing circuit, arranged between the charging circuit and the discharging circuit, for controlling the charging circuit and the discharging circuit during the charging and discharging process of the charge pump output node, so that the voltage of the charge pump output node is consistent with the reference node voltage;

[0012] The charge and discharge current matching circuit is arranged between the charging circuit and the discharging circuit, and is used to control the charging circuit and the discharging circuit during the charging and discharging process of the charge pump output node so that the current matching degree between the charging circuit and the discharging circuit is maintained within a preset range.

[0013] Optionally, the charging circuit includes: a first current source, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube;

[0014] The drain and gate of the first PMOS tube are both connected to the first current source; the gate of the first PMOS tube is also connected to the gate of the second PMOS tube, the gate of the third PMOS tube, and the gate of the fourth PMOS tube; the source of the first PMOS tube is connected to the source of the second PMOS tube, the source of the third PMOS tube, and the source of the fourth PMOS tube; the drain of the second PMOS tube is connected to the charge and discharge current matching circuit; the drain of the third PMOS tube is connected to the charge and discharge current matching circuit; and the drain of the fourth PMOS tube is connected to the charge and discharge voltage balancing circuit.

[0015] Optionally, the discharge circuit includes: a first NMOS tube, a second NMOS tube and a third NMOS tube;

[0016] The gate and drain of the first NMOS tube are both connected to the gate of the second NMOS tube and the gate of the third NMOS tube; the source of the first NMOS tube is both connected to the source of the second NMOS tube and the source of the third NMOS tube; the drain of the first NMOS tube is also connected to the charge and discharge current matching circuit; the drain of the second NMOS tube is connected to the charge and discharge current matching circuit; the drain of the third NMOS tube is connected to the charge and discharge voltage balancing circuit.

[0017] Optionally, the charging circuit also includes: a first transmission gate and a second transmission gate connected in parallel to each other and connected to the charge and discharge voltage balance circuit; the first transmission gate and the second transmission gate are used to control the conduction or disconnection of the connection between the charging circuit and the charge and discharge voltage balance circuit under the action of a charging control signal.

[0018] Optionally, the first transmission gate includes: a fifth PMOS tube and a fourth NMOS tube; the gate of the fifth PMOS tube and the gate of the fourth NMOS tube are used to receive the charging control signal, the source of the fifth PMOS tube and the drain of the fourth NMOS tube are both connected to the charging circuit voltage node, and the drain of the fifth PMOS tube and the source of the fourth NMOS tube are both connected to the charge and discharge voltage balance circuit;

[0019] The second transmission gate includes: a sixth PMOS tube and a fifth NMOS tube; the gate of the sixth PMOS tube and the gate of the fifth NMOS tube are used to receive the charging control signal, the source of the sixth PMOS tube and the drain of the fifth NMOS tube are both connected to the charging circuit voltage node, and the drain of the sixth PMOS tube and the source of the fifth NMOS tube are both connected to the charge and discharge voltage balance circuit.

[0020] Optionally, the discharge circuit also includes: a third transmission gate and a fourth transmission gate connected in parallel to each other and connected to the charge and discharge voltage balance circuit; the third transmission gate and the fourth transmission gate are used to control the connection between the discharge circuit and the charge and discharge voltage balance circuit to be turned on or off under the action of a discharge control signal; the third transmission gate is connected to the first transmission gate, and the fourth transmission gate is connected to the second transmission gate.

[0021] Optionally, the third transmission gate includes: a seventh PMOS tube and a sixth NMOS tube; the gate of the seventh PMOS tube and the gate of the sixth NMOS tube are used to receive the discharge control signal, the source of the seventh PMOS tube and the drain of the sixth NMOS tube are both connected to the charge and discharge voltage balance circuit, and the drain of the seventh PMOS tube and the source of the sixth NMOS tube are both connected to the discharge circuit voltage node;

[0022] The fourth transmission gate includes: an eighth PMOS tube and a seventh NMOS tube; the gate of the eighth PMOS tube and the gate of the seventh NMOS tube are used to receive the discharge control signal, the source of the eighth PMOS tube and the drain of the seventh NMOS tube are both connected to the charge and discharge voltage balance circuit, and the drain of the eighth PMOS tube and the source of the seventh NMOS tube are both connected to the discharge circuit voltage node.

[0023] Optionally, the charge-discharge voltage balancing circuit includes: a first amplifier;

[0024] The output end of the first amplifier is connected to the first transmission gate and the third transmission gate, and the non-inverting input end of the first amplifier is connected to the second transmission gate and the fourth transmission gate; the non-inverting input end of the first amplifier is also connected to the output node of the charge pump; the inverting input end of the first amplifier is connected to its output end.

[0025] Optionally, the charge and discharge current matching circuit includes: a second amplifier;

[0026] The output end of the second amplifier is connected to the second PMOS tube and the first NMOS tube, the non-inverting input end of the second amplifier is connected to the third PMOS tube and the second NMOS tube, and the inverting output end of the second amplifier is connected to the charge pump output node.

[0027] Optionally, the charge and discharge voltage balancing circuit and / or the charge and discharge current matching circuit includes a rail-to-rail amplifier.

[0028] One or more technical solutions provided in the present invention have at least the following technical effects or advantages:

[0029] In the scheme of the present invention, the high-performance charge pump used in the phase-locked loop includes: a charging circuit for charging the charge pump output node under the action of a charging control signal; a discharging circuit for discharging the charge pump output node under the action of a discharging control signal; a charge-discharge voltage balancing circuit arranged between the charging circuit and the discharging circuit, and used to control the charging circuit and the discharging circuit during the process of charging and discharging the charge pump output node so that the voltage of the charge pump output node is consistent with the voltage of the reference node; and a charge-discharge current matching circuit arranged between the charging circuit and the discharging circuit, and used to control the charging circuit and the discharging circuit during the process of charging and discharging the charge pump output node so that the current matching degree of the charging circuit and the discharging circuit is maintained within a preset range. That is, the scheme of the present invention reduces the charge sharing effect by adopting a charge-discharge voltage balancing circuit to make the charge pump output node voltage consistent with the reference node voltage; and at the same time, by adopting a charge-discharge current matching circuit, the current matching of the charge-discharge branch is increased, and the PLL reference spurious is reduced. It effectively solves the technical problem that the charge pump in the charge pump type phase-locked loop in the prior art is difficult to achieve high current matching and low current noise output. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0031] Figure 1 It is a schematic diagram of the structure of an integer frequency division charge pump phase-locked loop in the prior art;

[0032] Figure 2 A schematic diagram of a charge pump circuit for achieving CP current matching in the prior art;

[0033] Figure 3A A structural block diagram of a high-performance charge pump provided by an embodiment of the present invention;

[0034] Figure 3B A structural block diagram of another high-performance charge pump provided by an embodiment of the present invention;

[0035] Figure 4 A circuit schematic diagram of a high-performance charge pump provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The embodiment of the present invention solves the technical problem in the prior art that the charge pump in the charge pump type phase-locked loop is difficult to achieve high current matching and low current noise output by providing a high-performance charge pump applied to the phase-locked loop. The solution of the present invention adopts a charge and discharge voltage balancing circuit to make the charge pump output node voltage consistent with the reference node voltage, thereby reducing the charge sharing effect; at the same time, by adopting a charge and discharge current matching circuit, the current matching of the charge and discharge branches is increased, thereby reducing the PLL reference spurious.

[0037] The technical solution of the embodiment of the present invention is to solve the above technical problems, and the overall idea is as follows:

[0038] An embodiment of the present invention provides a high-performance charge pump for use in a phase-locked loop, including: a charging circuit, used to charge a charge pump output node under the action of a charging control signal; a discharging circuit, used to discharge the charge pump output node under the action of a discharging control signal; a charge-discharge voltage balancing circuit, arranged between the charging circuit and the discharging circuit, used to control the charging circuit and the discharging circuit during the process of charging and discharging the charge pump output node so that the charge pump output node voltage is consistent with a reference node voltage; a charge-discharge current matching circuit, arranged between the charging circuit and the discharging circuit, used to control the charging circuit and the discharging circuit during the process of charging and discharging the charge pump output node so that the current matching degree between the charging circuit and the discharging circuit is maintained within a preset range.

[0039] It can be seen that in the scheme of the present invention, the charge pump output node voltage is kept consistent with the reference node voltage by adopting the charge-discharge voltage balancing circuit, thereby reducing the charge sharing effect; at the same time, the charge-discharge current matching circuit is adopted to increase the current matching of the charge-discharge branch and reduce the PLL reference spurious. This effectively solves the technical problem that the charge pump in the charge pump type phase-locked loop in the prior art is difficult to achieve high current matching and low current noise output.

[0040] In order to better understand the above-mentioned technical scheme, the above-mentioned technical scheme will be described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical scheme of the present application, rather than limitations on the technical scheme of the present application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0041] Embodiment 1

[0042] Please refer to Figure 3A and Figure 4 , an embodiment of the present invention provides a high-performance charge pump applied to a phase-locked loop, comprising:

[0043] The charging circuit 10 is used to charge the charge pump output node CP_OUT under the action of the charging control signal;

[0044] The discharge circuit 20 is used to discharge the charge pump output node CP_OUT under the action of the discharge control signal;

[0045] The charge-discharge voltage balancing circuit 30 is disposed between the charging circuit 10 and the discharging circuit 20 and connected to the two circuits, and is used to control the charging circuit 10 and the discharging circuit 20 during the process of charging and discharging the charge pump output node CP_OUT, so that the voltage of the charge pump output node CP_OUT is consistent with the voltage of the reference node VF1;

[0046] The charge and discharge current matching circuit 40 is arranged between the charging circuit 10 and the discharging circuit 20 and is connected to the two. It is used to control the charging circuit 10 and the discharging circuit 20 during the charging and discharging process of the charge pump output node CP_OUT so that the current matching degree between the charging circuit 10 and the discharging circuit 20 is maintained within a preset range; preferably, the charge and discharge current matching degree is maintained at 98% to 100%; wherein the charge and discharge current matching circuit 40 is also connected to the charge pump output node CP_OUT to obtain the current output of the charge pump in real time, and adjust the current of the charging circuit 10 and the discharging circuit 20 based on the current output control of the charge pump so that the charge and discharge current matching degree is maintained within the preset range.

[0047] In the specific implementation process, the switch tubes in the charging circuit 10 and the discharging circuit 20 are correspondingly configured to generate mirror currents. For details, please refer to Figure 3A , Figure 3B and Figure 4 The charging circuit 10 includes: a first current source S1, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3 and a fourth PMOS tube MP4; the drain and gate of the first PMOS tube MP1 are both connected to the first current source S1; the gate of the first PMOS tube MP1 is also connected to the gate of the second PMOS tube MP2, the gate of the third PMOS tube MP3 and the gate of the fourth PMOS tube MP4; the source of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2, the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4; the drain of the second PMOS tube MP2 is connected to the charge and discharge current matching circuit 40; the drain of the third PMOS tube MP3 is connected to the charge and discharge current matching circuit 40; the drain of the fourth PMOS tube MP4 is connected to the charge and discharge voltage balance circuit 30. Among them, S1 is a schematic diagram of a precision current source, indicating a precise mirror current source provided by an NMOS tube; Iup indicates the charging current.

[0048] Please still refer to Figure 3A , Figure 3B and Figure 4 The discharge circuit 20 includes: a first NMOS transistor MN1, a second NMOS transistor MN2 and a third NMOS transistor MN3; the gate of the first NMOS transistor MN1 is connected to the drain of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2 and the gate of the third NMOS transistor MN3, and is further connected to the charge-discharge current matching circuit 40; the source of the first NMOS transistor MN1 is connected to the source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3; the drain of the second NMOS transistor MN2 is also connected to the charge-discharge current matching circuit 40; the drain of the third NMOS transistor MN3 is connected to the charge-discharge voltage balance circuit 30. Wherein, Idn indicates the discharge current.

[0049] Furthermore, in the specific implementation process, in order to make the charge injection effects introduced by the switch tubes in the charging circuit 10 and the discharging circuit 20 offset each other and speed up the switching time, the charge pump circuit uses a transmission gate for switch control. Figure 3B and Figure 4 The charging circuit 10 includes: a first transmission gate 101 and a second transmission gate 102 connected in parallel to each other and connected to the charge-discharge voltage balance circuit 30; the first transmission gate 101 and the second transmission gate 102 are used to control the connection between the charging circuit 10 and the charge-discharge voltage balance circuit 30 under the action of the charging control signal. The discharging circuit 20 also includes: a third transmission gate 201 and a fourth transmission gate 202 connected in parallel to each other and connected to the charge-discharge voltage balance circuit 30; the third transmission gate 201 and the fourth transmission gate 202 are used to control the connection between the discharging circuit 20 and the charge-discharge voltage balance circuit 30 under the action of the discharging control signal; the third transmission gate 201 is connected to the first transmission gate 101, and the fourth transmission gate 202 is connected to the second transmission gate 102.

[0050] For further information, please refer to Figure 3B and Figure 4 The first transmission gate 101 includes: a fifth PMOS tube MP5 and a fourth NMOS tube MN4; the gate of the fifth PMOS tube MP5 and the gate of the fourth NMOS tube MN4 are used to receive the charging control signal, and the source of the fifth PMOS tube MP5 and the drain of the fourth NMOS tube MN4 are both connected to the charging circuit voltage node VP; specifically connected to the drain of the fourth PMOS tube MP4, the connection node is the charging circuit voltage node VP (the charging circuit node voltage is obtained from the VP point), and is further connected to the first current source S1 through the charging branch formed by the fourth PMOS tube MP4, the third PMOS tube MP3, the second PMOS tube MP2, and the first PMOS tube MP1; the drain of the fifth PMOS tube MP5 and the source of the fourth NMOS tube MN4 are both connected to the charge and discharge voltage balance circuit 30.

[0051] The second transmission gate 102 includes: a sixth PMOS tube MP6 and a fifth NMOS tube MN5; the gate of the sixth PMOS tube MP6 and the gate of the fifth NMOS tube MN5 are used to receive the charging control signal, and the source of the sixth PMOS tube MP6 and the drain of the fifth NMOS tube MN5 are both connected to the charging circuit voltage node VP; specifically connected to the drain of the fourth PMOS tube MP4, the connection node is the charging circuit voltage node VP, and further connected to the first current source S1 through the charging branch formed by the fourth PMOS tube MP4, the third PMOS tube MP3, the second PMOS tube MP2, and the first PMOS tube MP1; the drain of the sixth PMOS tube MP6 and the source of the fifth NMOS tube MN5 are both connected to the charge and discharge voltage balance circuit 30.

[0052] The third transmission gate 201 includes: a seventh PMOS transistor MP7 and a sixth NMOS transistor MN6; the gate of the seventh PMOS transistor MP7 and the gate of the sixth NMOS transistor MN6 are used to receive the discharge control signal, the source of the seventh PMOS transistor MP7 and the drain of the sixth NMOS transistor MN6 are both connected to the charge and discharge voltage balance circuit 30, and the drain of the seventh PMOS transistor MP7 and the source of the sixth NMOS transistor MN6 are both connected to the discharge circuit voltage node VN; specifically, they are connected to the drain of the third NMOS transistor MN3, and the connection node is the discharge circuit voltage node VN (the discharge circuit node voltage is obtained from the VN point). The third transmission gate 201 is further connected to the first current source S1 through a branch formed by the third NMOS transistor MN3, the second NMOS transistor MN2, the first NMOS transistor MN1, the charge and discharge current matching circuit 40, the third PMOS transistor MP3, the second PMOS transistor MP2, and the first PMOS transistor MP1. That is, in the embodiment of the present application, the charging circuit and the discharging circuit refer to the same current source S1 to enhance the matching degree between the charging current Iup and the discharging current Idn, thereby reducing the PLL reference spurious.

[0053] The fourth transmission gate 202 includes: an eighth PMOS transistor MP8 and a seventh NMOS transistor MN7; the gate of the eighth PMOS transistor MP8 and the gate of the seventh NMOS transistor MN7 are used to receive the discharge control signal, the source of the eighth PMOS transistor MP8 and the drain of the seventh NMOS transistor MN7 are both connected to the charge and discharge voltage balance circuit 30, and the drain of the eighth PMOS transistor MP8 and the source of the seventh NMOS transistor MN7 are both connected to the discharge circuit voltage node VN; specifically, it is connected to the drain of the third NMOS transistor MN3, and the connection node is the discharge circuit voltage node VN, and is further connected to the first current source S1 through a branch formed by the third NMOS transistor MN3, the second NMOS transistor MN2, the first NMOS transistor MN1, the charge and discharge current matching circuit 40, the third PMOS transistor MP3, the second PMOS transistor MP2, and the first PMOS transistor MP1. In the specific implementation process, the first transmission gate 101 receives the control signals UP_P and UP_N from the phase frequency detector PFD through the gate of the fifth PMOS transistor MP5 and the gate of the fourth NMOS transistor MN4, the second transmission gate 102 receives the control signals UP_N and UP_P from the phase frequency detector PFD through the gate of the sixth PMOS transistor MP6 and the gate of the fifth NMOS transistor MN5, the third transmission gate 201 receives the control signals DN_P and DN_N from the phase frequency detector PFD through the gate of the seventh PMOS transistor MP7 and the gate of the sixth NMOS transistor MN6, and the fourth transmission gate 202 receives the control signals DN_N and DN_P from the phase frequency detector PFD through the gate of the eighth PMOS transistor MP8 and the gate of the seventh NMOS transistor MN7. That is to say, the first transmission gate 101, the second transmission gate 102, the third transmission gate 201 and the fourth transmission gate 202 perform switch control based on the control signal from the phase frequency detector PFD, so that the charge injection effects introduced by the switch tubes offset each other and the switch time is accelerated. The circuit can achieve excellent output current noise performance by appropriately designing the size of each transmission gate circuit.

[0054] In the specific implementation process, please refer to Figure 4 , the charge-discharge voltage balancing circuit 30 includes: a first amplifier OPA1, which can be a unit gain amplifier formed by connecting rail-to-rail amplifiers. The output end of the first amplifier OPA1 is connected to the first transmission gate 101 and the third transmission gate 201, and the non-inverting input end of the first amplifier OPA1 is connected to the second transmission gate 102 and the fourth transmission gate 202; the non-inverting input end of the first amplifier OPA1 is also connected to the charge pump output node CP_OUT; the inverting input end of the first amplifier OPA1 is connected to its output end. Under the action of the first amplifier OPA1, the voltage of the charge pump output node CP_OUT can be consistent with the voltage of the reference node VF1.

[0055] In the specific implementation process, please refer to Figure 4 , the output end of the first amplifier OPA1 is connected to the first transmission gate 101 through the ninth PMOS tube MP9, and is connected to the third transmission gate 201 through the eighth NMOS tube MN8; the in-phase input end of the first amplifier OPA1 is connected to the second transmission gate 102 through the tenth PMOS tube MP10, and is connected to the fourth transmission gate 202 through the ninth NMOS tube MN9. Among them, the ninth PMOS tube MP9, the eighth NMOS tube MN8, the tenth PMOS tube MP10 and the ninth NMOS tube MN9 are matching devices; wherein the matching devices are conducive to increasing the matching degree of each branch in voltage and current. The charge-discharge voltage balancing circuit 30 makes the voltage of the output node CP_OUT consistent with the voltage of the reference node VF1 within a large charge pump output voltage range, thereby reducing the charge sharing effect.

[0056] In the specific implementation process, please refer to Figure 4 , the charge-discharge current matching circuit 40 includes: a second amplifier OPA2, which can be a rail-to-rail operational amplifier. The output end of the second amplifier OPA2 is connected to the second PMOS tube MP2 and the first NMOS tube MN1, the in-phase input end of the second amplifier OPA2 is connected to the third PMOS tube MP3 and the second NMOS tube MN2, and the inverting output end of the second amplifier OPA2 is connected to the output node CP_OUT of the charge pump to obtain the current output of the charge pump in real time, and adjust the current of the charge-discharge circuit based on the current output control of the charge pump, so that the current matching degree is maintained within a preset range. That is, the charging current Iup and the discharging current Idn are matched as much as possible.

[0057] In the specific implementation process, Figure 4As shown, the output end of the second amplifier OPA2 is connected to the drain of the second PMOS tube MP2 through the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12 connected in series, and is connected to the gate and drain of the first MMOS tube MN1 through the tenth NMOS tube MN10 and the eleventh NMOS tube MN11 connected in series; the in-phase input end of the second amplifier OPA2 is connected to the gate and drain of the third PMOS tube MP3 through the thirteenth PMOS tube MP13 and the fourteenth PMOS tube MP14 connected in series, and is connected to the drain of the second MMOS tube MN2 through the twelfth NMOS tube MN12 and the thirteenth NMOS tube MN13 connected in series; wherein the eleventh PMOS tube MP11, the twelfth PMOS tube MP12, the tenth NMOS tube MN10, the eleventh NMOS tube MN11, the thirteenth PMOS tube MP13, the fourteenth PMOS tube MP14, the twelfth NMOS tube MN12 and the thirteenth NMOS tube MN13 are all matching devices; wherein the matching device is beneficial to increase the matching degree of each branch in voltage and current. The connection node VF2 between the in-phase input terminal of the second amplifier OPA2 and the drain of the twelfth NMOS tube MN12 is also connected to the gates of the first NMOS tube MN1, the second NMOS tube MN2, and the third NMOS tube MN3 through the compensation capacitor C0. The output of the second amplifier OPA2 is used to control the gate voltages of the first NMOS tube MN1, the second NMOS tube MN2, and the third NMOS tube MN3, so that the VF2 node voltage is consistent with the CP_OUT node voltage within a large CP output voltage range, thereby increasing the current matching of each branch. In addition, since the second amplifier OPA2 introduces both positive feedback and negative feedback loops, the addition of the compensation capacitor C0 ensures the stability of the circuit.

[0058] In the specific implementation process, the sources of the first to fourth PMOS tubes MP1~MP4 and the gates of the eighth to thirteenth NMOS tubes MN8~MN13 are all connected to the first voltage VDD, and the sources of the first to third NMOS tubes MN1~MN3 and the gates of the ninth to fourteenth PMOS tubes MP9~MP14 are all connected to the second voltage VSS.

[0059] In summary, the implementation of the embodiments of the present application has at least the following technical effects:

[0060] (1) By adopting a charge-discharge voltage balancing circuit, the charge pump output node voltage is kept consistent with the reference node voltage, thereby reducing the charge sharing effect; at the same time, by adopting a charge-discharge current matching circuit, the current matching of the charge-discharge branch is increased, thereby reducing the PLL reference spurious. This effectively solves the technical problem that the charge pump in the charge pump type phase-locked loop in the prior art is difficult to achieve high current matching and low current noise output.

[0061] (2) Use transmission gates for switch control. The transmission gates can offset the charge injection effects introduced by the switch tubes and speed up the switching time.

[0062] (3) Since the charge and discharge current matching circuit introduces both positive feedback and negative feedback loops, the addition of compensation capacitors ensures the stability of the circuit.

[0063] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0064] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A high performance charge pump for use in a phase-locked loop, characterized in that: include: A charging circuit (10) is used to charge the charge pump output node under the action of a charging control signal; A discharge circuit (20) for discharging the charge pump output node under the action of a discharge control signal; A charge-discharge voltage balancing circuit (30) is arranged between the charging circuit (10) and the discharging circuit (20), and is used to control the charging circuit (10) and the discharging circuit (20) during the process of charging and discharging the charge pump output node, so that the voltage of the charge pump output node is consistent with the reference node voltage; A charge and discharge current matching circuit (40) is arranged between the charging circuit (10) and the discharging circuit (20), and is used to control the charging circuit (10) and the discharging circuit (20) during the process of charging and discharging the charge pump output node, so that the current matching degree between the charging circuit (10) and the discharging circuit (20) is maintained within a preset range; The charging circuit (10) further comprises: a first transmission gate (101) and a second transmission gate (102) which are connected in parallel to each other and are connected to the charge-discharge voltage balance circuit (30); the first transmission gate (101) and the second transmission gate (102) are used to control the connection between the charging circuit (10) and the charge-discharge voltage balance circuit (30) to be turned on or off under the action of a charging control signal.

2. The high performance charge pump used in a phase locked loop as claimed in claim 1, characterized in that: The charging circuit (10) comprises: a first current source (S1), a first PMOS tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3) and a fourth PMOS tube (MP4); The drain and gate of the first PMOS tube (MP1) are both connected to the first current source (S1); the gate of the first PMOS tube (MP1) is also connected to the gate of the second PMOS tube (MP2), the gate of the third PMOS tube (MP3), and the gate of the fourth PMOS tube (MP4); the source of the first PMOS tube (MP1) is connected to the source of the second PMOS tube (MP2), the source of the third PMOS tube (MP3), and the source of the fourth PMOS tube (MP4); the drain of the second PMOS tube (MP2) is connected to the charge and discharge current matching circuit (40); the drain of the third PMOS tube (MP3) is connected to the charge and discharge current matching circuit (40); and the drain of the fourth PMOS tube (MP4) is connected to the charge and discharge voltage balancing circuit (30).

3. The high performance charge pump used in a phase locked loop as claimed in claim 2, characterized in that: The discharge circuit (20) comprises: a first NMOS tube (MN1), a second NMOS tube (MN2) and a third NMOS tube (MN3); The gate and drain of the first NMOS tube (MN1) are both connected to the gate of the second NMOS tube (MN2) and the gate of the third NMOS tube (MN3); the source of the first NMOS tube (MN1) is both connected to the source of the second NMOS tube (MN2) and the source of the third NMOS tube (MN3); the drain of the first NMOS tube (MN1) is also connected to the charge and discharge current matching circuit (40); the drain of the second NMOS tube (MN2) is connected to the charge and discharge current matching circuit (40); and the drain of the third NMOS tube (MN3) is connected to the charge and discharge voltage balancing circuit (30).

4. The high performance charge pump used in a phase locked loop as claimed in claim 1, characterized in that: The first transmission gate (101) comprises: a fifth PMOS tube (MP5) and a fourth NMOS tube (MN4); the gate of the fifth PMOS tube (MP5) and the gate of the fourth NMOS tube (MN4) are used to receive the charging control signal, the source of the fifth PMOS tube (MP5) and the drain of the fourth NMOS tube (MN4) are both connected to the charging circuit voltage node, and the drain of the fifth PMOS tube (MP5) and the source of the fourth NMOS tube (MN4) are both connected to the charging and discharging voltage balancing circuit (30); The second transmission gate (102) comprises: a sixth PMOS tube (MP6) and a fifth NMOS tube (MN5); the gate of the sixth PMOS tube (MP6) and the gate of the fifth NMOS tube (MN5) are used to receive the charging control signal, the source of the sixth PMOS tube (MP6) and the drain of the fifth NMOS tube (MN5) are both connected to the charging circuit voltage node, and the drain of the sixth PMOS tube (MP6) and the source of the fifth NMOS tube (MN5) are both connected to the charging and discharging voltage balancing circuit (30).

5. The high performance charge pump used in a phase locked loop as claimed in claim 1, characterized in that: The discharge circuit (20) further comprises: a third transmission gate (201) and a fourth transmission gate (202) which are connected in parallel to each other and are connected to the charge-discharge voltage balance circuit (30); the third transmission gate (201) and the fourth transmission gate (202) are used to control the connection between the discharge circuit (20) and the charge-discharge voltage balance circuit (30) to be turned on or off under the action of a discharge control signal; the third transmission gate (201) is connected to the first transmission gate (101), and the fourth transmission gate (202) is connected to the second transmission gate (102).

6. The high performance charge pump used in a phase locked loop as claimed in claim 5, characterized in that: The third transmission gate (201) comprises: a seventh PMOS tube (MP7) and a sixth NMOS tube (MN6); the gate of the seventh PMOS tube (MP7) and the gate of the sixth NMOS tube (MN6) are used to receive the discharge control signal, the source of the seventh PMOS tube (MP7) and the drain of the sixth NMOS tube (MN6) are both connected to the charge-discharge voltage balancing circuit (30), and the drain of the seventh PMOS tube (MP7) and the source of the sixth NMOS tube (MN6) are both connected to the discharge circuit voltage node; The fourth transmission gate (202) comprises: an eighth PMOS tube (MP8) and a seventh NMOS tube (MN7); the gate of the eighth PMOS tube (MP8) and the gate of the seventh NMOS tube (MN7) are used to receive the discharge control signal, the source of the eighth PMOS tube (MP8) and the drain of the seventh NMOS tube (MN7) are both connected to the charge-discharge voltage balancing circuit (30), and the drain of the eighth PMOS tube (MP8) and the source of the seventh NMOS tube (MN7) are both connected to the discharge circuit voltage node.

7. The high performance charge pump used in a phase locked loop as claimed in claim 5, characterized in that: The charge-discharge voltage balancing circuit (30) comprises: a first amplifier (OPA1); The output end of the first amplifier (OPA1) is connected to the first transmission gate (101) and the third transmission gate (201), and the non-inverting input end of the first amplifier (OPA1) is connected to the second transmission gate (102) and the fourth transmission gate (202); the non-inverting input end of the first amplifier (OPA1) is also connected to the output node of the charge pump; and the inverting input end of the first amplifier (OPA1) is connected to its output end.

8. The high performance charge pump used in a phase locked loop as claimed in claim 3, characterized in that: The charge and discharge current matching circuit (40) comprises: a second amplifier (OPA2); The output end of the second amplifier (OPA2) is connected to the second PMOS transistor (MP2) and the first NMOS transistor (MN1), the non-inverting input end of the second amplifier (OPA2) is connected to the third PMOS transistor (MP3) and the second NMOS transistor (MN2), and the inverting output end of the second amplifier (OPA2) is connected to the charge pump output node.

9. The high performance charge pump used in a phase locked loop as claimed in claim 1, characterized in that: The charge-discharge voltage balancing circuit (30) and / or the charge-discharge current matching circuit (40) include a rail-to-rail amplifier.

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