Memory test circuit and method, integrated circuit chip test system

Abstract

The present invention discloses a memory test circuit and method, and an integrated circuit chip test system, and relates to the field of integrated circuit testing. The memory test circuit includes a driver, a subtractor, and a receiver. Specifically, the driver can be used to respond to a test instruction from a test machine and send a first signal to the device under test via a single transmission line of the device under test; the subtractor can be used to receive the first signal and a second signal generated by the device under test in response to the first signal and sent via a single transmission line, and the second signal is subtracted from the first signal to obtain a third signal and output; the receiver can be used to receive the third signal and send the third signal to the test machine. The present disclosure can solve the problem that the signal output by the driver interferes with the signal received by the receiver due to the delay of signal transmission on the single transmission line and signal transmission.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit testing, and in particular to a memory testing circuit and method, and an integrated circuit chip testing system. Background Art

[0002] Integrated Circuit (IC) is a microelectronic device or component. It is an electronic device that is manufactured through semiconductor manufacturing processes such as oxidation, photolithography, diffusion, epitaxy, and film formation. The semiconductors, resistors, capacitors, and other components required to form a circuit with a certain function, as well as the connecting wires between them, are all integrated on a small silicon chip, and then welded and packaged in a tube shell. With the development of IC technology, integrated circuits have been applied to various types of electronic devices.

[0003] The integrated circuit transmits information to the outside world through a single transmission line (STL), which can be a bidirectional signal bus. In this case, the driver and the receiver share the single transmission line during the test. However, there is a delay between the tester and the integrated circuit, so the signal received by the receiver will be interfered by the signal sent by the driver.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a memory test circuit and method, and an integrated circuit chip test system, thereby overcoming, at least to a certain extent, the problem that the signal emitted by the driver will interfere with the signal received by the receiver due to the limitations and defects of the relevant technology.

[0006] According to one aspect of the present disclosure, a memory test circuit is provided. The memory test circuit may include a driver, a subtractor, and a receiver.

[0007] Specifically, the driver can be used to respond to a test instruction from a test machine and send a first signal to the device under test via the single transmission line of the device under test; the subtractor can be used to receive the first signal and a second signal generated by the device under test in response to the first signal and sent via the single transmission line, subtract the first signal from the second signal to obtain a third signal and output it; the receiver can be used to receive the third signal and send the third signal to the test machine.

[0008] Optionally, the driver has an input terminal, a first output terminal and a second output terminal; the subtractor has a first input terminal, a second input terminal and an output terminal; and the receiver has an input terminal and an output terminal.

[0009] Specifically, the input end of the driver is connected to the test machine, the first output end of the driver is connected to the single transmission line, the second output end of the driver is connected to the first input end of the subtractor; the second input end of the subtractor is connected to the single transmission line, the output end of the subtractor is connected to the input end of the receiver; the output end of the receiver is connected to the test machine.

[0010] Optionally, the memory test circuit may further include an operational amplifier.

[0011] Specifically, the operational amplifier can be used to compare the third signal with a threshold voltage, and output the comparison result to the tester.

[0012] Optionally, the operational amplifier has a first input terminal, a second input terminal and an output terminal. The first input terminal of the operational amplifier is connected to the output terminal of the receiver, the second input terminal of the operational amplifier is used to receive the threshold voltage, and the output terminal of the operational amplifier is connected to the tester.

[0013] Optionally, the memory test circuit may further include a first impedance and a second impedance. The first end of the first impedance is connected to the first output end of the driver, and the second end of the first impedance is connected to the single transmission line; the first end of the second impedance is connected to the second output end of the driver, and the second end of the second impedance is connected to the first input end of the subtractor.

[0014] Optionally, the memory test circuit may further include a switch element. Specifically, the switch element may be connected to a single transmission line to control whether to perform a memory test process.

[0015] According to one aspect of the present disclosure, there is provided an integrated circuit chip testing system, comprising any one of the above-mentioned memory testing circuits.

[0016] According to one aspect of the present disclosure, a memory testing method is provided, comprising: a driver sends a first signal to a device under test via a single transmission line of the device under test in response to a test instruction sent by a test machine; a subtractor receives the first signal and a second signal generated by the device under test in response to the first signal and sent via the single transmission line, subtracts the first signal from the second signal to obtain a third signal and outputs the third signal; and a receiver receives the third signal and sends the third signal to the test machine.

[0017] Optionally, the receiver sending the third signal to the tester includes: the receiver sending the third signal to an operational amplifier; the operational amplifier compares the third signal with a threshold voltage and outputs the comparison result to the tester.

[0018] Optionally, the memory test method further includes: controlling a switch state of a switch element connected to the single transmission line to control whether to perform a memory test process.

[0019] In the technical solutions provided in some embodiments of the present disclosure, the signal output by the device under test is processed by a subtractor so that the signal input to the receiver is the signal actually output by the device under test, thereby overcoming the problem that the signal output by the driver interferes with the signal received by the receiver due to the signal transmission by a single transmission line and the delay of signal transmission. In addition, compared with the dual transmission line solution adopted by some test circuits, the memory test circuit described in the present disclosure can reduce the number of test machine channels required.

[0020] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0022] Figure 1 A circuit diagram schematically illustrating a memory test circuit of some techniques;

[0023] Figure 2 Schematically shows a circuit diagram of a memory test circuit according to an exemplary embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram showing a memory test circuit according to an exemplary embodiment of the present disclosure applied to a high-speed continuous read and write test scenario is shown;

[0025] Figure 4 schematically shows a timing diagram of a receiver receiving a signal when the receiver is tested without using a subtractor;

[0026] Figure 5 A timing diagram schematically shows a signal received by a receiver tested by a subtractor according to the present disclosure;

[0027] Figure 6 A flowchart of a memory testing method according to an exemplary embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0028] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0029] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted.

[0030] In integrated circuit testing, each channel of the tester includes a driver and a receiver. The driver can send a signal (for example, a read signal) to the device under test (DUT) in response to the test instruction of the tester, and the receiver can receive a corresponding signal (for example, a write signal) sent by the device under test and send the corresponding signal to the tester for analysis by the tester.

[0031] Currently, the related technology uses a single transmission line or a dual transmission line (DTL) to test the device under test.

[0032] Figure 1 The circuit diagram of a memory test circuit of some technologies is schematically shown. This test circuit adopts a dual transmission line method, that is, the first channel 11 and the second channel 12 are independent of each other and will not interfere with each other. However, this test circuit requires multiple channels, that is, the number of drivers and receivers is large. It is not conducive to maintenance.

[0033] The single transmission line can be a bidirectional signal transmission line, through which the driver and the receiver are connected to the device under test. When a single transmission line is used to test an integrated circuit chip, due to the delay between the tester and the integrated circuit, the signal received by the receiver may be interfered by the signal sent by the driver, resulting in inaccurate test results.

[0034] In view of this, the present disclosure provides a memory test circuit to solve the above problems. It should be understood that the memory test circuit described below can be applied to the scenario of testing the bidirectional transmission pins of the chip. In addition, the following circuit can be particularly applied to the scenario where the delay between the driver and the chip is almost the same as the delay between the receiver and the chip.

[0035] refer to Figure 2 , the memory test circuit disclosed in the present invention can be implemented based on channel 20.

[0036] The memory test circuit of the present disclosure may include a driver 201 , a subtractor 203 , and a receiver 202 .

[0037] The driver 201 may be configured to send a first signal to the device under test 21 via the single transmission line of the device under test 21 in response to a test instruction from the test machine 22 .

[0038] Specifically, the driver 201 may send a first signal to a DQ pin (data input / output pin) or a DQS pin (data selection signal pin) of the device under test 21 via a single transmission line, and the first signal may be, for example, a data read signal. In addition, the driver 201 may send a first signal to other pins of the device under test 21 via a single transmission line, and the first signal may also be other signals except the data read signal, which is not particularly limited in this exemplary embodiment.

[0039] The device under test 21 can generate a second signal in response to the first signal, and send the second signal to the subtractor 203 via the single transmission line. In addition, the subtractor 203 can receive the first signal sent by the driver 201. In this case, the subtractor 203 can subtract the first signal from the second signal to obtain a third signal, and output the third signal to the receiver 202. After receiving the third signal, the receiver 202 can send the third signal to the test machine 22, so that other processing units of the test machine 22 analyze the third signal to achieve the purpose of testing the device under test 21.

[0040] The circuit structure of a memory test circuit according to an embodiment of the present disclosure is described below. The driver 201 may have an input terminal, a first output terminal, and a second output terminal; the subtractor 203 may have a first input terminal, a second input terminal, and an output terminal; and the receiver 202 may have an input terminal and an output terminal.

[0041] Specifically, the input end of the driver 201 can be connected to the test machine 22, the first output end of the driver 201 can be connected to the single transmission line, and the second output end of the driver 201 can be connected to the first input end of the subtractor 203; the second input end of the subtractor 203 can be connected to the single transmission line, and the output end of the subtractor 203 can be connected to the input end of the receiver 202; the output end of the receiver 202 can be connected to the test machine 22.

[0042] According to some embodiments of the present disclosure, the memory test circuit may further include an operational amplifier 204. The operational amplifier 204 may be used to compare the third signal with a threshold voltage Vth, and output the comparison result to the tester 22. For example, when the third signal is greater than the threshold voltage Vth, the operational amplifier 204 outputs 1, and when the third signal is less than the threshold voltage Vth, the operational amplifier 204 outputs 0.

[0043] Specifically, the operational amplifier 204 may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of the operational amplifier 204 may be connected to the output terminal of the receiver 202, the second input terminal of the operational amplifier 204 may be used to receive the threshold voltage Vth, and the output terminal of the operational amplifier 204 may be connected to the tester 22.

[0044] According to some embodiments of the present disclosure, the memory test circuit may further include a first impedance 205 and a second impedance 206. Specifically, the first end of the first impedance 205 may be connected to the first output end of the driver 201, and the second end of the first impedance 205 may be connected to the single transmission line. The first end of the second impedance 206 may be connected to the second output end of the driver 201, and the second end of the second impedance 206 may be connected to the first input end of the subtractor 201. In addition, the specific values ​​of the first impedance 205 and the second impedance 206 may vary according to different test scenarios, and the present disclosure does not impose any limitation on this.

[0045] According to some other embodiments, the memory test circuit may further include a switch element 207. Specifically, the switch element 207 may be connected to a single transmission line and may be used to control whether to perform the above-mentioned memory test process. For example, in the case where the memory test circuit of the present disclosure is applied to a test scenario of a read-write operation, the read-write test function may be turned off by the switch element 207, so that the test machine may implement a scenario such as a current test on an integrated circuit chip through other channels.

[0046] Figure 3 A schematic diagram of a memory test circuit according to an exemplary embodiment of the present disclosure applied to a high-speed continuous read and write test scenario is shown. In this case, the tester needs to determine the minimum value of the time tRTW from the read to the write command. Specifically, tRTW can be expressed as follows:

[0047] tRTW=RL+BL / 2-WL+2tCK

[0048] Among them, RL represents read latency, BL represents standard data length, WL represents write latency, and tCK represents clock time.

[0049] refer to Figure 3 , when the tester sends a command (CMD), the DQ pin of the DRAM (Dynamic Random Access Memory) can be tested for read and write. Due to the transmission delay between the tester and the DRAM, when the tester sends a read instruction (READ), a time interval RL as shown in the figure may be generated, and the DRAM can generate a read signal 31 in response to the read instruction. Similarly, when the tester sends a write instruction (WRITE), a time interval WL as shown in the figure may be generated, and the DRAM can generate a write signal 32 in response to the write instruction. It should be understood that the illustrated read signal 31 and write signal 32 are only examples of DQ pins. In fact, due to the delay, the signal received by the receiver will be disturbed.

[0050] Specifically, refer to Figure 4 In some technologies, when a single transmission line is used without a subtractor, the receiver receives the signal after interference. It can be seen that the waveform changes greatly.

[0051] refer to Figure 5 In the case of adopting the memory test circuit of the exemplary embodiment of the present disclosure, due to the effect of the subtractor, the third signal output by the subtractor can better reflect the output voltage of the device under test.

[0052] In the memory test circuit provided in some embodiments of the present disclosure, the signal output by the device under test is processed by a subtractor so that the signal input to the receiver is the signal actually output by the device under test, thereby overcoming the problem that the signal output by the driver interferes with the signal received by the receiver due to the signal transmission by a single transmission line and the delay of signal transmission. In addition, compared with the dual transmission line solution adopted by some test circuits, the memory test circuit described in the present disclosure can reduce the number of test machine channels required.

[0053] Furthermore, the present disclosure also provides an integrated circuit chip testing system, which includes the memory testing circuit of any one of the above embodiments.

[0054] Furthermore, the present disclosure also provides a memory testing method. Specifically, the memory testing method may include the following steps:

[0055] S62. The driver sends a first signal to the device under test via a single transmission line of the device under test in response to a test instruction sent by the test machine;

[0056] S64. The subtractor receives the first signal and the second signal generated by the device under test in response to the first signal and sent via the single transmission line, subtracts the first signal from the second signal to obtain a third signal and outputs the third signal;

[0057] S66. The receiver receives the third signal and sends the third signal to the tester.

[0058] In the memory test method provided in some embodiments of the present disclosure, the signal output by the device under test is processed by a subtractor so that the signal input to the receiver is the signal actually output by the device under test, thereby overcoming the problem that the signal output by the driver interferes with the signal received by the receiver due to the single transmission line transmission signal and the delay of signal transmission. In addition, compared with the dual transmission line solution adopted by some test circuits, the memory test circuit described in the present disclosure can reduce the number of test machine channels required.

[0059] According to an exemplary embodiment of the present disclosure, the receiver sending the third signal to the tester includes: the receiver sending the third signal to an operational amplifier; the operational amplifier compares the third signal with a threshold voltage and outputs the comparison result to the tester.

[0060] According to an exemplary embodiment of the present disclosure, the memory test method further includes: controlling a switch state of a switch element connected to the single transmission line to control whether to perform a memory test process.

[0061] The specific process of the memory testing method disclosed in the present invention is the same as the content of the memory testing circuit disclosed in the above description, and will not be repeated here.

[0062] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0063] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A memory test circuit, characterized in that: include: A driver, configured to send a first signal to the device under test via a single transmission line of the device under test in response to a test instruction from a test machine; a subtractor, configured to receive the first signal and a second signal generated by the device under test in response to the first signal and sent via the single transmission line, and to subtract the first signal from the second signal to obtain a third signal and output the third signal; a receiver, configured to receive the third signal and send the third signal to the tester; The driver has an input terminal, a first output terminal and a second output terminal; the subtractor has a first input terminal, a second input terminal and an output terminal; The receiver has an input and an output; The input end of the driver is connected to the tester, the first output end of the driver is connected to the single transmission line, and the second output end of the driver is connected to the first input end of the subtractor; The second input terminal of the subtractor is connected to the single transmission line, and the output terminal of the subtractor is connected to the input terminal of the receiver; The output end of the receiver is connected to the test machine.

2. The memory test circuit according to claim 1, characterized in that: The memory test circuit further includes: The operational amplifier is used to compare the third signal with a threshold voltage and output the comparison result to the tester.

3. The memory test circuit according to claim 2, characterized in that: The operational amplifier has a first input terminal, a second input terminal and an output terminal; The first input terminal of the operational amplifier is connected to the output terminal of the receiver, the second input terminal of the operational amplifier is used to receive the threshold voltage, and the output terminal of the operational amplifier is connected to the tester.

4. The memory test circuit according to claim 1, characterized in that: The memory test circuit also includes a first impedance and a second impedance; A first end of the first impedance is connected to a first output end of the driver, and a second end of the first impedance is connected to the single transmission line; A first end of the second impedance is connected to the second output end of the driver, and a second end of the second impedance is connected to the first input end of the subtractor.

5. The memory test circuit according to any one of claims 1, 3 or 4, characterized in that: The memory test circuit further includes: The switch element is connected to the single transmission line and is used to control whether to perform the memory test process.

6. An integrated circuit chip testing system, characterized in that: A memory test circuit comprising the memory test circuit described in any one of claims 1 to 5.

7. A memory testing method, characterized in that: include: The driver sends a first signal to the device under test via the single transmission line of the device under test in response to the test instruction sent by the test machine; A subtractor receives the first signal and a second signal generated by the device under test in response to the first signal and sent via the single transmission line, subtracts the first signal from the second signal to obtain a third signal and outputs the third signal; The receiver receives the third signal and sends the third signal to the tester; The driver has an input terminal, a first output terminal and a second output terminal; the subtractor has a first input terminal, a second input terminal and an output terminal; The receiver has an input and an output; The input end of the driver is connected to the tester, the first output end of the driver is connected to the single transmission line, and the second output end of the driver is connected to the first input end of the subtractor; The second input terminal of the subtractor is connected to the single transmission line, and the output terminal of the subtractor is connected to the input terminal of the receiver; The output end of the receiver is connected to the test machine.

8. The memory testing method according to claim 7, characterized in that: The receiver sending the third signal to the test machine comprises: The receiver sends the third signal to an operational amplifier; The operational amplifier compares the third signal with a threshold voltage and outputs the comparison result to the tester.

9. The memory testing method according to claim 7 or 8, characterized in that: The memory testing method further includes: The switch state of the switch element connected to the single transmission line is controlled to control whether to perform a memory test process.

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