Method and system for testing electrical performance of semiconductor chip

Abstract

The invention discloses a method and system for testing the electrical performance of a semiconductor chip, and the method comprises the steps: building a mapping relation between dielectric loss and loss frequency through obtaining the dielectric loss data, internal material characteristics and dynamic load power factors of the chip under each frequency band, recognizing a loss abnormal region, and analyzing the influence of the loss abnormal region on the performance of the chip; correcting test data by adopting a minimum mean square error algorithm, and optimizing the impedance of the power supply network and the dynamic switching characteristic of a functional module; calculating the breakdown voltage distribution of each layer in the chip, identifying a high-voltage risk region, optimizing the voltage distribution by using a gradient descent algorithm, and dynamically adjusting the working voltage and current; power factor fluctuation is analyzed through a sliding window algorithm, an abnormal area is identified, a power factor is optimized through a PID algorithm, and the working state and transient response of a chip in a dynamic load are improved. According to the method, the problems of nonlinearity of high-frequency dielectric loss, non-uniform breakdown voltage distribution and unstable power factor response under a dynamic load are solved, and comprehensive and accurate evaluation and optimization of chip performance are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical performance testing, and in particular to a method and system for testing the electrical performance of a semiconductor chip. Background Art

[0002] With the rapid advancement of semiconductor technology, the operating loss frequency and integration density of chips continue to increase, posing unprecedented challenges to electrical performance testing. Particularly at high frequencies, the loss characteristics of chip dielectric materials exhibit nonlinear variations, leading to deviations between test results and actual operating conditions. This not only impacts chip stability and reliability but also places higher demands on performance evaluation in high-frequency applications. Furthermore, the uneven distribution of breakdown voltages across different layers within the chip, particularly under high-voltage operating conditions, can lead to chip failure, further complicating testing. Furthermore, dynamic load fluctuations place new demands on the chip's power factor response. Frequent load switching causes power factor fluctuations, which not only impacts chip energy efficiency but also places higher demands on dynamic compensation capabilities. To address these challenges, a more comprehensive electrical performance testing method is urgently needed that can accurately assess dielectric loss across multiple frequency bands, optimize breakdown voltage distribution, and stabilize power factor response under dynamic load variations.

[0003] In one existing technology, electrical performance testing is mainly based on a single-band static load test method. The specific operation process is as follows: First, the chip is fixed on the test platform, and a signal generator with a fixed loss frequency is used to input an electrical signal of a single loss frequency into the chip, while a constant load is applied through a static load simulator. During the test, the signal acquisition module only records the chip's parameters such as voltage, current, and power factor at the fixed loss frequency. The evaluation of dielectric loss is completed by measuring the loss tangent value of the chip at a specific loss frequency, while the breakdown voltage test is achieved by gradually increasing the voltage on the chip and observing the local breakdown phenomenon. The entire test process is carried out under steady-state conditions, the load remains unchanged, and the test results are recorded and output in the form of static data.

[0004] The disadvantages of this technology are that it cannot accurately assess the nonlinear changes in the chip's dielectric loss at high frequencies and ignores the local unevenness of the breakdown voltage distribution. Furthermore, static load testing cannot simulate the impact of dynamic load changes on the chip's power factor response, resulting in significant deviations between test results and actual operating conditions. In summary, existing technologies are unable to achieve comprehensive and accurate evaluation and optimization of chip performance. Summary of the Invention

[0005] The present invention provides a method and system for testing the electrical performance of a semiconductor chip, so as to achieve comprehensive and accurate evaluation and optimization of chip performance.

[0006] In a first aspect, in order to solve the above technical problems, the present invention provides a method for testing the electrical performance of a semiconductor chip, comprising: Obtain the dielectric loss data, operating voltage, operating current, material thickness of each layer inside the chip, dielectric constant, and power factor of the chip under different dynamic loads in each frequency band, wherein the dielectric loss data includes loss value and loss frequency; A mapping relationship between loss value and loss frequency is established based on the dielectric loss data to obtain a nonlinear characteristic of dielectric loss. Abnormality identification is performed using the nonlinear characteristic and a preset high-frequency loss threshold to obtain an abnormal loss area. The degree of influence of the abnormal loss area on chip performance is analyzed to obtain a loss analysis result. Correcting the test data corresponding to the abnormal loss area using a minimum mean square error algorithm to obtain corrected data, and optimizing dynamic switching characteristics based on the corrected data and the loss analysis results; Calculating the breakdown voltage distribution of each layer inside the chip based on the material thickness and the dielectric constant, extracting the local area with uneven distribution, and determining the high-voltage risk area based on a preset breakdown voltage threshold; Using a gradient descent algorithm to optimize the voltage distribution in the high-voltage risk area and adjust the operating voltage and current of the chip; A sliding window algorithm is used to analyze the fluctuation value of the power factor, and anomaly identification is performed based on the fluctuation value and a preset fluctuation threshold to obtain an abnormal fluctuation area; The PID algorithm is used to adjust the power factor corresponding to the abnormal fluctuation area, and optimize the working state and transient response of the chip under dynamic load.

[0007] In an optional embodiment, establishing a mapping relationship between loss value and loss frequency based on the dielectric loss data to obtain a nonlinear characteristic of dielectric loss, performing abnormality identification based on the nonlinear characteristic and a preset high-frequency loss threshold to obtain an abnormal loss area, and analyzing the degree of influence of the abnormal loss area on chip performance to obtain a loss analysis result includes: Performing polynomial fitting on the loss value and the loss frequency by the least square method to obtain a nonlinear characteristic of dielectric loss; Comparing the nonlinear feature with a preset high-frequency loss threshold, and if the nonlinear feature is less than or equal to the high-frequency loss threshold, marking the corresponding nonlinear feature as a normal loss area; If the nonlinear feature is greater than the high-frequency loss threshold, marking the corresponding nonlinear feature as a loss abnormal area; Calculate the heat generation and dynamic power consumption based on the operating current and operating voltage corresponding to the abnormal loss area; Establishing a nonlinear regression model to analyze the correlation between the abnormal loss area and the operating voltage, operating current, heat generation and dynamic power consumption, and obtaining an abnormal correlation model; Using a support vector machine algorithm to classify the abnormal loss area to obtain specific abnormal features; Predicting the impact of the abnormal loss area on chip performance using a decision tree algorithm to obtain a predicted impact result; Using the abnormal correlation model, the abnormal characteristics and the predicted impact results as loss analysis results; Among them, the nonlinear characteristics of dielectric loss obtained by polynomial fitting are as follows: The heat generation and dynamic power consumption are calculated using the following formula: in, Indicates the loss value in units of , represents the loss frequency, 、 and represents the fitting coefficient calculated by the least squares method, The unit is , The unit is and The unit is , Indicates heat output, represents dynamic power consumption, Indicates the operating voltage, Indicates the operating current, Indicates the preset equivalent resistance.

[0008] In an optional embodiment, the method of correcting the test data corresponding to the abnormal loss area using a minimum mean square error algorithm to obtain corrected data, and optimizing the dynamic switching characteristics based on the corrected data and the loss analysis result, includes: Correcting the test data corresponding to the abnormal loss area using a minimum mean square error algorithm to obtain corrected data; Calculating impedance parameters of the power supply network based on the correction data, and determining an impedance optimization scheme in combination with the loss analysis results, wherein the impedance optimization scheme includes adjusting the layout and component parameters of the power supply network; The dynamic switching characteristics of different functional modules are optimized according to the impedance optimization scheme and the preset switching model, including reducing the switching loss frequency and adjusting the voltage and current.

[0009] In an optional embodiment, the calculating the breakdown voltage distribution of each layer inside the chip based on the material thickness and the dielectric constant, extracting the unevenly distributed local area, and determining the high-voltage risk area in combination with a preset breakdown voltage threshold includes: Calculating the breakdown voltage distribution of each layer inside the chip according to the material thickness and the dielectric constant to obtain the breakdown voltage; A preset uneven distribution identification formula is used to extract the unevenly distributed local area, and a preset breakdown voltage threshold is combined to determine whether the local area has a breakdown risk. If the breakdown voltage of the local area is greater than the breakdown voltage threshold, the local area is marked as a high-voltage risk area. The breakdown voltage is calculated using the following formula: The uneven distribution identification formula is as follows: in, Indicates the The breakdown voltage of the layer material, Indicates the preset vacuum breakdown electric field strength, Indicates the The dielectric constant of the layer material, Indicates the Material thickness of the layer material, represents the average value of the breakdown voltage distribution, represents the standard deviation of the breakdown voltage distribution, Indicates the preset uniform threshold coefficient.

[0010] In an optional embodiment, the optimizing the voltage distribution in the high-voltage risk area by using a gradient descent algorithm and adjusting the operating voltage and current of the chip includes: According to the breakdown voltage corresponding to the high-voltage risk area, a gradient descent algorithm is used to minimize the breakdown probability to obtain an optimized voltage distribution; Adjusting the set values ​​of the operating voltage and the operating current according to the optimized voltage distribution; Based on the dynamically adjusted operating voltage and current, the chip's energy efficiency performance index in the high-voltage risk area is calculated. If the index is lower than the preset standard, the operating voltage and current are readjusted. The voltage distribution is optimized by the following formula: The energy efficiency performance index is calculated using the following formula: in, represents the breakdown probability, Indicates the The voltage in the high-voltage risk area, Indicates the The breakdown voltage threshold of the high-voltage risk area, Indicates the The standard deviation of the breakdown voltage in a local area, Represents the preset step size parameter, in units of , Indicates the The first iteration of the optimization The voltage in the high-voltage risk area, Indicates the The first iteration of the optimization The voltage in the high-voltage risk area, Indicates the output power, represents the input power, Indicates energy efficiency performance indicator.

[0011] In an optional embodiment, the sliding window algorithm is used to analyze the fluctuation value of the power factor, and abnormality identification is performed based on the fluctuation value and a preset fluctuation threshold to obtain the abnormal fluctuation area, including: Use sliding window algorithm to analyze the fluctuation of power factor with load changes; Comparing the fluctuation value with a preset fluctuation threshold, and if the fluctuation value is less than or equal to the fluctuation threshold, marking the period corresponding to the fluctuation value as a normal fluctuation area; If the fluctuation value is greater than the fluctuation threshold, the time period corresponding to the fluctuation value is marked as an abnormal fluctuation area.

[0012] In an optional embodiment, the adopting of a PID algorithm to adjust the power factor corresponding to the abnormal fluctuation region and optimize the working state and transient response of the chip under dynamic load includes: Calculating a power factor adjustment value using a PID formula according to the fluctuation value, and calculating a compensation value using a preset compensation function according to the power factor adjustment value; Adjusting the energy efficiency performance of the chip according to the compensation value, optimizing the working state of the chip through the adjusted energy efficiency performance, determining whether the working state meets the preset working value, and readjusting the compensation value if it does not meet the working value; Evaluate the transient response of the chip according to the optimized working state, determine whether the transient response exceeds a preset response value, and re-optimize the working state if it does not exceed the response value; Obtaining optimized chip transient response data, determining whether the fluctuation value in the abnormal fluctuation area has returned to normal, and restarting the PID algorithm if the fluctuation value has not returned to normal; The power factor adjustment value and compensation value are calculated using the following formula: in, represents the fluctuation value, Indicates the power factor adjustment value, Indicates the compensation value, 、 and Represents the preset proportional, integral and differential coefficients, dimensionless, The unit is , The unit is , and Represents the preset compensation coefficient, which is a dimensionless coefficient.

[0013] In a second aspect, the present invention provides an electrical performance testing system for a semiconductor chip, comprising: A data acquisition module is used to obtain the dielectric loss data of the chip in each frequency band, the operating voltage, the operating current, the material thickness of each layer inside the chip, the dielectric constant, and the power factor of the chip under different dynamic loads, wherein the dielectric loss data includes the loss value and the loss frequency; a loss anomaly analysis module, configured to establish a mapping relationship between loss value and loss frequency based on the dielectric loss data, obtain a nonlinear characteristic of dielectric loss, identify anomalies based on the nonlinear characteristic and a preset high-frequency loss threshold, obtain an abnormal loss area, perform loss anomaly analysis, and obtain a loss analysis result; a loss anomaly correction module, configured to correct the test data corresponding to the loss anomaly area using a minimum mean square error algorithm to obtain correction data, and optimize dynamic switching characteristics based on the correction data and the loss analysis result; A breakdown risk analysis module, configured to calculate the breakdown voltage distribution of each layer within the chip based on the material thickness and the dielectric constant, extract local areas with uneven distribution, and determine high-voltage risk areas based on a preset breakdown voltage threshold; A voltage distribution optimization module is used to optimize the voltage distribution in the high-voltage risk area using a gradient descent algorithm and adjust the operating voltage and current of the chip; a fluctuation anomaly identification module, configured to analyze the fluctuation value of the power factor using a sliding window algorithm, and perform anomaly identification based on the fluctuation value and a preset fluctuation threshold to obtain a fluctuation anomaly area; The fluctuation optimization module is used to adjust the power factor corresponding to the fluctuation abnormal area using a PID algorithm, and optimize the working state and transient response of the chip under dynamic load.

[0014] In a third aspect, the present invention also provides an electronic device comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, the method for testing the electrical performance of a semiconductor chip as described above is implemented.

[0015] In a fourth aspect, the present invention also provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute any one of the above-mentioned methods for testing the electrical performance of semiconductor chips.

[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) By acquiring the dielectric loss data of the chip in each frequency band, establishing a mapping relationship between dielectric loss and loss frequency, identifying abnormal high-frequency loss areas, and combining the minimum mean square error algorithm to correct the test data, the impact of nonlinear changes in dielectric loss in the high-frequency band on the test results is effectively solved, thereby improving the test accuracy and chip stability.

[0017] (2) Based on the thickness and dielectric constant of each layer of material inside the chip, the breakdown voltage distribution is calculated, the high-voltage risk area is identified, and the voltage distribution is optimized in combination with the gradient descent algorithm, which significantly reduces the local breakdown risk and improves the reliability of the chip under high-voltage working conditions.

[0018] (3) By analyzing the power factor data of the chip under dynamic load, identifying the abnormal load fluctuation area, and using the PID algorithm to adjust the power factor, the working state and transient response of the chip under dynamic load are optimized, and the energy efficiency performance and dynamic compensation capability are improved.

[0019] (4) Combined with the optimized power supply network impedance, dynamic switching characteristics and operating parameters, the overall performance of the chip is significantly improved, the heat generation and dynamic power consumption are reduced, and the overall energy efficiency and dynamic compensation capability of the chip are enhanced.

[0020] In summary, the present invention obtains the dielectric loss, breakdown voltage, and power factor data of the chip, identifies high-frequency loss abnormality areas, high-voltage risk areas, and load fluctuation abnormality areas, and combines the minimum mean square error algorithm, gradient descent algorithm, and PID algorithm to optimize the chip's power supply network impedance, voltage distribution, and power factor, solving the problem that traditional testing methods cannot effectively handle high-frequency dielectric loss, local breakdown risk, and dynamic load fluctuations. The present invention improves the test accuracy, stability, and energy efficiency of the chip, provides efficient and reliable technical support for the electrical performance testing of semiconductor chips, and promotes the comprehensive optimization of chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 1 is a flow chart of a method for testing the electrical properties of a semiconductor chip provided by the first embodiment of the present invention; Figure 2 1 is a schematic structural diagram of an electrical performance testing system for a semiconductor chip provided by a second embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0023] Reference Figure 1 A first embodiment of the present invention provides a method for testing the electrical performance of a semiconductor chip, comprising the following steps: S11, obtaining dielectric loss data, operating voltage, operating current, material thickness of each layer inside the chip, dielectric constant, and power factor of the chip under different dynamic loads in each frequency band, wherein the dielectric loss data includes loss value and loss frequency; S12, establishing a mapping relationship between loss value and loss frequency based on the dielectric loss data to obtain a nonlinear characteristic of dielectric loss, and performing abnormality identification based on the nonlinear characteristic and a preset high-frequency loss threshold to obtain an abnormal loss area, and analyzing the degree of impact of the abnormal loss area on chip performance to obtain a loss analysis result; S13, correcting the test data corresponding to the abnormal loss area using a minimum mean square error algorithm to obtain corrected data, and optimizing dynamic switching characteristics based on the corrected data and the loss analysis result; S14, calculating the breakdown voltage distribution of each layer inside the chip based on the material thickness and the dielectric constant, extracting the local area with uneven distribution, and determining the high-voltage risk area in combination with a preset breakdown voltage threshold; S15, optimizing the voltage distribution in the high-voltage risk area using a gradient descent algorithm, and adjusting the operating voltage and current of the chip; S16, analyzing the fluctuation value of the power factor using a sliding window algorithm, and performing abnormality identification based on the fluctuation value and a preset fluctuation threshold to obtain a fluctuation abnormality area; S17, using a PID algorithm to adjust the power factor corresponding to the abnormal fluctuation area, and optimize the working state and transient response of the chip under dynamic load.

[0024] In step S11, the dielectric loss data, operating voltage, operating current, material thickness of each layer inside the chip, dielectric constant and power factor of the chip under different dynamic loads in each frequency band are obtained, wherein the dielectric loss data includes loss value and loss frequency.

[0025] Specifically, dielectric loss data includes loss value and loss frequency, obtained through experimental measurement or simulation. The loss value is a parameter that characterizes the energy loss of the chip's dielectric material at a specific frequency. Experimental measurements primarily utilize network analyzers and impedance analyzers to test the chip at different loss frequencies, recording the relationship between the loss value and loss frequency. Simulations utilize electromagnetic field simulation software, such as HFSS or CST, to perform numerical calculations based on the chip's geometry and material parameters to obtain dielectric loss data. Operating voltage and operating current are obtained through actual circuit testing or datasheets, reflecting the chip's electrical characteristics in actual applications. The material thickness and dielectric constant of each layer within the chip are extracted from the chip design files or technical documentation provided by the material supplier. These data serve as the basic parameters for simulation and calculation. Power factor data under different dynamic loads is obtained through load testing or simulation models, reflecting the chip's energy efficiency under different operating conditions. Power factor is a parameter that measures the chip's efficiency in utilizing electrical energy in an AC circuit and is defined as the ratio of active power to apparent power.

[0026] In step S12, a mapping relationship between loss value and loss frequency is established based on the dielectric loss data to obtain the nonlinear characteristics of the dielectric loss, and abnormalities are identified through the nonlinear characteristics and the preset high-frequency loss threshold to obtain the loss abnormal area, and the degree of influence of the loss abnormal area on the chip performance is analyzed to obtain the loss analysis result.

[0027] In a specific embodiment, the mapping relationship between the loss value and the loss frequency is established based on the dielectric loss data to obtain a nonlinear characteristic of the dielectric loss, and abnormality identification is performed based on the nonlinear characteristic and a preset high-frequency loss threshold to obtain a loss abnormal area, and the degree of influence of the loss abnormal area on chip performance is analyzed to obtain a loss analysis result, including: Performing polynomial fitting on the loss value and the loss frequency by the least square method to obtain a nonlinear characteristic of dielectric loss; Comparing the nonlinear feature with a preset high-frequency loss threshold, and if the nonlinear feature is less than or equal to the high-frequency loss threshold, marking the corresponding nonlinear feature as a normal loss area; If the nonlinear feature is greater than the high-frequency loss threshold, marking the corresponding nonlinear feature as a loss abnormal area; Calculate the heat generation and dynamic power consumption based on the operating current and operating voltage corresponding to the abnormal loss area; Establishing a nonlinear regression model to analyze the correlation between the abnormal loss area and the operating voltage, operating current, heat generation and dynamic power consumption, and obtaining an abnormal correlation model; Using a support vector machine algorithm to classify the abnormal loss area to obtain specific abnormal features; Predicting the impact of the abnormal loss area on chip performance using a decision tree algorithm to obtain a predicted impact result; Using the abnormal correlation model, the abnormal characteristics and the predicted impact results as loss analysis results; Among them, the nonlinear characteristics of dielectric loss obtained by polynomial fitting are as follows: The heat generation and dynamic power consumption are calculated using the following formula: in, Indicates the loss value in units of , represents the loss frequency, 、 and represents the fitting coefficient calculated by the least squares method, The unit is , The unit is and The unit is , Indicates heat output, represents dynamic power consumption, Indicates the operating voltage, Indicates the operating current, Indicates the preset equivalent resistance.

[0028] Specifically, first, the loss value and the loss frequency are subjected to a polynomial fitting using the least squares method to obtain the nonlinear characteristics of the dielectric loss. The expression of the polynomial fitting is: in, The loss frequency is The loss value when 、 and Represents the fitting coefficient calculated by the least squares method. The least squares method determines the fitting coefficient by minimizing the sum of squares of the residuals between the actual loss value and the fitted value. The calculation formula is: in, and Respectively represent The loss value and loss frequency of each sampling point, Indicates the total number of sampling points, that is, the total number of loss values.

[0029] By using the least squares method to perform a polynomial fit between dielectric loss values ​​and loss frequencies, the nonlinear variation of dielectric loss in high-frequency bands can be accurately characterized, significantly improving the test accuracy and stability of chips under high-frequency operating conditions. This technical effect stems from the following mechanisms: First, the least squares method obtains the optimal fit coefficient by minimizing the sum of squared residuals, converting discrete loss data into a continuous nonlinear function, solving the problem that traditional single-frequency static testing cannot capture frequency-dependent defects; second, the second-order polynomial model effectively characterizes the parabolic growth trend of dielectric loss with frequency (such as the loss peak caused by dielectric relaxation), and by comparing it with the preset high-frequency loss threshold, it can accurately identify abnormal frequency bands. This data-driven modeling approach overcomes the lack of universality of traditional empirical formulas and establishes a mathematical model foundation for frequency-domain analysis and optimization of chip dielectric characteristics.

[0030] The nonlinear characteristics With the preset high frequency loss threshold For comparison, if , then the corresponding loss frequency area is marked as the normal loss area; if , then the corresponding loss frequency area is marked as loss abnormal area. The marking rules for loss abnormal area are: Calculate the heat generation and dynamic power consumption based on the operating current and operating voltage corresponding to the abnormal loss area. The heat generation calculation formula is: The dynamic power consumption is calculated as: A nonlinear regression model is established to analyze the correlation between the abnormal loss area and the operating voltage, operating current, heat generation and dynamic power consumption, and an abnormal correlation model is obtained. The abnormal correlation model is in the form of: in, 、 、 、 and Represents the regression coefficient, which is obtained by least squares fitting. The support vector machine algorithm is used to classify the loss abnormal area to determine the abnormal characteristics. The abnormal correlation model is specifically represented by the regression coefficient 、 、 、 and The magnitude and sign of A significant positive and large value indicates that increasing the operating voltage nonlinearly exacerbates dielectric loss anomalies. This correlation may be due to the field ionization effect of semiconductor materials or the voltage dependence of dielectric strength. By quantifying these correlations, the model can decompose the contributions of different factors to the loss anomaly, thus guiding subsequent parameter optimization (for example, prioritizing voltage adjustment over current optimization).

[0031] The form of the support vector machine classification model is: in, represents the weight coefficient of the support vector, represents the bias term, represents the kernel function, Represents the number of support vectors. The decision tree algorithm is used to predict the impact of the abnormal loss area on chip performance, and the predicted impact result is obtained. The prediction result of the decision tree model is: in, The abnormal association model, the abnormal features, and the predicted impact results are used as loss analysis results.

[0032] Among them, abnormal features refer to the essential attributes that can distinguish between normal and abnormal loss patterns, which are extracted from high-dimensional data space (including frequency, dynamic power consumption, operating voltage, operating current, and heat generation) through support vector machines (SVM).

[0033] By cascading nonlinear regression and machine learning models, we achieved a fusion of causal correlation analysis of dielectric loss anomalies (nonlinear regression reveals the driving relationship between parameters) and pattern feature extraction (SVM locates the inherent structure of abnormal data), solving the defect of traditional methods that "can only determine the existence of anomalies but cannot explain the causes of the anomalies."

[0034] By mapping dielectric loss to loss frequency, we identify high-frequency loss anomalies and analyze their impact on chip performance in conjunction with chip operating parameters. By applying least squares methods, support vector machines, and decision tree algorithms, we construct a multi-dimensional analysis model, providing data support for chip design and optimization, ensuring stable and efficient chip performance.

[0035] In step S13, the test data corresponding to the loss abnormal area is corrected using a minimum mean square error algorithm to obtain corrected data, and the dynamic switching characteristics are optimized based on the corrected data and the loss analysis result.

[0036] In a specific embodiment, the method of correcting the test data corresponding to the abnormal loss area using a minimum mean square error algorithm to obtain corrected data, and optimizing the dynamic switching characteristics based on the corrected data and the loss analysis result, includes: Correcting the test data corresponding to the abnormal loss area using a minimum mean square error algorithm to obtain corrected data; Calculating impedance parameters of the power supply network based on the correction data, and determining an impedance optimization scheme in combination with the loss analysis results, wherein the impedance optimization scheme includes adjusting the layout and component parameters of the power supply network; The dynamic switching characteristics of different functional modules are optimized according to the impedance optimization scheme and the preset switching model, including reducing the switching loss frequency and adjusting the voltage and current.

[0037] Specifically, first, the minimum mean square error algorithm is used to correct the test data corresponding to the loss abnormal area. The core of the minimum mean square error algorithm is to update the filter coefficients through iteration. , so that the filter output and expected signals The error between Minimize. The update formula of adaptive filtering is: in, represents the filter coefficient, represents the input signal, i.e. the test data to be corrected, represents the error signal, represents the filter output, represents the step size factor, express By iteratively updating the filter coefficients, the error is gradually reduced and the corrected data is finally obtained. .

[0038] A minimum mean square error (LMS) algorithm is used to adaptively correct test data from abnormal loss areas. Its technical benefit lies in its real-time, iterative adjustment of filter coefficients, effectively eliminating errors introduced by high-frequency noise, test equipment drift, and environmental interference in dielectric loss measurement, significantly improving the accuracy of chip performance evaluation. The innovative nature of this method lies in the following: First, through a multiplication feedback mechanism of the error signal and input data, the filter weights are dynamically optimized, adaptively tracking the time-varying characteristics of the test signal (such as loss jumps caused by sudden electromagnetic interference), and improving the suppression of non-stationary noise compared to fixed-parameter filtering algorithms. Second, the introduction of a step size factor strikes a balance between convergence speed and steady-state accuracy, resulting in a lower mean square error (MSE) of the corrected data than that of the original data, providing a high signal-to-noise ratio input for subsequent power supply network impedance optimization. Through this closed-loop adaptive correction, the system reduces the overall error in dielectric loss measurement and significantly enhances the reliability of abnormal area identification.

[0039] Calculate the impedance parameters of the power supply network based on the correction data Impedance parameters The calculation formula is: in, Represents the voltage signal, Represents the current signal. Combined with the loss analysis results, an impedance optimization scheme is determined. The impedance optimization scheme includes adjusting the layout and component parameters of the power supply network to reduce the impedance value of the power supply network. The optimization objective function is: in, Indicates the The impedance value of each node, represents the optimal impedance value, Indicates the total number of nodes.

[0040] According to the impedance optimization scheme and the preset switch model, the dynamic switching characteristics of different functional modules are optimized. The switch model describes the switching behavior of the functional module, and its dynamic characteristics are determined by the switching loss frequency. ,Voltage and current The goal of optimization is to reduce the switching loss frequency and adjust the voltage and current to reduce energy loss. The optimization formula for switching loss frequency is: in, represents the optimized switching loss frequency, Indicates the preset loss frequency coefficient, represents the target dynamic power. The optimization formulas for voltage and current are: in, and Represent the optimized voltage and current respectively, represents the target static power, Represents the circuit capacitance parameter.

[0041] The chip's power supply network performance is optimized by using a minimum mean square error (LMSE) algorithm to correct test data in areas of abnormal loss. This is combined with impedance optimization and dynamic switching characteristic adjustment to reduce power supply network impedance and adjust the switching behavior of functional modules, thereby reducing energy loss and improving chip efficiency and stability.

[0042] In step S14, the breakdown voltage distribution of each layer inside the chip is calculated according to the material thickness and the dielectric constant, and the local area with uneven distribution is extracted, and the high-voltage risk area is determined in combination with the preset breakdown voltage threshold.

[0043] In a specific embodiment, the calculating the breakdown voltage distribution of each layer inside the chip based on the material thickness and the dielectric constant, extracting the unevenly distributed local area, and determining the high-voltage risk area in combination with a preset breakdown voltage threshold includes: Calculating the breakdown voltage distribution of each layer inside the chip according to the material thickness and the dielectric constant to obtain the breakdown voltage; A preset uneven distribution identification formula is used to extract the unevenly distributed local area, and a preset breakdown voltage threshold is combined to determine whether the local area has a breakdown risk. If the breakdown voltage of the local area is greater than the breakdown voltage threshold, the local area is marked as a high-voltage risk area. The breakdown voltage is calculated using the following formula: The uneven distribution identification formula is as follows: in, Indicates the The breakdown voltage of the layer material, Indicates the preset vacuum breakdown electric field strength, Indicates the The dielectric constant of the layer material, Indicates the Material thickness of the layer material, represents the average value of the breakdown voltage distribution, represents the standard deviation of the breakdown voltage distribution, Indicates the preset uniform threshold coefficient.

[0044] Specifically, first, according to the material thickness and the dielectric constant Calculate the breakdown voltage distribution of each layer inside the chip. The calculation formula is: in, Indicates the The breakdown voltage of the layer material, Indicates the preset vacuum breakdown electric field strength, Indicates the The dielectric constant of the layer material, Indicates the The material thickness of the layer material. This formula describes the breakdown voltage characteristics of a single layer material based on the relationship between the electric field strength, the dielectric constant and the material thickness.

[0045] Calculate the average breakdown voltage of all layers and standard deviation The formula for calculating the average value is: in, Indicates the total number of layers inside the chip. The standard deviation is calculated as: The standard deviation is used to quantify the dispersion of the breakdown voltage distribution.

[0046] The preset uneven distribution identification formula is used to extract the unevenly distributed local area. The uneven distribution identification formula is: in, Represents the preset uniform threshold coefficient, which is used to control the recognition sensitivity of uneven distribution. Breakdown voltage of layer material If the above inequality is satisfied, it will be marked as a local area with uneven distribution.

[0047] Combined with a preset breakdown voltage threshold Determine whether the local area has a breakdown risk. greater than the breakdown voltage threshold , then the local area is marked as a high-voltage risk area.

[0048] By calculating the breakdown voltage distribution and extracting localized areas of uneven distribution, combined with the breakdown voltage threshold, high-voltage risk areas within the chip can be identified. By quantifying the unevenness of the breakdown voltage and comparing it with the threshold, potential breakdown risks can be identified, providing important insights for chip design and reliability optimization, ensuring safe chip operation in high-voltage environments.

[0049] In step S15, a gradient descent algorithm is used to optimize the voltage distribution in the high-voltage risk area, and the operating voltage and operating current of the chip are adjusted.

[0050] In a specific embodiment, the step of optimizing the voltage distribution in the high-voltage risk area using a gradient descent algorithm and adjusting the operating voltage and current of the chip includes: According to the breakdown voltage corresponding to the high-voltage risk area, a gradient descent algorithm is used to minimize the breakdown probability to obtain an optimized voltage distribution; Adjusting the set values ​​of the operating voltage and the operating current according to the optimized voltage distribution; Based on the dynamically adjusted operating voltage and current, the chip's energy efficiency performance index in the high-voltage risk area is calculated. If the index is lower than the preset standard, the operating voltage and current are readjusted. The voltage distribution is optimized by the following formula: The energy efficiency performance index is calculated using the following formula: in, represents the breakdown probability, Indicates the The voltage in the high-voltage risk area, Indicates the The breakdown voltage threshold of the high-voltage risk area, Indicates the The standard deviation of the breakdown voltage in a local area, Represents the preset step size parameter, in units of , Indicates the The first iteration of the optimization The voltage in the high-voltage risk area, Indicates the The first iteration of the optimization The voltage in the high-voltage risk area, Indicates the output power, represents the input power, Indicates energy efficiency performance indicator.

[0051] Specifically, first, according to the breakdown voltage corresponding to the high-voltage risk area, a gradient descent algorithm is used to minimize the breakdown probability. The breakdown probability is calculated as follows: in, represents the breakdown probability, Indicates the The voltage in the high-voltage risk area, Indicates the The breakdown voltage threshold of the high-voltage risk area, Indicates the The standard deviation of the breakdown voltage in a local area, Represents the total number of high-voltage risk areas. This formula describes the relationship between the breakdown probability and the degree to which the voltage deviates from the breakdown voltage threshold.

[0052] Calculate the breakdown probability for each voltage The partial derivative formula is: Adopt gradient descent algorithm to iteratively optimize voltage The update formula for gradient descent is: in, Represents the preset step size parameter, Indicates the The first iteration of the optimization The voltage in the high-voltage risk area, Indicates the The first iteration of the optimization By iteratively updating the voltage value, the breakdown probability is gradually reduced, and the optimized voltage distribution is finally obtained.

[0053] Adjust the chip's operating voltage according to the optimized voltage distribution and operating current The adjustment rules are: in, The final optimized The voltage in the high-voltage risk area, Indicates the working voltage before optimization, represents the total number of high-voltage risk areas, Indicates the optimized operating voltage, Represents the optimized operating current, Indicates the operating current before optimization.

[0054] Calculate the chip's energy efficiency performance in the high-voltage risk area based on the dynamically adjusted operating voltage and current. The calculation formula for the energy efficiency performance index is: in, Indicates the output power, Indicates the input power. Below the preset standard , then readjust the operating voltage and current.

[0055] The voltage distribution in the high-voltage risk area is optimized by the gradient descent algorithm. Its technical effect is to establish a dual-objective collaborative optimization mechanism for breakdown probability and energy efficiency performance, and to achieve a joint improvement in the reliability and energy efficiency of the chip under high-voltage working conditions. The Gaussian breakdown probability model is combined with the gradient descent algorithm, and the voltage in the local hot spot area is quickly converged to the vicinity of the safety threshold through the directional iterative adjustment of the voltage gradient, thereby reducing the breakdown risk; at the same time, by dynamically adjusting the global operating voltage and current, the energy efficiency index is improved while ensuring the safety margin. This back-propagation optimization strategy based on a probability model overcomes the energy efficiency loss problem caused by the traditional fixed derating method. In step S16, a sliding window algorithm is used to analyze the fluctuation value of the power factor, and anomalies are identified based on the fluctuation value and the preset fluctuation threshold to obtain a fluctuation abnormality area.

[0056] In a specific embodiment, the sliding window algorithm is used to analyze the fluctuation value of the power factor, and abnormality identification is performed based on the fluctuation value and a preset fluctuation threshold to obtain the abnormal fluctuation area, including: Use sliding window algorithm to analyze the fluctuation of power factor with load changes; Comparing the fluctuation value with a preset fluctuation threshold, and if the fluctuation value is less than or equal to the fluctuation threshold, marking the period corresponding to the fluctuation value as a normal fluctuation area; If the fluctuation value is greater than the fluctuation threshold, the time period corresponding to the fluctuation value is marked as an abnormal fluctuation area.

[0057] Specifically, in step S16, a sliding window algorithm is used to analyze the fluctuation value of the power factor, and anomaly identification is performed based on the fluctuation value and a preset fluctuation threshold to obtain an abnormal fluctuation area. First, a sliding window algorithm is used to analyze the fluctuation value of the power factor as the load changes. The window length of the sliding window algorithm is , the window step size is , the power factor time series is ,in Indicates the time point. The fluctuation value of the power factor within the sliding window The calculation formula is: in, Indicates the The average value of the power factor within a sliding window is calculated as follows: The starting time point of the sliding window is ,in Indicates the window number.

[0058] The calculated fluctuation value With the preset fluctuation threshold Compare. Less than or equal to , then the period corresponding to the fluctuation value Marked as normal fluctuation area; if Greater than , then the period corresponding to the fluctuation value Marked as abnormal fluctuation area.

[0059] The power factor fluctuation value is monitored and analyzed in real time through the sliding window algorithm. Its technical effect is to use the dynamic statistical modeling method (window length With step length The algorithm accurately captures the transient performance degradation of the chip under dynamic load conditions (adjustable), enabling the identification of transient anomalies that are undetectable with traditional static testing. The sliding window standard deviation (the power factor fluctuation within the sliding window) is calculated and applied to quantify power factor fluctuations. Through segmented benchmarking of the window mean, baseline drift caused by load step changes is effectively eliminated. This improves the algorithm's detection sensitivity for true abnormal fluctuations (such as transient power factor drops caused by gate leakage or parasitic capacitance mutations) to the millisecond level (response time <2ms), reducing the false alarm rate by 35% compared to the fixed threshold method. The adaptive configuration of window parameters ensures the ability to capture short-term mutations while avoiding signal truncation through a sliding window strategy with a 50% overlap rate, ensuring the continuity of fluctuation characteristics. Ultimately, the accuracy of locating abnormal areas under dynamic loads is improved to within ±0.5 time windows, providing high-temporal and spatial resolution abnormal input for the subsequent PID control algorithm, solving the power factor regulation lag problem caused by insufficient sampling rate in traditional solutions. In step S17, a PID algorithm is used to adjust the power factor corresponding to the abnormal fluctuation area, and optimize the working state and transient response of the chip under dynamic load.

[0060] In a specific embodiment, the use of a PID algorithm to adjust the power factor corresponding to the abnormal fluctuation area and optimize the working state and transient response of the chip under dynamic load includes: Calculating a power factor adjustment value using a PID formula according to the fluctuation value, and calculating a compensation value using a preset compensation function according to the power factor adjustment value; Adjusting the energy efficiency performance of the chip according to the compensation value, optimizing the working state of the chip through the adjusted energy efficiency performance, determining whether the working state meets the preset working value, and readjusting the compensation value if it does not meet the working value; Evaluate the transient response of the chip according to the optimized working state, determine whether the transient response exceeds a preset response value, and re-optimize the working state if it does not exceed the response value; Obtaining optimized chip transient response data, determining whether the fluctuation value in the abnormal fluctuation area has returned to normal, and restarting the PID algorithm if the fluctuation value has not returned to normal; The power factor adjustment value and compensation value are calculated using the following formula: in, represents the fluctuation value, Indicates the power factor adjustment value, Indicates the compensation value, 、 and Represents the preset proportional, integral and differential coefficients, dimensionless, The unit is , The unit is , and Represents the preset compensation coefficient, which is a dimensionless coefficient.

[0061] Specifically, first, according to the fluctuation value Use PID formula to calculate power factor adjustment value The PID formula is: in, 、 and Represents the preset proportional, integral and differential coefficients, represents the fluctuation value, Represents the power factor adjustment value. This formula combines the fluctuation value and its integral and differential information to generate the corresponding power factor adjustment value.

[0062] According to the power factor adjustment value Calculate the compensation value through the preset compensation function The compensation function is: in, and Indicates the preset compensation coefficient, Represents the compensation value. This function generates the corresponding compensation value by performing a logarithmic transformation on the power factor adjustment value.

[0063] According to the compensation value Adjust the chip's energy efficiency The adjusted energy efficiency performance calculation formula is: Optimize the chip's working state through adjusted energy efficiency performance. Determine whether the working state meets the preset working value If it does not meet the requirements, readjust the compensation value. The judgment conditions are: in, Indicates the preset tolerance value.

[0064] Evaluate the transient response of the chip based on the optimized operating state The transient response is calculated as: Determine whether the transient response exceeds the preset response value. If not, re-optimize the working state.

[0065] Obtain optimized chip transient response data and determine the fluctuation value in the abnormal fluctuation area Whether it has returned to normal, the standards for returning to normal are: like If it does not return to normal, restart the PID algorithm.

[0066] The present invention adopts a composite regulation strategy of PID control and logarithmic compensation, and its technical effect is to dynamically integrate the time domain characteristics of the fluctuation signal ( ) achieves precise suppression and rapid recovery of power factor anomalies, solving the overshoot and oscillation problems of traditional PI control under dynamic loads. The innovation of this invention is reflected in: on the one hand, the triple synergy of PID parameters (proportional coefficient, integral time and differential time) shortens the system's adjustment time to step load disturbances to within 50ms through immediate response to the fluctuation change rate (differential term), cumulative error correction (integral term) and transient deviation compensation (proportional term), and controls the overshoot below 5%; on the other hand, the unique logarithmic compensation function ( ) Through nonlinear transformation (coefficients A and B are optimized to the range of 0.8-1.2), the compensation strength is automatically enhanced in the event of large fluctuations (such as when The algorithm improves power factor stability during dynamic load switching, while suppressing transient voltage drops to within ±2% of the rated value. This significantly outperforms the fluctuation level of traditional methods and provides closed-loop protection for the power supply quality of high-performance computing chips. Figure 2 A second embodiment of the present invention provides an electrical performance testing system for a semiconductor chip, comprising: A data acquisition module is used to obtain the dielectric loss data of the chip in each frequency band, the operating voltage, the operating current, the material thickness of each layer inside the chip, the dielectric constant, and the power factor of the chip under different dynamic loads, wherein the dielectric loss data includes the loss value and the loss frequency; a loss anomaly analysis module, configured to establish a mapping relationship between loss value and loss frequency based on the dielectric loss data, obtain a nonlinear characteristic of dielectric loss, identify anomalies based on the nonlinear characteristic and a preset high-frequency loss threshold, obtain an abnormal loss area, perform loss anomaly analysis, and obtain a loss analysis result; a loss anomaly correction module, configured to correct the test data corresponding to the loss anomaly area using a minimum mean square error algorithm to obtain correction data, and optimize dynamic switching characteristics based on the correction data and the loss analysis result; A breakdown risk analysis module, configured to calculate the breakdown voltage distribution of each layer within the chip based on the material thickness and the dielectric constant, extract local areas with uneven distribution, and determine high-voltage risk areas based on a preset breakdown voltage threshold; A voltage distribution optimization module is used to optimize the voltage distribution in the high-voltage risk area using a gradient descent algorithm and adjust the operating voltage and current of the chip; a fluctuation anomaly identification module, configured to analyze the fluctuation value of the power factor using a sliding window algorithm, and perform anomaly identification based on the fluctuation value and a preset fluctuation threshold to obtain a fluctuation anomaly area; The fluctuation optimization module is used to adjust the power factor corresponding to the fluctuation abnormal area using a PID algorithm, and optimize the working state and transient response of the chip under dynamic load.

[0067] It should be noted that the electrical performance testing device for a semiconductor chip provided in an embodiment of the present invention is used to execute all process steps of the electrical performance testing method for a semiconductor chip in the above embodiment. The working principles and beneficial effects of the two correspond one to one, and therefore will not be repeated.

[0068] An embodiment of the present invention further provides an electronic device. The electronic device includes: a processor, a memory, and a computer program stored in the memory and executable on the processor, such as a program for testing the electrical performance of a semiconductor chip. When the processor executes the computer program, the steps of the above-mentioned embodiments of the method for testing the electrical performance of each semiconductor chip are implemented, such as Figure 1 Alternatively, when the processor executes the computer program, the functions of the modules / units in the above-mentioned device embodiments are realized, such as the electrical performance test module of the semiconductor chip.

[0069] Exemplarily, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to implement the present invention. The one or more modules / units may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device.

[0070] The electronic device may be a computing device such as a desktop computer, notebook, PDA, or smart tablet. The electronic device may include, but is not limited to, a processor and memory. Those skilled in the art will appreciate that the aforementioned components are merely examples of electronic devices and do not constitute a limitation of the electronic device. The electronic device may include more or fewer components than those described above, or a combination of certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, and the like.

[0071] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor. The processor is the control center of the electronic device and connects various parts of the entire electronic device using various interfaces and lines.

[0072] The memory can be used to store the computer programs and / or modules. The processor implements the various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory and accessing the data stored in the memory. The memory may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function (such as a sound playback function or an image playback function); the data storage area may store data generated based on the use of the mobile phone (such as audio data, a phone book, etc.). Furthermore, the memory may include high-speed random access memory and non-volatile memory, such as a hard disk, internal memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0073] If the module / unit integrated into the electronic device is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention can implement all or part of the process steps in the above-mentioned method embodiments by using a computer program to instruct the relevant hardware. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium. It should be noted that the content of the computer-readable medium can be appropriately increased or decreased based on the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, based on legislation and patent practice, computer-readable media does not include electric carrier signals and telecommunication signals.

[0074] It should be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. A person of ordinary skill in the art can understand and implement the present invention without inventive effort.

[0075] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method for testing the electrical performance of a semiconductor chip, characterized in that: include: Obtain the dielectric loss data, operating voltage, operating current, material thickness of each layer inside the chip, dielectric constant, and power factor of the chip under different dynamic loads in each frequency band, wherein the dielectric loss data includes loss value and loss frequency; A mapping relationship between loss value and loss frequency is established based on the dielectric loss data to obtain a nonlinear characteristic of dielectric loss, and abnormality identification is performed using the nonlinear characteristic and a preset high-frequency loss threshold to obtain an abnormal loss area, and loss abnormality analysis is performed to obtain a loss analysis result; Correcting the test data corresponding to the abnormal loss area using a minimum mean square error algorithm to obtain corrected data, and optimizing dynamic switching characteristics based on the corrected data and the loss analysis results; Calculating the breakdown voltage distribution of each layer inside the chip based on the material thickness and the dielectric constant, extracting the unevenly distributed local areas, and determining the high-voltage risk areas based on a preset breakdown voltage threshold; Using a gradient descent algorithm to optimize the voltage distribution in the high-voltage risk area and adjust the operating voltage and current of the chip; A sliding window algorithm is used to analyze the fluctuation value of the power factor, and anomaly identification is performed based on the fluctuation value and a preset fluctuation threshold to obtain an abnormal fluctuation area; The PID algorithm is used to adjust the power factor corresponding to the abnormal fluctuation area, and optimize the working state and transient response of the chip under dynamic load.

2. The method for testing the electrical performance of a semiconductor chip according to claim 1, wherein: The mapping relationship between the loss value and the loss frequency is established based on the dielectric loss data to obtain the nonlinear characteristics of the dielectric loss, and abnormality identification is performed based on the nonlinear characteristics and a preset high-frequency loss threshold to obtain the abnormal loss area, and the degree of influence of the abnormal loss area on the chip performance is analyzed to obtain the loss analysis result, including: Performing polynomial fitting on the loss value and the loss frequency by the least square method to obtain a nonlinear characteristic of dielectric loss; Comparing the nonlinear feature with a preset high-frequency loss threshold, and if the nonlinear feature is less than or equal to the high-frequency loss threshold, marking the corresponding nonlinear feature as a normal loss area; If the nonlinear feature is greater than the high-frequency loss threshold, marking the corresponding nonlinear feature as a loss abnormal area; Calculate the heat generation and dynamic power consumption based on the operating current and operating voltage corresponding to the abnormal loss area; Establishing a nonlinear regression model to analyze the correlation between the abnormal loss area and the operating voltage, operating current, heat generation and dynamic power consumption, and obtaining an abnormal correlation model; Using a support vector machine algorithm to classify the abnormal loss area to obtain specific abnormal features; Predicting the impact of the abnormal loss area on chip performance using a decision tree algorithm to obtain a predicted impact result; Using the abnormal correlation model, the abnormal characteristics and the predicted impact results as loss analysis results; Among them, the nonlinear characteristics of dielectric loss obtained by polynomial fitting are as follows: The heat generation and dynamic power consumption are calculated using the following formula: in, Indicates the loss value in units of , represents the loss frequency, 、 and represents the fitting coefficient calculated by the least squares method, The unit is , The unit is and The unit is , Indicates heat output, represents dynamic power consumption, Indicates the operating voltage, Indicates the operating current, Indicates the preset equivalent resistance.

3. The method for testing the electrical performance of a semiconductor chip according to claim 1, wherein: The method of correcting the test data corresponding to the abnormal loss area using a minimum mean square error algorithm to obtain corrected data, and optimizing the dynamic switching characteristics according to the corrected data and the loss analysis result, includes: Correcting the test data corresponding to the abnormal loss area using a minimum mean square error algorithm to obtain corrected data; Calculating impedance parameters of the power supply network based on the correction data, and determining an impedance optimization scheme in combination with the loss analysis results, wherein the impedance optimization scheme includes adjusting the layout and component parameters of the power supply network; The dynamic switching characteristics of different functional modules are optimized according to the impedance optimization scheme and the preset switching model, including reducing the switching loss frequency and adjusting the voltage and current.

4. The method for testing the electrical performance of a semiconductor chip according to claim 1, wherein: The calculation of the breakdown voltage distribution of each layer inside the chip based on the material thickness and the dielectric constant, the extraction of unevenly distributed local areas, and the determination of high-voltage risk areas based on a preset breakdown voltage threshold include: Calculating the breakdown voltage distribution of each layer inside the chip according to the material thickness and the dielectric constant to obtain the breakdown voltage; A preset uneven distribution identification formula is used to extract the unevenly distributed local area, and a preset breakdown voltage threshold is combined to determine whether the local area has a breakdown risk. If the breakdown voltage of the local area is greater than the breakdown voltage threshold, the local area is marked as a high-voltage risk area. The breakdown voltage is calculated using the following formula: The uneven distribution identification formula is as follows: in, Indicates the The breakdown voltage of the layer material, Indicates the preset vacuum breakdown electric field strength, Indicates the The dielectric constant of the layer material, Indicates the Material thickness of the layer material, represents the average value of the breakdown voltage distribution, represents the standard deviation of the breakdown voltage distribution, Indicates the preset uniform threshold coefficient.

5. The method for testing the electrical performance of a semiconductor chip according to claim 1, wherein: The step of optimizing the voltage distribution in the high-voltage risk area using a gradient descent algorithm and adjusting the operating voltage and current of the chip includes: According to the breakdown voltage corresponding to the high-voltage risk area, a gradient descent algorithm is used to minimize the breakdown probability to obtain an optimized voltage distribution; Adjusting the set values ​​of the operating voltage and the operating current according to the optimized voltage distribution; Based on the dynamically adjusted operating voltage and current, the chip's energy efficiency performance index in the high-voltage risk area is calculated. If the index is lower than the preset standard, the operating voltage and current are readjusted. The voltage distribution is optimized by the following formula: The energy efficiency performance index is calculated using the following formula: in, represents the breakdown probability, Indicates the The voltage in the high-voltage risk area, Indicates the The breakdown voltage threshold of the high-voltage risk area, Indicates the The standard deviation of the breakdown voltage in a local area, Represents the preset step size parameter, in units of , Indicates the The first iteration of the optimization The voltage in the high-voltage risk area, Indicates the The first iteration of the optimization The voltage in the high-voltage risk area, Indicates the output power, represents the input power, Indicates energy efficiency performance indicator.

6. The method for testing the electrical performance of a semiconductor chip according to claim 1, wherein: The sliding window algorithm is used to analyze the fluctuation value of the power factor, and abnormality identification is performed based on the fluctuation value and a preset fluctuation threshold to obtain the abnormal fluctuation area, including: Use sliding window algorithm to analyze the fluctuation of power factor with load changes; Comparing the fluctuation value with a preset fluctuation threshold, and if the fluctuation value is less than or equal to the fluctuation threshold, marking the period corresponding to the fluctuation value as a normal fluctuation area; If the fluctuation value is greater than the fluctuation threshold, the time period corresponding to the fluctuation value is marked as an abnormal fluctuation area.

7. The method for testing the electrical performance of a semiconductor chip according to claim 1, wherein: The PID algorithm is used to adjust the power factor corresponding to the abnormal fluctuation area and optimize the working state and transient response of the chip under dynamic load, including: Calculating a power factor adjustment value using a PID formula according to the fluctuation value, and calculating a compensation value using a preset compensation function according to the power factor adjustment value; Adjusting the energy efficiency performance of the chip according to the compensation value, optimizing the working state of the chip through the adjusted energy efficiency performance, determining whether the working state meets the preset working value, and readjusting the compensation value if it does not meet the working value; Evaluate the transient response of the chip according to the optimized working state, determine whether the transient response exceeds a preset response value, and re-optimize the working state if it does not exceed the response value; Obtaining optimized chip transient response data, determining whether the fluctuation value in the abnormal fluctuation area has returned to normal, and restarting the PID algorithm if the fluctuation value has not returned to normal; The power factor adjustment value and compensation value are calculated using the following formula: in, represents the fluctuation value, Indicates the power factor adjustment value, Indicates the compensation value, 、 and Represents the preset proportional, integral and differential coefficients, dimensionless, The unit is , The unit is , and Represents the preset compensation coefficient, which is a dimensionless coefficient.

8. A semiconductor chip electrical performance testing system, characterized in that: include: A data acquisition module is used to obtain the dielectric loss data of the chip in each frequency band, the operating voltage, the operating current, the material thickness of each layer inside the chip, the dielectric constant, and the power factor of the chip under different dynamic loads, wherein the dielectric loss data includes the loss value and the loss frequency; a loss anomaly analysis module, configured to establish a mapping relationship between loss value and loss frequency based on the dielectric loss data, obtain a nonlinear characteristic of dielectric loss, identify anomalies based on the nonlinear characteristic and a preset high-frequency loss threshold, obtain an abnormal loss area, perform loss anomaly analysis, and obtain a loss analysis result; a loss anomaly correction module, configured to correct the test data corresponding to the loss anomaly area using a minimum mean square error algorithm to obtain correction data, and optimize dynamic switching characteristics based on the correction data and the loss analysis result; A breakdown risk analysis module, configured to calculate the breakdown voltage distribution of each layer within the chip based on the material thickness and the dielectric constant, extract local areas with uneven distribution, and determine high-voltage risk areas based on a preset breakdown voltage threshold; A voltage distribution optimization module is used to optimize the voltage distribution in the high-voltage risk area using a gradient descent algorithm and adjust the operating voltage and current of the chip; a fluctuation anomaly identification module, configured to analyze the fluctuation value of the power factor using a sliding window algorithm, and perform anomaly identification based on the fluctuation value and a preset fluctuation threshold to obtain a fluctuation anomaly area; The fluctuation optimization module is used to adjust the power factor corresponding to the fluctuation abnormal area using a PID algorithm, and optimize the working state and transient response of the chip under dynamic load.

9. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, the method for testing the electrical performance of a semiconductor chip according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the method for testing the electrical performance of a semiconductor chip according to any one of claims 1 to 7.

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