A chip pin identification module and identification method thereof

Abstract

The present invention aims to provide a chip pin identification module and its identification method which occupies a small space, has low cost, can allocate conductive circuits and automatically identify corresponding conductive circuits. The chip pin identification module includes a pin connection module, an open-short circuit detection module, a conduction module, a plurality of test circuits and a processor. The open-short circuit detection module and the conduction module are both connected to the output end of the pin connection module, the open-short circuit detection module is electrically connected to the processor, a plurality of the test circuits are connected to the output ends of the conduction module correspondingly, a plurality of the test circuits are electrically connected to the processor, and the processor is electrically connected to an external host computer; the identification method is a relatively automatic chip identification method based on the chip pin identification module. The present invention is applied to the technical field of chip testing.

Description

Technical Field

[0001] The present invention is applied to the technical field of chip testing, and particularly relates to a chip pin identification module and an identification method thereof. Background Art

[0002] With the development of semiconductor technology, the functions of integrated chips are becoming more and more powerful, and their size is getting smaller and smaller. When the size of the integrated chip is so small that the human eye cannot recognize its appearance features, both the automated production line and the manual production line need to use the visual inspection system to distinguish the pin sequence of the integrated chip, and then connect the test equipment to inspect the integrated chip. However, the visual inspection system is costly, complex in structure, occupies a large space, takes up a long time to test, and is difficult to maintain. Summary of the invention

[0003] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a chip pin identification module and an identification method thereof which occupies a small space, has low cost, can allocate conductive circuits and automatically identify corresponding conductive circuits.

[0004] The technical solution adopted by the present invention is: the chip pin identification module includes a pin connection module, an open-short circuit detection module, a conduction module, a plurality of test circuits and a processor, the open-short circuit detection module and the conduction module are both connected to the output end of the pin connection module, the open-short circuit detection module is electrically connected to the processor, a plurality of the test circuits are correspondingly connected to a plurality of output ends of the conduction module, a plurality of the test circuits are electrically connected to the processor, and the processor is electrically connected to an external host computer; the pin connection module includes at least two probes connected to the pins of the chip to be tested and a plurality of first relays whose number is equal to the number of the probes, and a plurality of input ends on all the first relays are correspondingly connected to the probes of the same sequence; the conduction module includes a plurality of second relays whose number is equal to the number of the probes, a plurality of input ends on all the second relays are correspondingly connected to the output ends of the first relays of the same sequence, and the output ends of a plurality of the second relays are correspondingly connected to a plurality of the test circuits.

[0005] It can be seen from the above scheme that the pin connection module is connected to the pins of the chip to be tested, and a number of the first relays are used as a switching structure to realize free switching of the conduction relationship of the pins of the chip to be tested, which is convenient for the open-short circuit detection module to detect the internal resistance of the circuit between the two pins to be tested, and switch different pin combinations. The conduction module is used to conduct the circuit between the pin and the corresponding test circuit after completing the pin detection, so as to achieve the pin connection and conduction with the test circuit without adjusting the chip posture after taking a picture. The chip pin identification module has a small overall footprint and low cost, which can save the time of adjustment before testing and improve test efficiency. Among them, the test circuit is the circuit required for product testing.

[0006] A preferred solution is that the open-short circuit detection module includes a third relay and a fourth relay, and several output ends of the third relay and the fourth relay are correspondingly connected to the output end of the first relay of the same sequence, the output end of the third relay is electrically connected to the processor through a voltage follower, the output end of the third relay is also connected to a low-voltage power supply through a fixed resistor, and the output end of the fourth relay is grounded.

[0007] It can be seen from the above scheme that by setting the custom resistor, short circuits are prevented from burning the circuit during detection, and by setting the fixed value resistor, the internal resistance of the circuit between the current conductive pins can be calculated. The third relay and the fourth relay cooperate to realize the connection between the pins and the open-short circuit detection module. The voltage value between the conductive pins is obtained by the voltage follower, and then the internal resistance value of the circuit between the conductive pins is calculated. The internal resistance value of the circuit between the conductive pins is used to compare with the parameters of the chip to be tested, and then the sequence relationship of the pins is obtained.

[0008] The identification method comprises the following steps:

[0009] A. docking the chip to be tested with a plurality of the probes, the processor starts to identify the pin position after receiving the detection instruction, and the processor disconnects the third relay, the fourth relay, all the first relays and the second relays by controlling the on and off of the interface;

[0010] B. the processor controls the first-order input terminals and output terminals of the two first relays of the first order and the second order to be turned on through the interface;

[0011] C. Then, the processor controls the first sequence input terminals and output terminals of the third relay and the fourth relay to be turned on through the interface, so that the current passes through the fixed value resistor, the third relay, the first relay, the chip to be tested, the second relay and the fourth relay in sequence;

[0012] D. Then, the voltage value of the pin connected to the current chip under test after being turned on is obtained by the voltage follower, and the resistance value between the pins connected to the current chip under test is calculated by the processor;

[0013] E. Cut off the two first relays, then switch to the next conduction combination, repeat step C, step D and switch the conduction combination until the resistance values ​​of the conduction combinations of all pins are obtained;

[0014] F. Compare the measured data with the parameters of the chip to be tested, and then obtain the pin sequence relationship of the chip to be tested;

[0015] G. The processor controls the input end of the first relay to be connected to the probe of the corresponding sequence through the interface, thereby making a plurality of the first relays serve as the extension ends of the corresponding probes;

[0016] H. The processor controls a plurality of the second relays to be turned on through an interface, and makes the probes turned on by the second relays match the test circuit.

[0017] As can be seen from the above scheme, by repeatedly switching the pin conduction combination and measuring the circuit resistance of all pin conduction combinations, the circuit resistance data is compared with the chip default parameters, and then the pin sequence relationship is obtained. Then, by controlling the conduction relationship of a number of the second relays, the product pins are connected to the test circuits of their corresponding sequence, thereby realizing automatic pin identification and conduction testing, without the need to adjust the product posture after determining the direction through the visual inspection system, saving adjustment time and improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a connection block diagram of the chip pin identification module;

[0019] Figure 2 is a circuit schematic diagram of the first part of the chip pin identification module;

[0020] Figure 3 is a circuit schematic diagram of the second part of the chip pin identification module;

[0021] Figure 4 is a circuit schematic diagram of the third part of the chip pin identification module;

[0022] Figure 5 is a circuit schematic diagram of the fourth part of the chip pin identification module;

[0023] Figure 6 is a flow chart of the identification method. DETAILED DESCRIPTION

[0024] like Figures 1 to 5As shown, in this embodiment, the chip pin identification module includes a pin connection module 1, an open-short circuit detection module 2, a conduction module 3, a plurality of test circuits 4 and a processor 5, the open-short circuit detection module 2 and the conduction module 3 are both connected to the output end of the pin connection module 1, the open-short circuit detection module 2 is electrically connected to the processor 5, a plurality of the test circuits 4 are correspondingly connected to a plurality of output ends of the conduction module 3, a plurality of the test circuits 4 are electrically connected to the processor 5, and the processor 5 is electrically connected to an external host computer; the pin connection module 1 includes at least two probes 6 connected to the pins of the chip to be tested and a plurality of first relays 7 whose number is equal to the number of the probes 6, and a plurality of input ends on all the first relays 7 are correspondingly connected to the probes 6 of the same sequence; the conduction module 3 includes a plurality of second relays 8 whose number is equal to the number of the probes 6, a plurality of input ends on all the second relays 8 are correspondingly connected to the output end of the first relay 7 of the same sequence, and the output ends of a plurality of the second relays 8 are correspondingly connected to a plurality of the test circuits 4.

[0025] The open-short circuit detection module 2 includes a third relay 9 and a fourth relay 10. Several output ends of the third relay 9 and the fourth relay 10 are correspondingly connected to the output end of the first relay 7 of the same sequence. The output end of the third relay 9 is electrically connected to the analog-to-digital conversion module of the processor 5 through a voltage follower 11. The output end of the third relay 9 is also connected to the low-voltage power supply through a fixed resistor 12, and the output end of the fourth relay 10 is grounded.

[0026] like Figure 3 As shown, the identification method comprises the following steps:

[0027] A. docking the chip to be tested with a plurality of the probes 6, the processor 5 starts to identify the pin position after receiving the detection instruction, and the processor 5 disconnects the third relay 9, the fourth relay 10, all the first relays 7 and the second relays 8 by controlling the on / off of the interface;

[0028] B. the processor 5 controls the first-order input terminals and output terminals of the two first relays 7 of the first order and the second order to be turned on through the interface;

[0029] C. Then, the processor 5 controls the first sequence input terminals and output terminals of the third relay 9 and the fourth relay 10 to be turned on through the interface, so that the current passes through the fixed value resistor 12, the third relay 9, the first relay 7, the chip to be tested, the second relay 8 and the fourth relay 10 in sequence;

[0030] D. Then, the voltage value of the pin connected to the current chip under test after being turned on is obtained by the voltage follower 11, and the resistance value between the pins connected to the current chip under test is calculated by the processor 5;

[0031] E. Cut off the two first relays 7, then switch to the next conduction combination, repeat step C, step D and switch the conduction combination, until the resistance values ​​of the conduction combinations of all pins are obtained;

[0032] F. Compare the measured data with the parameters of the chip to be tested, and then obtain the pin sequence relationship of the chip to be tested;

[0033] G. The processor 5 controls the input end of the first relay 7 to be connected to the probe 6 of the corresponding sequence through the interface, thereby making a plurality of the first relays 7 serve as the extension ends of the corresponding probes 6;

[0034] H. The processor 5 controls a plurality of the second relays 8 to be turned on through an interface, and makes the probes 6 turned on by the second relays 8 match the test circuit 4 .

[0035] In this embodiment, the product to be tested has four pins, and the number of the probe 6, the first relay 7, the second relay 8 and the test circuit 4 is four. The first relay 7, the second relay 8, the third relay 9 and the fourth relay 10 are all provided with four input terminals. The model of the first relay 7, the second relay, the third relay 9 and the fourth relay 10 are all SIP-1A05, and the processor 5 includes a processing chip of model STM32F103. The voltage value of the low-voltage power supply is 2.5V, the resistance value of the fixed resistor 12 is R1, and the circuit resistance value between the conductive pins is set to Rx.

[0036] From the voltage calculation formula, we can get the voltage value between the conduction pins: V1=2.5V*[Rx / (R1+RX)].

[0037] The voltage value transmitted by the voltage follower 11 to the processor 5 is V2. The analog-to-digital conversion module of the processor 5 in the present invention is a 12-bit (2^12), the reference voltage is 3V, and the conversion value of V2 is ADC_Read. Therefore, V2=V1=(ADC_Read*3V) / (2^12).

[0038] Combining the above formula, we can get the internal resistance of the circuit between the conducting pins Rx=(V1*R1) / (2.5V-V1).

[0039] In this embodiment, the circuit internal resistance value of each pin combination of the current chip is measured by the above method and its data is compared with the parameters of the current chip in turn, as shown in the following table:

[0040]

[0041] Table 1 Measured resistance values ​​between the pins of the chip under test

[0042]

[0043] Table 2 Resistance values ​​of known parameters between the pins of the chip under test

[0044] It can be concluded that the A, B, C, and D pins of the current chip under test are the 4th, 1st, 2nd, and 3rd pins of the chip respectively.

[0045] The processor controls through the interface to turn on the 1st and 5th pins of the first relay 7 of the first order, the 2nd and 5th pins of the first relay 7 of the second order, the 3rd and 5th pins of the first relay 7 of the third order, the 4th and 5th pins of the first relay 7 of the fourth order, and then controls the 1st and 5th pins of the second relay 8 of the fourth order, the 2nd and 5th pins of the second relay 8 of the first order, the 3rd and 5th pins of the second relay 8 of the second order, and the 4th and 5th pins of the second relay 8 of the third order. Then the pins of the chip to be tested are turned on with the corresponding test circuit 4, so that the chip to be tested can be tested normally.

Claims

1. A chip pin identification module identification method, characterized in that: The chip pin identification module comprises a pin connection module (1), an open-short circuit detection module (2), a conduction module (3), a plurality of test circuits (4) and a processor (5); the open-short circuit detection module (2) and the conduction module (3) are both connected to the output end of the pin connection module (1); the open-short circuit detection module (2) is electrically connected to the processor (5); a plurality of the test circuits (4) are correspondingly connected to a plurality of output ends of the conduction module (3); a plurality of the test circuits (4) are all electrically connected to the processor (5); and the processor (5) is electrically connected to an external host computer; the pin connection module (1) comprises at least two probes (6) connected to the pins of the chip to be tested and a plurality of first relays (7) whose number is equal to the number of the probes (6); a plurality of input ends on all the first relays (7) are connected to the probes (6) of the same sequence. ) are connected accordingly; the conduction module (3) comprises a number of second relays (8) equal to the number of the probes (6), a number of input terminals on all the second relays (8) are connected correspondingly to the output terminals of the first relays (7) of the same order, and the output terminals of a number of the second relays (8) are connected correspondingly to a number of the test circuits (4); the open-short circuit detection module (2) comprises a third relay (9) and a fourth relay (10), a number of output terminals of the third relay (9) and the fourth relay (10) are connected correspondingly to the output terminals of the first relays (7) of the same order, the output terminal of the third relay (9) is electrically connected to the processor (5) through a voltage follower (11), the output terminal of the third relay (9) is also connected to a low-voltage power supply through a fixed resistor (12), and the output terminal of the fourth relay (10) is grounded; The identification method comprises the following steps: A. docking the chip to be tested with a plurality of the probes (6); the processor (5) starts to identify the pin position after receiving the detection instruction; the processor (5) disconnects the third relay (9), the fourth relay (10), all the first relays (7) and the second relays (8) by controlling the on / off of the interface; B. the processor (5) controls the first-order input terminals and output terminals of the two first relays (7) of the first order and the second order through an interface to be turned on; C. Then, the processor (5) controls the first sequence input terminals and output terminals of the third relay (9) and the fourth relay (10) through the interface to be turned on, thereby causing the current to sequentially pass through the fixed value resistor (12), the third relay (9), the first relay (7), the chip to be tested, the second relay (8), and the fourth relay (10); D. Then, the voltage value of the pins connected to the current chip under test after being turned on is obtained by the voltage follower (11), and the resistance value between the pins connected to the current chip under test is calculated by the processor (5); E. Cut off the two first relays (7), then switch to the next conduction combination, repeat step C, step D and switch the conduction combination, until the resistance values ​​of the conduction combinations of all pins are obtained; F. Compare the measured data with the parameters of the chip to be tested, and then obtain the pin sequence relationship of the chip to be tested; G. The processor (5) controls the input end of the first relay (7) to be connected to the probe (6) of the corresponding sequence through the interface, thereby making a plurality of the first relays (7) serve as the extension ends of the corresponding probes (6); H. The processor (5) controls a plurality of the second relays (8) to be turned on through an interface, and makes the probes (6) turned on by the second relays (8) match the test circuit (4).

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