A new type of thyristor device with low clamping and built-in capacitance reduction diode

Abstract

A new type of thyristor device with low clamping and embedded capacitance reduction diode includes a thyristor module and a diode module. The thyristor module and the diode module are formed on a heteroepitaxial layer of a silicon substrate, and the thyristor module and the diode module are isolated by deep trench DTI. The product of the invention solves the problem of high clamping voltage of thyristor devices with integrated diodes, and obtains a device with lower clamping voltage under the same area and the same capacitance.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, relates to semiconductor component design technology, and in particular to a novel silicon controlled rectifier device with an embedded capacitance reduction diode. Background Art

[0002] IC chip (Integrated Circuit Chip) is an integrated circuit formed by a large number of microelectronic components (transistors, resistors, capacitors, etc.) placed on a plastic substrate to make a chip. The IC manufacturing process is constantly shrinking, and the area of ​​the integrated circuit is also developing towards miniaturization, making the integrated circuit increasingly vulnerable to external ESD and surge events. The current common solution is to connect a semiconductor protection device with overvoltage protection capability in parallel to the IC core circuit, and put forward higher requirements for the protection device. On the one hand, the operating voltage of the core circuit is constantly decreasing, and the breakdown voltage of the gate oxide is reduced. If the clamping voltage of the protection device is higher than the gate oxide breakdown voltage, the core circuit will burn out prematurely after the protection device is turned on. On the other hand, the transmission rate of terminal electronic products is constantly increasing, and the operating frequency of the integrated circuit is gradually increasing. The parasitic capacitance of the ESD protection device has an increasing impact on the IC circuit. When the capacitance of the device exceeds the maximum capacitance value that the circuit can accept, it will affect the integrity of the transmission signal. Therefore, it is necessary to select an ESD protection device with a small parasitic capacitance and meet the circuit ESD protection requirements.

[0003] In the field of semiconductor protection devices, Silicon Controlled Rectifier (thyristor) is one of the most efficient ESD protection devices. It can convert from a low current and high voltage state to a high current and low voltage state. Since there is a positive feedback loop inside the device, the current is continuously amplified after it is turned on, and the discharge path of the ESD current is very deep. Therefore, it has a very strong ESD current discharge capability and good low resistance characteristics after being turned on.

[0004] In recent years, the research on low capacitance protection devices has focused on diode devices, thyristor devices, and improved structures integrating these two types of devices. Figure 1 As shown in the figure, since there is often a contradiction between the ESD robustness of the device and the parasitic capacitance, both factors should be carefully considered when designing the device, so as to provide reliable and efficient ESD protection for the IC circuit under the premise of ensuring that the IC circuit can work normally. In other words, the research on low-capacitance ESD devices is to optimize the parasitic capacitance of the device, but more importantly, to improve the ESD robustness of the low-capacitance protection device. At present, many protection device structures integrate diodes on thyristor devices, such as Figure 1It is a schematic diagram of the equivalent circuit of the existing thyristor low capacitance device. The two diodes in the figure have the characteristics of high breakdown voltage and low capacitance. When the diodes are connected in series with the thyristor device, the device capacitance is greatly reduced. However, the series diodes have a higher on-resistance, which increases the clamping voltage of the integrated device. Therefore, how to compromise the low capacitance and low clamping characteristics is an urgent problem to be solved. Summary of the invention

[0005] The purpose of the present invention is to provide a novel thyristor device with a low clamping voltage and an embedded capacitance-reducing diode to solve the problem of high clamping voltage of thyristor devices with integrated diodes, and to obtain a device with lower clamping voltage under the same area and the same capacitance.

[0006] The object of the present invention is achieved by the following scheme: A novel thyristor device with low clamping and embedded capacitance reduction diode is prepared on a silicon substrate, including a thyristor module and a diode module. The thyristor module and the diode module are formed on a heteroepitaxial layer of the silicon substrate. The thyristor module and the diode module are isolated by deep trench DTI, wherein:

[0007] The thyristor module is composed of a P-type heavily doped region SP, an N-type well region (Nwell), a P-type well region (Pwell), and an N-type heavily doped region SN, wherein SP / Nwell / Pwell constitutes a parasitic PNP structure, and Nwell / Pwell / SN constitutes a parasitic NPN structure. Since the base of the parasitic NPN tube is connected to the collector of the parasitic PNP tube, that is, the base current of the former is equal to the collector current of the latter, when the parasitic PNP tube and the parasitic NPN tube are in the amplification state at the same time, the internal current is continuously amplified, the positive feedback is continuously increased, and the discharge current capability is enhanced;

[0008] The diode module is formed in a well and is led out by SP and SN. The well can be P-type doped or N-type doped. If it is P-type doped, the same or different process conditions as Pwell are selected. If it is N-type doped, the same or different process conditions as Nwell are selected.

[0009] In the thyristor module, the SN terminal in Nwell can be floated or led out as a control electrode according to needs. When it is a control electrode, the response time and turn-on voltage of the thyristor structure are controlled by applying an external voltage or current.

[0010] The diode module and the thyristor module are connected via metal electrodes, wherein the SN end in the well of the diode module is connected to the SP in the Nwell of the thyristor module to form a signal port IO, and the SP end in the well of the diode module is connected to the SN and SP in the Pwell of the thyristor module to form a ground terminal GND. The thyristor module and the diode module are connected via metal to form ESD protection from the signal end to the ground end.

[0011] Specifically, SN1, SP1 and SN2 are sequentially injected into the Nwell, and SN1 and SN2 are connected as control electrodes; SN3, SP2 and SN4 are sequentially injected into the Pwell, and SN3, SP2 and SN4 and SP in the diode module are grounded together.

[0012] To facilitate preparation and simplify the structure, the SN in the diode module, SN 1 and SN 2 in Nwell, and SN 3 and SN 4 in Pwell have the same structure and doping concentration; the SP in the diode module has the same structure and doping concentration as SP 1 and SP 2 in the thyristor module.

[0013] The SP of Nwell in the thyristor module is not only the anode of the thyristor, but also the PN junction formed by SP and Nwell has a low capacitance characteristic, that is, a forward switching diode is embedded in the thyristor.

[0014] In the present invention, the capacitance from the signal port IO to the ground terminal GND is directly related to the effective injection area of ​​SP in Nwell and the doping concentration of Nwell, that is, the capacitance is proportional to the effective injection area of ​​SP and inversely proportional to the doping concentration of Nwell; the surge or static electricity from the GND terminal to the IO terminal is absorbed by the diode module serving as a negative switch tube.

[0015] Based on the above scheme, the Nwell and Pwell are key layers for controlling the trigger voltage. When the injection dose of the two wells is small and the impurity concentration is low, the parasitic PNP or NPN is easy to penetrate to form a low trigger voltage; when the injection dose of the two wells is large, the trigger voltage is an avalanche breakdown voltage. The higher the concentration of the wells and the closer the distance between the wells, the smaller the trigger voltage.

[0016] The present invention can add a trigger junction or a gate grounded NMOS tube (GGNmos).

[0017] The trigger junction is injected into Nwell, located at the interface of Nwell and Pwell, and is no longer connected to the SN in Nwell.

[0018] When the trigger junction is injected into Nwell, which is an N-type heavily doped impurity region, the avalanche breakdown of the trigger junction and Pwell determines the trigger voltage of the thyristor; when the trigger junction is injected into a P-type heavily doped impurity region, the avalanche breakdown of the trigger junction and Nwell determines the trigger voltage of the thyristor.

[0019] Furthermore, GGNmos can be added to replace the trigger junction area, and the avalanche breakdown of the parasitic diode in the MOS can be used to determine the trigger voltage of the device.

[0020] Based on the above scheme, the silicon substrate can be an SOI substrate with an oxide buried layer on the substrate. The SOI substrate can be an N-type or P-type substrate. Correspondingly, the epitaxial layer is an N-type high-resistance epitaxial layer or a P-type high-resistance epitaxial layer. The diode module, Nwell and Pwell are formed on the epitaxial layer.

[0021] Based on the above solution, the silicon substrate is an SOI substrate, an oxide buried layer is provided on the substrate, and a trigger junction injection is added in Nwell at the interface between Nwell and Pwell.

[0022] Based on the above scheme, the silicon substrate can also use a secondary epitaxial layer, the silicon substrate is a high-concentration N-type or P-type doped area, the primary epitaxial layer is N-type doped, and the secondary epitaxial layer is P-type doped.

[0023] Furthermore, the thyristor module has a vertical structure, a P-type buried layer and an N-type buried layer are implanted on the primary epitaxial layer, a P-type groove is led out from the P-type buried layer through the secondary epitaxial layer; and an N-type groove is led out from the N-type buried layer through the secondary epitaxial layer, the P-type groove is a deep groove filled with P-type doped POLY, and the N-type groove is a deep groove filled with N-type doped POLY, a parasitic PNP device is formed by SP, Nwell, P-type buried layer and P-type groove; a parasitic NPN device is formed by Nwell, P-type secondary epitaxial layer, N buried layer and N-type groove.

[0024] The advantages of the present invention are: providing a new type of thyristor device with low clamping and embedded capacitance reduction diode, solving the problem of high clamping voltage of thyristor device with integrated diode, and obtaining a device with lower clamping voltage under the same area and the same capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of equivalent circuit of existing thyristor low-capacitance device;

[0026] Figure 2 It is a schematic diagram of the structure of a novel thyristor device according to the first embodiment;

[0027] Figure 3 This is a schematic diagram of an equivalent circuit of a novel thyristor device in Example 1;

[0028] Figure 4 This is a schematic diagram of the layout design of a novel thyristor device in Example 1;

[0029] Figure 5 is a schematic structural diagram of a novel thyristor device according to Embodiment 2;

[0030] Figure 6 is a schematic diagram of the structure of a novel thyristor device according to Embodiment 3;

[0031] Figure 7 is a schematic structural diagram of a novel thyristor device according to Embodiment 4;

[0032] Figure 8 is a schematic diagram of the structure of a novel thyristor device in Embodiment 5;

[0033] Description of the numbers in the figure:

[0034] 100——substrate;

[0035] 101——Epitaxial layer;

[0036] 102——Nwell;

[0037] 103 - Pwell;

[0038] 104——SN;

[0039] 1041, 1042, 1043, 1044——SN 1, 2, 3, 4;

[0040] 105——SP;

[0041] 1051, 1052——SP one and two;

[0042] 106 - well of the diode module;

[0043] 107——pressure welding area;

[0044] 108 - deep groove DTI;

[0045] 1081, 1082—deep groove DTI one and two;

[0046] 109——P-type groove;

[0047] 110——N-type groove;

[0048] 111——P-type buried layer; 112——N-type buried layer; 113——secondary epitaxial layer;

[0049] 115 – trigger knot;

[0050] 116——Buried oxide layer. DETAILED DESCRIPTION

[0051] Example 1

[0052] like Figure 2 is a schematic diagram of the structure of the novel thyristor device of this embodiment, Figure 3 This is a schematic diagram of the equivalent circuit of the novel thyristor device of this embodiment and Figure 4 The schematic diagram of the layout design of the novel thyristor device in this embodiment is shown as follows:

[0053] A new type of thyristor device with low clamping and built-in capacitance reduction diode, such as Figure 2 As shown, a thyristor module is included, which is composed of a P-type heavily doped region SP, an N-type well region Nwell102, a P-type well region Pwell103, and an N-type heavily doped region SN104. Among them, SP-1051 / Nwell102 / Pwell103 in Nwell102 constitutes a parasitic PNP structure, and SN104 in Nwell102 / Pwell103 / Pwell103 constitutes a parasitic NPN structure. Since the base of the parasitic NPN tube is connected to the collector of the parasitic PNP tube, the base current of the former is equal to the collector current of the latter, as shown in FIG. Figure 3 As shown in the equivalent circuit diagram, when the parasitic PNP tube and the parasitic NPN tube are in the amplification state at the same time, the current in the body is continuously amplified, the positive feedback is continuously increased, and the current discharge capacity is enhanced;

[0054] A diode module is formed in a well 106 of the diode module, and is led out by a P-type heavily doped region SP105 and an N-type heavily doped region SN104. The well 106 of the diode module can be P-type doped or N-type doped. Figure 2 and 4 As shown, if it is P-type doping, the same or different process conditions as Pwell 103 can be selected, and if it is N-type doping, the same or different process conditions as Nwell 102 can be selected;

[0055] In the thyristor module, the SN 104 terminal in the Nwell 102 is led out as a control electrode, and the response time and turn-on voltage of the thyristor structure are controlled by applying an external voltage or current;

[0056] The thyristor module and the diode module are both formed on the heteroepitaxial layer 101 to prevent the current from flowing into the ground through the substrate; the epitaxial layer 101 is a high resistivity doped region to reduce the parasitic capacitance of the device;

[0057] The doped region of SP 105 in the thyristor module Nwell 102 is not only the anode of the thyristor, but also the PN junction formed by SP 105 and Nwell 102 has a low capacitance characteristic by adjusting the process conditions, that is, a forward switch tube is embedded in the thyristor. Since this diode is connected in series to the thyristor path, the device capacitance is reduced, forming a new thyristor device with a low clamping embedded capacitance reduction diode.

[0058] like Figure 2 and 4As shown, the diode module and the thyristor module are both isolated by deep trench DTI 108, including deep trench DTI 1, 2 1081, 1082, wherein the diode module is isolated by deep trench DTI 1 1081; the thyristor module is isolated by deep trench DTI 2 1082. A pressure welding area 107 is set on the upper surface of the substrate 100 adjacent to the diode module and the thyristor module; SN 1 1041, SP 1 1051, SN 2 1042 are arranged at equal intervals in the thyristor module Nwell 102; SN 3 1043, SP 2 1052, SN 4 1044 are arranged at equal intervals in the thyristor module Pwell 103.

[0059] To facilitate preparation and simplify the structure, the SN in the diode module, SN 1 and SN 2 in Nwell, and SN 3 and SN 4 in Pwell in this embodiment have the same structure and the same doping concentration; the SP in the diode module has the same structure and the same doping concentration as SP 1 and SP 2 in the thyristor module.

[0060] Connect the electrodes via metal, such as Figure 2 As shown, the SN 104 end of the diode module is connected to the SP 1051 in the thyristor module Nwell 102 to form a signal port IO, the SN 1, SN 2 1041, 1042 in the thyristor module Nwell 102 are connected as control electrodes, and the SP 105 end of the diode module is connected to the SN 3 1043, SP 2 1052, and SN 4 1044 in the thyristor module Pwell 103 to form a ground terminal GND.

[0061] In the novel thyristor device with low clamping and built-in capacitance reduction diode, the diode acts as a negative switch tube to absorb surge or static electricity from the GND end to the IO end.

[0062] In the novel thyristor device with a low clamping embedded capacitance reduction diode, the capacitance from the signal terminal IO to the ground terminal GND is directly related to the effective injection area of ​​SP105 in Nwell102 and the doping concentration of Nwell102. Specifically, the capacitance is proportional to the effective injection area of ​​SP105 and inversely proportional to the doping concentration of Nwell102.

[0063] In the above-mentioned novel thyristor device with low clamping and built-in capacitance reduction diode, Nwell102 and Pwell103 are key layers for controlling the trigger voltage. When the injection dose of the two wells is small and the impurity concentration is low, the parasitic PNP or NPN is easy to penetrate to form a low trigger voltage. When the injection dose of the two wells is large, the trigger voltage is an avalanche breakdown voltage. The higher the concentration of the wells and the closer the distance between the wells, the smaller the trigger voltage.

[0064] Compared with the protection device of the traditional SCR structure, the new structure of this embodiment has the following advantages:

[0065] 1. By cleverly designing the Nwell process and SP size, not only can the capacitance of the thyristor device be effectively reduced, but also because there is one less forward switch tube than ordinary low-capacitance devices, the current flow path has one less forward conduction resistance, and the on-resistance of the entire device is significantly reduced, thereby reducing the clamping voltage of the device.

[0066] 2. Compared with the traditional structure, this embodiment does not increase the process level, the process is easy to implement, the effective area is smaller than that of the traditional device, the surge capacity of the device can be improved under the same area, and the integration is high.

[0067] 3. This embodiment can be adjusted according to different application requirements.

[0068] Example 2

[0069] A new type of thyristor device with low clamping and built-in capacitance reduction diode, such as Figure 5 As shown, the rest is the same as that of the embodiment 1, except that the trigger junction 115 is added (GGNmos may also be added) to adjust the trigger voltage.

[0070] like Figure 5 As shown in the figure, a trigger junction 115 is added to Nwell, located at the interface of Nwell102 and Pwell103, and is no longer connected to SN104 in Nwell102. When the trigger junction is injected as an N-type heavily doped impurity region, the avalanche breakdown of the trigger junction 115 and Pwell103 determines the trigger voltage of the thyristor; when the trigger junction 115 is injected as a P-type heavily doped impurity region, the avalanche breakdown of the trigger junction 115 and Nwell102 determines the trigger voltage of the thyristor. Alternatively, GGNmos can be added to replace the trigger junction 115 region, and the avalanche breakdown of the parasitic diode in the MOS can be used to determine the trigger voltage of the device.

[0071] Example 3

[0072] A new type of thyristor device with low clamping and built-in capacitance reduction diode, such as Figure 6 As shown, the rest is the same as the embodiment 1, except that this embodiment uses SOI substrate material and has an oxide buried layer 116 on the substrate 100 to further reduce the device capacitance.

[0073] like Figure 6 As shown; the difference from the first embodiment is that the substrate material is SOI, wherein the buried oxide layer 116 is dielectric silicon dioxide. Due to the presence of the oxide layer, the substrate parasitic capacitance is reduced, thereby reducing the capacitance of the thyristor. Figure 6In the embodiment, the SOI substrate 100 may be an N-type or P-type substrate, and correspondingly, the epitaxial layer 101 is an N-type high-resistance epitaxial layer or a P-type high-resistance epitaxial layer.

[0074] Example 4

[0075] A novel thyristor device with low clamping and built-in capacitance reduction diode has the same structure as that of embodiment 2, such as Figure 7 As shown, this embodiment uses SOI substrate material, has an oxide buried layer 116 on the substrate 100, and adds a trigger junction (115) injection to further reduce the device area.

[0076] This embodiment combines the advantages of Embodiments 2 and 3, and reduces the device capacitance and adjusts the trigger voltage at the same time.

[0077] Example 5

[0078] A new type of thyristor device with low clamping and built-in capacitance reduction diode, such as Figure 8 The schematic diagram of the structure of the novel thyristor device in this embodiment is similar to that in the first embodiment, and both include a thyristor module and a diode module, except that:

[0079] 1) The substrate 100 is made of secondary epitaxial material, and the substrate 100 is a high-concentration N-type or P-type doping region. When the epitaxial layer 101 is N-type doped, the secondary epitaxial layer 113 is P-type doped;

[0080] 2) The thyristor has a vertical structure, and is further provided with a P-type buried layer 111 injection, an N-type buried layer 112 injection, a P-type trench 109 lead-out, and an N-type trench 110 lead-out, wherein the P-type trench 109 is a deep trench filled with a P-type doped POLY, and the N-type trench 110 is a deep trench filled with an N-type doped POLY, and a parasitic PNP device is formed by SP105, Nwell102, the P-type buried layer 111, and the P-type trench 109 lead-out; a parasitic NPN device is formed by Nwell102, a P-type secondary epitaxial layer 113, an N-buried layer 112, and an N-type trench 110 lead-out, and its working principle is the same as that in the first embodiment, and will not be repeated here.

[0081] The present invention has been described in detail above, but the above is only a preferred embodiment of the present invention and should not limit the scope of the present invention. That is, all equivalent changes and modifications made according to the scope of the present invention should still fall within the scope of the patent of the present invention.

Claims

1. A novel thyristor device with a low clamping embedded capacitance reduction diode, prepared on a silicon substrate (100), characterized in that it comprises a thyristor module and a diode module, wherein the thyristor module and the diode module are formed on a heteroepitaxial layer of the silicon substrate, and the thyristor module and the diode module are isolated by deep trench DTI, wherein: The thyristor module is composed of a P-type heavily doped region SP, an N-type well region Nwell, a P-type well region Pwell, and an N-type heavily doped region SN, wherein SP / Nwell / Pwell constitutes a parasitic PNP structure, and Nwell / Pwell / SN constitutes a parasitic NPN structure. Since the base of the parasitic NPN tube is connected to the collector of the parasitic PNP tube, that is, the base current of the former is equal to the collector current of the latter, when the parasitic PNP tube and the parasitic NPN tube are in an amplification state at the same time, the internal current is continuously amplified, the positive feedback is continuously increased, and the discharge current capability is enhanced; The diode module is formed in a well and is led out by SP and SN. The well can be P-type doped or N-type doped. If it is P-type doped, the same or different process conditions as Pwell are selected. If it is N-type doped, the same or different process conditions as Nwell are selected. In the thyristor module, the SN terminal in Nwell is selected to be floating or led out as a control electrode. When it is a control electrode, the response time and turn-on voltage characteristics of the thyristor structure are controlled by applying an external voltage or current. The diode module and the thyristor module are connected to electrodes through metal, the SN end in the well of the diode module is connected to the SP in the Nwell of the thyristor module to form a signal port IO, the SP end in the well of the diode module is connected to the SN and SP in the Pwell of the thyristor module to form a ground terminal GND, and the thyristor module and the diode module are connected through metal to form ESD protection from the signal end to the ground end; SN1, SP1 and SN2 are sequentially injected into the Nwell, and SN1 and SN2 are connected to be led out as control electrodes; SN3, SP2 and SN4 are sequentially injected into the Pwell, and SN3, SP2 and SN4 and SP in the diode module are grounded together; The silicon substrate is an SOI substrate, and there is an oxide buried layer on the substrate. The SOI substrate is an N-type or P-type substrate, and correspondingly, the epitaxial layer is an N-type high-resistance epitaxial layer or a P-type high-resistance epitaxial layer, and the diode module, Nwell and Pwell are formed on the epitaxial layer; The silicon substrate has a secondary epitaxial layer, and the silicon substrate is a high-concentration N-type or P-type doping region. When the epitaxial layer is N-type doped, the secondary epitaxial layer is P-type doped.

2. According to claim 1, the novel thyristor device with low clamping and built-in capacitance reduction diode is characterized in that the SP of Nwell in the thyristor module is not only the anode of the thyristor, but also the PN junction formed by SP and Nwell has a low capacitance characteristic, that is, a forward switching diode is embedded inside the thyristor.

3. According to claim 1, the novel thyristor device with low clamping and built-in capacitance reduction diode is characterized in that: SN in the diode module, SN 1 and SN 2 in Nwell, and SN 3 and SN 4 in Pwell have the same structure and the same doping concentration; SP in the diode module has the same structure and the same doping concentration as SP 1 and SP 2 in the thyristor module.

4. The novel thyristor device with low clamping and built-in capacitance reduction diode according to claim 1 or 2 is characterized in that the capacitance from the signal port IO to the ground terminal GND is directly related to the effective injection area of ​​the SP (105) in the Nwell (102) and the doping concentration of the Nwell, that is, the capacitance is proportional to the effective injection area of ​​the SP and inversely proportional to the doping concentration of the Nwell; the surge or static electricity from the GND terminal to the IO terminal is absorbed by the diode module serving as a negative switch tube.

5. The novel thyristor device with low clamping and embedded capacitance reduction diode according to claim 1 is characterized in that a trigger junction is injected into Nwell, located at the interface of Nwell and Pwell, and is no longer connected to SN in Nwell; or a gate grounded Nwell is added. MOS Tube.

6. The novel thyristor device with a low clamping embedded capacitance reduction diode according to claim 5 is characterized in that, when the trigger junction is injected into Nwell and is an N-type heavily doped impurity region, the avalanche breakdown of the trigger junction and Pwell determines the trigger voltage of the thyristor; when the trigger junction is injected into a P-type heavily doped impurity region, the avalanche breakdown of the trigger junction and Nwell determines the trigger voltage of the thyristor.

7. The novel thyristor device with low clamping and built-in capacitance reduction diode according to claim 5 is characterized in that a GGNmos is added to replace the trigger junction area, and the avalanche breakdown of the parasitic diode in the MOS is used to determine the trigger voltage of the device.

8. The novel thyristor device with low clamping and built-in capacitance reduction diode according to claim 1 is characterized in that, in Nwell, a trigger junction injection is added at the interface between Nwell and Pwell.

9. The novel thyristor device with low clamping and built-in capacitance reduction diode according to claim 1 or 8, characterized in that the thyristor module is a vertical structure, a P-type buried layer (111) and an N-type buried layer (112) are implanted on the primary epitaxial layer (101), a P-type trench (109) is led out from the P-type buried layer (111) through the secondary epitaxial layer (113); and an N-type trench (110) is led out from the N-type buried layer (112) through the secondary epitaxial layer (113), and the P-type The groove (109) is a deep groove filled with P-type doped POLY, and the N-type groove (110) is a deep groove filled with N-type doped POLY. The SP (105), Nwell (102), P-type buried layer (111) and P-type groove (109) are connected to form a parasitic PNP device; the Nwell (102), secondary epitaxial layer (113), N-type buried layer (112) and N-type groove (110) are connected to form a parasitic NPN device.

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