Scan Driver

Abstract

The present disclosure relates to a scan driver, which includes: a first transistor, the first transistor having a first electrode coupled to an output scan line, a second electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor, the second transistor having a first electrode coupled to a first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node; a third transistor, the third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor, the fourth transistor having a first electrode coupled to the second node, and a second electrode and a gate electrode coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0152855 filed on November 30, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates generally to scan drivers. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has increased. Therefore, display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices are increasingly used.

[0005] Each pixel of the display device may emit light having brightness corresponding to a data voltage input through a data line. The display device may display an image frame using a combination of light-emitting pixels.

[0006] A plurality of pixels may be coupled to each data line. Therefore, a scan driver is required that provides a scan signal for selecting a pixel to which a data voltage is to be supplied from among a plurality of pixels.

[0007] In addition to selecting pixels to which data voltages are to be supplied, the scan signals of the scan driver may also be used as control signals for various operation phases of the pixels.

[0008] The Background section of the specification includes information intended to provide a background for example embodiments, and the information in this Background section does not necessarily constitute prior art. Summary of the invention

[0009] Aspects of some example embodiments include a scan driver capable of supplying a scan signal having a turn-on level for an N-type transistor.

[0010] According to some example embodiments of the present disclosure, a scan driver includes: a first transistor, the first transistor having an electrode coupled to an output scan line, another electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor, the second transistor having an electrode coupled to a first clock line, another electrode coupled to an output scan line, and a gate electrode coupled to a second node; a third transistor, the third transistor having an electrode coupled to the first node, another electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor, the fourth transistor having an electrode coupled to the second node, another electrode and a gate electrode coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other.

[0011] According to some example embodiments, the scan driver may further include: a fifth transistor having an electrode coupled to the first clock line, another electrode coupled to the second node, and a gate electrode coupled to the first node; and a first capacitor having an electrode coupled to the first clock line and another electrode coupled to the second node.

[0012] According to some example embodiments, the scan driver may further include: a second capacitor having one electrode coupled to the third node and another electrode coupled to the first node; and a sixth transistor having one electrode coupled to the third node, another electrode coupled to the third clock line, and a gate electrode coupled to the first node.

[0013] According to some example embodiments, the scan driver may further include a seventh transistor having one electrode coupled to the second power line, another electrode coupled to the third node, and a gate electrode coupled to the fourth clock line.

[0014] According to some example embodiments, the scan driver may further include a seventh transistor having one electrode coupled to the third clock line, another electrode coupled to the third node, and a gate electrode coupled to the fourth clock line.

[0015] According to some example embodiments, the scan driver may further include an eighth transistor having one electrode coupled to the second node, another electrode coupled to one electrode of the fourth transistor, and a gate electrode coupled to the control line.

[0016] According to some example embodiments, the scan driver may further include a ninth transistor having one electrode coupled to the first node, another electrode coupled to one electrode of the third transistor, and a gate electrode coupled to the first power line.

[0017] According to some example embodiments, the scan driver may further include: a tenth transistor having an electrode coupled to the second power line, another electrode coupled to the other electrode of the fourth transistor, and a gate electrode coupled to the second input scan line; and an eleventh transistor having an electrode coupled to the other electrode of the fourth transistor, another electrode coupled to the first power line, and a gate electrode coupled to the second input scan line.

[0018] According to some example embodiments, a pulse of a first scan signal input to a first input scan line may have a phase faster than a phase of a pulse of a second scan signal input to a second input scan line.

[0019] According to some example embodiments, pulses of the second scan signal may overlap with some pulses of the first clock signal input to the first clock line for a portion of the time.

[0020] According to some example embodiments, a time at which pulses of the second scan signal are generated may be earlier than a time at which some pulses of the first clock signal are generated.

[0021] According to some example embodiments, the second clock signal input to the second clock line may have the same cycle length as the third clock signal input to the third clock line but have a phase faster than that of the third clock signal.

[0022] According to some example embodiments, the pulse of the first clock signal may have a polarity opposite to that of the pulse of the third clock signal. The pulse of the first clock signal and the pulse of the third clock signal may overlap each other for a portion of the time. The pulse of the first clock signal may have a phase delayed from the phase of the pulse of the third clock signal.

[0023] According to some example embodiments, a fourth clock signal may be input to a fourth clock line. A pulse of the fourth clock signal may have a polarity opposite to that of a pulse of the first clock signal. A pulse of the fourth clock signal and a pulse of the first clock signal may overlap each other for a portion of the time. A pulse of the fourth clock signal may have a phase delayed from a phase of a pulse of the first clock signal.

[0024] According to some example embodiments, a pulse of the first clock signal may have a polarity opposite to that of a pulse of the third clock signal. A pulse of the first clock signal may be generated at a time at which a pulse of the third clock signal is generated. The time at which a pulse of the first clock signal is generated may be delayed from a time at which a pulse of the third clock signal is generated.

[0025] According to some example embodiments, a fourth clock signal may be input to a fourth clock line. A pulse of the fourth clock signal may have a polarity opposite to that of a pulse of the first clock signal. A pulse of the fourth clock signal may not overlap in time with a pulse of the first clock signal.

[0026] According to some example embodiments, in the first driving mode, the control signal applied to the control line may maintain a turn-on level during one period including a plurality of image frames.

[0027] According to some example embodiments, in a second driving mode different from the first driving mode, the control signal may maintain an on level during a partial period of one image frame in one cycle, and maintain an off level in other image frames in one cycle.

[0028] According to some example embodiments, in a second driving mode different from the first driving mode, the control signal may maintain an on-level during one cycle. The first clock signal input to the first clock line may include a pulse during a partial period of one image frame in one cycle, and may not include a pulse in other image frames in one cycle.

[0029] According to some example embodiments, a pulse of a first scan signal input to a first input scan line may have a faster phase than a pulse of a second scan signal input to a second input scan line. The pulse of the first scan signal and the pulse of the second scan signal may have the same polarity. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Hereinafter, various aspects of some example embodiments will now be more fully described with reference to the accompanying drawings; however, various aspects of some example embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be more thorough and complete, and to more fully convey the scope of the example embodiments to those skilled in the art.

[0031] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals always represent the same elements.

[0032] Figure 1 are diagrams illustrating display devices according to some example embodiments of the present disclosure.

[0033] Figure 2 is a diagram illustrating a scan driver according to some example embodiments of the present disclosure.

[0034] Figure 3It is shown Figure 2 A diagram of the scan stage of a scan driver is shown.

[0035] Figure 4 It is shown Figure 3 FIG. 1 is a diagram of an example driving method for a scanning stage shown.

[0036] Figure 5 is a diagram illustrating a scan driver according to some example embodiments of the present disclosure.

[0037] Figure 6 is a diagram showing some example embodiments according to the present disclosure Figure 5 A diagram of the scan stage of a scan driver is shown.

[0038] Figure 7 It is shown Figure 6 FIG. 1 is a diagram of an example driving method for a scanning stage shown.

[0039] Figures 8 to 11 It is shown Figure 6 A variation of the scanning stage is shown in FIG.

[0040] Fig.12 is a diagram illustrating a scan stage of a scan driver according to some example embodiments of the present disclosure.

[0041] Fig.13 It is shown Fig.12 FIG. 1 is a diagram of an example driving method for a scanning stage shown.

[0042] Fig.14 is a diagram illustrating pixels according to some example embodiments of the present disclosure.

[0043] Fig.15 is a diagram illustrating a high frequency driving method according to some example embodiments of the present disclosure.

[0044] Fig.16 is a diagram illustrating a data writing period of a pixel according to some example embodiments of the present disclosure.

[0045] Fig.17 is a diagram illustrating a low frequency driving method according to some example embodiments of the present disclosure.

[0046] Fig.18 is a diagram illustrating a low frequency driving method according to some example embodiments of the present disclosure.

[0047] Fig.19 is a diagram illustrating a bias period of a pixel according to some example embodiments of the present disclosure. DETAILED DESCRIPTION

[0048] Hereinafter, aspects of some example embodiments are described in more detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the example embodiments described in this specification.

[0049] Parts not related to the description will be omitted to clearly describe the present disclosure, and throughout the specification, the same or similar constituent elements will be represented by the same reference numerals. Therefore, the same reference numerals may be used to identify the same or similar elements in different drawings.

[0050] In addition, for better understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. For clear expression, the thickness of several parts and regions is exaggerated.

[0051] Figure 1 are diagrams illustrating display devices according to some example embodiments of the present disclosure.

[0052] refer to Figure 1 , a display device 9 according to some example embodiments of the present disclosure may include a timing controller 10 , a data driver 20 , a scan driver 30 , an emission driver 40 , and a pixel unit 50 .

[0053] The timing controller 10 may provide the data driver 20 with grayscale values ​​and control signals to suit the specifications of the data driver 20. In addition, the timing controller 10 may provide the scan driver 30 with a clock signal, a scan start signal, etc. to suit the specifications of the scan driver 30. In addition, the timing controller 10 may provide the emission driver 40 with a clock signal, an emission stop signal, etc. to suit the specifications of the emission driver 40.

[0054] The data driver 20 may generate data voltages to be supplied to the data lines DL1, DL2, ..., DLm, ... using the grayscale values ​​and control signals received from the timing controller 10. For example, the data driver 20 may sample the grayscale values ​​using the clock signal, and apply data voltages corresponding to the grayscale values ​​to the data lines DL1, DL2, ..., DLm, ... in pixel row units. Here, m may be a natural number greater than zero.

[0055] The scan driver 30 may generate scan signals to be supplied to the scan lines GIL1, GWNL1, GWPL1, GBL1, . . . , GILn, GWNLn, GWPLn, GBLn, . . . by receiving a clock signal, a scan start signal, etc. from the timing controller 10. Here, n may be a natural number greater than zero.

[0056] The scan driver 30 may include a plurality of sub-scan drivers. In an example, a first sub-scan driver may provide scan signals for the scan lines GIL1, ..., GILn, ..., a second sub-scan driver may provide scan signals for the scan lines GWNL1, ..., GWNLn, ..., a third sub-scan driver may provide scan signals for the scan lines GWPL1, ..., GWPLn, ..., and a fourth sub-scan driver may provide scan signals for the scan lines GBL1, ..., GBLn, ...

[0057] In another example, the first sub-scan driver and the second sub-scan driver may be integrated to provide scan signals for the scan lines GIL1, GWNL1, ..., GILn, GWNLn, ..., and the third sub-scan driver and the fourth sub-scan driver may be integrated to provide scan signals for the scan lines GWPL1, GBL1, ..., GWPLn, GBLn, .... For example, the previous scan line of the n-th scan line GWNLn (i.e., the (n-1)-th scan line) may be coupled to the same electrical node as the n-th scan line GILn. In addition, for example, the next scan line of the n-th scan line GWPLn (i.e., the (n+1)-th scan line) may be coupled to the same electrical node as the n-th scan line GBLn.

[0058] The first sub-scan driver and the second sub-scan driver may supply a scan signal having a pulse of a first polarity to the scan lines GIL1, GWNL1, ..., GILn, GWNLn, ... In addition, the third sub-scan driver and the fourth sub-scan driver may supply a scan signal having a pulse of a second polarity to the scan lines GWPL1, GBL1, ..., GWPLn, GBLn, ... The first polarity and the second polarity may be opposite polarities to each other.

[0059] In the following, polarity may refer to the logic level of a pulse. For example, when a pulse has a first polarity, the pulse may have a high level. A pulse having a high level may be referred to as a rising pulse. When a rising pulse is supplied to a gate electrode of an N-type transistor, the N-type transistor may be turned on. That is, the rising pulse may have a turn-on level for the N-type transistor. Assume a situation where a voltage having a level sufficiently lower than that of the gate electrode of the N-type transistor is applied to the source electrode of the N-type transistor. For example, the N-type transistor may be an NMOS transistor.

[0060] In addition, when the pulse has the second polarity, the pulse may have a low level. The pulse with a low level may be referred to as a falling pulse. When the falling pulse is supplied to the gate electrode of the P-type transistor, the P-type transistor may be turned on. That is, the falling pulse may be a turn-on level for the P-type transistor. Assume that a voltage having a level sufficiently higher than that of the gate electrode of the P-type transistor is applied to the source electrode of the P-type transistor. For example, the P-type transistor may be a PMOS transistor.

[0061] The emission driver 40 may generate an emission signal to be supplied to the emission lines EL1, EL2, ... and ELn, ... by receiving a clock signal, an emission stop signal, etc. from the timing controller 10. For example, the emission driver 40 may sequentially supply an emission signal having an off-level pulse to the emission lines EL1, EL2, ... and ELn, ... For example, the emission driver 40 may be configured in the form of a shift register, and generate an emission signal in such a manner that an off-level pulse of an emission stop signal is sequentially transferred to a next emission stage under the control of a clock signal.

[0062] The pixel unit 50 includes pixels. For example, the pixels PXnm may be coupled to corresponding data lines DLm, corresponding scan lines GILn, GWNLn, GWPLn, and GBLn, and corresponding emission lines ELn.

[0063] Figure 2 is a diagram illustrating a scan driver according to some example embodiments of the present disclosure.

[0064] Figure 2 The scan driver 30Na shown may correspond to the reference Figure 1 According to some example embodiments, referring to Figure 1 The first sub-scanning driver described above can be replaced by scanning lines GIL1, ..., GILn, ... Figure 2 It is realized by the scanning lines GWNL1, GWNL2, GWNL3, GWNL4, ..., GWNLn, ... shown in FIG.

[0065] refer to Figure 2 , the scan driver 30Na may include scan stages NST1a, NST2a, NST3a, NST4a, ..., NSTna, .... Each of the scan stages NST1a, NST2a, NST3a, NST4a, ..., NSTna, ... may be coupled to corresponding clock lines CCLKL1 and CCLKL2, corresponding one of the clock lines NCLK1, NCLK2, NCLK3, and NCLK4, and the preceding end scan line. However, the first scan stage NST1a does not have a preceding end scan line, and thus may be coupled to the scan start line FLMLa.

[0066] Scanning stages NST1a, NST2a, NST3a, NST4a, ..., NSTna, ... may be coupled to each other in the form of a shift register. For example, a scan signal may be generated in such a manner that a turn-on level pulse of a scan start signal supplied to a scan start line FLMLa is sequentially transferred to the next scan stage.

[0067] Figure 3 It is shown Figure 2 A diagram of the scan stage of a scan driver is shown.

[0068] refer to Figure 3 , showing Figure 2 An example of a first scanning stage NST1a of a scanning driver 30Na is shown. Figure 2 The other scanning stages NST2a, NST3a, NST4a, . . . , NSTna, . . . shown have substantially the same configuration as that of the scanning stage NST1a, and therefore, a repeated description will be omitted.

[0069] The scanning stage NST1a may include transistors P1 to P13 and capacitors CC1 to CC3. The transistors P1 to P13 may be P-type transistors.

[0070] One electrode of the transistor P1 may be coupled to the other electrode of the transistor P2 , the other electrode of the transistor P1 may be connected to the scan start line FLMLa, and a gate electrode of the transistor P1 may be coupled to the clock line NCLKL1 .

[0071] One electrode of the transistor P2 may be coupled to the other electrode of the transistor P13 , the other electrode of the transistor P2 may be coupled to one electrode of the transistor P1 , and a gate electrode of the transistor P2 may be coupled to the control clock line CCLKL1 .

[0072] One electrode of the transistor P3 may be coupled to the node NN3 , the other electrode of the transistor P3 may be coupled to the control clock line CCLKL1 , and the gate electrode of the transistor P3 may be coupled to one electrode of the transistor P2 .

[0073] The transistor P4 may be coupled to the node NN3 , the other electrode of the transistor P4 may be coupled to the power line VGLL, and the gate electrode of the transistor P4 may be coupled to the control clock line CCLKL1 .

[0074] One electrode of the transistor P5 may be coupled to the node NN4 , the other electrode of the transistor P5 may be coupled to the control clock line CCLKL2 , and the gate electrode of the transistor P5 may be coupled to the node NN2 .

[0075] One electrode of the transistor P6 may be coupled to the power line VGHL, the other electrode of the transistor P6 may be coupled to the node NN4 , and the gate electrode of the transistor P6 may be coupled to the node NN3 .

[0076] One electrode of the transistor P7 may be coupled to one electrode of the capacitor CC3 , the other electrode of the transistor P7 may be coupled to the control clock line CCLKL2 , and the gate electrode of the transistor P7 may be coupled to the other electrode of the capacitor CC3 .

[0077] One electrode of the transistor P8 may be coupled to the node NN1 , the other electrode of the transistor P8 may be coupled to the capacitor CC3 , and the gate electrode of the transistor P8 may be coupled to the control clock line CCLKL2 .

[0078] One electrode of the transistor P9 may be coupled to the clock line NCLKL1 , the other electrode of the transistor P9 may be coupled to the node NN1 , and the gate electrode of the transistor P9 may be coupled to the node NN2 .

[0079] One electrode of the transistor P10 may be coupled to the clock line NCLKL1 , the other electrode of the transistor P10 may be coupled to the scan line GWNL1 , and the gate electrode of the transistor P10 may be coupled to the node NN2 .

[0080] One electrode of the transistor P11 may be coupled to the scan line GWNL1 , the other electrode of the transistor P11 may be coupled to the power line VGLL, and the gate electrode of the transistor P11 may be coupled to the node NN2 .

[0081] One electrode of the transistor P12 may be coupled to the other electrode of the capacitor CC3 , the other electrode of the transistor P12 may be coupled to the node NN3 , and a gate electrode of the transistor P12 may be coupled to the power line VGLL.

[0082] One electrode of the transistor P13 may be coupled to the node NN2 , the other electrode of the transistor P13 may be coupled to one electrode of the transistor P2 , and a gate electrode of the transistor P13 may be coupled to the power line VGLL.

[0083] One electrode of the capacitor CC1 may be coupled to the clock line NCLKL1 , and the other electrode of the capacitor CC1 may be coupled to the node NN1 .

[0084] One electrode of the capacitor CC2 may be coupled to the node NN4 , and the other electrode of the capacitor CC2 may be coupled to the node NN2 .

[0085] One electrode of the capacitor CC3 may be coupled to one electrode of the transistor P7 , and the other electrode of the capacitor CC3 may be coupled to the gate electrode of the transistor P7 .

[0086] Figure 4 It is shown Figure 3 FIG. 1 is a diagram of an example driving method for a scanning stage shown.

[0087] refer to Figure 4 , a timing diagram of a scan start signal FLMa applied to a scan start line FLMLa, a control clock signal CCLK2 applied to a control clock line CCLKL2, a control clock signal CCLK1 applied to a control clock line CCLKL1, a clock signal NCLK1 applied to a clock line NCLKL1, a node voltage VNN2 of a node NN2, a node voltage VNN3 of a node NN3, a node voltage VNN1 of a node NN1, and a scan signal GWN1 applied to a scan line GWNL1 is shown. The horizontal synchronization signal Hsync is shown as a reference signal for timing. The interval between pulses of the horizontal synchronization signal Hsync may be referred to as a horizontal period.

[0088] A voltage having a high level may be applied to the power line VGHL, and a voltage having a low level may be applied to the power line VGLL. In the description of the driving method, the transistors P12 and P13 whose gate electrodes are coupled to the power line VGLL are in an on state during most periods, and therefore, the description of the transistors P12 and P13 will be omitted except for specific cases.

[0089] First, at time t1a, the scanning start signal FLMa having a high level is supplied. Since the transistor P1 is in a turned-on state by the clock signal NCLK1 having a low level, the scanning start signal FLMa having a high level is supplied to the other electrode of the transistor P2.

[0090] At time t2a, the control clock signal CCLK1 having a low level is supplied. Therefore, the transistors P2 and P4 are turned on.

[0091] When the transistor P2 is turned on, the scan start signal FLMa having a high level is transmitted to the node NN2, and the node voltage VNN2 becomes a high level. The transistors P3, P5, P9, and P11 are turned off by the node voltage VNN2 having a high level.

[0092] When the transistor P4 is turned on, the node NN3 and the power supply line VGLL are coupled to each other, and thus the node voltage VNN3 becomes a low level. The transistors P6 and P7 are turned on by the node voltage VNN3 having a low level.

[0093] When the transistor P6 is turned on, the node NN4 and the power line VGHL are coupled to each other. Therefore, the power line VGHL supports one end of the capacitor CC2, and thus the node voltage VNN2 of the node NN2 can be stably maintained.

[0094] When the transistor P7 is turned on, one electrode of the capacitor CC3 and the control clock line CCLKL2 are coupled to each other. Since the control clock signal CCLK2 having a high level is applied to the gate electrode of the transistor P8, the transistor P8 is in a turned-off state, and thus the node voltage VNN1 does not change.

[0095] At time t3a, the clock signal NCLK1 having a high level and the control clock signal CCLK2 having a low level are supplied.

[0096] The control clock signal CCLK2 having a low level is supplied to one electrode of the capacitor CC3 through the transistor P7. A voltage lower than the low level is applied to the gate electrode of the transistor P7 through the coupling of the capacitor CC3. Thus, the transistor P7 can stably maintain the on state, and the driving characteristics of the transistor P7 can be improved.

[0097] According to this embodiment, the node voltage VNN3 is not affected by the coupling of the capacitor CC3 due to the transistor P12. When a voltage lower than the low level is applied to one electrode of the transistor P12 through the coupling of the capacitor CC3, one electrode of the transistor P12 is used as a drain electrode. Therefore, the node NN3 corresponding to the other electrode of the transistor P12 is used as a source electrode. In addition, because a voltage with a low level is applied to the gate electrode of the transistor P12 through the power line VGLL, a voltage higher than the low level is applied to the source electrode of the transistor P12 so that the transistor P12 is turned on. Because the node voltage VNN3 of the node NN3 becomes a low level at the current time, the transistor P12 is in a cut-off state.

[0098] Thus, according to the present embodiment, the node voltage VNN3 is maintained by the transistor P12, so that the transient bias voltage can be prevented from being applied to the transistors P3 and P4. Therefore, the life of the transistors P3 and P4 can be extended.

[0099] In addition, the transistor P8 is turned on by the control clock signal CCLK2 having a low level. Therefore, the node NN1 and the control clock line CCLKL2 are coupled to each other through the transistors P7 and P8. Therefore, the transistor P10 is turned on by the node voltage VNN1 having a low level. The transistor P9 maintains a cut-off state due to the node voltage VNN2 having a high level.

[0100] The clock line NCLKL1 and the scan line GWNL1 are coupled to each other through the turned-on transistor P10. Therefore, the clock signal NCLK1 having a high level is supplied to the scan line GWNL1 as the scan signal GWN1 having a high level.

[0101] In addition, by the clock signal NCLK1 having a high level, the transistor P1 maintains the off state until at least time t5a. Therefore, although the level of the scanning start signal FLMa subsequently becomes a low level, the node voltage VNN2 maintains a high level.

[0102] At time t4a, the control clock signal CCLK1 having a low level is supplied. Therefore, the transistors P2 and P4 are turned on, and since the node NN3 is coupled to the power supply line VGLL, the node voltage VNN3 maintains a low level.

[0103] Although the transistor P2 is turned on, the transistor P1 is kept in the off state as described above, and thus the node voltage VNN2 is kept at a high level.

[0104] At time t5a, the clock signal NCLK1 with a low level is supplied. Due to the coupling of the capacitor CC1, the node voltage VNN1 is lower than the low level. Therefore, the transistor P10 stably maintains the on state. Therefore, the clock signal NCLK1 with a low level is supplied to the scanning line GWNL1 as the scanning signal GWN1 with a low level.

[0105] At time t6a, the control clock signal CCLK2 having a low level is supplied. Therefore, the voltage of the gate electrode of the transistor P7 drops to a voltage lower than the low level due to the coupling of the capacitor CC3. Thus, the transistor P7 can stably maintain the on state, and the driving characteristics of the transistor P7 can be improved. In addition, as described with reference to time t3a, the node voltage VNN3 maintains a low level without being affected by the coupling of the capacitor CC3, thereby preventing a transient bias voltage from being applied to the transistors P3 and P4.

[0106] Since the transistor P8 is turned on, the transistor P10 also maintains a turned-on state due to the control clock signal CCLK2 having a low level transmitted through the transistors P7 and P8.

[0107] At time t7a, the control clock signal CCLK1 having a low level is supplied, and transistors P2 and P4 are turned on. Node NN3 and the power supply line VGLL are coupled to each other through transistor P4. Therefore, node voltage VNN3 maintains a low level, and node NN4 maintains a state in which node NN4 is coupled to the power supply line VGHL due to the turned-on transistor P6.

[0108] At the same time, since the transistor P1 is in the on state, the scan start signal FLMa having a low level is supplied to the node NN2. Therefore, the node voltage VNN2 becomes a low level.

[0109] The transistors P3 , P5 , P9 , and P11 are turned on by the node voltage VNN2 having a low level.

[0110] When the transistor P9 is turned on, the transistor P10 is coupled in a diode manner. Therefore, the current can only flow from the scanning line GWNL1 to the clock line NCLKL1, and thus the change in the level of the clock signal NCLK1 has no effect on the scanning signal GWN1.

[0111] When the transistor P11 is turned on, the power line VGLL is coupled to the scanning line GWNL1. Therefore, the scanning signal GWN1 having a low level is output from the scanning line GWNL1.

[0112] At time t8a, the control clock signal CCLK1 having a high level is supplied. Since the transistor P3 is in the on state, the node NN3 and the control clock line CCLKL1 are coupled to each other. Therefore, the node voltage VNN3 becomes a high level. The transistors P6 and P7 are turned off by the node voltage VNN3 having a high level.

[0113] The voltage of the node NN4 is maintained at a high level through the power supply line VGLL and the capacitor CC2 , and thus the transistor P5 is maintained in an on state.

[0114] At time t9a, the control clock signal CCLK2 having a low level and the clock signal NCLK1 having a high level are supplied.

[0115] As described above, since the transistor P9 maintains the on state, the transistor P10 maintains the state in which the transistor P10 is diode-coupled, and thus the clock signal NCLK1 having a high level is not transmitted to the scanning line GWNL1 .

[0116] The control clock signal CCLK2 having a low level is applied to the node NN4 through the transistor P5 in the on state. Therefore, the node voltage VNN2 is lower than the low level due to the coupling of the capacitor CC2. Thus, the transistor P11 can stably maintain the on state, and the driving characteristics of the transistor P11 can be improved.

[0117] According to this embodiment, due to the transistor P13, the node corresponding to the other electrode of the transistor P13 is not affected by the coupling of the capacitor CC2. When a voltage lower than the low level due to the coupling of the capacitor CC2 is applied to the node NN2 as one electrode of the transistor P13, one electrode of the transistor P13 is used as a drain electrode. Therefore, the node corresponding to the other electrode of the transistor P13 is used as a source electrode. In addition, because a voltage with a low level is applied to the gate electrode of the transistor P13 through the power line VGLL, a voltage higher than the low level is applied to the source electrode of the transistor P13 so that the transistor P13 is turned on. Because a voltage with a low level is applied to the source electrode of the transistor P13 at the current time, the transistor P13 is in a cut-off state.

[0118] Thus, according to this embodiment, the voltage of the node corresponding to the other electrode of the transistor P13 is maintained by the transistor P13, so that the transient bias voltage can be prevented from being applied to the transistors P2 and P3. Therefore, the life of the transistors P2 and P3 can be extended.

[0119] Figure 5 is a diagram illustrating a scan driver according to some example embodiments of the present disclosure.

[0120] The scan driver 30Pb may correspond to the reference Figure 1 Although not shown in the drawings, those skilled in the art can replace the third sub-scanning driver with scanning lines GBL1, ..., GBLn, ... Figure 5 The scan lines shown in the figure are ..., GWPL(n-2), GWPL(n-1), GWPLn, GWPL(n+1), ... to realize the reference Figure 1 Described fourth sub-scan driver.

[0121] The scan driver 30Pb may include scan stages ..., PST(n-2)b, PST(n-1)b, PSTnb, PST(n+1)b, ​​.... Each of the scan stages ..., PST(n-2)b, PST(n-1)b, PSTnb, PST(n+1)b, ​​... may be coupled to a corresponding line among the clock lines PCLKL1, PCLKL2, PCLKL3, PCLKL4 and a previous end scan line (or a previous end scan line before a previous one).

[0122] The scanning stages ..., PST(n-2)b, PST(n-1)b, PSTnb, PST(n+1)b, ​​... may be coupled to each other in the form of a shift register. For example, the scanning signal may be generated in such a manner that the on-level pulse of the scanning signal supplied from the previous scanning line is sequentially transferred to the next scanning stage.

[0123] Advance reference Figure 7 , shows an example of clock signals PCLK1, PCLK2, PCLK3, and PCLK4 applied to clock lines PCLKL1, PCLKL2, PCLKL3, and PCLKL4 and scanning signals GWP(n-1) and GWPn applied to scanning lines GWPL(n-1) and GWPLn. The clock signals PCLK1, PCLK2, PCLK3, and PCLK4 and the scanning signals GWP(n-1) and GWPn may have pulses having a low level. As described above, the pulse having a low level may be represented as a pulse having a second polarity or a falling pulse.

[0124] The scan driver 30Nb may correspond to the reference Figure 1Although not shown in the drawings, a person skilled in the art can replace the second sub-scanning driver with scanning lines GIL1, ..., GILn, ... Figure 5 The scan lines shown in ..., GWNL(n-2), GWNL(n-1), GWNLn, GWNL(n+1), ... are used to realize the reference Figure 1 A first sub-scan driver is described.

[0125] The scan driver 30Nb may include scan stages ..., NST(n-2)b, NST(n-1)b, NSTnb, NST(n+1)b, ​​.... Each of the scan stages ..., NST(n-2)b, NST(n-1)b, NSTnb, NST(n+1)b, ​​... may be coupled to the corresponding lines of the clock lines PCLKL1, PCLKL2, PCLKL3, PCLKL4, NCLKL1, NCLKL2, NCLKL3, and NCLKL4, the control line PENL, the previous previous front-end scan line, and the previous front-end scan line of the scan driver 30Pb. For example, the scan stage NSTnb may be coupled to the corresponding lines of the clock lines PCLKL1, PCLKL2, PCLKL4, and NCLKL3, the control line PENL, the previous previous previous front-end scan line GWNL(n-2), and the previous front-end scan line GWPL(n-1) of the scan driver 30Pb. This embodiment illustrates the Figure 6 and Figure 7 An example coupling configuration of , and another coupling configuration may be applied to Figures 8 to 13 The scanning stages shown. The scanning stages ..., NST(n-2)b, NST(n-1)b, NSTnb, NST(n+1)b, ​​... may be coupled to each other in the form of a shift register.

[0126] The preceding end scanning signal applied to the preceding end scanning line may refer to a scanning signal that has a minimum phase difference with the current scanning signal applied to the current scanning line and has a faster phase than the phase of the current scanning signal. The preceding end scanning stage may refer to a scanning stage that uses the preceding end scanning line as an output line. The preceding end scanning signal applied to the preceding end scanning line before the preceding one may refer to a scanning signal that has a minimum phase difference with the preceding end scanning signal applied to the preceding end scanning line and has a faster phase than the phase of the preceding end scanning signal. The preceding end scanning stage before the preceding one may refer to a scanning stage that uses the preceding end scanning line before the preceding one as an output line. In the following, for the sake of convenience of description, the scanning signal may be expressed as a preceding end scanning signal or a preceding end scanning signal before the preceding one without considering the polarity of the pulse of the scanning signal. For example, the scanning signal applied to the scanning lines GWP (n-1) and GWNL (n-1) may be a preceding end scanning signal of the scanning signal applied to the scanning line GWNLn. Furthermore, for example, regardless of the polarity of the pulse, the scan signal applied to the scan lines GWPL(n-2) and GWNL(n-2) may be a preceding scan signal before the preceding one of the scan signals applied to the scan line GWNLn.

[0127] Advance Reference Figure 7 , shows an example of a clock signal NCLK3 applied to a clock line NCLKL3 and scan signals GWN(n-2) and GWNn applied to scan lines GWNL(n-2) and GWNLn. The clock signal NCLK3 and the scan signals GWN(n-2) and GWNn may have a pulse having a high level. As described above, the pulse having a high level may be represented as a pulse having a first polarity or a rising pulse.

[0128] Although in Figure 7 Although not shown in the figure, the clock signals applied to the clock lines NCLKL1, NCLKL2 and NCLKL4 may also have pulses with a high level. For example, the clock signal NCLK3 is an inverted signal of the clock signal PCLK3, and the clock signals applied to the clock lines NCLKL1, NCLKL2 and NCLKL4 may be inverted signals of the clock signals PCLK1, PCLK2 and PCLK4, respectively.

[0129] The clock signals applied to the clock lines PCLKL1, PCLKL2, PCLKL3, and PCLKL4 have the same cycle length (e.g., four horizontal cycles), but may have different phases. For example, the clock signal PCLK2 applied to the clock line PCLKL2 may have a phase delayed by 1 / 4 from the phase of the clock signal PCLK1 applied to the clock line PCLKL1. In addition, the clock signal PCLK3 applied to the clock line PCLKL3 may have a phase delayed by 1 / 4 from the phase of the clock signal PCLK2 applied to the clock line PCLKL2. In addition, the clock signal PCLK4 applied to the clock line PCLKL4 may have a phase delayed by 1 / 4 from the phase of the clock signal PCLK3 applied to the clock line PCLKL3.

[0130] Similarly, the clock signals applied to the clock lines NCLKL1, NCLKL2, NCLKL3, and NCLKL4 have the same cycle length (e.g., four horizontal cycles), but may have different phases. For example, the clock signal NCLK2 applied to the clock line NCLKL2 may have a phase delayed by 1 / 4 from the phase of the clock signal NCLK1 applied to the clock line NCLKL1. In addition, the clock signal NCLK3 applied to the clock line NCLKL3 may have a phase delayed by 1 / 4 from the phase of the clock signal NCLK2 applied to the clock line NCLKL2. In addition, the clock signal NCLK4 applied to the clock line NCLKL4 may have a phase delayed by 1 / 4 from the phase of the clock signal NCLK3 applied to the clock line NCLKL3.

[0131] Figure 6 is a diagram showing some example embodiments according to the present disclosure Figure 5 A diagram of the scan stage of a scan driver is shown.

[0132] refer to Figure 6 , showing Figure 5 An example of an n-th scanning stage NSTnb of a scanning driver 30Nb is shown. Figure 5 The other scanning stages . . . , NST(n-2)b, NST(n-1)b, NST(n+1)b, ​​. . . shown have substantially the same configuration as the scanning stage NSTnb, and therefore, repeated description will be omitted.

[0133] The scanning stage NSTnb may include transistors M1 to M9 and capacitors C1 and C2. The transistors M1 to M9 may be P-type transistors.

[0134] One electrode of the transistor M1 may be coupled to the scan line GWNLn, the other electrode of the transistor M1 may be coupled to the power line VGLL, and the gate electrode of the transistor M1 may be coupled to the node N1.

[0135] One electrode of the transistor M2 may be coupled to the clock line NCLKL3 , the other electrode of the transistor M2 may be coupled to the scan line GWNLn, and the gate electrode of the transistor M2 may be coupled to the node N2 .

[0136] One electrode of the transistor M3 may be coupled to the node N1 , the other electrode of the transistor M3 may be coupled to the scan line GWNL(n−2), and the gate electrode of the transistor M3 may be coupled to the clock line PCLKL1 .

[0137] One electrode of the transistor M4 may be coupled to the node N2 through the transistor M8 , and the other electrode and the gate electrode of the transistor M4 may be coupled to the scan line GWPL(n−1).

[0138] According to the present embodiment, the scan line GWNL (n-2) and the scan line GWPL (n-1) may be different from each other. For example, the scan line GWNL (n-2) may be a scan line extending from the previous end scan stage NST (n-2) b before the previous one of the scan driver 30Nb. In addition, the scan line GWPL (n-1) may be a scan line extending from the previous scan stage PST (n-1) b of the scan driver 30Pb. Therefore, the pulse of the scan signal GWN (n-2) input to the scan line GWNL (n-2) may have a phase faster than the phase of the pulse of the scan signal GWP (n-1) input to the scan line GWPL (n-1).

[0139] One electrode of the transistor M5 may be coupled to the clock line NCLKL3 , the other electrode of the transistor M5 may be coupled to the node N2 , and the gate electrode of the transistor M5 may be coupled to the node N1 .

[0140] One electrode of the capacitor C1 may be coupled to the clock line NCLKL3 , and the other electrode of the capacitor C1 may be coupled to the node N2 .

[0141] One electrode of the capacitor C2 may be coupled to the node N3 , and the other electrode of the capacitor C2 may be coupled to the node N1 .

[0142] One electrode of the transistor M6 may be coupled to the node N3 , the other electrode of the transistor M6 may be coupled to the clock line PCLKL2 , and the gate electrode of the transistor M6 may be coupled to the node N1 .

[0143] One electrode of the transistor M7 may be coupled to the power line VGHL, the other electrode of the transistor M7 may be coupled to the node N3 , and the gate electrode of the transistor M7 may be coupled to the clock line PCLKL4 .

[0144] One electrode of the transistor M8 may be coupled to the node N2 , the other electrode of the transistor M8 may be coupled to one electrode of the transistor M1 , and a gate electrode of the transistor M8 may be coupled to the control line PENL.

[0145] One electrode of the transistor M9 may be coupled to the node N1 , the other electrode of the transistor M9 may be coupled to one electrode of the transistor M3 , and a gate electrode of the transistor M9 may be coupled to the power line VGLL.

[0146] exist Figure 6 The scanning stage NSTnb shown in Figure 3 Compared with the scanning stage NST1a shown in FIG. 1 , four transistors and one capacitor CC3 are not required. Thus, the area required for each scanning stage can be reduced. In addition, the scanning stage NSTnb does not have power consumption caused by charging / discharging of the capacitor CC3, and thus, the power consumption of the scanning stage NSTnb can be further improved compared with the power consumption of the scanning stage NST1a.

[0147] Figure 7 It is shown Figure 6 FIG. 1 is a diagram of an example driving method for a scanning stage shown.

[0148] refer to Figure 7 , a timing diagram of clock signals PCLK1, PCLK2, PCLK3, PCLK4 and NCLK3 respectively applied to clock lines PCLKL1, PCLKL2, PCLKL3, PCLKL4 and NCLKL3 and scanning signals GWP(n-1), GWN(n-2), GWPn and GWNn respectively applied to scanning lines GWPL(n-1), GWNL(n-2), GWPLn and GWNLn is shown. The horizontal synchronization signal Hsync is shown as a reference signal for timing. The interval between pulses of the horizontal synchronization signal Hsync can be referred to as a horizontal period.

[0149] The pulse of the clock signal NCLK3 may have a polarity opposite to that of the pulse of the clock signal PCLK2, and the pulse of the clock signal NCLK3 and the pulse of the clock signal PCLK2 may overlap each other for part of the time. The pulse of the clock signal NCLK3 may have a phase delayed from the phase of the pulse of the clock signal PCLK2.

[0150] The pulse of the clock signal PCLK4 may have a polarity opposite to that of the pulse of the clock signal NCLK3, and the pulse of the clock signal PCLK4 and the pulse of the clock signal NCLK3 may overlap each other for part of the time. The pulse of the clock signal PCLK4 may have a phase delayed from that of the pulse of the clock signal NCLK3.

[0151] A voltage having a high level may be applied to the power line VGHL, and a voltage having a low level may be applied to the power line VGLL. In the description of the driving method, the transistor M9 whose gate electrode is coupled to the power line VGLL is in an on state in most periods, and therefore, the description of the transistor M9 will be omitted except for specific cases.

[0152] In addition, in the description of the driving method, it is assumed that the control signal PEN has a low level. Therefore, the transistor M8 maintains an on state, and therefore, the description of the transistor M8 will be omitted except for a specific case.

[0153] First, at time t1b, the clock signal PCLK1 having a low level and the scanning signal GWN(n-2) having a high level are supplied.

[0154] The transistor M3 is turned on by the clock signal PCLK1 having a low level, and supplies the scan signal GWN(n-2) having a high level to the node N1. Therefore, the transistors M1, M5, and M6, whose gate electrodes are coupled to the node N1, are turned off.

[0155] Since the transistor M4 is in a state where the transistor M4 is coupled in a diode manner, the direction of the current is from one electrode, which is the source electrode of the transistor M4, toward the other electrode, which is the drain electrode of the transistor M4. Therefore, at time t1b, the scan signal GWP(n-1) having a high level is not transmitted to the node N2. Therefore, the node N2 maintains the voltage of the previous period.

[0156] At time t2b, the scan signal GWP(n-1) having a low level and the clock signal PCLK2 having a low level are supplied.

[0157] Therefore, the voltage of the node N2 becomes a low level according to the scan signal GWP(n-1) having a low level, and the transistor M2 is turned on. Therefore, the clock line NCLKL3 and the scan line GWNLn are coupled to each other, and the clock signal NCLK3 having a low level is output as the scan signal GWNn having a low level.

[0158] Since the voltage of the node N1 is maintained at a high level due to the scan signal GWN(n-2) having a high level and the clock signal PCLK1 having a low level, the transistor M5 is in a turned-off state.

[0159] At time t3b, the clock signal NCLK3 having a high level is supplied.

[0160] The transistor M2 maintains the on state, and the transistor M5 maintains the off state. Therefore, the clock signal NCLK3 having a high level is output as the scanning signal GWNn having a high level.

[0161] According to an embodiment, the pulse of the scan signal GWP(n-1) may overlap with some pulses of the clock signal NCLK3 for part of the time. The time at which the pulse of the scan signal GWP(n-1) is generated may be earlier than the time at which some pulses of the clock signal NCLK3 are generated. That is, referring to Figure 7 , it can be seen that the first falling pulse of the scan signal GWP(n-1) is generated at time t2b, and the rising pulse of the clock signal NCLK3 is generated at time t3b. That is, when the clock signal NCLK3 rises to a high level at time t3b, if the scan signal GWP(n-1) having a low level is not in a state in which the scan signal GWP(n-1) having a low level is supplied to the node N2, there is a risk that the voltage of the node N2 will rise due to the coupling of the capacitor C1. The transistor M2 may be turned off. Thus, according to some example embodiments, the on state of the transistor M2 at time t3b may be enabled or ensured.

[0162] At time t4b, the clock signal NCLK3 having a low level is supplied.

[0163] The transistor M2 maintains the on state, and the transistor M5 maintains the off state. Therefore, the clock signal NCLK3 having a low level is output as the scanning signal GWNn having a low level.

[0164] The voltage of the node N2 is lower than a low level due to the coupling of the capacitor C1. Therefore, the transistor M2 is stably kept in a turned-on state, and the driving characteristics of the transistor M2 can be improved.

[0165] Although a voltage lower than the low level is applied to one electrode of the transistor M8, the voltage of the other electrode of the transistor M8 is not lower than the low level. When a voltage lower than the low level is applied to one electrode of the transistor M8 due to the coupling of the capacitor C1, one electrode of the transistor M8 is used as a drain electrode. In addition, because a voltage having a low level is applied to the gate electrode of the transistor M8 through the control line PENL, a voltage higher than the low level is applied to the source electrode of the transistor M8 so that the transistor M8 is turned on. A voltage having a low level is applied to the source electrode of the transistor M8 at the current time, and therefore, the transistor M8 is in a cut-off state.

[0166] Therefore, according to this embodiment, although the capacitor C1 is coupled, the voltage of the other electrode of the transistor M8 is maintained to prevent a transient bias voltage from being applied to the transistor M4. Therefore, the life of the transistor M4 can be extended.

[0167] At time t5b, the clock signal PCLK1 having a low level is supplied.

[0168] Since the scan signal GWN(n-2) having a low level is supplied to the scan line GWNL(n-2), the voltage of the node N1 becomes a low level. Therefore, the transistors M1, M5, and M6 whose gate electrodes are coupled to the node N1 are turned on.

[0169] When the transistor M1 is turned on, the power line VGLL and the scan line GWNLn are coupled to each other. Therefore, the power voltage having a low level is output as the scan signal GWNn having a low level.

[0170] When the transistor M5 is turned on, the transistor M2 is diode-coupled. Therefore, although the clock signal NCLK3 having a high level is subsequently supplied, the voltage having a high level is not transmitted to the scan line GWNn.

[0171] When the transistor M6 is turned on, the clock line PCLKL2 and the node N3 are coupled to each other. Therefore, the clock signal PCLK2 having a high level is applied to one electrode of the capacitor C2.

[0172] At time t6b, the clock signal PCLK2 having a low level is supplied.

[0173] Since the transistor M6 is in the on state, one electrode of the capacitor C2 and the clock line PCLKL2 are coupled to each other, and the voltage of the node N1 is lower than the low level due to the coupling of the capacitor C2. Thus, the transistor M1 is stably kept in the on state, and the driving characteristics of the transistor M1 can be improved.

[0174] Although a voltage lower than the low level is applied to the node N1 corresponding to one electrode of the transistor M9, the voltage of the other electrode of the transistor M9 is not lower than the low level. When a voltage lower than the low level is applied to one electrode of the transistor M9 due to the coupling of the capacitor C2, one electrode of the transistor M9 is used as a drain electrode. Therefore, the other electrode of the transistor M9 is used as a source electrode. In addition, because a voltage with a low level is applied to the gate electrode of the transistor M9 through the power line VGLL, a voltage higher than the low level is applied to the source electrode of the transistor M9 so that the transistor M9 is turned on. A voltage with a low level is applied to the source electrode of the transistor M9 at the current time, and therefore, the transistor M9 is in a cut-off state.

[0175] Therefore, according to some example embodiments, although the capacitor C2 is coupled, the voltage of the other electrode of the transistor M9 is maintained so as to prevent a transient bias voltage from being applied to the transistor M3. Therefore, the life of the transistor M3 may be extended.

[0176] In this embodiment, the case where the number of pulses of each scanning signal is three is shown. This is a driving method for applying a conduction bias voltage to the driving transistor of each pixel multiple times. In another embodiment, when the number of pulses of the scanning start signal is as follows: Figure 4 As shown in FIG. 1 , the number of pulses of each scanning signal may be one.

[0177] Figures 8 to 11 It is shown Figure 6 A variation of the scanning stage is shown in FIG.

[0178] and Figure 6 Compared with the scan level NSTnb shown, Figure 8 The scanning stage NSTnb2 shown does not include transistor M9. Figure 6 Compared with the scan level NSTnb shown, Figure 8 The scanning stage NSTnb2 shown has a feature that can reduce the area required for each scanning stage. Figure 7 The driving method shown is basically the same for Figure 8 The driving method of the scanning stage NSTnb2 is shown, and therefore, repeated description will be omitted.

[0179] and Figure 6 Compared with the scan level NSTnb shown, Fig. 9 The scanning stage NSTnb3 shown does not include transistors M8 and M9. Figure 6 Compared with the scan level NSTnb shown, Fig. 9 The scanning stage NSTnb3 shown has a feature that can reduce the area required for each scanning stage. Figure 7 The driving method shown is basically the same for Fig. 9 The driving method of the scanning stage NSTnb3 is shown, and therefore, repeated description will be omitted.

[0180] and Figure 6 Compared with the scan level NSTnb shown, Fig.10 The scan stage NSTnb4 shown further includes transistors M10 and M11, and the scan line GWPL(n-1) is replaced with the scan line GWNL(n-1).

[0181] One electrode of the transistor M10 may be coupled to the power line VGHL, the other electrode of the transistor M10 may be coupled to the other electrode of the transistor M4, and the gate electrode of the transistor M10 may be coupled to the scan line GWNL(n-1). The transistor M10 may be a P-type transistor.

[0182] One electrode of the transistor M11 may be coupled to the other electrode of the transistor M4, the other electrode of the transistor M11 may be coupled to the power line VGLL, and the gate electrode of the transistor M11 may be coupled to the scan line GWNL(n-1). The transistor 11 may be an N-type transistor.

[0183] according to Fig.10 In some example embodiments shown, the number of transistors included in each scan stage increases, but there is no need to extend the scan line GWPL(n-1) from the scan driver 30Pb to lead out the scan line GWPL(n-1), thereby reducing wiring complexity.

[0184] In addition to the scanning signal having a polarity opposite to that of the scanning signal GWP(n-1), Figure 7 The driving method shown can be applied to Fig.10 The driving method of the scanning stage NSTnb4 is shown, and therefore, repeated description will be omitted.

[0185] exist Fig.11 In the scanning stage NSTnb5 shown in FIG. 1 , compared with the scanning stage NSTnb, the clock line PCLKL2 is coupled to one electrode of the transistor M7 instead of the power line VGHL. Figure 7 , while the clock signal PCLK4 with a low level is applied to turn on the transistor M7, the clock signal PCLK2 with a high level is always supplied to one electrode of the transistor M7. Therefore, as far as the transistor M7 is concerned, the clock signal PCLK2 can operate like a power supply voltage with a high level.

[0186] according to Fig.11 In some example embodiments shown, it is not necessary to couple the power line VGHL to each scanning stage, thereby reducing the wiring complexity. Therefore, the area required for each scanning stage can be reduced. Figure 7 The driving method shown is basically the same for Fig.11 The driving method of the scanning stage NSTnb5 is shown, and therefore, repeated description will be omitted.

[0187] Fig.12 is a diagram illustrating a scan stage of a scan driver according to some example embodiments of the present disclosure.

[0188] refer to Fig.12 , the scanning stage NSTnc may include transistors M1 to M9 and capacitors C1 and C2. The transistors M1 to M9 may be P-type transistors.

[0189] Fig.12 The relative positions of transistors M1 to M9 and capacitors C1 and C2 are shown in FIG. Figure 6The relative position relationship of the transistors and capacitors of the scanning stage NSTnb shown is substantially the same, but the clock line and the scanning line coupled to the scanning stage NSTnc are different from the clock line and the scanning line coupled to the scanning stage NSTnb. Fig.13 To describe the driving method that changes due to this difference. Figure 7 The driving method shown can be expressed as an overlapping driving method. Fig.13 The driving method shown may be represented as a non-overlapping driving method.

[0190] One electrode of the transistor M1 may be coupled to the scan line GWNLn, the other electrode of the transistor M1 may be coupled to the power line VGLL, and the gate electrode of the transistor M1 may be coupled to the node N1.

[0191] One electrode of the transistor M2 may be coupled to the clock line NCLKL2 , the other electrode of the transistor M2 may be coupled to the scan line GWNLn, and the gate electrode of the transistor M2 may be coupled to the node N2 .

[0192] One electrode of the transistor M3 may be coupled to the node N1 , the other electrode of the transistor M3 may be coupled to the scan line GWNL(n−1), and the gate electrode of the transistor M3 may be coupled to the clock line PCLKL1 .

[0193] One electrode of the transistor M4 may be coupled to the node N2 , and the other electrode and the gate electrode of the transistor M4 may be coupled to the scan line GWPLn.

[0194] According to some example embodiments, the scan line GWNL(n-1) and the scan line GWPLn may be different from each other. A pulse of the scan signal GWN(n-1) input to the scan line GWNL(n-1) may have a phase faster than a phase of a pulse of the scan signal GWPn input to the scan line GWPLn.

[0195] One electrode of the transistor M5 may be coupled to the clock line NCLKL2 , the other electrode of the transistor M5 may be coupled to the node N2 , and the gate electrode of the transistor M5 may be coupled to the node N1 .

[0196] One electrode of the capacitor C1 may be coupled to the clock line NCLKL2 , and the other electrode of the capacitor C1 may be coupled to the node N2 .

[0197] One electrode of the capacitor C2 may be coupled to the node N3 , and the other electrode of the capacitor C2 may be coupled to the node N1 .

[0198] One electrode of the transistor M6 may be coupled to the node N3 , the other electrode of the transistor M6 may be coupled to the clock line PCLKL2 , and the gate electrode of the transistor M6 may be coupled to the node N1 .

[0199] One electrode of the transistor M7 may be coupled to the power line VGHL, the other electrode of the transistor M7 may be coupled to the node N3 , and the gate electrode of the transistor M7 may be coupled to the clock line PCLKL1 .

[0200] One electrode of the transistor M8 may be coupled to the node N2 , the other electrode of the transistor M8 may be coupled to one electrode of the transistor M4 , and a gate electrode of the transistor M8 may be coupled to the control line PENL.

[0201] One electrode of the transistor M9 may be coupled to the node N1 , the other electrode of the transistor M9 may be coupled to one electrode of the transistor M3 , and a gate electrode of the transistor M9 may be coupled to the power line VGLL.

[0202] exist Fig.12 In the scanning stage NSTnc shown, Figure 3 Compared with the scanning stage NST1a shown in FIG. 1 , four transistors and one capacitor CC3 are not required. Thus, the area required for each scanning stage can be reduced. In addition, the scanning stage NSTnc does not have power consumption caused by charging / discharging of the capacitor CC3, and thus, the power consumption of the scanning stage NSTnb can be further improved compared with the power consumption of the scanning stage NST1a.

[0203] Fig.13 It is shown Fig.12 FIG. 1 is a diagram of an example driving method for a scanning stage shown.

[0204] refer to Fig.13 , a timing diagram of clock signals NCLK1, NCLK2, PCLK1 and PCLK2 respectively applied to clock lines NCLKL1, NCLKL2, PCLKL1 and PCLKL2 and scanning signals GWN(n-1), GWPn and GWNn respectively applied to scanning lines GWNL(n-1), GWPLn and GWNLn is shown. The horizontal synchronization signal Hsync is shown as a reference signal for timing. The interval between pulses of the horizontal synchronization signal Hsync can be referred to as a horizontal period.

[0205] The pulse of the clock signal NCLK2 may have a polarity opposite to that of the pulse of the clock signal PCLK2, and the pulse of the clock signal NCLK2 may be generated at a time when the pulse of the clock signal PCLK2 is generated. The time when the pulse of the clock signal NCLK2 is generated may be delayed from the time when the pulse of the clock signal PCLK2 is generated.

[0206] The pulses of the clock signal PCLK1 may have a polarity opposite to that of the pulses of the clock signal NCLK2. The pulses of the clock signal PCLK1 may not overlap in time with the pulses of the clock signal NCLK2.

[0207] A voltage having a high level may be applied to the power line VGHL, and a voltage having a low level may be applied to the power line VGLL. In the description of the driving method, the transistor M9 whose gate electrode is coupled to the power line VGLL is in an on state during most periods, and therefore, the description of the transistor M9 will be omitted except for specific cases.

[0208] In addition, in the description of the driving method, it is assumed that the control signal PEN has a low level. Therefore, the transistor M8 maintains an on state, and therefore, the description of the transistor M8 will be omitted except for a specific case.

[0209] First, at time t1c, the scan signal GWN(n-1) having a high level is supplied.

[0210] Since the transistor M3 is in a state where the transistor M3 is turned on by the clock signal PCLK1 having a low level, the scan signal GWN(n-1) having a high level is supplied to the node N1. Therefore, the transistors M1, M5, and M6 whose gate electrodes are coupled to the node N1 are turned off.

[0211] Since the transistor M4 is in a state where the transistor M4 is coupled in a diode manner, the direction of the current is from one electrode as the source electrode of the transistor M4 toward the other electrode as the drain electrode of the transistor M4. Therefore, at time t1c, the scan signal GWPn having a high level is not transmitted to the node N2. Therefore, the node N2 maintains the voltage of the previous period.

[0212] At time t2c, the scan signal GWPn having a low level and the clock signal PCLK2 having a low level are supplied.

[0213] Therefore, the voltage of the node N2 becomes low level according to the scan signal GWPn having a low level, and the transistor M2 is turned on. Therefore, the clock line NCLKL2 and the scan line GWNLn are coupled to each other, and the clock signal NCLK2 having a low level is output as the scan signal GWNn having a low level.

[0214] Although the scan signal GWN(n-1) having a low level is supplied, the transistor M3 is in a turned-off state due to the clock signal PCLK1 having a high level. Therefore, the voltage of the first node N1 maintains a high level, and thus, the transistor M5 is in a turned-off state.

[0215] At time t3c, the clock signal NCLK2 having a high level is supplied.

[0216] The transistor M2 maintains the on state, and the transistor M5 maintains the off state. Therefore, the clock signal NCLK2 having a high level is output as the scanning signal GWNn having a high level.

[0217] According to some example embodiments, the pulse of the scan signal GWPn may overlap with some pulses of the clock signal NCLK2 for a portion of the time. The time at which the pulse of the scan signal GWPn is generated may be earlier than the time at which some pulses of the clock signal NCLK2 are generated. Fig.13 , it can be seen that the first falling pulse of the scan signal GWPn is generated at time t2c, and the rising pulse of the clock signal NCLK2 is generated at time t3c. That is, when the clock signal NCLK2 rises to a high level at time t3c, if the scan signal GWPn having a low level is not in a state in which the scan signal GWPn having a low level is supplied to the node N2, there is a risk that the voltage of the node N2 will rise due to the coupling of the capacitor C1. The transistor M2 may be turned off. Thus, according to some example embodiments, the on state of the transistor M2 at time t3c may be ensured.

[0218] At time t4c, the clock signal NCLK2 having a low level is supplied.

[0219] The transistor M2 maintains the on state, and the transistor M5 maintains the off state. Therefore, the clock signal NCLK2 having a low level is output as the scanning signal GWNn having a low level.

[0220] The voltage of the node N2 is lower than a low level due to the coupling of the capacitor C1. Therefore, the transistor M2 is stably kept in a turned-on state, and the driving characteristics of the transistor M2 can be improved.

[0221] Although a voltage lower than the low level is applied to one electrode of transistor M8, the voltage of the other electrode of transistor M8 is not lower than the low level. When a voltage lower than the low level is applied to one electrode of transistor M8 due to the coupling of capacitor C1, one electrode of transistor M8 is used as a drain electrode. In addition, because a voltage having a low level is applied to the gate electrode of transistor M8 through control line PENL, a voltage higher than the low level is applied to the source electrode of transistor M8 so that transistor M8 is turned on. Therefore, before the voltage of the source electrode of transistor M8 is lower than the low level, transistor M8 is turned off.

[0222] Thus, according to some example embodiments, although the capacitor C1 is coupled, the voltage of the other electrode of the transistor M8 is maintained so that the occurrence of a transient bias voltage applied to the transistor M4 can be prevented or reduced. Therefore, the life of the transistor M4 can be extended.

[0223] At time t5c, the clock signal PCLK1 having a low level is supplied.

[0224] Since the scan signal GWN(n-1) having a low level is supplied to the scan line GWNL(n-1), the voltage of the node N1 becomes a low level. Therefore, the transistors M1, M5, and M6 whose gate electrodes are coupled to the node N1 are turned on.

[0225] When the transistor M1 is turned on, the power line VGLL and the scan line GWNLn are coupled to each other. Therefore, the power voltage having a low level is output as the scan signal GWNn having a low level.

[0226] When the transistor M5 is turned on, the transistor M2 is diode-coupled. Therefore, although the clock signal NCLK2 having a high level is subsequently supplied, the voltage having a high level is not transmitted to the scan line GWNn.

[0227] When the transistor M6 is turned on, the clock line PCLKL2 and the node N3 are coupled to each other. Therefore, the clock signal PCLK2 having a high level is applied to one electrode of the capacitor C2.

[0228] At time t6c, the clock signal PCLK2 having a low level is supplied.

[0229] Since the transistor M6 is in the on state, one electrode of the capacitor C2 and the clock line PCLKL2 are coupled to each other, and the voltage of the node N1 is lower than the low level due to the coupling of the capacitor C2. Thus, the transistor M1 is stably kept in the on state, and the driving characteristics of the transistor M1 can be improved.

[0230] Although a voltage lower than the low level is applied to the node N1 corresponding to one electrode of the transistor M9, the voltage of the other electrode of the transistor M9 is not lower than the low level. When a voltage lower than the low level is applied to one electrode of the transistor M9 due to the coupling of the capacitor C2, one electrode of the transistor M9 is used as a drain electrode. Therefore, the other electrode of the transistor M9 is used as a source electrode. In addition, because a voltage with a low level is applied to the gate electrode of the transistor M9 through the power line VGLL, a voltage higher than the low level is applied to the source electrode of the transistor M9 so that the transistor M9 is turned on. A voltage with a low level is applied to the source electrode of the transistor M9 at the current time, and therefore, the transistor M9 is in a cut-off state.

[0231] Thus, according to some example embodiments, although the capacitor C2 is coupled, the voltage of the other electrode of the transistor M9 is maintained so as to prevent a transient bias voltage from being applied to the transistor M3. Therefore, the life of the transistor M3 may be extended.

[0232] In this embodiment, the case where the number of pulses of each scanning signal is three is shown. This is a driving method for applying a conduction bias voltage to the driving transistor of each pixel multiple times. In another embodiment, when the number of pulses of the scanning start signal is as follows: Figure 4 As shown in FIG. 1 , the number of pulses of each scanning signal may be one.

[0233] Fig.14 is a diagram illustrating pixels according to some example embodiments of the present disclosure.

[0234] refer to Fig.14 , a pixel PXnm according to some example embodiments of the present disclosure includes transistors T1 to T7 , a storage capacitor Cst, and a light emitting diode LD.

[0235] One electrode of transistor T1 may be coupled to one electrode of transistor T2, the other electrode of transistor T1 may be coupled to one electrode of transistor T3, and the gate electrode of transistor T1 may be coupled to the other electrode of transistor T3. Transistor T1 may be referred to as a driving transistor.

[0236] One electrode of transistor T2 may be coupled to one electrode of transistor T1, the other electrode of transistor T2 may be coupled to data line DLm, and the gate electrode of transistor T2 may be coupled to scan line GWPLn. Transistor T2 may be referred to as a switching transistor or a scan transistor, etc.

[0237] One electrode of the transistor T3 may be coupled to the other electrode of the transistor T1, the other electrode of the transistor T3 may be coupled to the gate electrode of the transistor T1, and the gate electrode of the transistor T3 may be coupled to the scan line GWNLn. The transistor T3 may be referred to as a diode-coupled transistor.

[0238] One electrode of the transistor T4 may be coupled to the other electrode of the capacitor Cst, the other electrode of the transistor T4 may be coupled to the initialization line VINTL, and the gate electrode of the transistor T4 may be coupled to the scan line GILn. The transistor T4 may be referred to as a gate initialization transistor.

[0239] One electrode of the transistor T5 may be coupled to the power line ELVDDL, the other electrode of the transistor T5 may be coupled to one electrode of the transistor T1, and the gate electrode of the transistor T5 may be coupled to the emission line ELn. The transistor T5 may be referred to as a first light emitting transistor.

[0240] One electrode of the transistor T6 may be coupled to the other electrode of the transistor T1, the other electrode of the transistor T6 may be coupled to the anode of the light emitting diode LD, and the gate electrode of the transistor T6 may be coupled to the emission line ELn. The transistor T6 may be referred to as a second light emitting transistor.

[0241] One electrode of the transistor T7 may be coupled to the anode of the light emitting diode LD, the other electrode of the transistor T7 may be coupled to the initialization line VINTL, and the gate electrode of the transistor T7 may be coupled to the scan line GBLn. The transistor T7 may be referred to as an anode initialization transistor.

[0242] One electrode of the storage capacitor Cst may be coupled to the power line ELVDDL, and the other electrode of the storage capacitor Cst may be coupled to the gate electrode of the transistor T1 .

[0243] The anode of the light emitting diode LD can be coupled to the other electrode of the transistor T6, and the cathode of the light emitting diode LD can be coupled to the power line ELVSSL. The voltage applied to the power line ELVSSL can be set to be lower than the voltage applied to the power line ELVDDL. The light emitting diode LD can be an organic light emitting diode or a nano light emitting diode, etc.

[0244] The transistors T1, T2, T5, T6 and T7 may be P-type transistors. The channels of the transistors T1, T2, T5, T6 and T7 may be configured with polysilicon. The polysilicon transistors may be low temperature polysilicon (LTPS) transistors. Polysilicon transistors have high electron mobility and therefore have fast driving characteristics.

[0245] Transistors T3 and T4 may be N-type transistors. The channels of transistors T3 and T4 may be configured with oxide semiconductors. Oxide semiconductor transistors may be formed by low temperature processing and have a charge mobility lower than that of polysilicon transistors. Therefore, compared with polysilicon transistors, oxide semiconductor transistors have a small amount of leakage current in the off state.

[0246] In some embodiments, the transistor T7 may be configured as an N-type oxide semiconductor transistor instead of a polysilicon transistor. Instead of the scan line GBLn, one of the scan lines GWNLn and GILn may be coupled to the gate electrode of the transistor T7.

[0247] Fig.15 is a diagram illustrating a high frequency driving method according to some example embodiments of the present disclosure.

[0248] When the display device 9 is driven by a high frequency driving method, it can be indicated that the display device 9 is in the first driving mode. In addition, when the display device 9 is driven by a low frequency driving method, it can be indicated that the display device 9 is in the second driving mode.

[0249] The first driving mode may be a normal driving mode, that is, when a user uses the display device 9, image frames may be displayed at a frequency not less than 20 Hz (eg, 60 Hz).

[0250] The second driving mode may be a low power driving mode. For example, when the user is not using the display device 9, the image frame may be displayed at less than 20 Hz (e.g., 1 Hz). For example, the case where only the time and date are displayed in the "always on mode" of the business model may correspond to the second driving mode.

[0251] In the first driving mode, a cycle may include a plurality of image frames. A cycle is an arbitrarily defined period and is defined as a period for comparing the first driving mode with the second driving mode. In the first driving mode and the second driving mode, a cycle may refer to the same time interval.

[0252] In the first driving mode, each image frame may include a data writing period WP and an emission period EP.

[0253] In the first driving mode, the control signal PEN applied to the control line PENL may maintain a turn-on level during one period including a plurality of image frames. Figure 6 and Fig.12 , the transistor M8 whose gate electrode is coupled to the control line PENL is an N-type transistor, and therefore, the conduction level may be a low level.

[0254] When the control signal PEN maintains the on level, the Figure 7 and Fig.13 The driving method described in the above is applied to a plurality of image frames in one cycle. Therefore, the scan driver 30Nb can output a scan signal having an on level in a plurality of image frames.

[0255] In the following, reference will be made to Fig.16 The driving method of the pixel PXnm for one arbitrary image frame in one cycle is described. The same driving method can also be applied to other image frames in one cycle, so repeated description will be omitted.

[0256] Fig.16 is a diagram illustrating a data writing period of a pixel according to some example embodiments of the present disclosure.

[0257] As described above, in the first driving mode, one image frame may include a data writing period WP and an emission period EP. However, the data writing period WP and the emission period EP of this embodiment are related to a specific pixel PXnm, and therefore, the data writing period and the emission period of another pixel coupled to another scan line may be different from the data writing period and the emission period of the pixel PXnm.

[0258] First, the emission signal En having a turn-off level (high level) may be supplied to the emission line ELn during the data writing period WP. Therefore, the transistors T5 and T6 may be in a turn-off state during the data writing period WP.

[0259] Next, a first pulse having a conduction level (high level) is supplied to the scan line GILn. Therefore, the transistor T4 is turned on, and the gate electrode of the transistor T1 and the initialization line VINTL are coupled to each other. Therefore, the voltage of the gate electrode of the transistor T1 is initialized to the initialization voltage of the initialization line VINTL and is maintained by the storage capacitor Cst. For example, the initialization voltage of the initialization line VINTL may be a voltage sufficiently lower than the voltage of the power line ELVDDL. For example, the initialization voltage may be a voltage having a level similar to the level of the voltage of the power line ELVSSL.

[0260] Next, the first pulse with the on level is supplied to the scan lines GWPLn and GWNLn, and the corresponding transistors T2 and T3 are turned on. Therefore, the data voltage applied to the data line DLm is written into the storage capacitor Cst through the transistors T2, T1 and T3. However, the data voltage is the data voltage of the previous pixel before the previous one. The data voltage is not used for the emission of the pixel PXnm, but is used to apply the on bias voltage to the transistor T1. When the on bias voltage is applied before the actual data voltage is written to the transistor T1, the hysteresis phenomenon can be prevented.

[0261] Next, the first pulse having a turn-on level (low level) is supplied to the scanning line GBLn, and the transistor T7 is turned on. Therefore, the anode voltage of the light emitting diode LD is initialized.

[0262] A second pulse having an on level (high level) is supplied to the scanning line GILn, and the above-mentioned driving process is performed again. That is, the on bias voltage is applied to the transistor T1 again, and the anode voltage of the light emitting diode LD is initialized.

[0263] When the third pulse having the on level is supplied to the scan lines GWPLn and GWNLn by repeating the above process, the data voltage of the pixel PXnm is written into the storage capacitor Cst. The data voltage written into the storage capacitor Cst is a voltage obtained by reflecting the reduction amount of the threshold voltage of the transistor T1.

[0264] Finally, when the emission signal En becomes a conduction level (low level), transistors T5 and T6 become a conduction state. Therefore, a drive current path is formed, through which the power line ELVDDL, transistors T5, T1 and T6, the light emitting diode LD and the power line ELVSSL are coupled, and the drive current flows through the drive current path. The amount of the drive current corresponds to the data voltage stored in the storage capacitor Cst. Because the drive current flows through the transistor T1, the reduction in the threshold voltage of the transistor T1 is reflected. Therefore, the reduction in the threshold voltage of the data voltage stored in the storage capacitor Cst and the reduction in the threshold voltage reflected in the drive current offset each other, so that regardless of the threshold voltage of the transistor T1, the drive current corresponding to the data voltage can flow.

[0265] The light emitting diode LD emits light having desired brightness according to the amount of driving current.

[0266] In some example embodiments, a case where each scan signal includes three pulses is described. However, according to some example embodiments, each scan signal may include two or four or more pulses. In addition, according to some example embodiments, each scan signal may be configured to include one pulse, and therefore, the process of applying the on-bias voltage to the transistor T1 is omitted.

[0267] Fig.17 is a diagram illustrating a low frequency driving method according to some example embodiments of the present disclosure.

[0268] In the second driving mode, one image frame in one cycle includes a data writing period WP and an emission period EP, and each of the other image frames in one cycle includes a bias period BP and an emission period EP.

[0269] In the second driving mode, the control signal PEN may maintain an on level (low level) during a partial period of one image frame in one cycle, and maintain an off level (high level) in the other image frames in one cycle.

[0270] The control signal PEN has an image frame reference of the on level Fig.15 and Fig.16 Description shown.

[0271] When the control signal PEN having the cut-off level is supplied, the reference Figure 6 and Fig.12 , the node N2 continuously maintains a high level, and the transistor M2 maintains a turned-off state. Therefore, the scan driver 30Nb does not output a scan signal having an on level in other image frames in one cycle.

[0272] Thus, the transistors T3 and T4 of the pixel PXnm maintain an off state in other image frames in one cycle, and thus the storage capacitor Cst maintains the same data voltage during multiple image frames. Specifically, the transistors T3 and T4 may be configured as oxide semiconductor transistors, thereby minimizing leakage current.

[0273] Therefore, the pixels PXnm may display the same image during one cycle based on the data voltage supplied during the data writing period WP of one image frame in one cycle.

[0274] Fig.18 is a diagram illustrating a low frequency driving method according to some example embodiments of the present disclosure.

[0275] refer to Fig.18 , the control signal PEN maintains an on level during one cycle. The clock signal NCLK input to the clock line includes a pulse during a partial period of one image frame in one cycle, and does not include a pulse in other image frames in one cycle.

[0276] For example, the clock signal NCLK may correspond to clock signals NCLK1, NCLK2, NCLK3, and NCLK4. That is, in the present embodiment, the transistor M8 of each scanning stage maintains a conductive state, and the clock signals NCLK1, NCLK2, NCLK3, and NCLK4 having a conductive level (high level) are not supplied to one electrode of the transistor M2, so that the scanning driver 30Nb does not output a scanning signal having a conductive level in other image frames in one cycle.

[0277] Thus, the transistors T3 and T4 of the pixel PXnm maintain the off state in other image frames in one cycle. Therefore, the pixel PXnm can display the same image during one cycle based on the data voltage supplied during the data writing period WP of one image frame in one cycle.

[0278] Fig.19 is a diagram illustrating a bias period of a pixel according to some example embodiments of the present disclosure.

[0279] refer to Fig.19 , in the bias period BP, the scan signals GIn and GWNn having the off level (low level) are supplied. Therefore, as described above, the data voltage stored in the storage capacitor Cst does not change in the bias period BP.

[0280] However, in the bias period BP and the data writing period WP, ​​the same emission signal En and the same scanning signals GWPn and GBn are supplied. A reference data voltage may be applied to the data line DLm. For this reason, the wavelengths of light output from the light emitting diode LD are similar to each other between multiple frames of a cycle, so that in low-frequency driving, the user does not see flicker.

[0281] According to some example embodiments of the present disclosure, the scan driver may supply a scan signal having a turn-on level for an N-type transistor.

[0282] Various aspects of certain example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art from the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless specifically indicated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the present disclosure and its equivalents.

Claims

1. A scanning driver, wherein: The scanning driver comprises: a first transistor having a first electrode coupled to the output scan line, a second electrode coupled to the first power line, and a gate electrode coupled to the first node; a second transistor having a first electrode coupled to the first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to the second node; a third transistor having a first electrode coupled to the first node, a second electrode coupled to the first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor having a first electrode coupled to the second node and a second electrode and a gate electrode coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other, The pulse of the first scan signal input to the first input scan line has a phase faster than the phase of the pulse of the second scan signal input to the second input scan line.

2. The scan driver according to claim 1, wherein: The scanning driver further comprises: a fifth transistor having a first electrode coupled to the first clock line, a second electrode coupled to the second node, and a gate electrode coupled to the first node; and A first capacitor has a first electrode coupled to the first clock line and a second electrode coupled to the second node.

3. The scan driver according to claim 2, wherein: The scanning driver further comprises: a second capacitor having a first electrode coupled to the third node and a second electrode coupled to the first node; and A sixth transistor has a first electrode coupled to the third node, a second electrode coupled to a third clock line, and a gate electrode coupled to the first node.

4. The scan driver according to claim 3, wherein: The scan driver also includes a seventh transistor having a first electrode coupled to the second power line, a second electrode coupled to the third node, and a gate electrode coupled to a fourth clock line.

5. The scan driver according to claim 3, wherein: The scan driver also includes a seventh transistor having a first electrode coupled to the third clock line, a second electrode coupled to the third node, and a gate electrode coupled to a fourth clock line.

6. The scan driver according to claim 4, wherein: The scan driver further includes an eighth transistor having a first electrode coupled to the second node, a second electrode coupled to the first electrode of the fourth transistor, and a gate electrode coupled to a control line.

7. The scan driver according to claim 6, wherein: The scan driver further includes a ninth transistor having a first electrode coupled to the first node, a second electrode coupled to the first electrode of the third transistor, and a gate electrode coupled to the first power line.

8. The scan driver according to claim 7, wherein: The scanning driver further comprises: a tenth transistor having a first electrode coupled to the second power line, a second electrode coupled to the second electrode of the fourth transistor, and a gate electrode coupled to the second input scan line; and an eleventh transistor having a first electrode coupled to the second electrode of the fourth transistor, a second electrode coupled to the first power line, and a gate electrode coupled to the second input scan line.

9. The scan driver according to claim 6, wherein: The pulses of the second scanning signal overlap with some pulses of the first clock signal input to the first clock line for a portion of time.

10. The scan driver according to claim 9, wherein: The pulses of the second scanning signal are generated at a time earlier than the time at which the some pulses of the first clock signal are generated.

11. The scan driver according to claim 10, wherein: The second clock signal input to the second clock line has the same cycle length as the third clock signal input to the third clock line, but has a phase faster than that of the third clock signal.

12. The scan driver according to claim 11, wherein: the pulses of the first clock signal have a polarity opposite to that of the pulses of the third clock signal, wherein the pulse of the first clock signal and the pulse of the third clock signal overlap each other for a portion of the time, and wherein the pulse of the first clock signal has a phase delayed from a phase of the pulse of the third clock signal.

13. The scan driver according to claim 12, wherein: inputting a fourth clock signal to the fourth clock line, wherein the pulse of the fourth clock signal has a polarity opposite to the polarity of the pulse of the first clock signal, wherein the pulse of the fourth clock signal and the pulse of the first clock signal overlap each other for a portion of the time, and wherein the pulse of the fourth clock signal has a phase delayed from a phase of the pulse of the first clock signal.

14. The scan driver according to claim 11, wherein: the pulses of the first clock signal have a polarity opposite to the polarity of the pulses of the third clock signal, wherein the pulse of the first clock signal is generated at the time when the pulse of the third clock signal is generated, and The time at which the pulse of the first clock signal is generated is delayed from the time at which the pulse of the third clock signal is generated.

15. The scan driver according to claim 14, wherein: inputting a fourth clock signal to the fourth clock line, wherein the pulses of the fourth clock signal have a polarity opposite to that of the pulses of the first clock signal, and The pulse of the fourth clock signal does not overlap with the pulse of the first clock signal in time.

16. The scan driver according to claim 6, wherein: In the first driving mode, the control signal applied to the control line maintains a turn-on level during one period including a plurality of image frames.

17. The scan driver according to claim 16, wherein: In a second driving mode different from the first driving mode, the control signal maintains the on-level during a partial period of one image frame in the one cycle, and maintains the off-level in other image frames in the one cycle.

18. The scan driver according to claim 16, wherein: In a second driving mode different from the first driving mode, the control signal maintains the conduction level during the one period, The first clock signal input to the first clock line includes a pulse during a partial period of one image frame in the one cycle, and does not include the pulse in other image frames in the one cycle.

19. The scan driver according to claim 9, wherein: The pulse of the first scan signal input to the first input scan line has a phase faster than a phase of the pulse of the second scan signal input to the second input scan line, and The pulse of the first scanning signal and the pulse of the second scanning signal have the same polarity.

Images