Method for managing a plurality of tasks by a multicore motor vehicle processor
A computer and motor vehicle technology, applied in computing, multi-programming device, program control design, etc., can solve problems such as processing speed change, system response speed reduction, slow software operation, etc.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Publication Date
- 2020-07-31
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Abstract
Description
technical field
[0001] The present invention relates to the field of on-board computers in motor vehicles, and more particularly to a method for managing multiple tasks by a multi-core microcontroller on-board in a motor vehicle. Background technique
[0002] As is known, motor vehicles today comprise a plurality of computers for performing various functions, such as, inter alia, controlling the engine of the vehicle. Each computer includes at least one processor or microcontroller that executes one or more software to perform the desired functions.
[0003] Software defines a number of functions to be performed in a definite sequence, or based on input data received or output data generated.
[0004] When software is executed on a processor or microcontroller with multiple cores, functional processing occurs in parallel on each core. To this end, each function is divided into multiple tasks, each task is performed by a core.
[0005] Some functions are called "regular (r...
Examples
Embodiment Construction
[0037] The invention is intended to be implemented by a multi-core processor or microcontroller of a computer on board a motor vehicle in order to manage the tasks related to the running of the vehicle, in particular its engine or engines.
[0038] To illustrate the invention, figure 2 A computer 1 comprising a microcontroller 10 is schematically shown. The microcontroller 10 includes three cores C1 , C2 , C3 and a memory area 100 .
[0039] It is to be pointed out that the invention can equally be implemented by a microcontroller or a processor comprising two or more cores. Also, as a variant, it is pointed out that the memory area 100 can be external to the microcontroller and can be located in another part of the computer 1 or outside the computer 1 .
[0040] In the multi-core microcontroller 10, each core C1, C2, C3 is configured to sequentially process tasks, each task being characterized by an identifier T1, T2, T3, T4, T5, T6, T7, T8, T9.
[0041] It is exemplified...