Display device

Abstract

A display device includes: a display panel that displays an image based on input image data; a drive controller that determines a low-frequency driving mode and a normal driving mode based on the input image data; a gate driver that outputs a gate signal; a data driver that outputs a data voltage; and a power supply voltage generator that outputs a power supply voltage. The drive controller is configured to generate a write frame for writing data in pixels of the display panel and a hold frame for maintaining the written data without writing data in the pixels in the low-frequency driving mode. The drive controller is configured to operate at least one of the drive controller, the data driver, and the power supply voltage generator in a power reduction mode during the hold frame.

Description

Technical Field

[0001] Exemplary embodiments of the inventive concept relate to a display device and a method of driving a display panel using the same. More particularly, exemplary embodiments of the inventive concept relate to a display device capable of reducing power consumption and a method of driving a display panel using the same. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel displays an image based on input image data. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. The display panel driver includes a gate driver, a data driver, and a drive controller. The gate driver outputs a gate signal to the plurality of gate lines. The data driver outputs a data voltage to the plurality of data lines. The drive controller controls the gate driver and the data driver.

[0003] When the display panel is driven at a fixed frequency regardless of input image data, power consumption may be high. When the display panel is used in a mobile device and power consumption is high, the use time of the mobile device may be limited. Summary of the invention

[0004] According to an exemplary embodiment of the present invention, a display device includes: a display panel, a driving controller, a gate driver, a data driver and a power supply voltage generator. The display panel is configured to display an image based on input image data. The driving controller is configured to determine a low-frequency driving mode and a normal driving mode based on the input image data. The gate driver is configured to output a gate signal to the display panel. The data driver is configured to output a data voltage to the display panel. The power supply voltage generator is configured to output a power supply voltage to the driving controller, the gate driver and the data driver. The driving controller is configured to generate a write frame for writing data in pixels of the display panel and a hold frame for maintaining the written data without writing data in the pixels in the low-frequency driving mode. The driving controller is configured to operate at least one of the driving controller, the data driver and the power supply voltage generator in a power reduction mode during the hold frame.

[0005] In an exemplary embodiment of the present inventive concept, the driving controller may include: a receiver configured to receive input image data and an input control signal; a frequency determiner configured to determine a driving frequency and a power reduction mode based on the input image data; a signal generator configured to generate a gate control signal for controlling a gate driver and a data control signal for controlling a data driver based on the driving frequency and the input control signal; and a data compensator configured to generate a data signal based on the driving frequency and the input image data.

[0006] In an exemplary embodiment of the inventive concept, an input buffer of a receiver may be configured to be turned off in a power reduction mode.

[0007] In an exemplary embodiment of the inventive concept, the power voltage generator may be configured not to output at least one of the power voltages in the power down mode.

[0008] In an exemplary embodiment of the inventive concept, the power voltage generator may be configured not to output some of the power voltages in the first power reduction mode. The power voltage generator may be configured not to output all of the power voltages in the second power reduction mode.

[0009] In an exemplary embodiment of the present invention, the power supply voltage generator may include: a first voltage generator configured to generate an oscillator voltage for operating an oscillator that generates a clock signal for a driving controller; a second voltage generator configured to generate a logic voltage for operating the driving controller; a third voltage generator configured to generate a memory voltage for operating a memory used by the driving controller; a fourth voltage generator configured to generate a signal transmission voltage for transmitting a signal between the driving controller and a data driver; and a fifth voltage generator configured to generate a data power supply voltage for operating the data driver.

[0010] In an exemplary embodiment of the present inventive concept, in a first power reduction mode, a first switch connected to the first voltage generator, a third switch connected to the third voltage generator, and a fifth switch connected to the fifth voltage generator may be configured to be opened, and a second switch connected to the second voltage generator and a fourth switch connected to the fourth voltage generator may be configured to be closed.

[0011] In an exemplary embodiment of the present inventive concept, in the second power reduction mode, a first switch connected to the first voltage generator, a second switch connected to the second voltage generator, a third switch connected to the third voltage generator, a fourth switch connected to the fourth voltage generator, and a fifth switch connected to the fifth voltage generator may be configured to be turned on.

[0012] In an exemplary embodiment of the inventive concept, an output buffer of a data driver may be configured to be turned off in a power down mode.

[0013] In an exemplary embodiment of the inventive concept, the data driver may include: a plurality of current sources connected in parallel to each other; a plurality of current switches connected in series to the plurality of current sources, respectively; a first transistor connected to the plurality of current switches; and a second transistor connected to the first transistor and an output buffer. The plurality of current switches may be configured to be turned on in a power reduction mode.

[0014] In an exemplary embodiment of the inventive concept, the driving controller may be configured to generate a synchronization signal having a valid pulse in a hold frame prior to a write frame in a power down mode.

[0015] In an exemplary embodiment of the inventive concept, the driving controller may be configured to generate a synchronization signal having a plurality of valid pulses in a hold frame prior to a write frame in a power down mode.

[0016] In an exemplary embodiment of the inventive concept, a pixel may include a first type of switching element and a second type of switching element different from the first type.

[0017] In an exemplary embodiment of the inventive concept, the second type switching element may be configured to be driven at a low driving frequency, and the first type switching element may be configured to be driven at a first driving frequency greater than the low driving frequency in a low frequency driving mode.

[0018] In an exemplary embodiment of the present inventive concept, the first type switching element and the second type switching element may be configured to be driven at a normal driving frequency greater than the low driving frequency in a normal driving mode.

[0019] In an exemplary embodiment of the present inventive concept, the first type switching element may be a polysilicon thin film transistor. The second type switching element may be an oxide thin film transistor.

[0020] In an exemplary embodiment of the inventive concept, the first type switching element may be a P-type transistor. The second type switching element may be an N-type transistor.

[0021] In an exemplary embodiment of the present inventive concept, a pixel may include: a first pixel switching element, the first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element, the second pixel switching element including a control electrode configured to receive a first data write gate signal, an input electrode configured to receive a data voltage, and an output electrode connected to the second node; a third pixel switching element, the third pixel switching element including a control electrode configured to receive a second data write gate signal, an input electrode connected to the first node, and an output electrode connected to the third node; a fourth pixel switching element, the fourth pixel switching element including a control electrode configured to receive a data initialization gate signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the first node; a fifth pixel switching element, The fifth pixel switching element includes a control electrode configured to receive an emission signal, an input electrode configured to receive a high power supply voltage, and an output electrode connected to a second node; a sixth pixel switching element, the sixth pixel switching element includes a control electrode configured to receive an emission signal, an input electrode connected to a third node, and an output electrode connected to an anode of an organic light-emitting element; a seventh pixel switching element, the seventh pixel switching element includes a control electrode configured to receive an organic light-emitting element initialization signal, an input electrode configured to receive an initialization voltage, and an output electrode connected to the anode of the organic light-emitting element; a storage capacitor, the storage capacitor includes a first electrode configured to receive a high power supply voltage and a second electrode connected to the first node; and an organic light-emitting element, the organic light-emitting element including an anode connected to the output electrode of the sixth pixel switching element and a cathode configured to receive a low power supply voltage.

[0022] In an exemplary embodiment of the present inventive concept, the first pixel switching element, the second pixel switching element, the fifth pixel switching element and the sixth pixel switching element may be polysilicon thin film transistors. The third pixel switching element, the fourth pixel switching element and the seventh pixel switching element may be oxide thin film transistors.

[0023] According to an exemplary embodiment of the present invention, a method for driving a display panel includes: using a driving controller to determine a low-frequency driving mode and a normal driving mode based on input image data; using a gate driver to output a gate signal to the display panel according to the low-frequency driving mode and the normal driving mode; and using a data driver to output a data voltage to the display panel according to the low-frequency driving mode and the normal driving mode. The driving controller is configured to generate a writing frame for writing data in pixels of the display panel and a holding frame for maintaining the written data without writing data in the pixels in the low-frequency driving mode. The driving controller is configured to operate at least one of the driving controller, the data driver, and the power supply voltage generator in a power reduction mode during the holding frame.

[0024] According to an exemplary embodiment of the inventive concept, a method of driving a display panel including pixels includes: receiving a second data write gate signal and a data initialization gate signal through the pixel, the second data write gate signal and the data initialization gate signal each having a first frequency; receiving a first data write gate signal, an emission signal, and an organic light emitting element initialization signal through the pixel, the first data write gate signal, the emission signal, and the organic light emitting element initialization signal each having a second frequency greater than the first frequency; periodically deactivating the emission signal during an emission off duration; activating the first data write gate signal, the data initialization gate signal, the second data write gate signal, and the organic light emitting element initialization signal during an emission off duration of a write frame; and activating the first data write gate signal and the organic light emitting element initialization signal during an emission off duration of a hold frame. During the emission off duration of the hold frame, the data initialization gate signal and the second data write gate signal remain inactive. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0026] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0027] Figure 2 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 Block diagram of the drive controller.

[0028] Figure 3A is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 Schematic diagram of the operation of the supply voltage generator in a first power reduction mode.

[0029] Figure 3B is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 Schematic diagram of the operation of the supply voltage generator in the second power reduction mode.

[0030] Figure 4 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 Schematic diagram of the operation of the receiver of the driving controller in the power reduction mode.

[0031] Figure 5 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 Schematic diagram of the operation of a data driver in a power reduction mode.

[0032] Figure 6is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 5 Circuit diagram of the output buffer operating in power reduction mode.

[0033] Figure 7 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 A timing diagram of the operation of the driving controller according to the input image data.

[0034] Figure 8 is a timing diagram illustrating an operation of a driving controller of a display device according to an exemplary embodiment of the inventive concept according to input image data.

[0035] Fig. 9 is a timing diagram illustrating an operation of a driving controller of a display device according to an exemplary embodiment of the inventive concept according to input image data.

[0036] Fig.10 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0037] Fig.11 is a diagram illustrating an exemplary embodiment according to the inventive concept Fig.10 Circuit diagram of a pixel of a display panel.

[0038] Fig.12 is a diagram illustrating an exemplary embodiment according to the inventive concept applied to Fig.11 Timing diagram of the pixel input signal.

[0039] Fig.13 is a diagram illustrating a circuit applied to a Fig.11 A timing diagram of the input signals to the pixels of the display panel. DETAILED DESCRIPTION

[0040] Exemplary embodiments of the inventive concept provide a display device that operates a display panel driver in a power reduction mode during a holding frame of a low frequency driving mode.

[0041] Exemplary embodiments of the inventive concept also provide a method of driving a display panel using the display device.

[0042] Hereinafter, exemplary embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.Throughout the application, the same reference numerals may refer to the same elements.

[0043] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0044] refer to Figure 1The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display device may further include a host 700 and a power supply voltage generator 800.

[0045] For example, the driving controller 200 and the data driver 500 may be integrally formed. For example, the driving controller 200, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed. For example, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed. For example, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400, the data driver 500, and the power supply voltage generator 800 may be integrally formed.

[0046] The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0047] For example, the display panel 100 may be a liquid crystal display panel including liquid crystal molecules. Alternatively, the display panel 100 may be an organic light emitting diode display panel including organic light emitting diodes.

[0048] The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 crossing the first direction D1.

[0049] The driving controller 200 receives input image data IMG and input control signal CONT from the host 700. The input image data IMG may include red image data, green image data and blue image data. The input image data IMG may include white image data. The input image data IMG may also include magenta image data, yellow image data and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0050] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0051] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0052] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0053] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0054] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0055] The gate driver 300 generates a gate signal driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 outputs the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to the gate line GL.

[0056] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0057] In an exemplary embodiment of the inventive concept, the gamma reference voltage generator 400 may be disposed in the driving controller 200 or may be disposed in the data driver 500 .

[0058] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage of an analog type using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0059] The host 700 may output input image data IMG and an input control signal CONT to the driving controller 200 .

[0060] The power supply voltage generator 800 outputs power supply voltages for the display panel 100, the driving controller 200, the gate driver 300, and the data driver 500. For example, the power supply voltage generator 800 may generate a logic voltage of the driving controller 200. For example, the power supply voltage generator 800 may generate a gate-on voltage and a gate-off voltage of the gate driver 300. For example, the power supply voltage generator 800 may generate a data power supply voltage of the data driver 500. For example, the power supply voltage generator 800 may generate a common voltage and a storage voltage of the display panel 100.

[0061] Figure 2 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 Block diagram of the drive controller.

[0062] refer to Figure 1 and Figure 2 , the driving controller 200 may include a receiver 220 , a frequency determiner 240 , a signal generator 260 , and a data compensator 280 .

[0063] The receiver 220 may receive input image data IMG and an input control signal CONT from the host 700. The receiver 220 may output the input image data IMG to the frequency determiner 240 and the data compensator 280. The receiver 220 may output the input control signal CONT to the signal generator 260.

[0064] The frequency determiner 240 may determine the driving frequency FR of the display device based on the input image data IMG. When the input image data IMG represents a video image, the driving frequency FR may be relatively high. When the input image data IMG represents a static image, the driving frequency FR may be relatively low.

[0065] The frequency determiner 240 may determine the low-frequency driving mode and the normal driving mode based on the input image data IMG. For example, when the input image data IMG represents a video image, the frequency determiner 240 may drive the display device in the normal driving mode. When the input image data IMG represents a static image, the frequency determiner 240 may drive the display device in the low-frequency driving mode.

[0066] In addition, the frequency determiner 240 may determine the low frequency driving mode and the normal driving mode based on the input mode of the display device. For example, when the input mode of the display device is the Always On Mode, the frequency determiner 240 may drive the display device in the low frequency driving mode.

[0067] The display panel 100 may be driven in units of frames. In the normal driving mode, the display panel 100 may be refreshed in each frame. Therefore, the normal driving mode only includes a writing frame in which data is written in pixels.

[0068] In the low frequency driving mode, the display panel 100 may be refreshed at a frequency of the low frequency driving mode. Therefore, the low frequency driving mode includes a writing frame for writing data in pixels and a holding frame for maintaining the written data without writing data in pixels.

[0069] For example, when the frequency of the normal driving mode is 60 Hz and the frequency of the low-frequency driving mode is 1 Hz, the low-frequency driving mode includes one write frame WRITE and fifty-nine hold frames HOLD in one second. For example, when the frequency of the normal driving mode is 60 Hz and the frequency of the low-frequency driving mode is 1 Hz, fifty-nine consecutive hold frames HOLD are arranged between two adjacent write frames WRITE.

[0070] For example, when the frequency of the normal driving mode is 60 Hz and the frequency of the low-frequency driving mode is 10 Hz, the low-frequency driving mode includes ten write frames WRITE and fifty hold frames HOLD in one second. For example, when the frequency of the normal driving mode is 60 Hz and the frequency of the low-frequency driving mode is 10 Hz, five consecutive hold frames HOLD are arranged between two adjacent write frames WRITE.

[0071] When the driving mode of the display device is the low frequency driving mode, the frequency determiner 240 may operate the display device in the power reduction mode. When the driving mode of the display device is the low frequency driving mode, the frequency determiner 240 may generate a power reduction signal BPC indicating the power reduction mode.

[0072] The frequency determiner 240 may output the driving frequency FR to the signal generator 260 and the data compensator 280 .

[0073] The frequency determiner 240 may output the power reduction signal BPC to at least one of the receiver 220 , the data driver 500 , the host 700 , and the power supply voltage generator 800 .

[0074] The signal generator 260 may generate a first control signal CONT1 based on the input control signal CONT and the driving frequency FR to control the operation of the gate driver 300, and output the first control signal CONT1 to the gate driver 300. The signal generator 260 may generate a second control signal CONT2 based on the input control signal CONT and the driving frequency FR to control the operation of the data driver 500, and output the second control signal CONT2 to the data driver 500. The signal generator 260 may generate a third control signal CONT3 based on the input control signal CONT and the driving frequency FR to control the operation of the gamma reference voltage generator 400, and output the third control signal CONT3 to the gamma reference voltage generator 400.

[0075] The data compensator 280 may generate a data signal DATA based on the input image data IMG and the driving frequency FR, and output the data signal DATA to the data driver 500. The data compensator 280 may compensate the input image data IMG to generate the data signal DATA. For example, the data compensator 280 may perform adaptive color correction using a gamma curve. For example, the data compensator 280 may perform dynamic capacitance compensation for compensating the current frame data using the previous frame data and the current frame data.

[0076] Figure 3A is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 Schematic diagram of the operation of the supply voltage generator in a first power reduction mode.

[0077] refer to Figures 1 to 3A , the power voltage generator 800 may receive the power reduction signal BPC from the frequency determiner 240 of the driving controller 200 .

[0078] In the power reduction mode, the power voltage generator 800 may not output at least one of the power voltages. Figure 3A As shown in , the power supply voltage generator 800 may be operated in a first power reduction mode. In the first power reduction mode, the power supply voltage generator 800 may not output some of the power supply voltages.

[0079] For example, the power supply voltage generator 800 may include a first voltage generator 810, a second voltage generator 820, a third voltage generator 830, a fourth voltage generator 840, and a fifth voltage generator 850. The first voltage generator 810 may generate an oscillator voltage VDDO for operating an oscillator that generates a clock signal of the drive controller 200. The second voltage generator 820 may generate a logic voltage VDDL for operating the drive controller 200. The third voltage generator 830 may generate a memory voltage VDDM for operating a memory. The fourth voltage generator 840 may generate a signal transmission voltage VDDI for transmitting a signal between the drive controller 200 and the data driver 500. The fifth voltage generator 850 may generate a data power supply voltage AVDD for operating the data driver 500. For example, the memory may store input image data IMG for operation of the data compensator 280. For example, the memory may be a frame memory. The signal transmission voltage VDDI may be a voltage for transmitting a signal in a differential mode.

[0080] For example, the oscillator voltage VDDO, the logic voltage VDDL, the memory voltage VDDM, and the signal transmission voltage VDDI may have a digital level. For example, the data power supply voltage AVDD may have an analog level greater than the digital level. For example, at least two of the oscillator voltage VDDO, the logic voltage VDDL, the memory voltage VDDM, and the signal transmission voltage VDDI may have substantially the same level. When at least two of the oscillator voltage VDDO, the logic voltage VDDL, the memory voltage VDDM, and the signal transmission voltage VDDI have substantially the same level, the first to fourth voltage generators 810, 820, 830, and 840 may be integrated in a single block.

[0081] In the first power reduction mode, the first switch S1 connected to the first voltage generator 810, the third switch S3 connected to the third voltage generator 830, and the fifth switch S5 connected to the fifth voltage generator 850 may be opened. In the first power reduction mode, the second switch S2 connected to the second voltage generator 820 and the fourth switch S4 connected to the fourth voltage generator 840 may be closed.

[0082] Figure 3B is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 Schematic diagram of the operation of the supply voltage generator in the second power reduction mode.

[0083] refer to Figures 1 to 3B In the power reduction mode, the power supply voltage generator 800 may not output all the power supply voltages. Figure 3BAs shown in , the power supply voltage generator 800 may be operated in the second power reduction mode. In the second power reduction mode, the power supply voltage generator 800 may not output all the power supply voltages.

[0084] In the second power reduction mode, the first switch S1 connected to the first voltage generator 810, the second switch S2 connected to the second voltage generator 820, the third switch S3 connected to the third voltage generator 830, the fourth switch S4 connected to the fourth voltage generator 840 and the fifth switch S5 connected to the fifth voltage generator 850 can be opened.

[0085] Figure 4 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 Schematic diagram of the operation of the receiver of the driving controller in the power reduction mode.

[0086] refer to Figure 1 , Figure 2 and Figure 4 , the operation of the receiver 220 may be disabled in the power reduction mode.

[0087] For example, the receiver 220 may include a plurality of input buffers IB1 to IBX for receiving input image data IMG. The input buffers IB1 to IBX of the receiver 220 may be turned off in the power reduction mode. For example, the input buffers IB1 to IBX of the receiver 220 may be turned off in response to the power reduction signal BPC.

[0088] In addition, when the receiver 220 is disabled in the power down mode, the host 700 may not output the input image data IMG to the receiver 220. For example, the host 700 may not output the input image data IMG to the receiver 220 in response to receiving the power down signal BPC from the frequency determiner 240.

[0089] Figure 5 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 Schematic diagram of the operation of a data driver in a power reduction mode. Figure 6 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 5 Circuit diagram of the output buffer operating in power reduction mode.

[0090] refer to Figure 1 , Figure 2 , Figure 5 and Figure 6 , the data driver 500 may include a shift register 520 , a latch 540 , a signal processor 560 , and a buffer 580 .

[0091] The shift register 520 outputs a latch pulse to the latch 540 .

[0092] The latch 540 temporarily stores the data signal DATA and outputs the data signal DATA.

[0093] The signal processor 560 converts the data signal DATA of a digital type into a data voltage of an analog type based on the data signal DATA and the gamma reference voltage VGREF. The signal processor 560 outputs the data voltage. For example, the signal processor 560 may include a first digital-to-analog converter that converts the data signal DATA into a data voltage of a first polarity and a second digital-to-analog converter that converts the data signal DATA into a data voltage of a second polarity opposite to the first polarity.

[0094] The buffer 580 buffers the data voltage output from the signal processor 560 and outputs the data voltage. The buffer 580 may include a plurality of output buffers OB1 to OBN that output the data voltage to the data lines.

[0095] The operation of the data driver 500 may be disabled in the power down mode. For example, the output buffers OB1 to OBN of the buffer 580 may be turned off in the power down mode. For example, the output buffers OB1 to OBN of the buffer 580 may be turned off in response to the power down signal BPC.

[0096] like Figure 6 As shown in the figure, the data driver 500 may include a plurality of current sources CS1, CS2, CS3 and CS4 connected in parallel to each other, a plurality of current switches SD1, SD2, SD3 and SD4 connected in series to the current sources CS1, CS2, CS3 and CS4, respectively, a first transistor TM1 connected to the current switches SD1, SD2, SD3 and SD4, and a second transistor TM2 connected to the first transistor TM1 and the output buffer OB.

[0097] Current sources CS1, CS2, CS3 and CS4, current switches SD1, SD2, SD3 and SD4, first transistor TM1 and second transistor TM2 may form a current mirror circuit so that current IREF flowing through first transistor TM1 may be equal to current IREF flowing through second transistor TM2.

[0098] For example, at least one of the current switches SD1, SD2, SD3, and SD4 may be turned on in the power reduction mode. For example, all of the current switches SD1, SD2, SD3, and SD4 may be turned on in the power reduction mode. When the current switches SD1, SD2, SD3, and SD4 are turned on, the data voltage VD may not be output from the output buffer OB.

[0099] According to an exemplary embodiment of the inventive concept, the current mirror circuit may be generally connected to Figure 5 Output buffers OB1 to OBN.

[0100] Figure 7 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 A timing diagram of the operation of the driving controller according to the input image data.

[0101] refer to Figures 1 to 7 , when the input image data IMG represents a video image, the drive controller 200 operates the display device in a normal drive mode. In the normal drive mode, data is written to the pixels of the display panel in each frame. The frame can be defined by the duration between adjacent rising edges of the vertical synchronization signal VSYNC.

[0102] In the normal driving mode, the input data enable signal IDE may be activated in each frame, and the output data enable signal ODE may be activated in each frame.

[0103] In the normal driving mode, the power reduction signal BPC_EN has an inactive level, and the display device is not operated in the power reduction mode (eg, the standby mode STBY).

[0104] When the input image data IMG represents a static image, the drive controller 200 operates the display device in the low-frequency drive mode. In the low-frequency drive mode, data may not be written to the pixels of the display panel in each frame. For example, when the driving frequency is 60 Hz in the normal drive mode and the driving frequency of the low-frequency drive mode is 20 Hz, one of the three adjacent frames may be a write frame, and the other two of the three adjacent frames may be hold frames.

[0105] In the low frequency driving mode, the input data enable signal IDE may be activated in every frame, and the output data enable signal ODE may be activated only in the write frame. In the low frequency driving mode, the output data enable signal ODE may be deactivated in the hold frame.

[0106] In the low frequency driving mode, the power reduction signal BPC_EN has an active level, and the display device is operated in a power reduction mode (eg, a standby mode STBY). Figure 7 The active level of the middle power down signal BPC_EN and the active level of the power down mode STBY are high levels, but the inventive concept is not limited thereto.

[0107] According to the present exemplary embodiment, during the holding frame of the low frequency driving mode, at least one of the receiver 220 of the driving controller 200, the output buffer OB of the data driver 500, and the power supply voltage generator 800 is operated in the power reduction mode, so that the power consumption of the display device can be reduced.

[0108] Figure 8 is a timing diagram illustrating an operation of a driving controller of a display device according to an exemplary embodiment of the inventive concept according to input image data.

[0109] The display device and the method of driving the display panel according to the present exemplary embodiment are similar to those of the reference 1 except that the signal is generated by the driving controller. Figures 1 to 7 The display device and the method of driving the display panel of the exemplary embodiments described are substantially the same. Therefore, the same reference numerals will be used to refer to the same Figures 1 to 7 The present invention relates to components that are the same as or similar to those described in the exemplary embodiments of the present invention, and any repeated explanation concerning the above elements will be omitted.

[0110] refer to Figures 1 to 6 as well as Figure 8 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400 and a data driver 500. The display device may further include a host 700. The display device may further include a power supply voltage generator 800.

[0111] The driving controller 200 may include a receiver 220 , a frequency determiner 240 , a signal generator 260 , and a data compensator 280 .

[0112] The frequency determiner 240 may determine the driving frequency FR of the display device based on the input image data IMG. When the input image data IMG represents a video image, the driving frequency FR may be relatively high. When the input image data IMG represents a static image, the driving frequency FR may be relatively low.

[0113] The frequency determiner 240 may determine the low-frequency driving mode and the normal driving mode based on the input image data IMG. For example, when the input image data IMG represents a video image, the frequency determiner 240 may drive the display device in the normal driving mode. For example, when the input image data IMG represents a static image, the frequency determiner 240 may drive the display device in the low-frequency driving mode.

[0114] In the power reduction mode, the power supply voltage generator 800 may not output at least one of the power supply voltages. Alternatively, in the power reduction mode, the power supply voltage generator 800 may not output all of the power supply voltages. The operation of the receiver 220 may be disabled in the power reduction mode. For example, the input buffers IB1 to IBX of the receiver 220 may be turned off in the power reduction mode. The operation of the data driver 500 may be disabled in the power reduction mode. For example, the output buffers OB1 to OBN of the buffer 580 may be turned off in the power reduction mode.

[0115] When the input image data IMG represents a video image, the driving controller 200 operates the display device in a normal driving mode. In the normal driving mode, data is written to pixels of the display panel in each frame.

[0116] When the input image data IMG represents a static image, the drive controller 200 operates the display device in the low-frequency drive mode. In the low-frequency drive mode, data may not be written to the pixels of the display panel in each frame. For example, when the driving frequency is 60 Hz in the normal drive mode and the driving frequency of the low-frequency drive mode is 20 Hz, one of the three adjacent frames may be a write frame, and the other two of the three adjacent frames may be hold frames.

[0117] In the low frequency driving mode, the input data enable signal IDE may be activated in every frame, and the output data enable signal ODE may be activated only in the write frame. In the low frequency driving mode, the output data enable signal ODE may be deactivated in the hold frame.

[0118] In the low frequency driving mode, the power reduction signal BPC_EN has an active level, and the display device is operated in a power reduction mode (eg, a standby mode STBY).

[0119] In the present exemplary embodiment, the drive controller 200 may generate the synchronization signal SYNC1 having a valid pulse in a hold frame immediately before a write frame in the power down mode STBY. Figure 8 The valid pulse of the synchronization signal SYNC1 has a low level, but the inventive concept is not limited thereto.

[0120] According to the present exemplary embodiment, during the holding frame of the low frequency driving mode, at least one of the receiver 220 of the driving controller 200, the output buffer OB of the data driver 500, and the power supply voltage generator 800 is operated in the power reduction mode, so that the power consumption of the display device can be reduced.

[0121] Fig. 9is a timing diagram illustrating an operation of a driving controller of a display device according to an exemplary embodiment of the inventive concept according to input image data.

[0122] The display device and the method of driving the display panel according to the present exemplary embodiment are similar to those of the reference 1 except that the signal is generated by the driving controller. Figures 1 to 7 The display device and the method of driving the display panel of the exemplary embodiments described are substantially the same. Therefore, the same reference numerals will be used to refer to the same Figures 1 to 7 The present invention relates to components that are the same as or similar to those described in the exemplary embodiments of the present invention, and any repeated explanation concerning the above elements will be omitted.

[0123] refer to Figures 1 to 6 as well as Fig. 9 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400 and a data driver 500. The display device may further include a host 700. The display device may further include a power supply voltage generator 800.

[0124] The driving controller 200 may include a receiver 220 , a frequency determiner 240 , a signal generator 260 , and a data compensator 280 .

[0125] The frequency determiner 240 may determine the driving frequency FR of the display device based on the input image data IMG. When the input image data IMG represents a video image, the driving frequency FR may be relatively high. When the input image data IMG represents a static image, the driving frequency FR may be relatively low.

[0126] The frequency determiner 240 may determine the low-frequency driving mode and the normal driving mode based on the input image data IMG. For example, when the input image data IMG represents a video image, the frequency determiner 240 may drive the display device in the normal driving mode. For example, when the input image data IMG represents a static image, the frequency determiner 240 may drive the display device in the low-frequency driving mode.

[0127] In the power reduction mode, the power supply voltage generator 800 may not output at least one of the power supply voltages. Alternatively, in the power reduction mode, the power supply voltage generator 800 may not output all of the power supply voltages. The operation of the receiver 220 may be disabled in the power reduction mode. For example, the input buffers IB1 to IBX of the receiver 220 may be turned off in the power reduction mode. The operation of the data driver 500 may be disabled in the power reduction mode. For example, the output buffers OB1 to OBN of the buffer 580 may be turned off in the power reduction mode.

[0128] When the input image data IMG represents a video image, the driving controller 200 operates the display device in a normal driving mode. In the normal driving mode, data is written to pixels of the display panel in each frame.

[0129] When the input image data IMG represents a static image, the drive controller 200 operates the display device in the low-frequency drive mode. In the low-frequency drive mode, data may not be written to the pixels of the display panel in each frame. For example, when the driving frequency is 60 Hz in the normal drive mode and the driving frequency of the low-frequency drive mode is 20 Hz, one of the three adjacent frames may be a write frame, and the other two of the three adjacent frames may be hold frames.

[0130] In the low frequency driving mode, the input data enable signal IDE may be activated in every frame, and the output data enable signal ODE may be activated only in the write frame. In the low frequency driving mode, the output data enable signal ODE may be deactivated in the hold frame.

[0131] In the low frequency driving mode, the power reduction signal BPC_EN has an active level, and the display device is operated in a power reduction mode (eg, a standby mode STBY).

[0132] In the present exemplary embodiment, the drive controller 200 may generate the synchronization signal SYNC2 having a plurality of valid pulses in a hold frame immediately before a write frame in the power down mode STBY. Fig. 9 The valid pulse of the synchronization signal SYNC2 has a low level, but the inventive concept is not limited thereto.

[0133] According to the present exemplary embodiment, during the holding frame of the low frequency driving mode, at least one of the receiver 220 of the driving controller 200, the output buffer OB of the data driver 500, and the power supply voltage generator 800 is operated in the power reduction mode, so that the power consumption of the display device can be reduced.

[0134] Fig.10 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept. Fig.11 is a diagram illustrating an exemplary embodiment according to the inventive concept Fig.10 Circuit diagram of a pixel of a display panel. Fig.12 is a diagram illustrating an exemplary embodiment according to the inventive concept applied to Fig.11 Timing diagram of the pixel input signal. Fig.13 is a diagram illustrating a circuit applied to a Fig.11 A timing diagram of the input signals to the pixels of the display panel.

[0135] The display device and the method of driving the display panel according to the present exemplary embodiment are similar to those of the reference numerals except for the structure of the display panel, the signals generated by the gate driver and the emission driver. Figures 1 to 7 The display device and the method of driving the display panel of the exemplary embodiments described are substantially the same. Therefore, the same reference numerals will be used to refer to the same Figures 1 to 7 The present invention relates to components that are the same as or similar to those described in the exemplary embodiments of the present invention, and any repeated explanation concerning the above elements will be omitted.

[0136] refer to Figures 2 to 7 and Figures 10 to 13 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600. The display device may further include a host 700. The display device may further include a power supply voltage generator 800.

[0137] The display panel 100 includes a plurality of gate lines GWPL, GWNL, GIL, and GBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the gate lines GWPL, GWNL, GIL, and GBL, the data lines DL, and the emission lines EL. The gate lines GWPL, GWNL, GIL, and GBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EL may extend in the first direction D1.

[0138] The gate driver 300 generates a gate signal driving the gate lines GWPL, GWNL, GIL, and GBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may sequentially output the gate signal to the gate lines GWPL, GWNL, GIL, and GBL.

[0139] The emission driver 600 generates an emission signal to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission line EL.

[0140] The display panel 100 may include a plurality of pixels. Each of the pixels may include an organic light emitting diode OLED.

[0141] The pixel receives data write gate signals GWP and GWN, data initialization gate signal GI, organic light emitting element initialization signal GB, data voltage VDATA and emission signal EM, and the organic light emitting element OLED of the pixel emits light corresponding to the level of data voltage VDATA to display an image.

[0142] In this exemplary embodiment, the pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin film transistor. For example, the first type of switching element may be a low temperature polysilicon (LTPS) thin film transistor. For example, the second type of switching element may be an oxide thin film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0143] For example, the data write gate signal may include a first data write gate signal GWP and a second data write gate signal GWN. The first data write gate signal GWP may be applied to a P-type transistor so that the first data write gate signal GWP has a low-level activation signal corresponding to the data write timing. The second data write gate signal GWN may be applied to an N-type transistor so that the second data write gate signal GWN has a high-level activation signal corresponding to the data write timing.

[0144] At least one of the pixels may include first to seventh pixel switching elements T1 to T7 , a storage capacitor CST, and an organic light emitting element OLED.

[0145] The first pixel switching element T1 includes a control electrode connected to the first node N1, an input electrode connected to the second node N2, and an output electrode connected to the third node N3.

[0146] For example, the first pixel switch element T1 may be a polysilicon thin film transistor. For example, the first pixel switch element T1 may be a P-type thin film transistor. The control electrode of the first pixel switch element T1 may be a gate electrode, the input electrode of the first pixel switch element T1 may be a source electrode, and the output electrode of the first pixel switch element T1 may be a drain electrode.

[0147] The second pixel switching element T2 includes a control electrode to which the first data write gate signal GWP is applied, an input electrode to which the data voltage VDATA is applied, and an output electrode connected to the second node N2.

[0148] For example, the second pixel switch element T2 may be a polysilicon thin film transistor. For example, the second pixel switch element T2 may be a P-type thin film transistor. The control electrode of the second pixel switch element T2 may be a gate electrode, the input electrode of the second pixel switch element T2 may be a source electrode, and the output electrode of the second pixel switch element T2 may be a drain electrode.

[0149] The third pixel switching element T3 includes a control electrode to which the second data write gate signal GWN is applied, an input electrode connected to the first node N1 , and an output electrode connected to the third node N3 .

[0150] For example, the third pixel switch element T3 may be an oxide thin film transistor. For example, the third pixel switch element T3 may be an N-type thin film transistor. The control electrode of the third pixel switch element T3 may be a gate electrode, the input electrode of the third pixel switch element T3 may be a source electrode, and the output electrode of the third pixel switch element T3 may be a drain electrode.

[0151] The fourth pixel switching element T4 includes a control electrode to which the data initialization gate signal GI is applied, an input electrode to which the initialization voltage VI is applied, and an output electrode connected to the first node N1.

[0152] For example, the fourth pixel switch element T4 may be an oxide thin film transistor. For example, the fourth pixel switch element T4 may be an N-type thin film transistor. The control electrode of the fourth pixel switch element T4 may be a gate electrode, the input electrode of the fourth pixel switch element T4 may be a source electrode, and the output electrode of the fourth pixel switch element T4 may be a drain electrode.

[0153] The fifth pixel switching element T5 includes a control electrode to which the emission signal EM is applied, an input electrode to which the high power voltage ELVDD is applied, and an output electrode connected to the second node N2.

[0154] For example, the fifth pixel switch element T5 may be a polysilicon thin film transistor. For example, the fifth pixel switch element T5 may be a P-type thin film transistor. The control electrode of the fifth pixel switch element T5 may be a gate electrode, the input electrode of the fifth pixel switch element T5 may be a source electrode, and the output electrode of the fifth pixel switch element T5 may be a drain electrode.

[0155] The sixth pixel switching element T6 includes a control electrode to which the emission signal EM is applied, an input electrode connected to the third node N3, and an output electrode connected to the anode of the organic light emitting element OLED.

[0156] For example, the sixth pixel switch element T6 may be a polysilicon thin film transistor. For example, the sixth pixel switch element T6 may be a P-type thin film transistor. The control electrode of the sixth pixel switch element T6 may be a gate electrode, the input electrode of the sixth pixel switch element T6 may be a source electrode, and the output electrode of the sixth pixel switch element T6 may be a drain electrode.

[0157] The seventh pixel switching element T7 includes a control electrode to which the organic light emitting element initialization signal GB is applied, an input electrode to which the initialization voltage V1 is applied, and an output electrode connected to the anode of the organic light emitting element OLED.

[0158] For example, the seventh pixel switch element T7 may be an oxide thin film transistor. For example, the seventh pixel switch element T7 may be an N-type thin film transistor. The control electrode of the seventh pixel switch element T7 may be a gate electrode, the input electrode of the seventh pixel switch element T7 may be a source electrode, and the output electrode of the seventh pixel switch element T7 may be a drain electrode.

[0159] The storage capacitor CST includes a first electrode to which the high power voltage ELVDD is applied and a second electrode connected to the first node N1.

[0160] The organic light emitting element OLED includes an anode and a cathode to which a low power voltage ELVSS is applied.

[0161] exist Fig.12 During the first duration DU1, the first node N1 and the storage capacitor CST are initialized in response to the data initialization gate signal GI. During the second duration DU2, the threshold voltage |VTH| of the first pixel switch element T1 is compensated, and the data voltage VDATA whose threshold voltage |VTH| is compensated is written to the first node N1 in response to the first data write gate signal GWP and the second data write gate signal GWN. During the third duration DU3, the anode of the organic light emitting element OLED is initialized in response to the organic light emitting element initialization signal GB. During the fourth duration DU4, the organic light emitting element OLED emits light in response to the emission signal EM, so that the display panel 100 displays an image.

[0162] Although in the present exemplary embodiment, the emission off duration of the emission signal EM corresponds to the first to third durations DU1, DU2, and DU3, the inventive concept is not limited thereto. The emission off duration of the emission signal EM may be set to include a data write duration, such as the second duration DU2. The emission off duration of the emission signal EM may be longer than the sum of the first to third durations DU1, DU2, and DU3.

[0163] During the first duration DU1, the data initialization gate signal GI may have an effective level. For example, the effective level of the data initialization gate signal GI may be a high level. When the data initialization gate signal GI has an effective level, the fourth pixel switching element T4 is turned on so that the initialization voltage VI may be applied to the first node N1. The data initialization gate signal GI[N] of the current stage may be generated based on the scan signal SCAN[N-1] of the previous stage.

[0164] During the second duration DU2, the first data write gate signal GWP and the second data write gate signal GWN may have an effective level. For example, the effective level of the first data write gate signal GWP may be a low level, and the effective level of the second data write gate signal GWN may be a high level. When the first data write gate signal GWP and the second data write gate signal GWN have an effective level, the second pixel switch element T2 and the third pixel switch element T3 are turned on. In addition, the first pixel switch element T1 is turned on in response to the initialization voltage VI. The first data write gate signal GWP[N] of the current level may be generated based on the scan signal SCAN[N] of the current level. The second data write gate signal GWN[N] of the current level may be generated based on the scan signal SCAN[N] of the current level.

[0165] A voltage obtained by subtracting the threshold voltage |VTH| of the first pixel switching element T1 from the data voltage VDATA may be charged at the first node N1 along a path generated by the first to third pixel switching elements T1 , T2 , and T3 .

[0166] During the third duration DU3, the organic light emitting element initialization signal GB may have an effective level. For example, the effective level of the organic light emitting element initialization signal GB may be a high level. When the organic light emitting element initialization signal GB has an effective level, the seventh pixel switch element T7 is turned on so that the initialization voltage V1 may be applied to the anode of the organic light emitting element OLED. The organic light emitting element initialization signal GB[N] of the current stage may be generated based on the scan signal SCAN[N+1] of the next stage.

[0167] During the fourth duration DU4, the emission signal EM may have an effective level. The effective level of the emission signal EM may be a low level. When the emission signal EM has an effective level, the fifth pixel switching element T5 and the sixth pixel switching element T6 are turned on. In addition, the first pixel switching element T1 is turned on by the data voltage VDATA.

[0168] The driving current flows through the fifth pixel switching element T5, the first pixel switching element T1, and the sixth pixel switching element T6 to drive the organic light emitting element OLED. The intensity of the driving current can be determined by the level of the data voltage VDATA. The brightness of the organic light emitting element OLED is determined by the intensity of the driving current ISD. The driving current ISD flowing in the path from the input electrode to the output electrode of the first pixel switching element T1 is determined according to the following equation 1.

[0169] [Equation 1]

[0170]

[0171] In Equation 1, μ is the mobility of the first pixel switch element T1. Cox is the capacitance per unit area of ​​the first pixel switch element T1. W / L is the ratio of the width to the length of the first pixel switch element T1. VSG is the voltage between the input electrode of the first pixel switch element T1 and the control electrode of the first pixel switch element T1. |VTH| is the threshold voltage of the first pixel switch element T1.

[0172] During the second duration DU2 , after compensation of the threshold voltage |VTH|, the voltage VG of the first node N1 may be expressed according to Equation 2 below.

[0173] [Equation 2]

[0174] VG=VDATA-|VTH|

[0175] When the organic light emitting element OLED emits light during the fourth duration DU4, the driving voltage VOV and the driving current ISD may be expressed according to the following Equations 3 and 4. In Equation 3, VS is the voltage of the second node N2.

[0176] [Equation 3]

[0177] VOV=VS-VG-|VTH|=ELVDD-(VDATA-|VTH|)-|VTH|=ELVDD-VDATA

[0178] [Equation 4]

[0179]

[0180] During the second duration DU2 , the threshold voltage |VTH| is compensated so that when the organic light emitting element OLED emits light during the fourth duration DU4 , the driving current ISD may be determined regardless of the threshold voltage |VTH| of the first pixel switching element T1 .

[0181] In this exemplary embodiment, when the image displayed on the display panel 100 is a static image or the display panel is operated in a normally-on mode, the driving frequency of the display panel 100 can be reduced to reduce power consumption. When all the switching elements of the pixels of the display panel 100 are polysilicon thin film transistors, flickering may occur due to the leakage current of the pixel switching elements in the low-frequency driving mode. Therefore, some of the pixel switching elements can be designed using oxide thin film transistors. In this exemplary embodiment, the third pixel switching element T3, the fourth pixel switching element T4, and the seventh pixel switching element T7 can be oxide thin film transistors. The first pixel switching element T1, the second pixel switching element T2, the fifth pixel switching element T5, and the sixth pixel switching element T6 can be polysilicon thin film transistors.

[0182] The display panel 100 may be driven in a normal driving mode in which the display panel 100 is driven at a normal driving frequency, and may be driven in a low frequency driving mode in which the display panel 100 is driven at a frequency less than the normal driving frequency.

[0183] For example, when the input image data represents a video image, the display panel 100 may be driven in a normal driving mode. For example, when the input image data represents a static image, the display panel 100 may be driven in a low-frequency driving mode. For example, when the display device is operated in a normally-on mode, the display panel 100 may be driven in a low-frequency driving mode.

[0184] In the present exemplary embodiment, the second data write gate signal GWN[1] and the data initialization gate signal GI[1] may have a first frequency in the low frequency driving mode. The first frequency may be the frequency of the low frequency driving mode. Conversely, the first data write gate signal GWP

[60] , the emission signal EM

[60] , and the organic light emitting element initialization signal GB

[60] may have a second frequency greater than the first frequency. The second frequency may be a normal frequency in the normal driving mode. Fig.13 , the first frequency is 1 Hz and the second frequency is 60 Hz.

[0185] The transmission signal EM

[60] in a frame may include a transmission off-duration OD when the transmission signal EM

[60] has an inactive level and a transmission on-duration OD when the transmission signal EM

[60] has an active level.

[0186] The driving controller 200 may include a receiver 220 , a frequency determiner 240 , a signal generator 260 , and a data compensator 280 .

[0187] The frequency determiner 240 may determine the driving frequency FR of the display device based on the input image data IMG. When the input image data IMG represents a video image, the driving frequency FR may be relatively high. When the input image data IMG represents a static image, the driving frequency FR may be relatively low.

[0188] The frequency determiner 240 may determine the low-frequency driving mode and the normal driving mode based on the input image data IMG. For example, when the input image data IMG represents a video image, the frequency determiner 240 may drive the display device in the normal driving mode. For example, when the input image data IMG represents a static image, the frequency determiner 240 may drive the display device in the low-frequency driving mode.

[0189] In the power reduction mode, the power supply voltage generator 800 may not output at least one of the power supply voltages. Alternatively, in the power reduction mode, the power supply voltage generator 800 may not output all of the power supply voltages. The operation of the receiver 220 may be disabled in the power reduction mode. For example, the input buffers IB1 to IBX of the receiver 220 may be turned off in the power reduction mode. The operation of the data driver 500 may be disabled in the power reduction mode. For example, the output buffers OB1 to OBN of the buffer 580 may be turned off in the power reduction mode.

[0190] According to the present exemplary embodiment, the display panel 100 includes the first type switching element and the second type switching element, so that power consumption can be reduced in the low frequency driving mode and the display quality of the display panel can be improved.

[0191] In addition, during the holding frame of the low frequency driving mode, at least one of the receiver 220 of the driving controller 200, the output buffer OB of the data driver 500, and the power supply voltage generator 800 is operated in the power reduction mode, so that the power consumption of the display device can be further reduced.

[0192] According to the exemplary embodiments of the inventive concept as explained above, the display quality of the display panel may be improved and the power consumption of the display device may be reduced.

[0193] While the present inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as set forth in the following claims.

Claims

1. A display device, comprising: a display panel configured to display an image based on input image data; a driving controller configured to determine a low-frequency driving mode and a normal driving mode based on the input image data; a gate driver configured to output a gate signal to the display panel; a data driver configured to output a data voltage to the display panel; as well as a power supply voltage generator configured to output a power supply voltage to the driving controller, the gate driver, and the data driver, The driving controller is configured to generate a writing frame for writing data in pixels of the display panel and a holding frame for maintaining the written data without writing data in the pixels in the low-frequency driving mode, wherein the driving controller is configured to operate at least one of the driving controller, the data driver and the power supply voltage generator in a power reduction mode during the holding frame, and Wherein, the driving controller includes a frequency determiner configured to determine a driving frequency and the power reduction mode based on the input image data.

2. The display device according to claim 1, wherein: The drive controller further comprises: a receiver configured to receive the input image data and an input control signal; a signal generator configured to generate a gate control signal for controlling the gate driver and a data control signal for controlling the data driver based on the driving frequency and the input control signal; and A data compensator is configured to generate a data signal based on the driving frequency and the input image data.

3. The display device according to claim 2, wherein: An input buffer of the receiver is configured to be turned off in the power reduction mode.

4. The display device according to claim 1, wherein: The power supply voltage generator is configured not to output at least one of the power supply voltages in the power reduction mode.

5. The display device according to claim 4, wherein: The power supply voltage generator is configured to not output some of the power supply voltages in a first power reduction mode, and The power supply voltage generator is configured not to output all of the power supply voltage in the second power reduction mode.

6. The display device according to claim 5, wherein: The power supply voltage generator comprises: a first voltage generator configured to generate an oscillator voltage for operating an oscillator that generates a clock signal for the drive controller; a second voltage generator configured to generate a logic voltage for operating the drive controller; a third voltage generator configured to generate a memory voltage for operating a memory used by the drive controller; a fourth voltage generator configured to generate a signal transmission voltage for transmitting a signal between the driving controller and the data driver; and a fifth voltage generator configured to generate a data power supply voltage for operating the data driver.

7. The display device according to claim 6, wherein: In the first power reduction mode, the first switch connected to the first voltage generator, the third switch connected to the third voltage generator, and the fifth switch connected to the fifth voltage generator are configured to be opened, and the second switch connected to the second voltage generator and the fourth switch connected to the fourth voltage generator are configured to be closed.

8. The display device according to claim 6, wherein: In the second power reduction mode, a first switch connected to the first voltage generator, a second switch connected to the second voltage generator, a third switch connected to the third voltage generator, a fourth switch connected to the fourth voltage generator, and a fifth switch connected to the fifth voltage generator are configured to be opened.

9. The display device according to claim 1, wherein: An output buffer of the data driver is configured to be turned off in the power reduction mode.

10. The display device according to claim 9, wherein: The data driver comprises: a plurality of current sources connected in parallel with each other; a plurality of current switches respectively connected in series to the plurality of current sources; a first transistor connected to the plurality of current switches; and connected to the first transistor and a second transistor of the output buffer, Wherein, the plurality of current switches are configured to be turned on in the power reduction mode.

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