Organic Light-Emitting Diode Display

Abstract

An organic light emitting diode display includes: a first thin film transistor having a channel formed in a polycrystalline semiconductor layer; a second thin film transistor having a channel formed in an oxide semiconductor layer; an organic light emitting diode electrically connected to the first thin film transistor; a storage capacitor having a first electrode and a second electrode, wherein the second electrode of the storage capacitor is electrically connected to the gate electrode of the first thin film transistor; and an overlapping layer overlapping the oxide semiconductor layer in a plan view and receiving a positive voltage. The oxide semiconductor layer is placed higher than the gate electrode of the first thin film transistor and the second electrode of the storage capacitor.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0015016, filed on February 8, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present invention relates to an organic light - emitting diode display, and more particularly, to an organic light - emitting diode display including transistors using different semiconductor layers. Background art

[0004] Recently, organic light - emitting diode displays have attracted attention as devices for displaying images.

[0005] Unlike liquid crystal display devices, since organic light - emitting diode displays are self - emissive without a light source, thickness and weight can be reduced. In addition, organic light - emitting diode displays have high - quality characteristics such as low power consumption, high brightness, and high response speed.

[0006] Generally, an organic light - emitting diode display includes a substrate, a plurality of thin - film transistors disposed on the substrate, a plurality of insulating films disposed between wirings for configuring the thin - film transistors, and an organic light - emitting diode (OLED) connected to the thin - film transistors. Specifically, at least two or more thin - film transistors are used to allow one organic light - emitting diode (OLED) to emit light.

[0007] The above information disclosed in this background section is only for enhancing the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art in the country. Summary of the invention

[0008] In some of the plurality of transistors for driving one organic light - emitting diode (OLED), the reliability of these transistors has been improved and / or the leakage current of these transistors has been removed by other transistors. In addition, this embodiment has been committed to providing an organic light - emitting diode display that can stably use the characteristics of transistors using an oxide semiconductor. Further, this embodiment has been committed to providing an organic light - emitting diode display that can have such a structure required for forming an organic light - emitting diode display without increasing the number of processes.

[0009] According to an exemplary embodiment of the present invention, an organic light emitting diode display includes: a substrate; a polycrystalline semiconductor layer disposed on the substrate; a first insulating film covering the polycrystalline semiconductor layer; a first conductor disposed on the first insulating film; a second insulating film covering the first conductor and the first insulating film; a second conductor disposed on the second insulating film; a third insulating film covering the second insulating film and the second conductor; an oxide semiconductor layer disposed on the third insulating film; a fourth insulating film covering the oxide semiconductor layer and the third insulating film; a third conductor disposed on the fourth insulating film; a fifth insulating film covering the third conductor and the fourth insulating film; a fourth conductor disposed on the fifth insulating film; and a passivation layer covering the fourth conductor and the fifth insulating film. The first conductor includes a gate electrode of a driving transistor, the gate electrode of the driving transistor overlaps with the polycrystalline semiconductor layer to form a driving transistor, and the second conductor includes a storage electrode overlapping with the gate electrode of the driving transistor and an overlapping layer overlapping with the oxide semiconductor layer.

[0010] According to an exemplary embodiment of the present invention, an organic light emitting diode display includes: a first thin film transistor having a channel formed in a polycrystalline semiconductor layer; a second thin film transistor having a channel formed in an oxide semiconductor layer; an organic light emitting diode electrically connected to the first thin film transistor; a storage capacitor having a first electrode and a second electrode, wherein the second electrode of the storage capacitor is electrically connected to the gate electrode of the first thin film transistor; and an overlapping layer overlapping with the oxide semiconductor layer in a plan view and receiving a positive voltage. The oxide semiconductor layer is placed higher than the gate electrode of the first thin film transistor and the second electrode of the storage capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An equivalent circuit diagram of one pixel of an organic light emitting diode display according to an embodiment is illustrated.

[0012] Figure 2 A timing diagram of signals applied to one pixel of an organic light emitting diode display according to an embodiment is illustrated.

[0013] Figure 3 A layout diagram of one pixel region of an organic light emitting diode display according to an embodiment is illustrated.

[0014] Figure 4 Illustrated is along Figure 3 sectional view taken along line IV-IV.

[0015] Figure 5 Illustrated is along Figure 3 sectional view taken along line V-V.

[0016] Figure 6 An equivalent circuit diagram of one pixel of an organic light emitting diode display according to an embodiment is illustrated.

[0017] Figure 7 The layout diagram of a pixel region of an organic light emitting diode display according to an embodiment is illustrated.

[0018] Figure 8 Illustrated along Figure 7 is a cross-sectional view taken along line VIII-VIII.

[0019] Figure 9 The equivalent circuit diagram of a pixel of an organic light emitting diode display according to an embodiment is illustrated.

[0020] Figure 10 The layout diagram of a pixel region of an organic light emitting diode display according to an embodiment is illustrated.

[0021] Figure 11 and Figure 12 is a cross-sectional view of a part of a pixel in an organic light emitting diode display according to an embodiment.

[0022] Figure 13 The equivalent circuit diagram of a pixel of an organic light emitting diode display according to an embodiment is illustrated.

[0023] Figure 14 The equivalent circuit diagram of a pixel of an organic light emitting diode display according to an embodiment is illustrated. Detailed Description

[0024] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art will recognize, the described embodiments can be modified in various different ways, all of which do not depart from the spirit or scope of the present disclosure.

[0025] To clearly describe the present disclosure, parts not relevant to the description will be omitted, and throughout the specification, the same reference numerals refer to the same elements.

[0026] In addition, in the drawings, for ease of description, the dimensions and thicknesses of each element are arbitrarily illustrated, and the present disclosure is not necessarily limited to those illustrated in the drawings. In the drawings, for clarity, the thicknesses of layers, films, panels, regions, etc. are exaggerated. In the drawings, for ease of description, the thicknesses of some layers and regions are exaggerated.

[0027] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly" on another element, no intervening elements are present. Further, in the specification, the words "on" or "above" mean being placed above or below the object part, and do not necessarily mean being placed above the object part based on the direction of gravity.

[0028] In addition, unless otherwise explicitly stated to the contrary, the words "comprise" and its variants (such as "comprising" or "including") will be understood to mean including the stated elements but not excluding any other elements.

[0029] Further, throughout the specification, the phrase "in a plan view" means observing the target part from the top, and the phrase "in a cross-section" means observing the cross-section formed by vertically cutting the target part from the side.

[0030] Hereinafter, reference will be made to Figure 1 and Figure 2 to describe an organic light emitting diode display according to an embodiment.

[0031] Figure 1 illustrates an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an embodiment, and Figure 2 illustrates a timing diagram of signals applied to a pixel of an organic light emitting diode display according to an embodiment.

[0032] First, referring to Figure 1 , a pixel PX of an organic light emitting diode display includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to a plurality of signal lines 127, 151, 151-1, 152-1, 152-1', 153, 171, 172, and 741, a storage capacitor Cst, and an organic light emitting diode OLED.

[0033] In addition, as shown in Figure 1 for one embodiment, the pixel further includes an overlap layer 125. In a plan view, the overlap layer 125 is disposed under the semiconductor layer of the third transistor T3 to overlap with the semiconductor layer of the third transistor T3. Here, the semiconductor layer of the third transistor T3 is formed of an oxide semiconductor. That is, the overlap layer 125 is disposed between the substrate 110 and the oxide semiconductor layer of the third transistor T3. (See Figure 4 )

[0034] In addition, the overlap layer 125 is electrically connected to a protruding portion 172-1 of the driving voltage line 172 through an opening 66 (see Figure 5),The driving voltage ELVDD is transmitted to the driving voltage line 172. According to an embodiment, the opening 66 and the protruding portion 172-1 of the driving voltage line 172 may be arranged in the pixel PX or in a pixel adjacent to the pixel PX. The overlapping layer 125 may be made of a metal having a conductive property, and in this embodiment, the overlapping layer 125 may be made of the same material as one of the two storage electrodes of the storage capacitor Cst.

[0035] Although the driving voltage ELVDD is applied to Figure 1 the overlapping layer 125, the present invention is not limited thereto, and due to the characteristics of the oxide semiconductor, a positive voltage may be applied to the overlapping layer 125. According to the voltage applied to the overlapping layer 125, the threshold voltage (Vth) of the channel of the third transistor T3 overlapping with the overlapping layer 125 can be changed, the leakage current can be reduced, and the characteristics of the third transistor T3 can be stabilized. Here, since the semiconductor layer of the third transistor T3 is made of an oxide semiconductor, the third transistor T3 has n-type transistor characteristics and is turned on when a high voltage is applied to the gate electrode G3.

[0036] In the organic light emitting diode display according to an embodiment, one pixel PX is configured as in Figure 1 the circuit diagram shown, and a plurality of pixels are arranged in various forms such as a matrix form.

[0037] At least one of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 included in the pixel PX may include a semiconductor layer formed of an oxide semiconductor such as the third transistor T3 and may be used as an n-type transistor, and the remaining transistors may include a semiconductor layer formed of a polycrystalline semiconductor such as the driving transistor T1 and may be used as a p-type transistor. Hereinafter, the transistor group of n-type transistors will be referred to as the "switch transistor group", and the transistor group of p-type transistors will be referred to as the "driving transistor group".

[0038] Since leakage current occurs in the n-type transistor, in this embodiment, a positive voltage is applied to the overlapping layer 125, and then the voltage of the oxide semiconductor layer is stabilized, and the operation of the switching transistor is also compensated. In this embodiment, only the third transistor T3 among the transistors of the switch transistor group includes the overlapping layer 125. In Figure 1 the embodiment of, the switch transistor group includes the third transistor T3, the fourth transistor T4, and the seventh transistor T7.

[0039] On the other hand, the p-type transistor has excellent reliability and is related to the basic operation of the driving transistor T1, that is, outputting a driving current. This ensures reliability by using a polycrystalline semiconductor as the semiconductor layer. In Figure 1In the embodiment, the driving transistor group includes a driving transistor T1, a second transistor T2, a fifth transistor T5, and a seventh transistor T7.

[0040] In some embodiments, the transistors included in the switching transistor group and the transistors included in the driving transistor group may be changed.

[0041] Multiple signal lines 127, 151, 151-1, 152-1, 152-1’, 153, 171, 172, and 741 may include a scan line 151, a main inversion scan line 151-1, a previous inversion scan line 152-1, a light emission control line 153, a bypass control line 152-1’, a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741. The bypass control line 152-1’ in this embodiment may be electrically connected to the previous inversion scan line of the previous pixel.

[0042] The scan line 151 is connected to a gate driving part (not shown) to transmit a scan signal Sn to the second transistor T2.

[0043] Although the main inversion scan line 151-1 has the same timing as the signal of the scan line 151, they may have opposite voltage levels. For example, when a high voltage is applied to the scan line 151, a low voltage is applied to the main inversion scan line 151-1, and when a low voltage is applied to the scan line 151, a high voltage is applied to the main inversion scan line 151-1, and hereinafter, this is simply referred to as inversion. When the scan line 151 transmits the scan signal Sn to the second transistor T2, the main inversion scan line 151-1 transmits an inversion scan signal Sn’ (an inversion signal of the scan signal Sn) to the third transistor T3.

[0044] The previous inversion scan line 152-1 is connected to the gate driving part to transmit an inversion signal Sn-1’ (also referred to as a previous inversion scan signal) of the line scan signal applied to the pixel PX arranged at the previous stage to the fourth transistor T4.

[0045] The light emission control line 153 is connected to a light emission control part (not shown) to transmit a light emission control signal EM for controlling the light emission time of the organic light emitting diode OLED to the fifth transistor T5 and the sixth transistor T6.

[0046] The bypass control line 152-1’ transmits a bypass signal GB to the seventh transistor T7, and referring to Figure 2 , it transmits an inversion signal of the signal before the line scan signal (hereinafter referred to as a previous-previous inversion signal) to the seventh transistor T7.

[0047] The data line 171 is a wiring for transmitting the data voltage Dm generated by a data driving part (not shown), and the luminance of the organic light emitting diode OLED can be changed according to the data voltage Dm applied to the pixel PX.

[0048] The driving voltage line 172 applies the driving voltage ELVDD, the initialization voltage line 127 transmits the initialization voltage Vint for initializing the gate electrode G1 of the driving transistor T1 and the anode of the organic light emitting diode OLED, and the common voltage line 741 transmits the common voltage ELVSS to the cathode of the organic light emitting diode OLED. The voltages applied to the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741 may be constant. In an exemplary embodiment, the driving voltage line 172 may be electrically connected to a driving voltage source that supplies the driving voltage ELVDD. For example, the driving voltage source may include a voltage generator or a voltage converter.

[0049] Hereinafter, a plurality of transistors will be specifically described.

[0050] First, the driving transistor T1 is formed as a p-type transistor having a semiconductor layer of polycrystalline semiconductor, and controls the amount of current output to the anode electrode of the organic light emitting diode OLED according to the data voltage Dm applied to the gate electrode G1 of the driving transistor T1 (hereinafter also referred to as the gate electrode of the driving transistor). The luminance of the organic light emitting diode OLED is controlled according to the amount of the driving current Id output to the anode of the organic light emitting diode OLED, and thus the luminance of the organic light emitting diode OLED can be controlled according to the data voltage Dm applied to the pixel PX. To this end, in Figure 1 an embodiment, the first electrode S1 (input side electrode) of the driving transistor T1 is arranged to receive the driving voltage ELVDD and is connected to the driving voltage line 172 through the fifth transistor T5. In addition, the first electrode S1 of the driving transistor T1 is connected to the second electrode D2 of the second transistor T2 to receive the data voltage Dm. The second electrode D1 is arranged to output current toward the organic light emitting diode OLED and is connected to the anode of the organic light emitting diode OLED through the sixth transistor T6. In addition, the second electrode D1 transmits the data voltage Dm applied to the first electrode S1 to the third transistor T3. The operation of transmitting the data voltage Dm to the third transistor T3 through the driving transistor T1 and the operation of transmitting the output current to the organic light emitting diode OLED are performed at different time periods. On the other hand, the gate electrode G1 is connected to one electrode (second storage electrode E2) of the storage capacitor Cst. Therefore, the voltage of the gate electrode G1 changes according to the voltage stored in the storage capacitor Cst, and thus the driving current Id output by the driving transistor T1 changes. In addition, the storage capacitor Cst can be used to keep the voltage of the gate electrode G1 of the driving transistor T1 constant during one frame.

[0051] The driving transistor T2 is formed as a p-type transistor, has a semiconductor layer of polycrystalline semiconductor, and receives a data voltage Dm for the pixel PX. The driving transistor T2 has a gate electrode G2 connected to the scanning line 151 and a first electrode S2 connected to the data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on in response to a low voltage of the scanning signal Sn transmitted through the scanning line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the first electrode S1 of the driving transistor T1.

[0052] The driving transistor T3 is formed as an n-type transistor, has a semiconductor layer formed of an oxide semiconductor, and is electrically connected to the second electrode D1 and the gate electrode G1 of the driving transistor T1. As a result, the driving transistor T3 changes the compensation voltage (a voltage of Dm + Vth) while the data voltage Dm passes through the driving transistor T1 to be delivered to the second storage electrode E2 of the storage capacitor Cst. The gate electrode G3 is connected to the main inverted scanning line 151-1, and the first electrode S3 is connected to the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. The third transistor T3 is turned on by a high voltage of the inverted scanning signal Sn' transmitted through the main inverted scanning line 151-1 to connect the gate electrode G1 and the second electrode D1 of the driving transistor T1, and transmits the voltage applied to the gate electrode G1 of the driving transistor T1 to the second storage electrode E2 of the storage capacitor Cst, so that the voltage applied to the gate electrode G1 is stored in the storage capacitor Cst.

[0053] The third transistor T3 further includes an overlapping layer 125 disposed under the oxide semiconductor layer to compensate for the characteristics of the semiconductor layer made of the oxide semiconductor. In Figure 1 the embodiment, a driving voltage ELVDD is applied to the overlapping layer 125. By applying the driving voltage ELVDD to the overlapping layer 125, it is possible to prevent the potential of the overlapping layer 125 itself from being changed and prevent the voltage of the oxide semiconductor layer of the third transistor T3 from being easily changed. As a result, the leakage current problem that may occur in the third transistor T3 is solved, and thus it can be stably operated.

[0054] The fourth transistor T4 is formed as an n-type transistor having a semiconductor layer formed of an oxide semiconductor, and is used to initialize the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 is connected to the previous inverted scan line 152-1, and the first electrode S4 is connected to the initialization voltage line 127. The second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst, the gate electrode G1 of the driving transistor T1, and the second electrode D3 of the third transistor T3. The fourth transistor T4 is turned on by the high voltage of the previous inverted scan signal Sn-1’ transmitted through the previous inverted scan line 152-1 to transmit the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. Accordingly, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint has a low voltage value that can be a voltage capable of turning on the driving transistor T1.

[0055] The fifth transistor T5 is formed as a p-type transistor having a semiconductor layer formed of a polycrystalline semiconductor, and is used to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode G5 is connected to the light emission control line 153, and the first electrode S5 is connected to the driving voltage line 172. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1.

[0056] Similar to the fifth transistor T5, the sixth transistor T6 is formed as a p-type transistor having a semiconductor layer formed of a polycrystalline semiconductor, and is used to transmit the driving current Id output from the driving transistor T1 to the organic light emitting diode OLED. The gate electrode G6 is connected to the light emission control line 153, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode of the organic light emitting diode OLED.

[0057] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on by the low voltage of the light emission control signal EM transmitted through the light emission control line 153. When the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs the driving current Id according to the voltage of the gate electrode G1 of the driving transistor T1 (i.e., the voltage of the second storage electrode E2 of the storage capacitor Cst). The output driving current Id is transmitted to the organic light emitting diode OLED through the sixth transistor T6. As the current Ioled flows through the organic light emitting diode OLED, the organic light emitting diode OLED emits light.

[0058] The seventh transistor T7 is formed as an n-type transistor having a semiconductor layer formed of an oxide semiconductor and is used to initialize the anode of the organic light-emitting diode OLED. The gate electrode G7 of the seventh transistor T7 is connected to the bypass control line 152-1', the first electrode S7 of the seventh transistor T7 is connected to the anode of the organic light-emitting diode OLED, and the second electrode D7 of the seventh transistor T7 is connected to the initialization voltage line 127. The bypass control line 152-1' may be connected to the previous inversion scan line of the previous pixel, and the bypass signal GB may be applied as an inversion scan signal (previous-previous inversion signal) faster than the previous inversion scan signal Sn-1'. In some embodiments, the bypass control line 152-1' may not be connected to the previous inversion scan line of the previous pixel, but may transmit a separate signal different from the previous inversion scan signal Sn-1'. When the seventh transistor T7 is turned on by the high voltage of the bypass signal GB, the initialization voltage Vint is applied to the anode of the organic light-emitting diode OLED to be initialized.

[0059] The first storage electrode E1 of the storage capacitor Cst is connected to the driving voltage line 172, and the second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. As a result, the second storage electrode E2 determines the voltage of the gate electrode G1 of the driving transistor T1 and receives the data voltage Dm through the second electrode D3 of the third transistor T3 or the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0060] On the other hand, the anode of the organic light-emitting diode OLED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7, and the cathode of the organic light-emitting diode OLED is connected to the common voltage line 741 for transmitting the common voltage ELVSS.

[0061] In Figure 1 an exemplary embodiment of, the pixel circuit includes seven transistors T1 to T7 and one capacitor Cst, but the present invention is not limited thereto. In an exemplary embodiment, the number of transistors, the number of capacitors, and their connections can be variously changed.

[0062] Reference will be made to Figure 1 and Figure 2 to describe the operation of one pixel of an organic light-emitting diode display according to an embodiment.

[0063] The initialization period can be mainly divided into a period of applying the bypass signal GB (a period during the application of the previous-previous inversion scan signal) and a period of applying the previous inversion scan signal Sn-1' through the previous inversion scan line 152-1.

[0064] First, the seventh transistor T7 operates during a period when a bypass signal GB of a high voltage is applied. In other words, when the bypass signal GB (i.e., the previous-previous inverted scan signal) is applied during the initialization period, the seventh transistor T7 is turned on by the high voltage of the bypass signal GB, so that the initialization voltage Vint is applied to the anode of the organic light-emitting diode OLED through the seventh transistor T7. As a result, the anode of the organic light-emitting diode OLED is initialized.

[0065] Thereafter, the fourth transistor T4 is turned on during a period when the previous inverted scan signal Sn-1’ of a high voltage is applied through the previous inverted scan line 152-1, and the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst through the fourth transistor T4. Accordingly, the driving transistor T1 and the storage capacitor Cst are initialized using the initialization voltage Vint. The initialization voltage Vint has a low voltage value such that the driving transistor T1 can be turned on.

[0066] Then, during the data writing period, a low voltage scan signal Sn and a high voltage inverted scan signal Sn’ are supplied to the pixel PX through the scan line 151 and the main inverted scan line 151-1, respectively. The second transistor T2 is turned on by the low voltage scan signal Sn, and the third transistor T3 is turned on by the high voltage inverted scan signal Sn’.

[0067] When the second transistor T2 is turned on, the data voltage Dm is input to the first electrode S1 of the driving transistor T1 through the second transistor T2.

[0068] In addition, during the data writing period, the third transistor T3 is turned on so that the second electrode D1 of the driving transistor T1 is electrically connected to the gate electrode G1 and the second storage electrode E2 of the storage capacitor Cst. In this case, the driving transistor T1 is diode-connected. Further, since a low voltage (initialization voltage Vint) is applied to the gate electrode G1 during the initialization period, the driving transistor T1 is in an on state. Accordingly, the data voltage Dm input to the first electrode S1 of the driving transistor T1 is output from the second electrode D1 through the channel of the driving transistor T1, and then is stored in the second storage electrode E2 of the storage capacitor Cst through the third transistor T3.

[0069] In this case, the voltage applied to the second storage electrode E2 varies according to the threshold voltage (Vth) of the driving transistor T1. That is, when the data voltage Dm is applied to the first electrode S1 of the driving transistor T1 and the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1, the voltage output to the second electrode D1 can be "Vgs + Vth". Herein, Vgs is the difference between the voltage applied to the gate electrode G1 and the first electrode S1 of the driving transistor T1, so it can be "Dm - Vint". Therefore, the voltage output from the second electrode D1 and stored in the second storage electrode E2 can be "Dm - Vint + Vth".

[0070] Thereafter, during the light emission period, since the light emission control signal EM supplied from the light emission control line 153 has a low voltage, the fifth transistor T5 and the sixth transistor T6 are turned on. As a result, the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1, and the second electrode D1 of the driving transistor T1 is connected to the anode of the organic light emitting diode OLED. The driving transistor T1 outputs a driving current Id according to the difference between the voltage of the gate electrode G1 and the voltage of the first electrode S1 (i.e., the driving voltage ELVDD). The driving current Id of the driving transistor T1 can have a value proportional to the square value of "Vgs - Vth". Herein, Vgs is the difference between the voltages applied to the two terminals of the storage capacitor Cst, and since Vgs is "Vg - Vs", it can be "Dm - Vint + Vth - ELVDD". Herein, when "Vgs - Vth" is obtained by subtracting Vth, it is "Dm - Vint - ELVDD". That is, the driving current Id of the driving transistor T1 can be a current independent of the threshold voltage (Vth) of the driving transistor T1.

[0071] Therefore, even if the driving transistors T1 arranged in the corresponding pixels PX have different threshold voltages (Vth) due to process dispersion, a constant output current of the driving transistor T1 can be output, thereby improving the non-uniformity of its characteristics.

[0072] In the above calculation formula, when the transistor is a p-type transistor using polycrystalline semiconductor, Vth can be a value slightly greater than 0 or a negative value. In addition, the signs of + and - can be changed according to the direction of calculating the voltage. However, even in this case, the driving current Id as the output current of the driving transistor T1 can have a value independent of the threshold voltage (Vth).

[0073] When the above light emission period ends, the same operation is repeated starting from the initialization period.

[0074] Depending on the direction in which the voltage or current is applied, one of the first and second electrodes of each of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 can be a source electrode, and the other can be a drain electrode.

[0075] In some exemplary embodiments, during the initialization period in which the seventh transistor T7 initializes the anode of the organic light-emitting diode OLED, the seventh transistor T7 can even prevent a small amount of current emitted when the driving transistor T1 is not actually turned on from flowing to the organic light-emitting diode OLED. In this case, the small amount of current is discharged to the terminal of the initialization voltage Vint through the seventh transistor T7 as a bypass current Ibp. As a result, the organic light-emitting diode OLED does not emit unnecessary light, enabling a black grayscale to be displayed more clearly and improving the contrast.

[0076] In the pixel PX operating as described above, the driving voltage ELVDD is constantly applied to the overlapping layer 125. By applying a constant voltage, it is possible to prevent the potential of the overlapping layer 125 itself from being changed when a specific charge is injected, and to prevent the voltage of the oxide semiconductor layer of the third transistor T3 overlapping with the overlapping layer 125 from being easily changed. As a result, the characteristics of the third transistor T3 are improved, and the leakage current problem of transistors using an oxide semiconductor is solved, enabling it to operate stably. When leakage current occurs in the third transistor T3, the initialization voltage Vint is applied to the second storage electrode E2 of the storage capacitor Cst, so the voltage stored in the storage capacitor Cst is changed. This means that the voltage of the gate electrode G1 of the driving transistor T1 is changed, and as a result, the output current output from the driving transistor T1 is changed, and thus the display brightness of the organic light-emitting diode OLED may be changed. Therefore, since the leakage current in the third transistor T3 significantly affects the display quality, it is necessary to block the leakage current. Therefore, according to this embodiment, the leakage current is removed or reduced by the overlapping layer 125, and stable display quality is obtained.

[0077] Hereinafter, reference will be made to Figures 3 to 5 describe the arrangement and connection relationship of the pixel and the overlapping layer 125 of the organic light-emitting diode display according to the embodiment.

[0078] Figure 3 The layout diagram of one pixel region of the organic light-emitting diode display according to the embodiment is illustrated, Figure 4 illustrated along Figure 3 a cross-sectional view taken along line IV-IV, and Figure 5 illustrated along Figure 3 a cross-sectional view taken along line V-V.

[0079] Reference Figures 3 to 5, an organic light emitting diode display according to an exemplary embodiment includes scan lines 151, main inverted scan lines 151-1, previous inverted scan lines 152-1, light emission control lines 153, bypass control lines 152-1', and initialization voltage lines 127 that mainly extend in a first direction and respectively transmit scan signals Sn, inverted scan signals Sn', previous inverted scan signals Sn-1', light emission control signals EM, bypass signals GB, and initialization voltage Vint. The bypass signal GB may be a previous-previous inverted scan signal and is transmitted through the previous inverted scan line of the previous pixel. The organic light emitting diode display includes data lines 171 and drive voltage lines 172 that extend in a second direction intersecting the first direction and respectively transmit data voltages Dm and drive voltage ELVDD.

[0080] In an organic light emitting diode display, one pixel PX includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and an organic light emitting diode OLED.

[0081] In addition, according to Figures 3 to 5 the organic light emitting diode display further includes an overlapping layer 125 formed of a metal having conductive properties or a semiconductor material equivalent thereto. The overlapping layer 125 may be disposed below a semiconductor layer formed of an oxide semiconductor, may overlap a channel of the third transistor T3 in a plan view, and may at least partially overlap a first electrode and a second electrode of the third transistor T3. Referring to Figure 5 , the overlapping layer 125 is connected to a protruding portion 172-1 of the drive voltage line 172 in an adjacent pixel PX through an opening 66 to receive the drive voltage ELVDD. The overlapping layer 125 to which the drive voltage ELVDD is applied is used to keep a constant voltage of the oxide semiconductor forming the channel of the third transistor T3, and thus the third transistor T3 does not generate leakage current, enabling it to operate stably.

[0082] The organic light emitting diode OLED includes an anode, an organic light emitting layer, and a cathode.

[0083] The driving transistors T1, second transistors T2, third transistors T3, fourth transistors T4, fifth transistors T5, sixth transistors T6, and seventh transistors T7 are mainly divided into two types distinguished by the materials forming the corresponding channels. That is, they are divided into a group of switching transistors formed of an oxide semiconductor and having n-type transistor characteristics and a group of driving transistors formed of a polycrystalline semiconductor and having p-type transistor characteristics.

[0084] In Figure 3In an embodiment, the driving transistor group includes a driving transistor T1, a second transistor T2, a fifth transistor T5, and a sixth transistor T6. The switching transistor group includes the remaining transistors, that is, a third transistor T3, a fourth transistor T4, and a seventh transistor T7.

[0085] The transistors included in the corresponding transistor groups may be formed to include semiconductor layers having structures connected to each other.

[0086] First, the structure of the polycrystalline semiconductor layer 130 of the driving transistor group will be described. The polycrystalline semiconductor layer 130 includes a first polycrystalline semiconductor layer 131, a second polycrystalline semiconductor layer 132, and a third polycrystalline semiconductor layer 133 connecting the first polycrystalline semiconductor layer 131 and the second polycrystalline semiconductor layer 132.

[0087] The first polycrystalline semiconductor layer 131 has a structure extending mainly in the Figure 3 left side in the first direction, and the channels of the second transistor T2 and the fifth transistor T5 are formed in the first polycrystalline semiconductor layer 131. The portions of the first polycrystalline semiconductor layer 131 other than the channels of the second transistor T2 and the fifth transistor T5 may be doped to have the same characteristics as the wiring.

[0088] The second polycrystalline semiconductor layer 132 has a structure extending mainly in the Figure 3 right side in the first direction, and the channel of the sixth transistor T6 is formed in the second polycrystalline semiconductor layer 132. The portions of the second polycrystalline semiconductor layer 132 other than the channel of the sixth transistor T6 may be doped to have the same characteristics as the wiring.

[0089] The third polycrystalline semiconductor layer 133 connects the first polycrystalline semiconductor layer 131 and the second polycrystalline semiconductor layer 132 and has a U-shaped structure. The third polycrystalline semiconductor layer 133 includes the channel of the driving transistor T1 and portions other than the channel of the driving transistor T1 that are doped to have the same characteristics as the wiring.

[0090] In addition, the polycrystalline semiconductor layer 130 relates to at least one of the first electrode and the second electrode of the driving transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6. The first electrode and the second electrode are disposed in the doped regions and are electrically connected to the adjacent transistors.

[0091] Each of the channels of the driving transistors T1, second transistor T2, fifth transistor T5, and sixth transistor T6 included in the driving transistor group overlaps with a corresponding gate electrode and is disposed between the first electrode and the second electrode. The driving transistors T1, second transistor T2, fifth transistor T5, and sixth transistor T6 included in the driving transistor group have substantially the same stacked structure. Hereinafter, the structures of the driving transistors T1, second transistor T2, fifth transistor T5, and sixth transistor T6 included in the driving transistor group will be described.

[0092] The driving transistor T1 includes a channel, a gate electrode 155, a first electrode S1, and a second electrode D1. The channel of the driving transistor T1 is between the first electrode S1 and the second electrode D1 and overlaps with the gate electrode 155 in a plan view. The channel is formed in the third polycrystalline semiconductor layer 133 and is bent into a U shape to form a long channel in a limited area. As the length of the channel increases, the driving voltage range of the gate voltage (Vg) applied to the gate electrode 155 of the driving transistor T1 can increase, and the driving current Id increases steadily according to the gate voltage (Vg). Therefore, the gray scale of the light emitted from the organic light emitting diode OLED can be finely controlled by changing the gate voltage (Vg), and the display quality of the organic light emitting diode display can also be improved. In addition, since the channel extends in several directions instead of one direction, the influence caused by directionality is canceled in the manufacturing process, thereby reducing the influence of process variations. Therefore, it is possible to avoid deterioration of image quality such as point defects (for example, a brightness difference occurs according to pixels even when the same data voltage Dm is applied). Point defects may occur because the characteristics of the driving transistor T1 vary according to the region of the display device due to process dispersion. The shape of the channel is not limited to the U shape shown, but can be various shapes such as an Ω shape, an S shape, etc.

[0093] The gate electrode 155 overlaps with the channel in a plan view. The first electrode S1 and the second electrode D1 are disposed on opposite sides of the channel. An extended portion of the storage line 126 is isolated from the gate electrode 155 and is disposed on the gate electrode 155. In a plan view, the extended portion of the storage line 126 overlaps with the gate electrode 155 with a second gate insulating film therebetween to form a storage capacitor Cst. The extended portion of the storage line 126 is the first storage electrode ( Figure 1 E1) of the storage capacitor Cst, and the gate electrode 155 is the second storage electrode ( Figure 1For E2). An extension of the storage line 126 is provided with an opening 56 such that the gate electrode 155 can be connected to the first data connection member 71. In the opening 56, the upper surface of the gate electrode 155 and the first data connection member 71 are electrically connected through the opening 61. The first data connection member 71 is connected to the second electrode D3 of the third transistor T3 to connect the gate electrode 155 of the driving transistor T1 to the second electrode D3 of the third transistor T3.

[0094] The gate electrode of the second transistor T2 can be part of the scanning line 151. The data line 171 is connected to the first electrode S2 of the second transistor T2 through the opening 62, and the first electrode S2 and the second electrode D2 can be arranged on the first polysemiconductor layer 131.

[0095] The gate electrode of the fifth transistor T5 can be part of the light emission control line 153. The driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the opening 67, and the second electrode D5 is connected to the first electrode S1 of the driving transistor T1 through the first polysemiconductor layer 131.

[0096] The gate electrode of the sixth transistor T6 can be part of the light emission control line 153. The second electrode D6 of the sixth transistor T6 is connected to the first electrode S7 of the seventh transistor T7 and also to the anode of the organic light-emitting diode OLED using the opening 64 that exposes the second polysemiconductor layer 132, the opening 64-1 that exposes the oxide semiconductor layer 135, and the fourth data connection member 74. In addition, the first electrode S6 is connected to the second electrode D1 of the driving transistor T1 through the second polysemiconductor layer 132.

[0097] On the other hand, the oxide semiconductor layer 135 of the switching transistor group is formed on a layer different from the polysemiconductor layer 130 and has a long extension structure. The oxide semiconductor layer 135 is arranged on a layer higher than the gate electrode 155 and the storage line 126. The oxide semiconductor layer 135 includes the channels of the third transistor T3, the fourth transistor T4, and the seventh transistor T7. In addition, the portion of the oxide semiconductor layer 135 excluding the channels of the third transistor T3, the fourth transistor T4, and the seventh transistor T7 is doped to have the same characteristics as the wiring. In this case, the channel of the seventh transistor T7 is included in the following pixel PX, and the seventh transistor T7 arranged in the oxide semiconductor layer 135 is included in the pixel PX.

[0098] In addition, at least some of the channels of the third transistor T3, the fourth transistor T4, and the first and second electrodes of the seventh transistor T7 are formed in the oxide semiconductor layer 135. The first and second electrodes are arranged in the doped region and are electrically connected to the adjacent transistors.

[0099] Each of the channels of the third transistor T3, the fourth transistor T4, and the seventh transistor T7 included in the switching transistor group overlaps with each gate electrode and is disposed between the first electrode and the second electrode. The stacked structures around the channels of the third transistor T3, the fourth transistor T4, and the seventh transistor T7 included in the switching transistor group are substantially the same. Hereinafter, the structures of the channels of the third transistor T3, the fourth transistor T4, and the seventh transistor T7 included in the switching transistor group will be described.

[0100] The channel of the third transistor T3 is formed at a portion where the main reverse scan line 151-1 meets the oxide semiconductor layer 135. The gate electrode G3 of the third transistor T3 may be a part of the main reverse scan line 151-1. The first electrode S3 of the third transistor T3 is connected to the second polysemiconductor layer 132 through the third data connection member 73, and thus it is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the first data connection member 71 through the opening 61-1.

[0101] The overlapping layer 125 is formed under the channel of the third transistor T3. The overlapping layer 125 may overlap with the channel of the third transistor T3 in a plan view and may partially overlap with at least some of the first electrode S3 and the second electrode D3 of the third transistor T3, and in some embodiments, the overlapping layer 125 may overlap with the entire first electrode S3 and the second electrode D3 of the third transistor T3.

[0102] The overlapping layer 125 includes a portion overlapping with the channel of the third transistor T3 and a connecting portion connected thereto. Refer to Figure 3 , the connecting portion of the overlapping layer 125 extends from the portion overlapping with the channel of the third transistor T3 toward the right pixel PX and is connected to the driving voltage line 172 through the opening 66 in the right pixel PX to receive the driving voltage ELVDD. The overlapping layer 125 is formed in the second gate conductor. Hereinafter, the second gate conductor may also be referred to as the second conductor.

[0103] The connecting portion of the overlapping layer 125 is connected to the driving voltage line 172 through the opening 66 in the right pixel PX to receive the driving voltage ELVDD. The driving voltage line 172 has an extension or protrusion 172-1, and this extension is electrically connected to the overlapping layer 125 through the opening 66 to transmit the driving voltage ELVDD to the overlapping layer 125. The opening 66 is formed in the third gate insulating film 143, the fourth gate insulating film 144, and the interlayer insulating film 160 (see Figure 5)。Hereinafter, the third gate insulating film 143, the fourth gate insulating film 144, and the interlayer insulating film 160 may also be referred to as the third insulating film, the fourth insulating film, and the fifth insulating film, respectively.

[0104] Although a structure including two transistors for eliminating the leakage current from the third transistor T3 (a structure in which the same signal is applied to the gate electrodes of the two transistors and one signal input to one transistor is output to the other transistor) may be provided, in the present embodiment, since the leakage current is reduced by the overlapping layer 125, a structure not including two transistors can be provided. With the development of high-resolution pixels, there has been a problem of a reduced space for forming actual pixels, but this structure has the advantage that pixels can be formed even in a small area.

[0105] The channel of the fourth transistor T4 is formed at a portion where the previous inversion scan line 152-1 meets the oxide semiconductor layer 135. The gate electrode G4 of the fourth transistor T4 may be a part of the previous inversion scan line 152-1. The second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the opening 65-1 to receive the initialization voltage Vint, and the first data connection member 71 is connected to the second electrode D2 of the fourth transistor T4 through the opening 61-1.

[0106] The channel of the seventh transistor T7 is formed at a portion where the bypass control line 152-1' meets the oxide semiconductor layer 135. The gate electrode G7 of the seventh transistor T7 may be a part of the bypass control line 152-1', and the bypass control line 152-1' may be electrically connected to the previous inversion scan line 152-1 of the previous pixel PX. The first electrode S7 of the seventh transistor T7 is connected to the fourth data connection member 74 through the opening 64-1 and is electrically connected to the anode of the organic light-emitting diode OLED. In addition, the second electrode D7 is connected to the second data connection member 72 through the opening 65-1, and the initialization voltage Vint is applied to the second electrode D7.

[0107] The storage capacitor Cst includes a first storage electrode E1 and a second storage electrode E2 that overlap each other with the second gate insulating film 142 therebetween. Hereinafter, the second gate insulating film 142 may be referred to as the second insulating film. The second storage electrode E2 corresponds to the gate electrode 155 of the driving transistor T1, and the first storage electrode E1 may be an extension of the storage line 126. Herein, the second gate insulating film 142 becomes a dielectric, and the capacitance is determined by the charge stored in the storage capacitor Cst and the voltage between the first storage electrode E1 and the second storage electrode E2. By using the gate electrode 155 as the second storage electrode E2, a space for forming the storage capacitor Cst can be ensured in a space narrowed due to the channel of the driving transistor T1 occupying a large area in the pixel.

[0108] The driving voltage line 172 is connected to the first storage electrode E1 through the contact opening 68. Accordingly, the storage capacitor Cst stores charges corresponding to the difference between the driving voltage ELVDD transmitted to the first storage electrode E1 through the driving voltage line 172 and the gate voltage (Vg) of the gate electrode 155.

[0109] The first data connection member 71 includes one end connected to the gate electrode 155 through the opening 56 formed in the storage line 126 and the other end connected to the second electrode D3 of the third transistor T3 disposed in the oxide semiconductor layer 135. The first data connection member 71 is connected to the gate electrode 155 through the opening 61 and to the oxide semiconductor layer 135 through the opening 61-1.

[0110] The second data connection member 72 includes one end connected to the initialization voltage line 127 through the opening 65 and the other end connected to the second electrode D7 of the seventh transistor T7 disposed in the oxide semiconductor layer 135 and connected to the first electrode S4 of the fourth transistor T4 through the opening 65-1.

[0111] The oxide semiconductor layer 135 and the second polycrystalline semiconductor layer 132 are electrically connected to each other through the third data connection member 73 and the fourth data connection member 74.

[0112] The third data connection member 73 is connected to the second polycrystalline semiconductor layer 132 through the opening 63 and to the oxide semiconductor layer 135 through the opening 63-1. As a result, the second electrode D1 of the driving transistor T1 and the first electrode S3 of the third transistor T3 are electrically connected.

[0113] The fourth data connection member 74 is connected to the second polycrystalline semiconductor layer 132 through the opening 64 and to the oxide semiconductor layer 135 through the opening 64-1. As a result, the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7 are electrically connected, and although not shown, they are electrically connected to the anode of the organic light-emitting diode OLED. When electrically connected to the anode of the organic light-emitting diode OLED, they may be connected through an additional connection member (not shown).

[0114] Hereinafter, reference will be made to Figure 4 and Figure 5 The cross-sectional structure of the organic light-emitting diode display according to the embodiment will be described according to the stacking order.

[0115] The organic light-emitting diode display according to the embodiment includes a rigid substrate such as glass or a substrate formed of a flexible material such as plastic or polyimide (PI).

[0116] The blocking layer 111 is disposed on the substrate 110, and the buffer layer 112 is disposed on the blocking layer 111. The blocking layer 111 and the buffer layer 112 may include inorganic insulating materials such as silicon oxide, silicon nitride, or aluminum oxide, and may also include organic insulating materials such as polyimide acrylic (added with epoxy resin).

[0117] The semiconductor layer for the transistors included in the driving transistor group is formed on the buffer layer 112. That is, the polycrystalline semiconductor layer 130 is disposed on the buffer layer 112, and the polycrystalline semiconductor layer 130 includes the channels of the driving transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6, as well as the first electrode or the second electrode of these transistors.

[0118] The first gate insulating film 141 covering the polycrystalline semiconductor layer 130 is disposed on the polycrystalline semiconductor layer 130 including the second polycrystalline semiconductor layer 132 and the third polycrystalline semiconductor layer 133. Hereinafter, the first gate insulating film 141 may also be referred to as the first insulating film.

[0119] The first gate conductor including the gate electrodes of the transistors included in the driving transistor group, the scanning line 151, and the light emission control line 153 is disposed on the first gate insulating film 141. Hereinafter, the first gate conductor may also be referred to as the first conductor. The gate electrodes of the transistors included in the driving transistor group overlap with the channels of the transistors included in each driving transistor group. The scanning line 151 and the light emission control line 153 extend in the first direction.

[0120] The first gate conductor will be described in more detail below.

[0121] The scanning line 151 extends in the first direction, and the portion thereof overlapping with the first polycrystalline semiconductor layer 131 serves as the gate electrode of the second transistor T2.

[0122] The light emission control line 153 also extends in the first direction. The portion thereof overlapping with the first polycrystalline semiconductor layer 131 serves as the gate electrode of the fifth transistor T5, and the portion thereof overlapping with the second polycrystalline semiconductor layer 132 serves as the gate electrode of the sixth transistor T6.

[0123] On the other hand, the gate electrode 155 of the driving transistor T1 is also formed by the first gate conductor and has an island structure.

[0124] The second gate insulating film 142 covering the first gate conductor and the exposed first gate insulating film 141 is disposed thereon.

[0125] The second gate conductor including the storage line 126, the initialization voltage line 127, and the overlapping layer 125 is disposed on the second gate insulating film 142.

[0126] The second gate conductor will be described in more detail below.

[0127] The storage line 126 extends in a first direction and has an extension. The extension of the storage line 126 serves as a first storage electrode E1 and has an opening 56 that exposes a part of the gate electrode 155 formed by the first gate conductor.

[0128] The initialization voltage line 127 also extends in the first direction and transmits a constant initialization voltage Vint.

[0129] The overlap layer 125 is disposed at a portion where the channel of the third transistor T3 is to be formed and has an island-like structure. Additionally, the overlap layer 125 according to the present embodiment has a structure that extends to the pixel PX arranged on the right side and receives the driving voltage ELVDD from the pixel PX arranged on the right side.

[0130] A third gate insulating film 143 that covers the second gate conductor and the exposed second gate insulating film 142 is disposed thereon.

[0131] An oxide semiconductor layer 135 for the transistors included in the switching transistor group is formed on the third gate insulating film 143. The oxide semiconductor layer 135 includes the channels of the third transistor T3, the fourth transistor T4, and the seventh transistor T7, and may include the first electrode or the second electrode of these transistors.

[0132] A fourth gate insulating film 144 that covers the oxide semiconductor layer 135 and the exposed third gate insulating film 143 is disposed thereon. Refer to Figure 4 and Figure 5 , although the fourth gate insulating film 144 is formed over the entire area, as Figure 11 and Figure 12 shown, the fourth gate insulating film 144 is etched together with the third gate conductor existing thereon so that the third gate conductor and the fourth gate insulating film 144 can be formed to have the same planar structure. Hereinafter, the third gate conductor may also be referred to as the third conductor.

[0133] The first gate insulating film 141, the second gate insulating film 142, the third gate insulating film 143, and the fourth gate insulating film 144 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride (SiON).

[0134] A third gate conductor including the gate electrodes of the transistors included in the switching transistor group, the main reverse scan line 151-1, the previous reverse scan line 152-1, and the bypass control line 152-1' is disposed on the fourth gate insulating film 144.

[0135] The third gate conductor will be described in more detail below.

[0136] The main reverse scan line 151-1 extends in the first direction, and the portion thereof overlapping with the oxide semiconductor layer 135 serves as the gate electrode of the third transistor T3.

[0137] The previous reverse scan line 152-1 also extends in the first direction, and the portion thereof overlapping with the oxide semiconductor layer 135 (which is the upward protruding portion) serves as the gate electrode of the fourth transistor T4.

[0138] The bypass control line 152-1' also extends in the first direction, and the portion thereof overlapping with the oxide semiconductor layer 135 serves as the gate electrode of the seventh transistor T7. Specifically, in the present embodiment, the bypass control line 152-1' is the same line as the previous reverse scan line 152-1 connected to the gate electrode of the fourth transistor T4 in the previous pixel PX.

[0139] The interlayer insulating film 160 covering the third gate conductor is disposed on the third gate conductor. The interlayer insulating film 160 can be formed of an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride (SiON).

[0140] The interlayer insulating film 160, the fourth gate insulating film 144, the third gate insulating film 143, the second gate insulating film 142, and the first gate insulating film 141 may be provided with openings so that the data conductor formed on the interlayer insulating film 160 can be connected to another conductor or semiconductor layer. Hereinafter, the data conductor may also be referred to as the fourth conductor. In this case, the depth of the opening may be very deep. When forming the opening, an opening having a certain depth and an opening having a deeper depth may be formed by different processes, thereby reducing the etching burden applied to each layer.

[0141] A data conductor including a data line 171, a driving voltage line 172, a first data connection member 71, a second data connection member 72, a third data connection member 73, and a fourth data connection member 74 is disposed on the interlayer insulating film 160.

[0142] The data conductor will be described in more detail below.

[0143] The data line 171 extends in the second direction and is electrically connected to the first polycrystalline semiconductor layer 131 through an opening 62 at a portion overlapping with the first polycrystalline semiconductor layer 131 to transmit a data voltage to the first electrode S2 of the second transistor T2. Here, the opening 62 is formed in the first gate insulating film 141, the second gate insulating film 142, the third gate insulating film 143, the fourth gate insulating film 144, and the interlayer insulating film 160.

[0144] The driving voltage line 172 also extends in the second direction and transmits the driving voltage ELVDD. The driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through an opening 67 formed in the first gate insulating film 141, the second gate insulating film 142, the third gate insulating film 143, and the fourth gate insulating film 144, and is connected to an extension (first storage electrode E1) of the storage line 126 through a contact opening 68 formed in the third gate insulating film 143, the fourth gate insulating film 144, and the interlayer insulating film 160. Additionally, the driving voltage line 172 has an extension or protruding portion 172-1, and this extension is electrically connected to the overlapping layer 125 through the opening 66 to transmit the driving voltage ELVDD to the overlapping layer 125. The opening 66 is formed in the third gate insulating film 143, the fourth gate insulating film 144, and the interlayer insulating film 160.

[0145] One end of the first data connection member 71 is connected to the gate electrode 155 through an opening 61 formed in the second gate insulating film 142, the third gate insulating film 143, the fourth gate insulating film 144, and the interlayer insulating film 160, and the other end of the first data connection member 71 is connected to the second electrode D3 of the third transistor T3 and the second electrode D4 of the fourth transistor T4 through an opening 61-1 formed in the fourth gate insulating film 144 and the interlayer insulating film 160.

[0146] One end of the second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 and the second electrode D7 of the seventh transistor T7 through an opening 65-1 formed in the fourth gate insulating film 144 and the interlayer insulating film 160, and the other end of the second data connection member 72 is connected to the initialization voltage line 127 through an opening 65 formed in the third gate insulating film 143, the fourth gate insulating film 144, and the interlayer insulating film 160.

[0147] Additionally, the data conductor further includes a third data connection member 73 and a fourth data connection member 74 that connect the polycrystalline semiconductor layer 130 and the oxide semiconductor layer 135.

[0148] The third data connection member 73 is connected to the second polycrystalline semiconductor layer 132 through an opening 63 and is connected to the oxide semiconductor layer 135 through an opening 63-1.

[0149] The fourth data connection member 74 is connected to the second polycrystalline semiconductor layer 132 through an opening 64 and is connected to the oxide semiconductor layer 135 through an opening 64-1.

[0150] Here, the openings 63 and 64 are formed in the first gate insulating film 141, the second gate insulating film 142, the third gate insulating film 143, the fourth gate insulating film 144, and the interlayer insulating film 160, and the openings 63-1 and 64-1 are formed in the fourth gate insulating film 144 and the interlayer insulating film 160.

[0151] When a data conductor is electrically connected to a polycrystalline semiconductor layer, a first gate conductor, a second gate conductor, or a third gate conductor disposed thereunder, due to the difference in depth between the layers, the electrical connection therebetween may be difficult, and thus an auxiliary gate electrode may be further formed as a layer (the first gate conductor, the second gate conductor, or the third gate conductor) disposed therebetween.

[0152] A passivation layer 180 covering the data conductor is disposed on the data conductor. The passivation layer 180 (also referred to as a planarization film) may include an organic insulating material. An anode (not shown) serving as an electrode of an organic light-emitting diode (OLED) is disposed on the passivation layer 180. The anode is electrically connected to a sixth transistor T6 and a seventh transistor T7 through an opening (not shown) formed in the passivation layer 180. A partition wall (not shown) is disposed on the passivation layer 180 and the anode. The partition wall has an opening portion overlapping with the anode, and an organic light-emitting layer (not shown) is disposed in the opening portion. A cathode (not shown) serving as the other electrode of the organic light-emitting diode OLED is disposed on the organic light-emitting layer and the partition wall. The anode, the organic light-emitting layer, and the cathode form the organic light-emitting diode OLED. In some embodiments, the positions of the anode and the cathode may be changed. When holes and electrons are injected into the light-emitting layer from the anode and the cathode, respectively, light is emitted when the excitons formed by the combined injected holes and electrons transition from the excited state to the ground state.

[0153] Although not shown, a packaging layer (not shown) for protecting the organic light-emitting diode (OLED) is disposed on the common electrode. The packaging layer may be in contact with the common electrode or may be spaced apart from the common electrode. The packaging layer may be a thin-film packaging layer in which an inorganic film and an organic film are stacked, and may include three layers formed of an inorganic film, an organic film, and an inorganic film. A capping layer and a functional layer may be disposed between the common electrode and the packaging layer.

[0154] In Figure 4 and Figure 5 the cross-sectional position of the overlapping layer 125 in the present embodiment and the structure in which the overlapping layer 125 is electrically connected to the driving voltage line 172 are specifically shown in the specific cross-sectional view.

[0155] Figure 4 The cross-sectional position of the overlapping layer 125 is specifically illustrated.

[0156] The blocking layer 111, the buffer layer 112, the first gate insulating film 141, and the second gate insulating film 142 are sequentially disposed on the substrate 110, and the overlapping layer 125 is disposed thereon. The third gate insulating film 143 is disposed on the overlapping layer 125, and the oxide semiconductor layer 135 is disposed on the third gate insulating film 143. The fourth gate insulating film 144 is disposed on the oxide semiconductor layer 135. The gate electrode of the third transistor T3 is formed on the fourth gate insulating film 144, and the gate electrode of the third transistor T3 is disposed on the main reverse scan line 151-1. The interlayer insulating film 160 is disposed on the gate electrode of the third transistor T3, and the passivation layer 180 is disposed on the interlayer insulating film 160.

[0157] Reference Figure 5 , it can be clearly seen the connection structure of the overlapping layer 125 and the driving voltage line 172.

[0158] The blocking layer 111, the buffer layer 112, the first gate insulating film 141, and the second gate insulating film 142 are sequentially disposed on the substrate 110, and the overlapping layer 125 is disposed thereon. The third gate insulating film 143 is disposed on the overlapping layer 125, the fourth gate insulating film 144 is disposed on the third gate insulating film 143, and the interlayer insulating film 160 is disposed on the fourth gate insulating film 144. The extension or protrusion 172-1 of the driving voltage line 172 is disposed on the interlayer insulating film 160, and the extension or protrusion 172-1 of the driving voltage line 172 is electrically connected to the overlapping layer 125 through the opening 66. The opening 66 is formed in the third gate insulating film 143, the fourth gate insulating film 144, and the interlayer insulating film 160.

[0159] The overlapping layer 125 according to the above embodiment has a structure to which the driving voltage ELVDD is applied, and it overlaps with the channel of the third transistor T3 in the plan view. In addition, since the driving voltage ELVDD, which is a positive voltage, is applied to this structure, the voltage of the oxide semiconductor layer 135 in the underlying portion is maintained, so that the leakage current generated from the oxide semiconductor is reduced, and it is used to stably operate the organic light emitting diode display.

[0160] Above, an example is described in which in a pixel of an organic light emitting diode display for including transistors in a driving transistor group (wherein the semiconductor layer is formed of polycrystalline semiconductor) and transistors in a switching transistor group (wherein an oxide semiconductor layer is formed), the third transistor T3, which is one of the transistors in the switching transistor group, is provided with the overlapping layer 125 that overlaps with the channel of the third transistor T3, and the overlapping layer 125 is applied with the driving voltage ELVDD.

[0161] Hereinafter, reference will be made to Figures 6 to 8 Describe another embodiment.

[0162] In Figures 6 to 8 the embodiment, the voltage applied to the overlapping layer 125 is connected to the gate electrode G3 which is one of the three electrodes of the third transistor T3.

[0163] Hereinafter, features different from those of the Figures 1 to 5 embodiment will be mainly described.

[0164] First, the circuit configuration will be described with reference to Figure 6 the

[0165] Figure 6 FIG. illustrates an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an embodiment.

[0166] Figure 6 The difference from the Figure 1 embodiment is that the overall circuit configuration of the pixel PX is basically similar, but the overlapping layer 125 is connected to the gate electrode G3 of the third transistor T3. That is, instead of the driving voltage ELVDD, the inverted scan signal Sn' applied to the main inverted scan line 151-1 connected to the gate electrode G3 of the third transistor T3 is applied to the overlapping layer 125 disposed under the oxide semiconductor layer 135 of the third transistor T3. Since the gate electrode G3 of the third transistor T3 is disposed on the upper side of the oxide semiconductor layer 135, and the same signal is applied to the gate electrode G3 and the overlapping layer 125 disposed on the upper side and the lower side of the oxide semiconductor layer 135, respectively, the same operation is performed as in the structure in which two gate electrodes (bottom gate and top gate) are present. A transistor having such a double gate structure may have a lower voltage difference (Vgs) between the gate electrode and the source electrode than a transistor having a structure using a single gate electrode, resulting in more stable characteristics and reduced leakage current.

[0167] Hereinafter, the structure of the pixel PX in which the characteristics of the circuit having the Figure 7 and Figure 8 are actually implemented will be described with reference to Figure 6 the

[0168] Figure 7 FIG. illustrates a layout diagram of a pixel region of an organic light emitting diode display according to an embodiment, and Figure 8 FIG. illustrates a cross-sectional view taken along line VIII-VIII of the Figure 7 embodiment.

[0169] Figure 7 and Figure 8 The embodiments of the Figures 3 to 5 are different from those of the

[0170] The overlapping layer 125 includes a portion overlapping with the channel of the third transistor T3 and a connecting portion connected thereto. Refer to Figure 7 , the portion of the overlapping layer 125 overlapping with the channel of the third transistor T3 and the connecting portion of the overlapping layer 125 connected to the third transistor T3 have a structure bent at 90 degrees to each other. The overlapping layer 125 is formed in the second gate conductor.

[0171] The overlapping layer 125 and the gate electrode of the third transistor T3 are connected to each other to receive the inverted scan signal Sn'. The main inverted scan line 151-1 and the overlapping layer 125 are connected to each other using the connection auxiliary portion 75. Here, the connection auxiliary portion 75 is formed in the data conductor. That is, one end of the connection auxiliary portion 75 is connected to the overlapping layer 125 through the opening 66, and the other end is connected to the main inverted scan line 151-1 through the opening 66-1. Here, the opening 66 is formed by passing through the third gate insulating film 143, the fourth gate insulating film 144, and the interlayer insulating film 160, and the opening 66-1 is formed by passing through the interlayer insulating film 160.

[0172] The structure of the overlapping layer 125 as an additional gate electrode of the third transistor T3 has been described above.

[0173] Hereinafter, refer to Figure 9 and Figure 10 to describe an embodiment in which a separate voltage from the outside is applied to the overlapping layer 125.

[0174] Hereinafter, the features different from those of Figures 1 to 5 will be mainly described, and first, the circuit configuration will be described with reference to Figure 9 .

[0175] Figure 9 The equivalent circuit diagram of one pixel of an organic light emitting diode display according to an embodiment is illustrated.

[0176] Figure 9 The difference from Figure 1 is that the overall circuit configuration of the pixel PX is basically similar, but the overlapping layer 125 receives a separate input signal IND. That is, instead of the driving voltage ELVDD, a separate input signal IND applied from the outside is applied to the overlapping layer 125 disposed below the oxide semiconductor layer 135 of the third transistor T3, and the input signal IND of this embodiment has a constant positive voltage. The separate input signal IND disposed below the oxide semiconductor layer 135 of the third transistor T3 is used to maintain the voltage of the oxide semiconductor layer 135, so that the leakage current of the third transistor T3 is removed and the third transistor T3 is stabilized.

[0177] Hereinafter, refer to Figure 10 to describe an embodiment in whichFigure 9 The structure of the pixel PX for the characteristics of the circuit.

[0178] Figure 10 The layout diagram of one pixel region of the organic light emitting diode display according to an embodiment is illustrated.

[0179] Figure 10 The embodiment of Figures 3 to 5 differs from the embodiment of

[0180] The overlapping layer 125 includes a portion overlapping with the channel of the third transistor T3 and a connecting portion connected thereto. Additionally, Figure 10 The embodiment of

[0181] differs from other embodiments in that Figure 10 the structure of the overlapping layer 125 shown has the difference that no opening is separately formed in the pixel PX.

[0182] In the above description, the overlapping layer 125 receives the input signal IND from the outside through the voltage application line 125-1, and the input signal IND has a constant positive voltage. In the exemplary embodiment, the voltage application line 125-1 is spaced apart from the driving voltage source that supplies the driving voltage ELVDD to the organic light emitting diode OLED.

[0183] Hereinafter, with reference to Figure 11 and Figure 12 the structure in which the overlapping layer 125 is connected to the first electrode or the second electrode of the third transistor T3 will be described.

[0184] Figure 11 and Figure 12 The cross-sectional view of a part of one pixel in the organic light emitting diode display according to an embodiment is illustrated.

[0185] Figure 11 and Figure 12 The embodiment of Figures 6 to 8 is a similar embodiment to the embodiment of Figure 4 except that the overlapping layer 125 is electrically connected to one of the electrodes of the third transistor T3. Different from the cross-sectional views of Figure 5 etc., Figure 11 and Figure 12The figure mainly shows a cross-sectional view of a characteristic part of a pixel of an organic light-emitting diode display.

[0186] First, the Figure 11 embodiment will be described.

[0187] Unlike Figure 4 and Figure 5 , the barrier layer 111 and the buffer layer 112 disposed on the substrate 110 are not shown. This indicates that the barrier layer 111 and the buffer layer 112 can be omitted in some embodiments. Figure 11 The structure shown on the right side of

[0188] Figure 11 is a cross-sectional structure on which the driving transistor T1 and the storage capacitor Cst are disposed, and Figure 11 the structure shown on the left side of

[0189] is a cross-sectional structure of the third transistor T3 and the overlapping layer 125 overlapping with the third transistor T3. Figure 11 The structure shown on the right side of

[0190] will be described. Figure 11 As shown on the right side of

[0191] , the driving transistor T1 is formed by disposing a polycrystalline semiconductor layer 130 on the substrate 110, covering the polycrystalline semiconductor layer 130 with the first gate insulating film 141, and then forming a gate electrode G1 on the first gate insulating film 141. The channel, the first electrode, and the second electrode of the driving transistor T1 are formed on the polycrystalline semiconductor layer 130.

[0192] The storage capacitor Cst is formed in the pixel PX according to the present embodiment, and the two electrodes of the storage capacitor Cst are formed as the gate electrode G1 of the driving transistor T1 and the extension of the storage line 126 that are insulated from each other and overlap each other. The second gate insulating film 142 disposed therebetween serves as the dielectric layer of the storage capacitor Cst. Figure 4 and Figure 5 Unlike Figure 11 , in the

[0193] embodiment, since the fourth gate insulating film 144 is only partially formed, the fourth gate insulating film 144 is not formed on the storage capacitor Cst. In some embodiments, the fourth gate insulating film 144 can be only partially formed. Figure 11 Referring to the structure shown on the left side of

[0194] The first gate insulating film 141 and the second gate insulating film 142 are sequentially stacked on the substrate 110. Thereafter, the overlapping layer 125 is disposed on the second gate insulating film 142. The third gate insulating film 143 is disposed on the overlapping layer 125. The oxide semiconductor layer 135 is disposed on the third gate insulating film 143. The fourth gate insulating film 144 is disposed on the oxide semiconductor layer 135, and the gate electrode G3 of the third transistor T3 is formed on the fourth gate insulating film 144. Here, the fourth gate insulating film 144 and the gate electrode G3 of the third transistor T3 may have the same planar shape.

[0195] The interlayer insulating film 160 is disposed on the gate electrode G3 of the third transistor T3, and the connection auxiliary portion 75 for electrically connecting the first electrode S3 of the third transistor T3 and the overlapping layer 125 is formed on the interlayer insulating film 160. One end of the connection auxiliary portion 75 is connected to the overlapping layer 125 through the opening 66, and the other end of the connection auxiliary portion 75 is connected to the first electrode S3 of the third transistor T3 through the opening 66-1. The opening 66 penetrates through the third gate insulating film 143 and the interlayer insulating film 160 to expose the overlapping layer 125, and the opening 66-1 penetrates through the interlayer insulating film 160 to expose the first electrode S3.

[0196] Meanwhile, in some embodiments, the overlapping layer 125 may be connected to Figure 12 the second electrode D3 of the third transistor T3 shown.

[0197] Figure 12 Same as Figure 11 basically, except that the connection auxiliary portion 75 electrically connected to the overlapping layer 125 is connected to the second electrode D3 of the third transistor T3 instead of the first electrode S3 of the third transistor T3.

[0198] As in the Figure 6 embodiment of, in Figure 11 and Figure 12 the overlapping layer 125 is electrically connected to one electrode of the third transistor T3 overlapping the overlapping layer 125, thereby stabilizing the characteristics of the oxide semiconductor layer 135.

[0199] In the above description, the overlapping layer 125 overlaps with the third transistor T3.

[0200] Hereinafter, embodiments in which the overlapping layer 125 overlaps with the fourth transistor T4 or the seventh transistor T7 of the switching transistor group including the oxide semiconductor layer will be described.

[0201] First, embodiments in which the overlapping layer 125 overlaps with the fourth transistor T4 will be described with reference to Figure 13 .

[0202] Figure 13The equivalent circuit diagram of one pixel of an organic light emitting diode display according to an embodiment is illustrated.

[0203] Compared with Figure 1 in Figure 13 , the overlapping layer 125 does not overlap with the third transistor T3, but overlaps with the fourth transistor T4. In addition, Figure 13 the structure of the pixel of Figure 1 is the same as the structure of the pixel of

[0204] In addition, different from the embodiment of Figure 13 , the overlapping layer 125 may be connected to one electrode of the transistor overlapping with the overlapping layer 125, or may be applied with a predetermined positive voltage instead of the driving voltage ELVDD.

[0205] Furthermore, in some embodiments, Figure 1 and Figure 13 the embodiments of

[0206] may be applied together to include both the overlapping layer 125 overlapping with the third transistor T3 and the overlapping layer 125 overlapping with the fourth transistor T4. Figure 14 Hereinafter, an embodiment in which the overlapping layer 125 overlaps with the seventh transistor T7 will be described with reference to

[0207] Figure 14 The equivalent circuit diagram of one pixel of an organic light emitting diode display according to an embodiment is illustrated.

[0208] Compared with Figure 1 in Figure 14 , the overlapping layer 125 does not overlap with the third transistor T3, but overlaps with the seventh transistor T7. In addition, Figure 14 the structure of the pixel of Figure 1 is the same as the structure of the pixel of

[0209] In addition, different from the embodiment of Figure 14 , the overlapping layer 125 may be connected to one electrode of the transistor overlapping with the overlapping layer 125, or may be applied with a predetermined positive voltage instead of the driving voltage ELVDD.

[0210] Furthermore, in some embodiments, Figure 1 and Figure 14The embodiments of can be applied together to include both the overlapping layer 125 that overlaps with the third transistor T3 and the overlapping layer 125 that overlaps with the seventh transistor T7. In addition, Figure 1 , Figure 13 and Figure 14 The embodiments of can be applied together to include all of the overlapping layer 125 that overlaps with the third transistor T3, the overlapping layer 125 that overlaps with the fourth transistor T4, and the overlapping layer 125 that overlaps with the seventh transistor T7.

[0211] Although the present invention has been described with respect to exemplary embodiments currently considered to be practicable, it should be understood that the present invention is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0212] Description of Reference Numerals

[0213] 110: Substrate 111: Barrier layer

[0214] 112: Buffer layer 125: Overlapping layer

[0215] 125-1: Voltage application line for overlapping layer

[0216] 126: Storage line

[0217] 155: Gate electrode

[0218] 130: Polycrystalline semiconductor layer

[0219] 131: First polycrystalline semiconductor layer

[0220] 132: Second polycrystalline semiconductor layer

[0221] 133: Third polycrystalline semiconductor layer

[0222] 135: Oxide semiconductor layer

[0223] 141: First gate insulating film 142: Second gate insulating film

[0224] 143: Third gate insulating film 144: Fourth gate insulating film

[0225] 160: Interlayer insulating film 171: Data line

[0226] 172: Drive voltage line 180: Passivation layer

[0227] 71: First data connection member

[0228] 72: Second data connection member

[0229] 73: Third data connection member

[0230] 74: Fourth data connection member

[0231] 75: Connection auxiliary part 151: Scanning line

[0232] 151-1: Main reverse scanning line 152-1: Previous reverse scanning line

[0233] 152-1’: Bypass control line 153: Light emission control line

[0234] 127: Initialization voltage line 741: Common voltage line

[0235] 56: Opening Cst: Storage capacitor

[0236] OLED: Organic light-emitting diode PX: Pixel

[0237] Sn: Scanning signal Sn’: Reverse scanning signal

[0238] Sn-1’: Previous reverse scanning signal

[0239] 61, 61-1, 62, 63, 63-1, 64, 64-1, 65, 65-1, 66, 66-1, 67, 68: Opening

Claims

1. An organic light-emitting diode display, comprising: a substrate; a polycrystalline semiconductor layer disposed on the substrate; a first insulating film covering the polycrystalline semiconductor layer; a first conductor disposed on the first insulating film; a second insulating film covering the first conductor and the first insulating film; a second conductor disposed on the second insulating film; a third insulating film covering the second insulating film and the second conductor; an oxide semiconductor layer disposed on the third insulating film; a fourth insulating film covering the oxide semiconductor layer and the third insulating film; a third conductor disposed on the fourth insulating film; a fifth insulating film covering the third conductor and the fourth insulating film; a fourth conductor disposed on the fifth insulating film; and a passivation layer covering the fourth conductor and the fifth insulating film, wherein the first conductor includes a gate electrode of a driving transistor, and the gate electrode of the driving transistor overlaps with the polycrystalline semiconductor layer to form the driving transistor, wherein the second conductor includes a storage electrode overlapping with the gate electrode of the driving transistor and an overlapping layer overlapping with the oxide semiconductor layer, and wherein a voltage is applied to the overlapping layer.

2. The organic light-emitting diode display according to claim 1, wherein, the storage electrode includes an opening exposing at least a part of the gate electrode of the driving transistor, the fourth conductor further includes a first connection member, and a first end of the first connection member is electrically connected to the gate electrode of the driving transistor through the opening of the storage electrode, and a second end of the first connection member is electrically connected to the oxide semiconductor layer.

3. The organic light-emitting diode display according to claim 2, wherein, the second end of the first connection member is connected to an electrode of a third transistor disposed in the oxide semiconductor layer overlapping with the overlapping layer.

4. The organic light-emitting diode display according to claim 1, wherein, the fourth conductor includes a connection member electrically connecting the oxide semiconductor layer and the polycrystalline semiconductor layer.

5. The organic light-emitting diode display according to claim 1, wherein, the first conductor includes a scan line extending in a first direction, and the scan line and the polycrystalline semiconductor layer overlap with each other to form a second transistor.

6. The organic light-emitting diode display according to claim 5, wherein, the first conductor further includes a light emission control line extending in the first direction, the polycrystalline semiconductor layer includes a first polycrystalline semiconductor layer and a second polycrystalline semiconductor layer extending in a second direction intersecting with the first direction, the light emission control line and the first polycrystalline semiconductor layer overlap with each other to form a fifth transistor, the light emission control line and the second polycrystalline semiconductor layer overlap with each other to form a sixth transistor, and the polycrystalline semiconductor layer further includes a third polycrystalline semiconductor layer connecting the first polycrystalline semiconductor layer and the second polycrystalline semiconductor layer and overlapping with the gate electrode of the driving transistor.

7. The organic light emitting diode display according to claim 5, wherein, the third conductor includes a main reverse scan line extending in the first direction, and the main reverse scan line and the oxide semiconductor layer overlap each other to form a third transistor.

8. The organic light emitting diode display according to claim 7, wherein, the overlapping layer is electrically connected to one electrode of the third transistor.

9. The organic light emitting diode display according to claim 7, wherein, the third conductor further includes a previous reverse scan line extending in the first direction, and a protruding portion of the previous reverse scan line and the oxide semiconductor layer overlap each other to form a fourth transistor.

10. The organic light emitting diode display according to claim 1, wherein, the overlapping layer is applied with the same voltage as the voltage applied to the storage electrode or a positive voltage.

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