Display device

Abstract

A display device includes an active pattern disposed on a substrate; a first transistor including a first gate electrode disposed in a first overlapping region overlapping the active pattern; a first scan line disposed adjacent to the first gate electrode; a first power voltage line including a first electrode portion overlapping the first gate electrode and a second electrode portion extending from the first electrode portion in a direction crossing the first scan line and overlapping the first scan line; a first electrode pattern connected to the first gate electrode and overlapping the second electrode portion; and an organic light emitting layer disposed on the first electrode pattern.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device and a method of manufacturing the same, and more particularly, to a display device for improving display quality and a method of manufacturing the same. BACKGROUND

[0002] Recently, flat panel display devices are widely used as display devices. Among the flat panel display devices, an organic light emitting display device has advantages of being relatively thin and light, low power consumption, and fast response speed, and thus is being spotlighted as a next generation display device.

[0003] The organic light emitting display device can include a plurality of thin film transistors and organic light emitting elements connected to the thin film transistors. The organic light emitting elements can emit light of a luminance corresponding to a voltage supplied to the organic light emitting elements through the thin film transistors. SUMMARY

[0004] An object of the present application is to provide a display device for improving display quality.

[0005] Another object of the present application is to provide a method of manufacturing a display device for improving display quality.

[0006] However, the objects of the present application are not limited to the above-mentioned objects, and various extensions can be made without departing from the spirit and scope of the present application.

[0007] To achieve the above-mentioned object of the present application, a display device according to an embodiment includes an active pattern disposed on a substrate; a first transistor including a first gate electrode disposed in a first overlapping area overlapping the active pattern; a first scan line disposed adjacent to the first gate electrode; a first power voltage line including a first electrode portion overlapping the first gate electrode to form a first storage capacitor with the first gate electrode and a second electrode portion extending from the first electrode portion in a direction crossing the first scan line and overlapping the first scan line; a first electrode pattern connected to the first gate electrode and overlapping the second electrode portion to form a second storage capacitor with the second electrode portion; and an organic light emitting layer disposed on the first electrode pattern. Further, the first electrode portion forms the first storage capacitor with the first gate electrode, and the first electrode pattern forms the second storage capacitor with the second electrode portion.

[0008] In an embodiment, the display device can further include a first insulating layer disposed on the active pattern, a second insulating layer disposed on the first gate electrode, a third insulating layer disposed on the first power voltage line, and a fourth insulating layer disposed on the first electrode pattern, wherein the first gate electrode is disposed on the first insulating layer, the first power voltage line is disposed on the second insulating layer, and the first electrode pattern is disposed on the third insulating layer.

[0009] In an embodiment, the display device can further include a second transistor including a second gate electrode disposed in a second overlap region where the first scan line overlaps the active pattern, and a third transistor including a third gate electrode disposed in a third overlap region where the first scan line overlaps the active pattern, wherein the first electrode pattern is connected to a third drain electrode of the third transistor.

[0010] In an embodiment, the display device can further include a data line crossing the first scan line, and a second power voltage line crossing the first power voltage line and connected to the first power voltage line.

[0011] In an embodiment, the display device can further include a second scan line parallel to the first scan line, a fourth transistor including a fourth gate electrode disposed in a fourth overlap region where the second scan line overlaps the active pattern, and a seventh transistor including a seventh gate electrode disposed in a seventh overlap region where the second scan line overlaps the active pattern.

[0012] In an embodiment, the display device can further include an initialization voltage line parallel to the first scan line, and a second electrode pattern connecting the initialization voltage line and a seventh drain electrode of the seventh transistor.

[0013] In an embodiment, the display device can further include a light emitting line parallel to the first scan line, a fifth transistor including a fifth gate electrode disposed in a fifth overlap region where the light emitting line overlaps the active pattern, and a sixth transistor including a sixth gate electrode disposed in a sixth overlap region where the light emitting line overlaps the active pattern.

[0014] In an embodiment, the display device can further include a third electrode pattern connected to a sixth drain electrode of the sixth transistor.

[0015] To achieve the aforementioned objective of the present invention, a display device according to an embodiment includes: a first transistor; a second transistor including a gate electrode, a source electrode, and a drain electrode respectively connected to a first scan line, a data line intersecting the first scan line, and a source electrode of the first transistor; a power supply voltage line transmitting a first power supply voltage; a first storage capacitor including an electrode connected to the power supply voltage line and an electrode connected to the gate electrode of the first transistor; a second storage capacitor connected to the power supply voltage line and the gate electrode of the first transistor; a third transistor including a gate electrode, a drain electrode, and a source electrode respectively connected to the first scan line, the gate electrode of the first transistor, and the drain electrode of the first transistor; and an organic light-emitting diode, which is subjected to a second power supply voltage and emits light according to the driving of the first transistor. The electrode of the second storage capacitor connected to the gate electrode of the first transistor is formed between the first scan line and another electrode of the second storage capacitor.

[0016] In one embodiment, the display device may further include: a fifth transistor, including a gate electrode, a drain electrode, and a source electrode respectively connected to the light-emitting line, the power supply voltage line, and the source electrode of the first transistor; and a sixth transistor, including a gate electrode, a source electrode, and a drain electrode respectively connected to the light-emitting line, the drain electrode of the first transistor, and the organic light-emitting diode.

[0017] In one embodiment, the display device may further include: a fourth transistor connected to the second scan line, the gate electrode of the first transistor, and an initialization voltage line to which an initialization voltage is applied; and a seventh transistor connected to the second scan line, the initialization voltage line, and the organic light-emitting diode.

[0018] In one embodiment, the first scan line may receive the nth scan signal (n is a positive integer), and the second scan line may receive the (n-1)th scan signal.

[0019] In one embodiment, the display device may further include a capacitor connected between the power supply voltage line and the gate electrode of the second transistor.

[0020] To achieve the aforementioned objective of the present invention, a method for manufacturing a display device according to an embodiment includes the following steps: forming an active pattern on a substrate; forming a first transistor, the first transistor including a first gate electrode disposed in a first overlapping region overlapping the active pattern; forming a first scan line disposed adjacent to the first gate electrode; forming a first power supply voltage line, the first power supply voltage line including a first electrode portion and a second electrode portion, the first electrode portion overlapping the first gate electrode, the second electrode portion extending from the first electrode portion in a direction intersecting the first scan line and overlapping the first scan line; forming a first electrode pattern, the first electrode pattern being connected to the first gate electrode and overlapping the second electrode portion; and forming an organic light-emitting layer on the substrate on which the first electrode pattern is formed.

[0021] In one embodiment, the method may further include the following steps: forming a first insulating layer on the active pattern; forming a second insulating layer on the first gate electrode; forming a third insulating layer on the first power supply voltage line; and forming a fourth insulating layer on the first electrode pattern, wherein the first gate electrode is disposed on the first insulating layer, the first power supply voltage line is disposed on the second insulating layer, and the first electrode pattern is disposed on the third insulating layer.

[0022] In one embodiment, the method may further include the steps of: forming a second transistor, the second transistor including a second gate electrode disposed in a second overlapping region where the first scan line overlaps with the active pattern; and forming a third transistor, the third transistor including a third gate electrode disposed in a third overlapping region where the first scan line overlaps with the active pattern, wherein the first electrode pattern is connected to the third drain electrode of the third transistor.

[0023] In one embodiment, the method may further include the following steps: forming a data line that intersects with the first scan line; and forming a second power supply voltage line that intersects with and is connected to the first power supply voltage line.

[0024] In one embodiment, the method may further include the following steps: forming a second scan line parallel to the first scan line; forming a fourth transistor, the fourth transistor including a fourth gate electrode disposed in a fourth overlapping region where the second scan line overlaps with the active pattern; and forming a seventh transistor, the seventh transistor including a seventh gate electrode disposed in a seventh overlapping region where the second scan line overlaps with the active pattern.

[0025] In one embodiment, the method may further include the following steps: forming a light-emitting line parallel to the first scan line; forming a fifth transistor, the fifth transistor including a fifth gate electrode disposed in a fifth overlapping region where the light-emitting line overlaps with the active pattern; and forming a sixth transistor, the sixth transistor including a sixth gate electrode disposed in a sixth overlapping region where the light-emitting line overlaps with the active pattern.

[0026] In one embodiment, the method may further include the following steps: forming an initialization voltage line parallel to the first scan line; forming a second electrode pattern, the second electrode pattern connecting the initialization voltage line to the seventh drain electrode of the seventh transistor; and forming a third electrode pattern, the third electrode pattern connecting to the sixth drain electrode of the sixth transistor.

[0027] According to the display device and manufacturing method of the present invention, by arranging an electrode of a second conductive pattern, to which a power supply voltage is applied, between a scan line, which is a first conductive pattern, and the drain electrode of a third transistor, which is a third conductive pattern, parasitic capacitance can be blocked and storage capacitance increased. Accordingly, the switching voltage of the third transistor is reduced, thereby preventing display defects such as brightness reduction and low-brightness spots caused by changes in switching voltage.

[0028] However, the effects of the present invention are not limited to those described above, and various extensions can be made without departing from the spirit and scope of the present invention. Attached Figure Description

[0029] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present invention.

[0030] Figure 2 It is used for explanation Figure 1 The pixel circuit diagram of the pixels.

[0031] Figure 3 It is used to explain the basis Figure 1 Waveform diagram of the driving method of pixels in a display device.

[0032] Figure 4 It is used for explanation Figure 1 A magnified plan view of a display device with pixels.

[0033] Figure 5 It is along Figure 4 A cross-sectional view of the display device taken by the I-I' line.

[0034] Figures 6 to 10 This is a cross-sectional view used to illustrate the manufacturing method of the display device of the present invention.

[0035] Figure 11a and Figure 11b This is a diagram used to illustrate the pixel circuit according to the comparative example.

[0036] Figure 12 This is a pixel circuit diagram based on an embodiment used for comparison with a comparative example. Detailed Implementation

[0037] Hereinafter, with reference to the accompanying drawings, an organic light-emitting display device and a method for manufacturing an organic light-emitting display device according to embodiments of the present invention will be described in more detail. The same or similar reference numerals are used for the same constituent elements in the drawings.

[0038] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present invention. Figure 2 It is used for explanation Figure 1 The pixel circuit diagram of the pixels. Figure 3 It is used to explain the basis Figure 1 Waveform diagram of the driving method of pixels in a display device.

[0039] Reference Figure 1 The display device 1000 includes a panel 100, a main driving unit 200, a scanning driving unit 300, and a light-emitting driving unit 400.

[0040] The panel portion 100 includes: a display portion DA; and a surrounding portion PA, including a plurality of surrounding areas surrounding the display portion DA.

[0041] The display unit DA includes multiple scan lines SLn-1, SLn, multiple data lines DLm, multiple light-emitting lines ELn, multiple first power supply voltage lines PVL1, multiple second power supply voltage lines PVL2, multiple initialization voltage lines IVL, and multiple pixels P (n and m are positive integers).

[0042] The plurality of scan lines SLn-1 and SLn can extend along a first direction DD1 and be arranged along a second direction DD2 that intersects the first direction DD1. The plurality of scan lines SLn-1 and SLn are connected to the scan driving unit 300 arranged in the surrounding portion PA. The plurality of scan lines SLn-1 and SLn transmit a plurality of scan signals provided by the scan driving unit 300 to the plurality of pixels P.

[0043] The plurality of data lines DLm can extend along the second direction DD2 and be arranged along the first direction DD1. The plurality of data lines DLm are connected to the main driving unit 200 arranged in the surrounding portion PA. The plurality of data lines DLm transmit a plurality of data signals provided by the main driving unit 200 to the plurality of pixels P.

[0044] The plurality of light-emitting lines ELn can extend along the first direction DD1 and be arranged along the second direction DD2. The plurality of light-emitting lines ELn are connected to the light-emitting driving unit 400 arranged in the surrounding portion PA. The plurality of light-emitting lines ELn transmit a plurality of light-emitting control signals provided by the light-emitting driving unit 400 to the plurality of pixels P.

[0045] The plurality of first power supply voltage lines PVL1 can extend along the first direction DD1 and be arranged along the second direction DD2. The plurality of first power supply voltage lines PVL1 can be connected to the main driving unit 200. The plurality of first power supply voltage lines PVL1 transmit the first light-emitting power supply voltage ELVDD provided by the main driving unit 200 to the plurality of pixels P.

[0046] The plurality of second power supply voltage lines PVL2 can extend along the second direction DD2 and be arranged along the first direction DD1. The plurality of second power supply voltage lines PVL2 are connected to the plurality of first power supply voltage lines PVL1 and transmit the first light-emitting power supply voltage ELVDD provided from the main driving unit 200 to the plurality of pixels P. The plurality of first power supply voltage lines PVL1 and the plurality of second power supply voltage lines PVL2 can be arranged in a mesh pattern.

[0047] The plurality of initialization voltage lines IVL can extend along the first direction DD1 and be arranged along the second direction DD2. The plurality of initialization voltage lines IVL can be connected to the main driving unit 200. The plurality of initialization voltage lines IVL transmit the initialization voltage Vinit provided by the main driving unit 200 to the plurality of pixels P.

[0048] The plurality of pixels P may each include an organic light-emitting diode (OLED) for displaying an image and a plurality of transistors for driving the OLED.

[0049] For example, refer to Figure 2 The pixel P may include a pixel circuit PC.

[0050] The pixel circuit PC may include an organic light-emitting diode (OLED), a first transistor T1, a first storage capacitor CST1, a second storage capacitor CST2, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0051] The organic light-emitting diode (OLED) includes a first diode electrode E1 and a second diode electrode E2. The first diode electrode E1 can be an anode electrode, and the second diode electrode E2 can be a cathode electrode. A second light-emitting voltage ELVSS can be applied to the second diode electrode E2.

[0052] The first transistor T1 includes a first gate electrode G1 connected to the first node N1, a first source electrode S1 connected to the second node N2, and a first drain electrode D1 connected to the third node N3.

[0053] The first storage capacitor CST1 includes a first storage electrode CE1 connected to the first node N1 and a second storage electrode CE2 connected to the power supply voltage line PLL.

[0054] The second storage capacitor CST2 includes a third storage electrode CE3 connected to the first node N1 and a fourth storage electrode CE4 connected to the power supply voltage line PVL. The first storage capacitor CST1 and the second storage capacitor CST2 are connected in parallel to each other, thereby increasing the overall storage capacitance.

[0055] The second transistor T2 includes a second gate electrode G2 connected to the nth scan line SLn, a second source electrode S2 connected to the data line DLm, and a second drain electrode D2 connected to the second node N2.

[0056] The third transistor T3 includes a third gate electrode G3 connected to the nth scan line SLn, a third source electrode S3 connected to the third node N3, and a third drain electrode D3 connected to the first node N1. The third drain electrode D3 of the third transistor T3 is connected to the first storage capacitor CST1 and the second storage capacitor CST2. The switching voltage V of the third transistor T3 is... kickback It can be defined by the following formula.

[0057] Mathematical Formula 1

[0058]

[0059] Here, C para C is the parasitic capacitance of the third transistor T3. ST1 It is the capacitance of the first storage capacitor CST1, C ST2 It is the capacitance of the second storage capacitor CST2, and ΔVg is the difference between the high voltage and low voltage of the signal applied to the gate electrode of the third transistor T3.

[0060] As stated in mathematical formula 1, if the capacitances of the first storage capacitor CST1 and the second storage capacitor CST2 increase, then the switching voltage V of the third transistor T3 will increase. kickback This can be reduced. Accordingly, by reducing the switching voltage V of the third transistor T3... kickback This can reduce the voltage jump V caused by the thermal deviation of the third transistor T3. kickbackThe deviation can be mitigated. This improves the brightness reduction and low-brightness spot caused by the thermalization of the third transistor T3.

[0061] The fourth transistor T4 includes a fourth gate electrode G4 connected to the (n-1)th scan line SLn-1, a fourth source electrode S4 connected to the initialization voltage line IVL, and a fourth drain electrode D4 connected to the first node N1.

[0062] The fifth transistor T5 includes a fifth gate electrode G5 connected to the nth light-emitting line ELn, a fifth source electrode S5 connected to the power supply voltage line PVL, and a fifth drain electrode D5 connected to the second node N2.

[0063] The sixth transistor T6 includes a sixth gate electrode G6 connected to the nth light-emitting line ELn, a sixth source electrode S6 connected to the third node N3, and a sixth drain electrode D6 connected to the first diode electrode E1 of the organic light-emitting diode OLED.

[0064] The seventh transistor T7 includes a seventh gate electrode G7 connected to the (n-1)th scan line SLn-1, a seventh source electrode S7 connected to the first diode electrode E1 of the organic light-emitting diode OLED, and a seventh drain electrode D7 connected to the initialization voltage line IVL.

[0065] The driving method for the pixel circuit PC is as follows.

[0066] Reference Figure 3 During the first time period a of the frame, in response to a low voltage applied to the (n-1)th scan signal SSn-1 as the turn-on voltage for the (n-1)th scan line SLn-1, the fourth transistor T4 and the seventh transistor T7 are turned on, while the remaining transistors T1, T2, T3, T5, and T6 are turned off. Accordingly, the previous data voltage charged in the first storage capacitor CST1 and the second storage capacitor CST2 is initialized to the initialization voltage Vinit applied to the initialization voltage line IVL, and the anode electrode of the first diode electrode E1 of the organic light-emitting diode (OLED) is initialized to the initialization voltage Vinit.

[0067] During the second time period b of the frame, in response to the low voltage applied to the nth scan signal SSn of the nth scan line SLn, the second transistor T2 and the third transistor T3 are turned on, while the remaining transistors T1, T4, T5, T6, and T7 are turned off.

[0068] Accordingly, the third transistor T3 is turned on, and the first transistor T1 is diode connected. The voltage difference between the voltage (i.e., the data voltage) Vdata corresponding to the data signal applied to the data line DLm and the threshold voltage Vth of the first transistor T1, which is applied to the second node N2, is applied to the first node N1. Therefore, the voltage difference between the absolute values ​​of the voltage Vdata corresponding to the data signal and the threshold voltage Vth is applied to the first node N1, thereby compensating for the threshold voltage of the first transistor T1.

[0069] Furthermore, the first storage capacitor CST1 and the second storage capacitor CST2 are charged with a voltage corresponding to the data voltage Vdata.

[0070] As described above, during the second time period b of the frame, the threshold voltage of the first transistor T1 is compensated, and the voltage corresponding to the data voltage Vdata is stored in the first storage capacitor CST1 and the second storage capacitor CST2.

[0071] During the third time period c of the frame, if a low-voltage nth emission control signal EMn is applied to the nth emission line ELn, the fifth transistor T5 and the sixth transistor T6 will be turned on, and the remaining transistors T2, T3, T4, and T7 will be turned off.

[0072] Accordingly, the first transistor T1 is turned on by the voltage corresponding to the data voltage Vdata stored in the first storage capacitor CST1 and the second storage capacitor CST2, and the driving current corresponding to the data voltage Vdata flows through the organic light-emitting diode (OLED). The OLED can then be driven to display an image.

[0073] Figure 4 It is used for explanation Figure 1 A magnified plan view of a display device with pixels.

[0074] Reference Figure 4 The pixel P may include an active pattern ACT, a first gate electrode G1, an nth scan line SLn, a first power supply voltage line PVL1, a first electrode pattern EP1, an (n-1)th scan line SLn-1, an initialization voltage line IVL, a second electrode pattern EP2, an nth light emission line ELn, a third electrode pattern EP3, an mth data line DLm, and a second power supply voltage line PVL2.

[0075] The active pattern ACT can be formed as a single pattern within the pixel region of the substrate that defines the pixel P.

[0076] The first gate electrode G1 may be disposed in the central portion of the pixel P and may have an island shape. A first transistor T1 may be defined in the first overlapping region of the active pattern ACT that overlaps with the first gate electrode G1. The first gate electrode G1 may be the first storage electrode CE1 of the first storage capacitor CST1.

[0077] The nth scan line SLn extends along the first direction DD1. A second transistor T2 can be defined in the second overlapping region of the active pattern ACT that overlaps with the nth scan line SLn. Furthermore, a third transistor T3 can be defined in the third overlapping region of the active pattern ACT that overlaps with the nth scan line SLn.

[0078] The first power supply voltage line PVL1 is arranged adjacent to the nth scan line SLn in the second direction DD2 and extends along the first direction DD1. The first power supply voltage line PVL1 may include a first electrode portion CE2, a second electrode portion CE4, and a third electrode portion LE that are interconnected. Hereinafter, the first electrode portion CE2 is referred to as the second storage electrode CE2, the second electrode portion CE4 is referred to as the fourth storage electrode CE4, and the third electrode portion LE is referred to as the line electrode LE.

[0079] The second storage electrode CE2 is disposed in the central portion of the pixel P, overlapping the first gate electrode G1, and includes a hole H formed by removing the central portion corresponding to the first gate electrode G1. The fourth storage electrode CE4 extends from the second storage electrode CE2 toward the nth scan line SLn, overlapping the nth scan line SLn. The line electrode LE connects the second storage electrodes CE2 disposed in adjacent pixels. The first storage capacitor CST1 can be defined by the first storage electrode CE1, which is the first gate electrode G1, and the second storage electrode CE2 included in the first power supply voltage line PVL1.

[0080] The first electrode pattern EP1 overlaps with the fourth storage electrode CE4 included in the first power supply voltage line PVL1. The first electrode pattern EP1 is connected to the first gate electrode G1 through the hole H of the second storage electrode CE2, and overlaps with the fourth storage electrode CE4 that overlaps with the nth scan line SLn, and is connected to the active pattern ACT that defines the third drain electrode D3 of the third transistor T3. The first electrode pattern EP1 can define the third storage electrode CE3 in the region overlapping with the fourth storage electrode CE4. The second storage capacitor CST2 can be defined by the third storage electrode CE3 included in the first electrode pattern EP1 and the fourth storage electrode CE4 included in the first power supply voltage line PVL1.

[0081] The (n-1)th scan line SLn-1 is arranged in the second direction DD2 relative to the nth scan line SLn and extends along the first direction DD1. A fourth transistor T4 can be defined in the fourth overlapping region of the active pattern ACT that overlaps with the (n-1)th scan line SLn-1. Furthermore, a seventh transistor T7 can be defined in the seventh overlapping region of the active pattern ACT that overlaps with the (n-1)th scan line SLn-1.

[0082] The initialization voltage line IVL is arranged in the second direction DD2 relative to the (n-1)th scan line SLn-1, and extends along the first direction DD1.

[0083] The second electrode pattern EP2 is connected to the active pattern ACT defined by the initialization voltage line IVL and the seventh drain electrode D7 of the seventh transistor T7.

[0084] The nth light-emitting line ELn is arranged in the second direction DD2 relative to the (n-1)th scan line SLn-1 and extends along the first direction DD1. A fifth transistor T5 can be defined in the fifth overlapping region of the active pattern ACT that overlaps with the nth light-emitting line ELn. Furthermore, a sixth transistor T6 can be defined in the sixth overlapping region of the active pattern ACT that overlaps with the nth light-emitting line ELn.

[0085] The third electrode pattern EP3 is connected to the active pattern ACT defined by the sixth drain electrode D6 of the sixth transistor T6.

[0086] The m-th data line DLm extends along the second direction DD2 and is connected to the active pattern ACT defined by the second source electrode S2 of the second transistor T2.

[0087] The second power supply voltage line PVL2 extends along the second direction DD2 and is connected to the first power supply voltage line PVL1. For example, the second power supply voltage line PVL2 may be connected to the second storage electrode CE2 included in the first power supply voltage line PVL1.

[0088] Figure 5 It is along Figure 4 A cross-sectional view of the display device taken by the I-I' line. Figures 6 to 10 This is a cross-sectional view used to illustrate the manufacturing method of the display device of the present invention.

[0089] Reference Figure 5 and Figure 6 The substrate 110 may be an insulating substrate including glass, polymer, stainless steel, etc. In one embodiment, the substrate 110 may include a first plastic layer, a first barrier layer, a second plastic layer, and a second barrier layer stacked sequentially. For example, the first plastic layer and the second plastic layer may include plastics such as polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate (PAR), polycarbonate (PC), polyetherimide (PEI), and polyethersulfone (PS), and the first barrier layer and the second barrier layer may include plastics such as amorphous silicon (a-Si) and silicon oxide (SiO2). x ), silicon nitride (SiN) x Silicon compounds such as )

[0090] A semiconductor layer is formed on the substrate 110, and the semiconductor layer is patterned to form an active pattern ACT. The active pattern ACT can be formed as a single pattern within a pixel region defining pixel P.

[0091] The active pattern ACT can be formed using polycrystalline silicon or oxide semiconductors. The oxide semiconductor can include oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), and / or as composite oxides thereof, such as zinc oxide (ZnO), indium-gallium-zinc oxide (In-Ga-Zn-O), indium-zinc oxide (Zn-In-O), zinc-tin oxide (Zn-Sn-O), indium-gallium oxide (In-Ga-O), indium-tin oxide (In-Sn-O), indium-zirconium oxide (In-Zr-O), indium-zirconium-zinc oxide (In-Zr-Zn-O), indium-zirconium-tin oxide (In-Zr-Sn-O), indium-zirconium-gallium oxide (In-Zr-Ga-O), and indium-aluminum oxide (In-A). It can be any one of the following: l-O), indium-zinc-aluminum oxide (In-Zn-Al-O), indium-tin-aluminum oxide (In-Sn-Al-O), indium-aluminum-gallium oxide (In-Al-Ga-O), indium-tantalum oxide (In-Ta-O), indium-tantalum-zinc oxide (In-Ta-Zn-O), indium-tantalum-tin oxide (In-Ta-Sn-O), indium-tantalum-gallium oxide (In-Ta-Ga-O), indium-germanium oxide (In-Ge-O), indium-germanium-zinc oxide (In-Ge-Zn-O), indium-germanium-tin oxide (In-Ge-Sn-O), indium-germanium-gallium oxide (In-Ge-Ga-O), titanium-indium-zinc oxide (Ti-In-Zn-O), and hafnium-indium-zinc oxide (Hf-In-Zn-O).

[0092] Reference Figure 5 and Figure 7 A first insulating layer 120 is formed on a substrate 110 on which the active pattern ACT is formed. The first insulating layer 120 may cover the active pattern ACT and is disposed on the substrate 110. The first insulating layer 120 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxide nitride, etc.

[0093] A first conductive layer is formed on a substrate 110 on which the first insulating layer 120 is formed, and the first conductive layer is patterned to form a first conductive pattern. The first conductive pattern may include a first gate electrode G1, an (n-1)th scan line SLn-1, an nth scan line SLn, and the nth light-emitting line ELn.

[0094] A transistor channel, source electrode, and drain electrode are formed by doping an impurity into a substrate 110 having the first conductive patterns G1, SLn-1, SLn, and ELn. The channel may be doped with N-type or P-type impurities, and the source electrode and drain electrode are respectively separated by the channel and doped with an impurity of the opposite type to that doped into the channel.

[0095] like Figure 7 As shown, a first channel C1 can be formed in the first overlapping region of the active pattern ACT that overlaps with the region where the first gate electrode G1 is formed. A first source electrode S1 and a first drain electrode D1 can be formed in the region of the active pattern ACT that separates the first channel C1. The first gate electrode G1 can be defined as the first storage electrode CE1 of the first storage capacitor CST1. A first transistor T1 can be formed from the first gate electrode G1, the first source electrode S1, and the first drain electrode D1.

[0096] A second channel C2 can be formed in the second overlapping region of the active pattern ACT that overlaps with the region where the nth scan line SLn is formed. A second source electrode S2 and a second drain electrode D2 can be formed in the region of the active pattern ACT that separates the second channel C2 from the second channel C2. The region of the nth scan line SLn that overlaps with the second channel C2 can be defined as the second gate electrode G2. A second transistor T2 can be formed from the second gate electrode G2, the second source electrode S2, and the second drain electrode D2.

[0097] A third channel C3 can be formed in the third overlapping region of the active pattern ACT that overlaps with the region where the nth scan line SLn is formed. A third source electrode S3 and a third drain electrode D3 can be formed in the region of the active pattern ACT that separates the third channel C3 from the existing channel C3. The region of the nth scan line SLn that overlaps with the third channel C3 can be defined as the third gate electrode G3. A third transistor T3 can be formed from the third gate electrode G3, the third source electrode S3, and the third drain electrode D3.

[0098] A fourth channel C4 can be formed in the fourth overlapping region of the active pattern ACT that overlaps with the region where the (n-1)th scan line SLn-1 is formed. A fourth source electrode S4 and a fourth drain electrode D4 can be formed in the region of the active pattern ACT that separates the fourth channel C4 from the existing channel C4. The region of the (n-1)th scan line SLn-1 that overlaps with the fourth channel C4 can be defined as the fourth gate electrode G4. A fourth transistor T4 can be formed from the fourth gate electrode G4, the fourth source electrode S4, and the fourth drain electrode D4.

[0099] A seventh channel C7 can be formed in the seventh overlapping region of the active pattern ACT that overlaps with the region where the (n-1)th scan line SLn-1 is formed. A seventh source electrode S7 and a seventh drain electrode D7 can be formed in the regions of the active pattern ACT that separate the seventh channel C7. The region of the (n-1)th scan line SLn-1 that overlaps with the seventh channel C7 can be defined as the seventh gate electrode G7. A seventh transistor T7 can be formed from the seventh gate electrode G7, the seventh source electrode S7, and the seventh drain electrode D7.

[0100] A fifth channel C5 can be formed in the fifth overlapping region of the active pattern ACT that overlaps with the region where the nth light-emitting line ELn is formed. A fifth source electrode S5 and a fifth drain electrode D5 can be formed in the region of the active pattern ACT that separates the fifth channel C5 from the nth light-emitting line ELn. The region of the nth light-emitting line ELn that overlaps with the fifth channel C5 can be defined by a fifth gate electrode G5. A fifth transistor T5 can be formed from the fifth gate electrode G5, the fifth source electrode S5, and the fifth drain electrode D5.

[0101] A sixth channel C6 can be formed in the sixth overlapping region of the active pattern ACT that overlaps with the region where the nth light-emitting line ELn is formed. A sixth source electrode S6 and a sixth drain electrode D6 can be formed in the regions of the active pattern ACT that separate the sixth channel C6. The region of the nth light-emitting line ELn that overlaps with the sixth channel C6 can be defined as the sixth gate electrode G6. A sixth transistor T6 can be formed from the sixth gate electrode G6, the sixth source electrode S6, and the sixth drain electrode D6.

[0102] Reference Figure 5 and Figure 8 A second insulating layer 130 is formed on a substrate 110 on which the first conductive patterns G1, SLn-1, SLn, and ELn are formed. The second insulating layer 130 may cover the first conductive patterns G1, SLn-1, SLn, and ELn and is disposed on the first insulating layer 120. The second insulating layer 130 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon oxide nitride, etc.

[0103] A second conductive layer is formed on the second insulating layer 130, and the second conductive layer is patterned to form a second conductive pattern.

[0104] The second conductive pattern may include an initialization voltage line IVL and a first power supply voltage line PVL1.

[0105] The initialization voltage line IVL transmits the initialization voltage Vinit. The initialization voltage line IVL is arranged on the second direction DD2 and extends along the first direction DD1 relative to the (n-1)th scan line SLn-1.

[0106] The first power supply voltage line PVL1 transmits the first light-emitting power supply voltage ELVDD. The first power supply voltage line PVL1 is arranged adjacent to the nth scan line SLn in the second direction DD2 and extends along the first direction DD1. The first power supply voltage line PVL1 includes a second storage electrode CE2, a fourth storage electrode CE4, and a line electrode LE, formed as a single pattern.

[0107] The second storage electrode CE2 overlaps with the first gate electrode G1 and has a hole H formed corresponding to the central portion of the first gate electrode G1. The fourth storage electrode CE4 extends from the second storage electrode CE2 toward the nth scan line SLn and overlaps with the nth scan line SLn. The line electrodes LE connect the second storage electrodes CE2 formed in adjacent pixels to each other. The first storage capacitor CST1 can be formed using the first storage electrode CE1, which serves as the first gate electrode G1, and the second storage electrode CE2.

[0108] Reference Figure 5 and Figure 9 A third insulating layer 140 is formed on the substrate 110 on which the second conductive patterns IVL and PVL1 are formed. The third insulating layer 140 may cover the second conductive patterns IVL and PVL1 and be disposed on the second insulating layer 130. The third insulating layer 140 may be an inorganic insulating layer including silicon nitride, silicon oxide, silicon nitride, etc., or an organic insulating layer including acrylic resin, epoxy resin, polyimide resin, polyester resin, etc.

[0109] A plurality of contact holes CH, a plurality of first through holes VH1 and a plurality of second through holes VH2 are formed on a substrate 110 having the third insulating layer 140 formed by removing at least one insulating layer.

[0110] The plurality of contact holes CH penetrate the first insulating layer 120, the second insulating layer 130 and the third insulating layer 140 to expose the active pattern ACT.

[0111] The plurality of first vias VH1 penetrate the second insulating layer 130 and the third insulating layer 140 to expose the first conductive pattern. For example, the first vias VH1 can penetrate the second insulating layer 130 and the third insulating layer 140 to expose the first gate electrode G1.

[0112] The plurality of second vias VH2 penetrate the third insulating layer 140 to expose the second conductive pattern. For example, the second vias VH2 can expose the first power supply voltage line PVL1 and a portion of the initialization voltage line IVL.

[0113] Reference Figure 5 and Figure 10 A third conductive layer is formed on a substrate 110 having the plurality of contact holes CH, the plurality of first through holes VH1 and the plurality of second through holes VH2, and the third conductive layer is patterned to form a third conductive pattern.

[0114] The third conductive pattern may include the m-th data line DLm, the second power supply voltage line PVL2, the first electrode pattern EP1, the second electrode pattern EP2, and the third electrode pattern EP3.

[0115] The m-th data line DLm extends along the second direction DD2 and is connected to the active pattern ACT that defines the second source electrode S2 of the second transistor T2.

[0116] The second power supply voltage line PVL2 extends along the second direction DD2 and is connected to the first power supply voltage line PVL1. For example, the second power supply voltage line PVL2 can be connected to the second storage electrode CE2 of the first power supply voltage line PVL1.

[0117] The first electrode pattern EP1 overlaps with the fourth storage electrode CE4 included in the first power supply voltage line PVL1. The first electrode pattern EP1 is connected to the first gate electrode G1 through a hole H formed in the second storage electrode CE2, and overlaps with the fourth storage electrode CE4 that overlaps with the nth scan line SLn, and is connected to the active pattern ACT that defines the third drain electrode D3 of the third transistor T3. The first electrode pattern EP1 can define the third storage electrode CE3 in the region that overlaps with the fourth storage electrode CE4. In addition, the fourth storage electrode CE4 included in the first power supply voltage line PVL1 is arranged between the first electrode pattern EP1 that overlaps with the nth scan line SLn and the nth scan line SLn, thereby blocking the parasitic capacitance generated between the third drain electrode D3 of the third transistor T3 formed by the nth scan line SLn and the first electrode pattern EP1.

[0118] The second storage capacitor CST2 can be formed by the third storage electrode CE3 and the fourth storage electrode CE4.

[0119] The second electrode pattern EP2 is connected to the initialization voltage line IVL and the active pattern ACT that defines the seventh drain electrode D7 of the seventh transistor T7.

[0120] The third electrode pattern EP3 is connected to the active pattern ACT that defines the sixth drain electrode D6 of the sixth transistor T6.

[0121] A fourth insulating layer 150 is formed on the substrate 110 on which the third conductive patterns DLm, PVL2, EP1, EP2, and EP3 are formed. The fourth insulating layer 150 may have a flat surface on top of the third conductive patterns DLm, PVL2, EP1, EP2, and EP3. The fourth insulating layer 150 may be an organic insulating layer including acrylic resins, epoxy resins, polyimide resins, polyester resins, etc., or an inorganic insulating layer including silicon nitrides, silicon oxides, silicon nitrides, etc.

[0122] Pixel electrodes E1 may be disposed on the fourth insulating layer 150. Pixel electrodes E1 may be formed for each pixel. Pixel electrodes E1 may be connected to the sixth drain electrode D6 of the sixth transistor T6 through contact holes formed in the fourth insulating layer 150. Pixel electrodes E1 may include metal, transparent conductive oxide, etc.

[0123] A fifth insulating layer 160 may be disposed on the pixel electrode E1. The fifth insulating layer 160 may cover the edge portion of the pixel electrode E1 and be disposed on the fourth insulating layer 150. The fifth insulating layer 160 may include an opening that exposes a portion of the pixel electrode E1. The opening may define the light-emitting area of ​​the pixel. The fifth insulating layer 160 may include an organic insulating material such as acrylic resin, epoxy resin, polyimide resin, or polyester resin.

[0124] An organic light-emitting layer OL can be disposed over the entire area of ​​the substrate 110 where the pixel electrode E1 is arranged. The organic light-emitting layer OL can be provided with a hole injection layer (HIL) and / or a hole transport layer (HTL). The hole transport layer has excellent hole transport properties and suppresses the movement of electrons that are not bound in the organic light-emitting layer OL, thereby increasing the recombination opportunity between holes and electrons.

[0125] A counter electrode layer E2 can be disposed over the entire area of ​​the substrate 110 where the organic light-emitting layer OL is arranged. The counter electrode layer E2 may include metal, transparent conductive oxide, etc. An organic light-emitting diode (OLED) can be formed using the pixel electrode E1, the organic light-emitting layer OL, and the counter electrode layer E2.

[0126] Figure 11a and Figure 11b This is a diagram used to illustrate the pixel circuit according to the comparative example. Figure 12 This is a pixel circuit diagram based on an embodiment used for comparison with a comparative example.

[0127] Reference Figure 11a and Figure 11b The pixel in the comparative example includes a first transistor T1, a first power supply voltage line PVL1, a storage capacitor CST, and a third transistor T3.

[0128] The first transistor T1 may include a first gate electrode G1, which is defined as the first storage electrode CE1 of the storage capacitor CST.

[0129] The first power supply voltage line PVL1 includes: a second storage electrode CE2, which overlaps with the first gate electrode G1, which is the first storage electrode CE1; and a line electrode LE, which connects the second storage electrodes of adjacent pixels to each other.

[0130] The storage capacitor CST can be defined by the first storage electrode CE1, which serves as the first gate electrode G1, and the second storage electrode CE2, which serves as the first power supply voltage line PVL1.

[0131] The third transistor T3 includes a third drain electrode D3, which is formed by a first electrode pattern EP1. The first electrode pattern EP1 is connected to the first gate electrode G1 and overlaps with the nth scan line SLn.

[0132] The nth scan line SLn is formed by a first conductive pattern, and the first electrode pattern EP1, which serves as the third drain electrode D3, is formed by a third conductive pattern.

[0133] Therefore, as Figure 11b As shown, a parasitic capacitance Cpara_1 is formed in the overlapping region of the nth scan line SLn and the third drain electrode D3.

[0134] The parasitic capacitance Cpara_1 can control the switching voltage V of the third transistor T3 generated when the nth scan signal applied to the nth scan line SLn changes from the on-voltage to the off-voltage. kickback_1 Increase.

[0135] According to the comparative example, the switching voltage V of the third transistor T3 kickback_1 It can be defined as shown in the following mathematical formula 2.

[0136] Mathematical formula 2

[0137]

[0138] As described in mathematical formula 2, the parasitic capacitance Cpara_1 can cause the switching voltage V of the third transistor T3 to change. kickback_1 Increase. The jump voltage V caused by the heating of the third transistor T3. kickback_1 The deviation may increase. The switching voltage deviation of the third transistor T3 may lead to a decrease in brightness and low-brightness spots.

[0139] Additionally, refer to Figure 4 , Figure 5 and Figure 12 According to this embodiment, the pixel includes a first transistor T1, a first storage capacitor CST1, a first power supply voltage line PVL1, a third transistor T3, and a second storage capacitor CST2.

[0140] The first transistor T1 may include a first gate electrode G1, which is defined as the first storage electrode CE1 of the first storage capacitor CST1.

[0141] The first power supply voltage line PVL1 may include a second storage electrode CE2, a fourth storage electrode CE4, and a line electrode LE, all integrally formed. The second storage electrode CE2 is arranged in the central portion of the pixel, overlapping with the first gate electrode G1. The fourth storage electrode CE4 extends from the second storage electrode CE2 toward the nth scan line SLn, thereby overlapping with the nth scan line SLn. The line electrode LE connects the second storage electrodes CE2 of adjacent pixels to each other.

[0142] The first storage capacitor CST1 can be defined in the region where the first gate electrode G1 and the second storage electrode CE2 overlap.

[0143] The third transistor T3 includes a third drain electrode D3, which is formed by a first electrode pattern EP1. The first electrode pattern EP1 is connected to the first gate electrode G1 and overlaps with the fourth memory electrode CE4, which overlaps with the nth scan line SLn. The third memory electrode CE3 can be defined in the region where the first electrode pattern EP1 overlaps with the fourth memory electrode CE4.

[0144] The second storage capacitor CST2 can be defined in the overlapping area of ​​the first electrode pattern EP1 and the fourth storage electrode CE4.

[0145] Additionally, a parasitic capacitance Cpara* can be formed in the region where the nth scan line SLn overlaps with the fourth storage electrode CE4, which is part of the first power supply voltage line PVL1.

[0146] According to an embodiment, the fourth storage electrode CE4, extending from the second storage electrode CE2 which is a second conductive pattern, overlaps with the nth scan line SLn formed by the first conductive pattern and the third drain electrode D3 formed by the third conductive pattern. Accordingly, the parasitic capacitance Cpara_1 of the comparative example can be changed to a second storage capacitor CST2 connected in parallel with the first storage capacitor CST1 of the embodiment and a parasitic capacitance Cpara* connected to the nth scan line SLn and the first power supply voltage line PVL1.

[0147] Therefore, the switching voltage V of the third transistor T3 according to the embodiment kickback The capacitance can decrease due to the increase in the capacitance of the first storage capacitor CST1 and the second storage capacitor CST2.

[0148] Furthermore, according to an embodiment, the parasitic capacitance Cpara* is removed from the first gate electrode G1 of the first transistor T1, thereby improving the driving reliability of the first transistor T1 and the third transistor T3.

[0149] Furthermore, according to the embodiment, the fourth storage electrode CE4 of the first power supply voltage line PVL1 on which the second conductive pattern is formed shields the nth scan line SLn formed by the first conductive pattern and the third drain electrode D3 formed by the third conductive pattern, thereby preventing the generation of parasitic capacitance.

[0150] According to this embodiment, by arranging an electrode of a second conductive pattern, for which a power supply voltage is applied, between a scan line serving as a first conductive pattern and the drain electrode of a third transistor serving as a third conductive pattern, parasitic capacitance can be blocked and storage capacitance increased. Accordingly, the switching voltage of the third transistor is reduced, thereby preventing display defects such as brightness reduction and low-brightness spots caused by voltage fluctuations.

[0151] Industrial availability

[0152] The organic light-emitting display device according to an exemplary embodiment of the present invention can be applied to display devices including computers, laptops, mobile phones, smartphones, smart tablets, personal multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, etc.

[0153] Although the organic light-emitting display device and the method of manufacturing the organic light-emitting display device according to exemplary embodiments of the present invention have been described above with reference to the accompanying drawings, the above embodiments are exemplary, and modifications and alterations can be made by those skilled in the art without departing from the technical concept of the present invention as set forth in the claims.

Claims

1. A display device comprising: an active pattern arranged over a substrate; a first transistor including a first gate electrode arranged in a first overlapping region overlapping with the active pattern; a first scan line arranged adjacent to the first gate electrode; a first power supply voltage line including a first electrode portion overlapping with the first gate electrode and a second electrode portion extending from the first electrode portion in a direction crossing the first scan line and overlapping with the first scan line; a first electrode pattern connected to the first gate electrode and overlapping with the second electrode portion; a third transistor including a third gate electrode arranged in a third overlapping region overlapping with the first scan line and the active pattern; and an organic light emitting layer arranged over the first electrode pattern, wherein the first electrode pattern is connected to a third drain electrode of the third transistor. Further comprising:

2. The display device according to claim 1, wherein a first insulating layer arranged over the active pattern; a second insulating layer arranged over the first gate electrode; a third insulating layer arranged over the first power supply voltage line; a fourth insulating layer arranged over the first electrode pattern, wherein the first gate electrode is arranged over the first insulating layer, the first power supply voltage line is arranged over the second insulating layer, and the first electrode pattern is arranged over the third insulating layer. Further comprising:

3. The display device according to claim 1, wherein a second transistor including a second gate electrode arranged in a second overlapping region overlapping with the first scan line and the active pattern. Further comprising:

4. The display device according to claim 1, wherein a data line crossing the first scan line; and a second power supply voltage line crossing the first power supply voltage line and connected to the first power supply voltage line. Further comprising: a second scan line parallel to the first scan line; 5. The display device according to claim 1, wherein a fourth transistor including a fourth gate electrode arranged in a fourth overlapping region overlapping with the second scan line and the active pattern; and a seventh transistor including a seventh gate electrode arranged in a seventh overlapping region overlapping with the second scan line and the active pattern. Further comprising: an initialization voltage line parallel to the first scan line; and a second electrode pattern connecting the initialization voltage line and a seventh drain electrode of the seventh transistor.

6. The display device according to claim 5, wherein Further comprising: an emission line parallel to the first scan line; a fifth transistor including a fifth gate electrode arranged in a fifth overlapping region overlapping with the emission line and the active pattern; and a sixth transistor including a sixth gate electrode arranged in a sixth overlapping region overlapping with the emission line and the active pattern.

7. The display device according to claim 1, wherein Further comprising: a third electrode pattern connected to a sixth drain electrode of the sixth transistor.

9. The display device according to claim 1, wherein the first electrode portion and the first gate electrode form a first storage capacitor, the first electrode pattern and the second electrode portion form a second storage capacitor.

8. The display device according to claim 7, wherein 10. A display device comprising: a first transistor; a second transistor including a gate electrode, a source electrode, and a drain electrode connected to a first scan line, a data line crossing the first scan line, and a source electrode of the first transistor, respectively; a power supply voltage line transmitting a first power supply voltage; ​ ​ ​ ​ ​ a first storage capacitor including an electrode connected to the power supply voltage line and an electrode connected to the gate electrode of the first transistor; a second storage capacitor including an electrode connected to the power supply voltage line and an electrode connected to the gate electrode of the first transistor; a third transistor including a gate electrode, a drain electrode, and a source electrode connected to the first scan line, the gate electrode of the first transistor, and the drain electrode of the first transistor, respectively; and an organic light emitting diode to which a second power supply voltage is applied and which emits light according to driving of the first transistor.

11. The display device according to claim 10, wherein Further comprising: a fifth transistor including a gate electrode, a drain electrode, and a source electrode connected to a light emitting line, the power supply voltage line, and the source electrode of the first transistor, respectively; a sixth transistor including a gate electrode, a source electrode, and a drain electrode connected to the light emitting line, the drain electrode of the first transistor, and the organic light emitting diode, respectively.

12. The display device according to claim 10, wherein The electrode of the second storage capacitor connected to the gate electrode of the first transistor is formed between the first scan line and the other electrode of the second storage capacitor.

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