Propagation Delay Test Circuit for Digital Isolators

Abstract

The present invention provides a propagation delay test circuit for a digital isolator, comprising a digital isolator and a test machine for testing the propagation delay of the digital isolator, wherein the test circuit further comprises: a pulse generating circuit connected to the digital isolator, for converting the input signal and the output signal of the digital isolator into a pulse signal, wherein the delay of the output signal relative to the input signal is equal to the pulse width of the pulse signal; and a filter connected between the pulse generating circuit and the test machine, for converting the pulse signal into a DC voltage signal, and sending the signal to the test machine. The pulse generating circuit can convert the input signal and the output signal of the digital isolator into a pulse signal, and the filter can convert the pulse signal into a DC voltage signal. The test machine can directly measure the DC voltage signal without detecting the input signal and the output signal of the digital isolator, thereby greatly reducing the requirements for the test machine and reducing the test cost.

Description

Technical Field

[0001] The invention relates to the field of digital isolators, in particular to a propagation delay test circuit of a digital isolator. Background Art

[0002] A digital isolator is a chip that transmits digital signals between two electrically isolated voltage domains, and its transmission rate can often reach 100MHZ or above. For ATE testers, the circuit design requirements for 100MHZ-level signal testing are relatively high, so the price of ATE testers at 100MHZ or above is also quite expensive, which increases the testing cost.

[0003] Therefore, in the prior art, a low-cost test machine and an oscilloscope can be used to perform propagation delay testing of digital isolators. However, this method requires multiple communications between the test machine and the oscilloscope, which will result in a long test time, which also increases the test cost from another perspective.

[0004] Therefore, a low-cost and efficient propagation delay test circuit for digital isolators must be designed. Summary of the invention

[0005] In order to solve one of the above problems, the present invention provides a propagation delay test circuit of a digital isolator, comprising a digital isolator and a test machine for testing the propagation delay of the digital isolator, the test circuit also comprising:

[0006] A pulse generating circuit connected to the digital isolator, for converting the input signal and the output signal of the digital isolator into a pulse signal, wherein the delay of the output signal relative to the input signal is equal to the pulse width of the pulse signal;

[0007] The filter is connected between the pulse generating circuit and the tester to convert the pulse signal into a DC voltage signal and send it to the tester.

[0008] As a further improvement of the present invention, the pulse signal includes a first pulse signal, and the rising delay of the output signal relative to the input signal is equal to the pulse width of the first pulse signal; the DC voltage signal includes a first DC voltage signal, and the first pulse signal is converted into a first DC voltage signal.

[0009] As a further improvement of the present invention, the pulse generating circuit includes first to fifth inverters and a first AND gate; the first inverter and the third inverter are connected in series and connected to the first input terminal of the first AND gate, the second inverter, the fourth inverter and the fifth inverter are connected in series and connected to the second input terminal of the first AND gate, the input signal is connected to the input terminal of the first inverter, and the output signal is connected to the input terminal of the second inverter; the output terminal of the first AND gate outputs a first pulse signal.

[0010] As a further improvement of the present invention, the filter includes a first resistor and a first capacitor, the first pulse signal is connected to one end of the first resistor, and the other end of the first resistor outputs a first DC voltage signal; one end of the first capacitor is grounded and the other end is connected to the other end of the first resistor.

[0011] As a further improvement of the present invention, the rising delay Tplh of the output signal relative to the input signal is:

[0012]

[0013] Wherein, VR is the first DC voltage signal, VDD is the voltage of the delay test circuit, and Tper is the period of the input signal.

[0014] As a further improvement of the present invention, the pulse signal includes a second pulse signal, and the falling delay of the output signal relative to the input signal is equal to the pulse width of the second pulse signal; the DC voltage signal includes a second DC voltage signal, and the second pulse signal is converted into a second DC voltage signal.

[0015] As a further improvement of the present invention, the pulse generating circuit includes first, second and fourth inverters and a second AND gate; the second inverter and the fourth inverter are connected in series and connected to the second input terminal of the second AND gate, the first inverter is connected to the first input terminal of the second AND gate, the input signal is connected to the input terminal of the first inverter, and the output signal is connected to the input terminal of the second inverter; the output terminal of the second AND gate outputs a second pulse signal.

[0016] As a further improvement of the present invention, the filter includes a second resistor and a second capacitor, the second pulse signal is connected to one end of the second resistor, and the other end of the second resistor outputs a second DC voltage signal; one end of the second capacitor is grounded and the other end is connected to the other end of the second resistor.

[0017] As a further improvement of the present invention, the falling edge delay Tphl of the input signal and the output signal is:

[0018]

[0019] Wherein, VF is the second DC voltage signal, VDD is the voltage of the delay test circuit, and Tper is the period of the input signal.

[0020] Compared with the prior art, in the present invention, the pulse generating circuit can convert the input signal and output signal of the digital isolator into a pulse signal, and the filter can convert the pulse signal into a DC voltage signal. The test machine can directly measure the DC voltage signal without detecting the input signal and output signal of the digital isolator, thereby greatly reducing the requirements for the test machine and reducing the test cost. In addition, since the pulse width of the pulse signal is equal to the delay of the input signal and the output signal, the DC voltage signal also has a certain linear relationship with the delay of the input signal and the output signal, which is more convenient for the test machine to measure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural schematic diagram of a propagation delay test circuit of a digital isolator of the present invention;

[0022] Figure 2 The figure is a schematic diagram of the circuit structure of the pulse generating circuit and the filter of the present invention;

[0023] Figure 3 is a timing diagram of the first pulse signal of the present invention;

[0024] Figure 4 It is a timing diagram of the second pulse signal of the present invention. Specific embodiments

[0025] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] like Figures 1 to 4 The figure shows a propagation delay test circuit of a digital isolator 1, comprising a digital isolator 1 and a tester 4 for testing the propagation delay of the digital isolator 1, and the test circuit further comprises:

[0027] A pulse generating circuit 2, connected to the digital isolator 1, for converting the input signal DATA_IN and the output signal DATA_OUT of the digital isolator 1 into a pulse signal, wherein the delay of the output signal DATA_OUT relative to the input signal DATA_IN is equal to the pulse width of the pulse signal;

[0028] The filter 3 is connected between the pulse generating circuit 2 and the tester 4 to convert the pulse signal into a DC voltage signal and send it to the tester 4 .

[0029] Therefore, if Figure 1 As shown, the pulse generating circuit 2 can convert the input signal DATA_IN and the output signal DATA_OUT of the digital isolator 1 into pulse signals, and the filter 3 can convert the pulse signals into DC voltage signals. The test machine 4 can directly measure the DC voltage signal without detecting the input signal DATA_IN and the output signal DATA_OUT of the digital isolator 1, thereby greatly reducing the requirements for the test machine 4 and reducing the test cost. In addition, since the pulse width of the pulse signal is equal to the delay of the input signal DATA_IN and the output signal DATA_OUT, the DC voltage signal also has a certain linear relationship with the delay of the input signal DATA_IN and the output signal DATA_OUT, which is more convenient for the test machine 4 to measure.

[0030] The pulse signal includes a first pulse signal DR, and the rising delay Tplh of the output signal DATA_OUT relative to the input signal DATA_IN is equal to the pulse width of the first pulse signal DR; the DC voltage signal includes a first DC voltage signal VR, and the first pulse signal DR is converted into the first DC voltage signal VR.

[0031] The digital isolator 1 generates an input signal DATA_IN and an output signal DATA_OUT, and the output signal DATA_OUT has a rise delay Tplh relative to the input signal DATA_IN. In the present invention, the first pulse signal DR corresponds to the rise delay Tplh, and the pulse width of the first pulse signal DR is equal to the rise delay Tplh. The first pulse signal DR is also converted into a first DC voltage signal VR through a filter 3 for the test machine 4 to detect the rise delay Tplh.

[0032] Specifically, an embodiment of the present invention provides a circuit structure for converting a rising delay Tplh into a first pulse signal DR. Specifically, the pulse generating circuit 2 includes first to fifth inverters INV1 to INV5 and a first AND gate AND1; the first inverter INV1 and the third inverter INV3 are connected in series and connected to the first input terminal D1 of the first AND gate AND1, the second inverter INV2, the fourth inverter INV4 and the fifth inverter INV5 are connected in series and connected to the second input terminal D2 of the first AND gate AND1, the input signal DATA_IN is connected to the input terminal of the first inverter INV1, and the output signal DATA_OUT is connected to the input terminal of the second inverter INV2; the output terminal of the first AND gate AND1 outputs the first pulse signal DR.

[0033] like Figure 2 and 3 As shown, the input signal DATA_IN passes through two stages of inverters, so the signal at the first input terminal D1 of the first AND gate AND1 is in phase with the input signal DATA_IN, and the output signal DATA_OUT passes through three stages of inverters, so the signal at the second input terminal D2 of the first AND gate AND1 is in phase with the output signal DATA_OUT. Therefore, after the logic operation of the first AND gate AND1, the first pulse signal DR at the output terminal of the first AND gate AND1 is the rising delay Tplh of the output signal DATA_OUT relative to the input signal DATA_IN.

[0034] The filter 3 includes a first resistor R1 and a first capacitor C1, the first pulse signal DR is connected to one end of the first resistor R1, and the other end of the first resistor R1 outputs a first DC voltage signal VR; one end of the first capacitor C1 is grounded, and the other end is connected to the other end of the first resistor R1. The first resistor R1 and the first capacitor C1 form a low-pass filter 3, so that the first pulse signal DR can be converted into a first DC voltage signal VR, and the first DC voltage signal VR is directly related to the rising delay Tplh.

[0035] The rising delay Tplh of the output signal DATA_OUT relative to the input signal DATA_IN is:

[0036]

[0037] Wherein, VR is the first DC voltage signal VR, VDD is the voltage of the delay test circuit, and Tper is the period of the input signal DATA_IN.

[0038] Then, if VDD = 5V, Tper = 100ns, and VR is measured to be 0.45V, the rise delay Tplh is:

[0039]

[0040] On the other hand, the pulse signal includes a second pulse signal DF, and the falling delay Tphl of the output signal DATA_OUT relative to the input signal DATA_IN is equal to the pulse width of the second pulse signal DF; the DC voltage signal includes a second DC voltage signal VF, and the second pulse signal DF is converted into a second DC voltage signal VF.

[0041] The digital isolator 1 generates an output signal DATA_OUT through an input signal DATA_IN, and the output signal DATA_OUT has a falling delay Tphl relative to the input signal DATA_IN. In the present invention, the second pulse signal DF corresponds to the falling delay Tphl, and the pulse width of the second pulse signal DF is equal to the falling delay Tphl. The second pulse signal DF is also converted into a second DC voltage signal VF through a filter 3 for the test machine 4 to detect the falling delay Tphl.

[0042] Similarly, an embodiment of the present invention provides a circuit structure for converting the falling delay Tphl into a second pulse signal DF. Specifically, the pulse generating circuit 2 includes a first, second and fourth inverter INV1, INV2 and INV4 and a second AND gate AND2; the second inverter INV2 and the fourth inverter INV4 are connected in series and connected to the second input terminal D4 of the second AND gate AND2, and the first inverter INV1 is connected to the first input terminal D3 of the second AND gate AND2. Similarly, the input signal DATA_IN is connected to the input terminal of the first inverter INV1, the output signal DATA_OUT is connected to the input terminal of the second inverter INV2, and the output terminal of the second AND gate AND2 outputs the second pulse signal DF.

[0043] like Figure 2 and 4 As shown, the input signal DATA_IN passes through one stage of inverter, so the signal at the first input terminal D3 of the second AND gate AND2 is in phase with the input signal DATA_IN, and the output signal DATA_OUT passes through two stages of inverters, so the signal at the second input terminal D4 of the second AND gate AND2 is in phase with the output signal DATA_OUT. Therefore, after the logic operation of the second AND gate AND2, the second pulse signal DF at the output terminal of the second AND gate AND2 is the falling delay Tphl of the output signal DATA_OUT relative to the input signal DATA_IN.

[0044] The filter 3 includes a second resistor R2 and a second capacitor C2, the second pulse signal DF is connected to one end of the second resistor R2, and the second end of the second resistor R2 outputs a second DC voltage signal VF; one end of the second capacitor C2 is grounded, and the other end is connected to the other end of the second resistor R2. The second resistor R2 and the second capacitor C2 form a low-pass filter 3, so that the second pulse signal DF can be converted into a second DC voltage signal VF, and the second DC voltage signal VF is directly related to the falling delay Tphl.

[0045] The falling delay Tphl of the output signal DATA_OUT relative to the input signal DATA_IN is:

[0046]

[0047] Wherein, VF is the second DC voltage signal VF, VDD is the voltage of the delay test circuit, and Tper is the period of the input signal DATA_IN.

[0048] Then, similarly, if VDD = 5V, Tper = 100ns, and VF is measured to be 0.55V, the falling delay Tphl is:

[0049]

[0050] Of course, as described above, the pulse generating circuit 2 processes the input signal DATA_IN and the output signal DATA_OUT through a multi-stage inverter. For example, the signal at the second input terminal D2 of the first AND gate AND1 is formed by the output signal DATA_OUT after passing through three stages of inverters in series. However, it is obvious that the three-stage inverter has the same function as the one-stage inverter, the five-stage inverter, and the 2n+1 (n≥0)-stage inverter, and thus, it can also be formed by inverters of other stages. Similarly, the two-stage inverter has the same function as the four-stage inverter and the 2n+2 (n≥0)-stage inverter, and can also be formed by inverters of other stages, which is also within the scope of the present invention.

[0051] Alternatively, the inverter and the AND gate may also be implemented by using other logic circuit combinations. As long as the functions of the inverter and the AND gate can be achieved, they are within the protection scope of the present invention.

[0052] In addition, in the present invention, the low-pass filter 3 is implemented by a single-stage RC circuit. Of course, it can also be implemented by a multi-stage RC circuit connected in series, which is also within the scope of the present invention.

[0053] In the present invention, the digital signal generated by the crystal oscillator OSC generates an input signal DATA_IN and is given to the digital isolator 1, and the digital isolator 1 generates an output signal DATA_OUT. After the input signal DATA_IN and the output signal DATA_OUT pass through the delay test circuit of the present invention, a first DC voltage signal VR linearly related to the rising delay Tplh and a second DC voltage signal VF linearly related to the falling delay Tphl are generated, and can be converted into the rising delay Tplh and the falling delay Tphl by the tester 4. Therefore, the delay test circuit can be used for the delay measurement of the multi-channel digital isolator 1, and the measurement is more convenient and fast.

[0054] However, the minimum delay that can be measured by the delay test circuit is limited by the rise time and fall time of the internal node of the delay test circuit, and the maximum delay of the delay test circuit is half of the clock period of the crystal oscillator OSC. For example, if the rise time and fall time of the internal node of a delay test circuit are 1ns respectively, and the clock period of the crystal oscillator OSC is 100ns, then the delay range that can be measured by the delay test circuit is 2ns to 50ns. The propagation delay of a conventional digital isolator 1 is 3ns to 15ns, so the delay test circuit can meet the measurement requirements of the high-speed digital isolator 1.

[0055] In summary, in the propagation delay test circuit of the digital isolator 1 of the present invention, the input signal DATA_IN and the output signal DATA_OUT of the digital isolator 1 can be converted into a DC voltage signal through the pulse generating circuit 2 and the filter 3 for measurement by the tester 4, and the delay is calculated by the DC voltage signal and the calculation formula of the delay. The whole process only needs to measure the DC voltage signal, and there is no need to detect the input signal DATA_IN and the output signal DATA_OUT again, so the requirements for the tester 4 are greatly reduced, reducing the test cost.

[0056] Moreover, in the specific pulse generating circuit 2, the input signal DATA_IN and the output signal DATA_OUT are respectively logically operated through the coordinated connection of multiple stages of inverters connected in series and AND gates, thereby generating a first pulse signal DR equal to the rising delay Tplh and a second pulse signal DF equal to the falling delay Tphl. The input signal DATA_IN and the output signal DATA_OUT are processed by the logic circuit and the corresponding logic operation to form the first pulse signal DR and the second pulse signal DF, which has a better effect and uses less devices.

[0057] In addition, the first pulse signal DR and the second pulse are converted into a first DC voltage signal VR and a second DC voltage signal VF through a filter 3. The filter 3 is a low-pass filter 3, which is certainly not limited to the one-stage RC circuit in the specific implementation of the present invention, and can also be implemented through a multi-stage RC circuit.

[0058] Finally, the first DC voltage signal VR and the second DC voltage signal VF are linearly related to the rising delay Tplh and the falling delay Tphl, respectively, so that the ATE tester 4 used in the present invention can obtain the rising delay Tplh and the falling delay Tphl by measuring the first DC voltage signal VR and the second DC voltage signal VF, respectively.

[0059] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0060] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. All equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A propagation delay test circuit for a digital isolator, comprising a digital isolator and a test machine for testing the propagation delay of the digital isolator, characterized in that: The test circuit further comprises: A pulse generating circuit connected to the digital isolator, for converting the input signal and the output signal of the digital isolator into a pulse signal, wherein the delay of the output signal relative to the input signal is equal to the pulse width of the pulse signal; A filter is connected between the pulse generating circuit and the tester to convert the pulse signal into a DC voltage signal and send it to the tester; The pulse signal includes a first pulse signal and a second pulse signal, and the pulse generating circuit includes first to fifth inverters, a first AND gate and a second AND gate; the first inverter and the third inverter are connected in series and connected to the first input end of the first AND gate, the second inverter, the fourth inverter and the fifth inverter are connected in series and connected to the second input end of the first AND gate, the input signal is connected to the input end of the first inverter, and the output signal is connected to the input end of the second inverter; the output end of the first AND gate outputs the first pulse signal; The second inverter and the fourth inverter are connected in series and connected to the second input terminal of the second AND gate, the first inverter is connected to the first input terminal of the second AND gate, the input signal is connected to the input terminal of the first inverter, and the output signal is connected to the input terminal of the second inverter; the output terminal of the second AND gate outputs a second pulse signal.

2. The delay test circuit according to claim 1, characterized in that: The rising delay of the output signal relative to the input signal is equal to the pulse width of the first pulse signal; the DC voltage signal includes a first DC voltage signal, and the first pulse signal is converted into the first DC voltage signal.

3. The delay test circuit according to claim 1, characterized in that: The filter includes a first resistor and a first capacitor, the first pulse signal is connected to one end of the first resistor, and the other end of the first resistor outputs a first DC voltage signal; one end of the first capacitor is grounded, and the other end is connected to the other end of the first resistor.

4. The delay test circuit according to claim 2, characterized in that: The rising delay Tplh of the output signal relative to the input signal is: Wherein, VR is the first DC voltage signal, VDD is the voltage of the delay test circuit, and Tper is the period of the input signal.

5. The delay test circuit according to claim 1, characterized in that: The falling delay of the output signal relative to the input signal is equal to the pulse width of the second pulse signal; the DC voltage signal includes the second DC voltage signal, and the second pulse signal is converted into the second DC voltage signal.

6. The delay test circuit according to claim 5, characterized in that: The filter includes a second resistor and a second capacitor, the second pulse signal is connected to one end of the second resistor, and the other end of the second resistor outputs a second DC voltage signal; one end of the second capacitor is grounded and the other end is connected to the other end of the second resistor.

7. The delay test circuit according to claim 5, characterized in that: The falling edge delay Tphl of the input signal and the output signal is: Wherein, VF is the second DC voltage signal, VDD is the voltage of the delay test circuit, and Tper is the period of the input signal.

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