PWM Clipping Detector Circuit, Corresponding Electronic System and Method

Abstract

Embodiments of the present disclosure relate to a PWM clipping detector circuit, a corresponding electronic system, and a method. The clipping detector circuit includes a timer circuit and a counter circuit. The timer circuit is configured to: monitor the time period elapsed since the last edge occurred in the PWM signal; assert a first signal when the time period has elapsed; and de-assert the first signal and reset the time period due to an edge occurring in the PWM signal. The counter circuit is configured to: determine the number of pulses in the PWM signal since the last de-assertion of the first signal; and assert a second signal when the number of pulses in the PWM signal since the last de-assertion of the first signal reaches m pulses. The clipping detector circuit is configured to: generate a clipping detection signal indicating whether the pulse width modulation signal is clipped based on the first signal and the second signal.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Italian Patent Application No. 102019000002953, filed on February 28, 2019, which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to an electronic system and method, and in particular embodiments, to a pulse width modulation (PWM) clipping detector circuit, corresponding electronic system, and method. Background Art

[0004] Clipping is a form of waveform distortion that limits a signal once it exceeds a certain threshold. For example, clipping may occur when an amplifier is overdriven and attempts to deliver an output voltage or current that exceeds its maximum capacity, i.e., when the amplifier saturates.

[0005] In the case of a PWM signal, clipping (also referred to as "saturation" in this specification) may cause the duty cycle to approach or equal 0% or 100%.

[0006] Especially in the case of an audio system including a switched PWM modulator, the behavior of the audio system may be affected due to saturation or near-saturation of the PWM signal (i.e., when clipping occurs).

[0007] Therefore, it may be important to detect the clipping phenomenon of a PWM signal. In terms of detecting clipping, a method may be provided to identify the saturation of the PWM signal, thereby triggering feedback devices and / or correction techniques to limit the distortion effect on the output signal of the (audio) system.

[0008] Known solutions for detecting clipping of a PWM signal are based on counting "missing" pulses in the PWM signal generated by a PWM modulator circuit, as Figure 1 and Figure 2 shown.

[0009] Figure 1 is a circuit diagram of an example PWM modulator circuit 10 and a clipping detection circuit 12 coupled thereto. The PWM modulator circuit 10 is configured to generate a PWM signal PWM out , and the clipping detection circuit 12 is configured to detect clipping (i.e., saturation) of the signal PWM out .

[0010] The PWM modulator circuit 10 includes:

[0011] - A signal integrator, which includes an operational amplifier 100 and a capacitor 102. The capacitor 102 is coupled between the output node of the operational amplifier 100 and the first input node of the operational amplifier 100. The operational amplifier 100 is configured to receive an input square wave (current) signal Isq at the first input node and thereby generate an output periodic carrier signal V tri , such as a triangular or sawtooth periodic carrier signal, and

[0012] - A comparator circuit 104, which receives the periodic carrier signal V tri at the first input node and receives a modulation signal V mod at the second input node, thereby generating an output pulse width modulation signal PWM out with a duty cycle that is a function of the amplitude of the modulation signal V mod .

[0013] As long as the modulation signal V mod is included between the upper threshold V tri and the lower threshold V tri,H of the periodic carrier signal V tri,L , the signal PWM out will not saturate (or clip) and includes pulses (i.e., a pair of edges, a rising edge and a falling edge) at each period of the periodic carrier signal V tri .

[0014] Conversely, since the modulation signal V mod is not included between the upper threshold V tri,H and the lower threshold V tri,L (i.e., V mod is higher than V tri,H or lower than V tri,L ), the output node of the comparator circuit 104 does not commute and the signal PWM out saturates, i.e., the signal PWM out does not include edges and remains at a low logic level (as Figure 2 shown, when V mod > V tri,H ) or a high logic level.

[0015] Therefore, by using the clipping detection circuit 12 to sense the signal PWM out and detect the "missing" pulses therein (i.e., detect the absence of pulses in the signal PWM tri within at least one period of the periodic carrier signal V out ), the saturation (clipping) of the signal PWM out can be detected.

[0016] In such as Figure 1In the known solution shown, the clipping detection circuit 12 includes an up-counter 120 (e.g., implemented by one or more flip-flops), which is configured to receive the signal PWM out and the clock signal ClkPkTri.

[0017] The clock signal ClkPkTri is a clock signal synchronized with the periodic carrier signal V tri For example, the clock signal ClkPkTri can be synchronized with the peaks and valleys of the periodic carrier signal V tri as shown. For example, when the periodic carrier signal V Figure 2 reaches the upper threshold V tri , the clock signal ClkPkTri has a falling edge; and when the periodic carrier signal V tri,H reaches the lower threshold V tri , the clock signal ClkPkTri has a rising edge. tri,L

[0018] The signal PWM is received at the (asynchronous) reset input R of the up-counter 120 out , such that the up-counter 120 increments the internal count number (e.g., increments by one unit) at each period of the clock signal ClkPkTri (e.g., at each rising or falling edge of the clock signal ClkPkTri), where each time a pulse appears in the PWM out signal, the internal count number is (asynchronously) reset to zero.

[0019] Therefore, the clipping detection circuit 12 counts the number of consecutive missing pulses in the received signal PWM out , where the missing pulse is the pulse expected at each period of the clock signal ClkPkTri if the signal PWM out is not saturated.

[0020] When the count of consecutive missing pulses reaches a certain value n (e.g., n = 3), the output signal ClipDet of the clipping detection circuit 12 is asserted (e.g., set high, see Figure 2 the moment t1 in), thus indicating the saturation of the signal PWM out .

[0021] In the known solution shown as Figure 1 , the clipping detection circuit 12 further includes an internal logic reset circuit (not visible in the attached drawings herein), which is configured to: after the saturation condition is asserted (e.g., see Figure 2 the moment t2 in), the signal PWM outWhen the pulse in [[]] first appears (i.e., when the internal count number is reset to zero), the output signal ClipDet is de-asserted (e.g., set low). SUMMARY OF THE INVENTION

[0022] Despite extensive activities in this field, there is still a need for further improved solutions.

[0023] Some embodiments relate to circuits and methods for detecting clipping of a signal.

[0024] One or more embodiments can be applied to detecting clipping of a pulse width modulation (PWM) signal. For example, one or more embodiments can be applied to detecting clipping of a PWM signal in an audio system.

[0025] Some embodiments improve the robustness of clipping detection circuits and methods for PWM signals against possible spurious commutation due to noise.

[0026] Some embodiments reduce the instability of the output signal in a clipping detection circuit for a PWM signal, especially when the PWM signal is at a relatively high frequency (e.g., higher than 1 MHz).

[0027] The inventors have observed that Figure 1 the known solutions illustrated in [[]] are not suitable for use with PWM signals at relatively high frequencies (e.g., frequencies higher than 1 MHz) because they may be unstable.

[0028] In particular, the inventors have observed that at higher frequencies, the up-counter 120 in the clipping detection circuit 12 increases the internal count number at a faster rate. Thus, at low frequencies, when the signal PWMout is not clipped, clipping detection may also occur unexpectedly quickly unless n is selected to be high. Considering low-frequency signals such as 1 kHz or lower, the time interval for clipping detection is long, during which the PWM amplifier loses and acquires pulses (corresponding to the unstable region of a class-D amplifier) due to the inherent limitations of the minimum / maximum duty cycle implemented by the switching stage. This phenomenon deteriorates as the frequency of the clock signal ClockPkTri increases, e.g., from 300 kHz to 2 MHz, resulting in the output signal ClipDet being turned on / off multiple times.

[0029] Similarly, the known solutions may have noise in the modulation signal V mod especially when the duty cycle of the signal PWM out is close to 0% or 100%, i.e., when the modulation signal V mod is close to the upper threshold V of the periodic carrier signal V tri of thetri,H and a lower threshold V tri,L When one of them is reached. In these cases, the signal PWM out may be very unstable and have fewer regular pulses, so the output signal ClipDet may also be affected by the instability, including, for example, false commutation. In the case of a relatively high switching frequency (such as 2 MHz), this problem is even more important.

[0030] Some embodiments relate to a circuit for detecting signal clipping.

[0031] Some embodiments relate to corresponding electronic systems.

[0032] Some embodiments relate to corresponding methods.

[0033] As described above, various embodiments of the present disclosure relate to a clipping detector circuit.

[0034] In various embodiments, the clipping detector circuit is configured to detect clipping of a pulse width modulation signal and includes:

[0035] - A timer circuit configured to monitor the edges of the pulse width modulation signal and:

[0036] - Monitor the time period elapsed since the last edge occurred in the pulse width modulation signal,

[0037] - Assert a first signal when this time period has elapsed, and

[0038] - Due to the occurrence of an edge in the pulse width modulation signal, de-assert the first signal and reset the time period; and

[0039] - A counter circuit configured to:

[0040] - Monitor the pulse width modulation signal and the first signal,

[0041] - Determine the number of pulses in the pulse width modulation signal since the last de-assertion of the first signal, and

[0042] - Assert a second signal when the number of pulses in the pulse width modulation signal since the last de-assertion of the first signal reaches a certain number m of pulses.

[0043] In various embodiments, the clipping detector circuit is configured to generate a clipping detection signal at the output based on the first signal and the second signal, the clipping detection signal indicating whether the pulse width modulation signal is clipped.

[0044] In various embodiments, the timer circuit in the clipping detector circuit is implemented with an additional counter circuit that is configured to: receive a clock signal and assert a first signal due to a certain number n of clock signal cycles having elapsed since the last occurrence of an edge in the pulse width modulation signal.

[0045] In various embodiments, the clock signal has the same period as the pulse width modulation signal.

[0046] In various embodiments, the additional counter circuit in the clipping detector circuit is configured to:

[0047] - receive the pulse width modulation signal at a corresponding reset input and receive the clock signal at a corresponding clock input,

[0048] - increment a corresponding internal count number at each cycle of the clock signal and reset the corresponding internal count number to zero each time an edge appears in the pulse width modulation signal, and

[0049] - assert the first signal due to the corresponding internal count number reaching a certain number n.

[0050] In various embodiments, the counter circuit in the clipping detector circuit is configured to:

[0051] - receive the first signal at a corresponding reset input and receive the pulse width modulation signal at a corresponding clock input,

[0052] - increment a corresponding internal count number each time a pulse appears in the pulse width modulation signal and reset the corresponding internal count number to zero each time the first signal is asserted, and

[0053] - assert a second signal as a result of the corresponding internal count number reaching a certain number m.

[0054] In various embodiments, the clipping detector circuit includes an OR logic gate that is configured to generate an output clipping detection signal by OR-ing the first signal and a complementary copy of the second signal.

[0055] Various embodiments relate to an electronic system that includes:

[0056] - a switched PWM modulator circuit that is configured to generate a pulse width modulation signal by comparing a modulation signal with a periodic carrier signal,

[0057] - a clipping detector circuit according to one or more embodiments that is coupled to the switched PWM modulator circuit and is configured to generate a clipping detection signal at an output indicating whether the pulse width modulation signal is clipped, and

[0058] - A control unit configured to receive a clipping detection signal from a clipping detector circuit and act on a switched PWM modulator circuit since the clipping detection signal indicates that a pulse width modulation signal is clipped to counter the clipping of the pulse width modulation signal.

[0059] Each embodiment relates to a method of detecting clipping of a pulse width modulation signal by using a circuit according to one or more embodiments or an electronic system according to one or more embodiments, the method comprising:

[0060] - Monitoring an edge of the pulse width modulation signal,

[0061] - Monitoring a time period elapsed since the last occurrence of an edge in the pulse width modulation signal,

[0062] - Asserting a first signal when the time period has elapsed,

[0063] - De-asserting the first signal and resetting the time period due to the occurrence of an edge in the pulse width modulation signal,

[0064] - Determining a number of pulses in the pulse width modulation signal since the last de-assertion of the first signal,

[0065] - Asserting a second signal when the number of pulses in the pulse width modulation signal since the last de-assertion of the first signal reaches a certain number of pulses; and

[0066] - Generating a clipping detection signal indicating whether the pulse width modulation signal is clipped based on the first signal and the second signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0068] Figure 1 and Figure 2 has been described previously.

[0069] Figure 3 is a flowchart of one or more embodiments.

[0070] Figure 4 is an exemplary circuit diagram of one or more embodiments.

[0071] Figures 5 to 8 is an example of a possible temporal behavior of signals in one or more embodiments; and

[0072] Figure 9 is an example of a possible environment in which one or more embodiments are used. DETAILED DESCRIPTION

[0073] In the following description, one or more specific details are set forth in order to provide an in-depth understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more specific details, or by using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been described in detail so as not to obscure certain aspects of the embodiments.

[0074] References to "an embodiment" or "one embodiment" in the context of this specification are intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to one and the same embodiment. Moreover, in one or more embodiments, the particular configurations, structures, or characteristics may be combined in any suitable manner.

[0075] Throughout the accompanying drawings, like parts or elements are denoted by like reference numerals / numbers, and the corresponding descriptions will not be repeated for the sake of brevity.

[0076] The reference numerals used herein are provided solely for convenience and thus do not delimit the scope of protection or the scope of embodiments.

[0077] Figure 3 is an exemplary flowchart of the steps of a method for detecting clipping of a PWM signal according to one or more embodiments.

[0078] The method includes:

[0079] - Monitoring a pulse width modulation signal PWM out to determine the time period elapsed since the last occurrence of an edge in the pulse width modulation signal PWM out and

[0080] - Asserting a first signal ClipDet when the time period reaches a certain threshold

[0081] - De-asserting the first signal ClipDet and resetting the time period due to the occurrence of an edge in the pulse width modulation signal PWM out and

[0082] - Determining the number of pulses in the pulse width modulation signal PWM out since the last de-assertion of the first signal ClipDet

[0083] - Asserting a second signal ClipOut when the number of pulses in the pulse width modulation signal PWM out since the last de-assertion of the first signal ClipDet reaches a certain number m of pulses, and

[0084] - Generate a pulse width modulation signal PWM based on a first signal ClipDet and a second signal ClipOut out A clipping detection signal ClipDet’ indicating whether [the signal] is clipped.

[0085] In particular, the method may include:

[0086] - Receive the pulse width modulation signal PWM out , for example, which is generated by comparing a modulation signal V mod with a periodic carrier signal V tri (such as a triangular or sawtooth periodic signal) in a switch PWM modulator circuit 10,

[0087] - Receive a clock signal ClkPkTri having the same period as the pulse width modulation signal PWM out , for example, which is synchronized with the periodic carrier signal V tri (for example, having a falling edge and a rising edge corresponding to the peak and valley values of the periodic carrier signal V tri ), and

[0088] - Thereby generate an output clipping detection signal ClipDet’ indicating whether the signal PWM out is clipped.

[0089] It will be understood that receiving the signals PWM out and ClkPkTri and generating the signal ClipDet' are actions that can be continuously performed according to the method, where the value of the output signal ClipDet' can vary at any time point according to the signal PWM out .

[0090] In particular, after starting from step 300, the method may include: at step 302, setting the clipping detection signal ClipDet’ to a first (default) value, where the first value (for example, ClipDet’ = 0, de-asserted) indicates that the signal PWM out is not clipped and the switch PWM modulator operates in a so-called "linear region".

[0091] After setting the clipping detection signal ClipDet’ to the first (default) value, the method may include: periodically checking, for example, at each period of the clock signal ClkPkTri (for example, at each of its rising or falling edges), whether the signal PWM out has at least one voltage transition (for example, a rising edge or a falling edge, also referred to as a voltage commutation in this disclosure) within a certain time period T MAX , as shown in block 304 of Figure 3 . For example, the time period TMAX may correspond to a number n (e.g., n = 3) of past (most recent) cycles of the clock signal ClkPkTri before the checking operation 304.

[0092] If the signal PWM out has at least one voltage transition during a time period T before the checking operation 304 MAX (e.g., during the past n cycles of the clock signal ClkPkTri), corresponding to an affirmative result Y of block 304, the value of the clipping detection signal ClipDet’ may not change (i.e., may leave a first value indicating that the signal PWM out is not clipped), and, for example, in the next cycle of the clock signal ClkPkTri, the checking operation 304 may be repeated on the signal PWM out .

[0093] Thus, if the signal PWM out has at least one voltage transition in each time period T MAX (e.g., every n clock cycles), it may be detected as not clipped (saturated), and the method may cycle through steps 302 and 304, periodically performing the checking operation 304 (e.g., at each clock cycle), and as long as the result of the checking operation 304 is affirmative, i.e., as long as the signal PWM out is not clipped, the value of the clipping detection signal ClipDet' remains unchanged.

[0094] If the checking operation 304 detects that the signal PWM out does not have at least one voltage transition during the time period T before the checking operation 304 MAX (e.g., during n cycles in the most recent past cycles of the clock signal ClkPkTri), corresponding to a negative result N of block 304, the value of the clipping detection signal ClipDet’ may be changed in the action illustrated by block 306 (e.g., may be switched to a second value indicating that the signal PWM out is clipped and the switch PWM modulator is operating in a so-called “clipping region”).

[0095] After setting the clipping detection signal ClipDet' to the second value, the method may include again periodically checking, e.g., at each cycle of the clock signal ClkPkTri, whether the signal PWM out has at least one voltage transition during a specific time period T MAX (e.g., again during a number n of cycles in the most recent past cycles of the clock signal ClkPkTri), as shown in Figure 3 block 308.

[0096] If signal PWM out has no at least one voltage transition within time period T MAX (e.g., within the past n cycles of clock signal ClkPkTri), corresponding to the negative result N of block 308, the value of the clipping detection signal ClipDet’ may remain unchanged (i.e., the remaining second value indicates that signal PWM out is clipped), and, for example, in the next cycle of clock signal ClkPkTri, the verification operation 308 may be repeated for signal PWM out .

[0097] Thus, if signal PWM out is clipped (saturated) even when no voltage transition occurs within time period T MAX (e.g., the past n cycles of clock signal ClkPkTri), the method may cyclically go through steps 306 and 308, periodically perform the verification operation 308 (e.g., in each clock cycle), and as long as the result of the verification operation 308 is negative, i.e., as long as signal PWM out is clipped, the value of the clipping detection signal ClipDet’ remains unchanged.

[0098] If the verification operation 308 detects that signal PWM out has had at least one voltage transition within time period T MAX (e.g., the past n cycles of clock signal ClkPkTri), corresponding to the positive result Y of block 308, the verification operation 310 may be further performed.

[0099] The further verification operation 310 includes: since the last occurrence of the negative result of the verification operation 308, i.e., since the last time signal PWM out was clipped (saturated), verifying whether signal PWM out has at least a certain number m of pulses.

[0100] If signal PWM out has no a certain number m of pulses since the last occurrence of the negative result of the verification operation 308 (negative result N of block 310), the value of the clipping detection signal ClipDet’ may remain unchanged (i.e., the second value may be retained, and this second value indicates that signal PWMout is clipped), and, for example, in the next cycle of clock signal ClkPkTri, the verification operation 308 may be repeated for signal PWMout.

[0101] Thus, even if signal PWM out may have (temporarily) exited the saturation / clipping condition (as indicated by the positive result of the verification operation 308), (only) since outDetected in the time period T MAX After the last voltage transition within, the signal PWM out Includes at least a certain number m of pulses, so the clipped detection signal ClipDet’ can be de-asserted.

[0102] If the verification operation 310 detects that the signal PWM out Has had a certain number m of pulses since the last negative result of the verification operation 308 (positive result Y of box 310), the value of the clipped detection signal ClipDet’ can be changed (e.g., it can be switched to a first value indicating that the signal PWM out Is not clipped), and the method can resume operation from step 302.

[0103] Therefore, relative to known solutions, it is advantageous that, for example Figure 3 The illustrated embodiment method improves the stability of the clipped detection signal ClipDet’, especially when the signal PWM out Exits the clipped condition, and / or in the case where the duty cycle of the signal PWM out Is close to 0% or 100% (i.e., when the signal PWM out Is almost saturated and spurious commutations of the clipped detection signal ClipDet' may occur).

[0104] Figure 4 Is suitable for implementing one or more embodiments of the method exemplified in the reference Figure 3 Exemplary circuit diagrams of the embodiments.

[0105] In Figure 4 The reference numeral 12 indicates a clipped detection circuit 12, which is configured to cooperate with the switch PWM modulator circuit 10.

[0106] As described above, the switch PWM modulator circuit 10 is configured to generate a pulse width modulation signal PWM mod By comparing the modulation signal V tri With a periodic carrier signal V out (e.g., a triangular or sawtooth signal).

[0107] The clipped detection circuit 12 includes a first timer circuit 120, which is configured to monitor whether the signal PWM out Has at least one voltage transition over a specific time period T MAX Or not.

[0108] For example, the timer circuit 120 can be configured to sense (monitor) the edges (rising and / or falling) of the signal PWM out And since the last occurrence of the signal PWM outAfter a certain time period T after the edge of MAX , the corresponding output signal ClipDet is asserted (e.g., set high), thereby indicating the saturation of the signal PWM out .

[0109] In addition, the timer circuit 120 is configured to invalidate the corresponding output signal ClipDet, and reset the internal timer due to the occurrence of an edge in the signal PWM out .

[0110] Preferably, the timer circuit 120 can be implemented by a first up-counter 120 configured to receive the signal PWM out and the clock signal ClkPkTri.

[0111] Thus, in the currently considered embodiment, the signal PWM is received at the reset input R of the up-counter 120 out , such that the up-counter 120 periodically increments the internal count number (e.g., in each period of the clock signal ClkPkTri), and resets the internal count number to zero each time a pulse appears in the signal PWM out .

[0112] Due to the count of consecutive missing pulses in the signal PWM out reaching a certain value n (e.g., n = 6), the output signal ClipDet of the up-counter 120 is asserted (e.g., set high), thereby indicating the saturation of the signal PWM out .

[0113] In a preferred embodiment, the clock signal ClkPkTri is synchronized with the periodic carrier signal V tri .

[0114] In addition, a second up-counter 122 is provided in the clipping detection circuit 12. The second up-counter 122 is configured to:

[0115] - Monitor the output signal ClipDet from the timer circuit 120 and the signal PWM out ,

[0116] - Determine the number of pulses that have occurred in the signal PWM since the last de-assertion of the output signal ClipDet from the timer circuit 120 out , and

[0117] - When the number of pulses in the signal PWM since the last de-assertion of the output signal ClipDet reaches a certain number m of pulses, assert the corresponding output signal ClipOut. out

[0118] In particular, the second up-counter 122 can be configured to receive, at a respective (asynchronous) reset input, an output signal ClipDet from the timer circuit 120, and to receive the signal PWM out as a clock signal.

[0119] Thus, the second up-counter 122 increments a respective internal count number (e.g., increments by one unit) at each pulse that occurs in the signal PWM out and, at each assertion of the signal ClipDet, i.e., when it is detected that the signal PWM out enters the clipping region, resets the respective internal count number (asynchronously) to zero.

[0120] Accordingly, since the last de-assertion of the signal ClipDet, the second up-counter 122 counts the number of pulses in the received signal PWM out .

[0121] Since, since the last de-assertion of the signal ClipDet, the count of the pulses in the received signal PWM out reaches a certain value m (e.g., m = 3), the output signal ClipOut of the second up-counter 122 is asserted (e.g., set high).

[0122] Additionally, the output signal ClipDet’ of the clipping detection circuit 12 can be generated at the output of an OR logic gate 124 that receives the signal ClipDet and a complementary copy of the signal ClipOut, as Figure 4 shown.

[0123] In one or more embodiments, the modulation signal V mod can cause the switched PWM modulator circuit 10 to operate in the linear region (i.e., where V tri,L < V mod < V tri,H ), resulting in the generation of a pulse of the signal PWM out on each period of a clock signal ClkPkTri that is synchronous with the periodic carrier signal Vtri, or to operate in the saturation (clipping) region, resulting in a duty cycle of the signal PWM out that is close to 0% or 100%, and few pulses in the signal PWM out .

[0124] Since the switching PWM modulator circuit 10 operates in the linear region, the first timer circuit 120 can be reset at each period of the clock signal ClkPkTri, thereby keeping the signal ClipDet de-asserted (i.e., ClipDet = 0). Additionally, the second up-counter 122 is not reset and provides an asserted signal ClipOut (i.e., ClipOut = 1). As a result, the output clip detection signal ClipDet’ is de-asserted, i.e., remains at the low logic level indicating that the signal PWM out is not clipped.

[0125] Since the modulation signal V mod decreases below V tri,L or increases above V tri,H , causing the switching PWM modulator circuit 10 to start operating in the clip region, no pulses are generated in the signal PWM out .

[0126] If no pulses are generated in the signal PWM MAX during a certain time period T out , e.g., during a certain number n of consecutive periods of the clock signal ClkPkTri, the signal ClipDet is toggled to the high logic value, thereby also causing the clip detection signal ClipDet’ to be toggled to the high logic value, and the internal counter of the second up-counter 122 is reset to zero. The switching PWM modulator circuit 10 is detected to be operating in the clip region.

[0127] As long as no pulses are detected in the signal PWM out , the state of the clip detection circuit 12 remains unchanged, i.e., ClipDet = 1, ClipOut = 0 and ClipDet’ = 1.

[0128] Since a pulse is detected in the signal PWM out , the counter of the first timer circuit 120 is reset to zero, causing the signal ClipDet to be toggled low. In the case of ClipDet = 0, the counter of the second up-counter 122 is not reset and starts counting the pulses in the signal PWM out .

[0129] The state of the circuit remains unchanged, where ClipDet = 0, ClipOut = 0 and ClipDet' = 1, until the counter of the second up-counter 122 reaches a certain value m. In this case (assuming ClipDet remains at the low logic value), the signal ClipOut is toggled to the high logic value, causing the output clip detection signal ClipDet' to be toggled to the low logic value. Thus, the switching PWM modulator circuit 10 is detected to be operating in the linear region again.

[0130] It should be noted that the signal ClipDet from the first timer circuit 120 is directly coupled to the OR logic gate 124, causing the output clip detection signal ClipDet' to switch high in any case, regardless of the value of the signal ClipOut, because n consecutive missing pulses are detected in the signal PWM out .

[0131] Figures 5 to 8 is an illustration of the possible temporal behavior of the signal in one or more embodiments according to different operating states.

[0132] For example, Figure 5 is an illustration of the case where n = 6 and m = 3. The switched PWM modulator circuit 10 initially operates in the linear region, where the first timer circuit 120 is reset at each period of the clock signal ClkPkTri and causes ClipDet = 0. The second up-counter 122 is not reset and provides ClipOut = 1. As a result, ClipDet' = 0. Since the switched PWM modulator circuit 10 enters the clip region, no pulses are generated in the signal PWM out . After n = 6 missing pulses in the signal PWMout, the signal ClipDet switches to the high logic value, thereby also causing the clip detection signal ClipDet' to switch to the high logic value, and the counter of the second up-counter 122 is reset to zero, resulting in ClipOut = 0.

[0133] Figure 6 is an example of a case where the switched PWM modulator circuit 10 initially operates in the linear region, where ClipDet = 0, ClipOut = 1 and ClipDet' = 0, and then transitions to the clip region, where ClipDet = 1, ClipOut = 0 and ClipDet' = 1 (i.e., Figure 6 the initial part of the signal shown may correspond to Figure 5 the last part of the signal shown).

[0134] Since a pulse P1 is detected in the signal PWM out , the counter of the first timer circuit 120 is reset to zero, resulting in the signal ClipDet switching low. In the case of ClipDet = 0, the counter of the second up-counter 122 is not reset, but starts counting the pulses in the signal PWM out when ClipOut = 0. As shown in Figure 6 , the signal ClipOut is not switched high until the second up-counter 122 reaches the value m (e.g., m = 3) (not visible in Figure 6 ).

[0135] As Figure 7 shown (again, the initial portion of the signal shown Figure 7 can correspond to the last portion of the signal shown Figure 6 ), after a pair of pulses P1 and P2, the signal PWM out can be free of other pulses for a period of time. In this case, if n clock cycles (e.g., n = 6) have elapsed after pulse P2 and there are no additional pulses in the signal PWM out , the signal ClipDet switches back to high. The signal ClipOut remains low, and the signal ClipDet' remains high, so the pulses P1 and P2 are identified as spurious pulses and do not cause the signal ClipDet' to switch to low.

[0136] Figure 8 (Again, the initial portion of the signal illustrated Figure 8 can correspond to the final portion of the signal illustrated Figure 7 ) is an example of a situation where the switch PWM modulator circuit 10 initially operates in the clipping region. Since a pulse P3 is detected in the signal PWM out , the counter of the timer circuit 120 is reset to zero, causing the signal ClipDet to switch to low. In the case where ClipDet = 0, the counter of the second up-counter 122 is not reset but starts counting the pulses P3, P4, P5,... in the signal PWM out when ClipOut = 0. Once the second up-counter 122 reaches the value m (e.g., m = 3), the signal ClipOut is switched to high, determining that the signal ClipDet' switches to low, indicating that the switch PWM modulator circuit 10 has exited the clipping region.

[0137] Thus, one or more embodiments can be applicable to PWM-based systems where the detection of a saturated PWM signal can trigger a feedback system and / or correction and / or diagnostic circuitry. For example, Figure 9 the audio amplifier shown

[0138] Figure 9 is a circuit diagram of a PWM amplifier 90 that illustrates a possible environment for the use of the clipping detection circuit 12 according to one or more embodiments.

[0139] The PWM amplifier 90 (e.g., a class D amplifier) is configured to receive an input analog signal V in . The input analog signal Vin is propagated to an integrator circuit 900, resulting in a modulation signal V mod. As described above, in the comparator circuit 104, the modulation signal V mod is compared with a triangular or sawtooth signal V tri to generate a PWM signal that oscillates between the values +V sig and -V sig . This PWM signal is used to drive a PWM amplifier stage 902, such as a half-bridge arrangement, to generate an output PWM signal that oscillates between the values +V pot and -V pot . Thus, the output PWM signal propagates through the LC filter 904 to provide an output signal K·V in , which is an amplified copy of the input analog signal V in . A feedback network 906 with a gain factor of 1 / K is also provided between the output of the PWM amplifier stage 902 and the input of the integrator circuit 900.

[0140] As Figure 9 shown, the clip detection circuit 12 receives the signal PWM out generated at the output of the comparator circuit 104 and a clock signal ClkPkTri that may be synchronized with the signal V tri to generate a clip detection signal ClipDet’. For example, the clip detection signal ClipDet’ may be received at a processing and / or control unit 92 (e.g., a microprocessor), which may use ClipDet’ as an interrupt signal and / or a control signal to trigger a feedback and / or correction device to limit the distortion effect on the output signal K·Vin of the PWM amplifier 90.

[0141] One or more embodiments may advantageously be used with a high-frequency (e.g., above 1 MHz, such as 2 MHz) switched PWM modulator.

[0142] One or more embodiments may facilitate the generation of an output clip detection signal ClipDet’ that is stable and free of spurious commutations or glitches due to the high frequencies involved, and is robust to oscillations and / or noise in the modulation signal V mod .

[0143] One or more embodiments may facilitate monitoring the pulses in the signal PWM out in real time and independently of the clock signal.

[0144] One or more embodiments may be tunable and / or adjustable, for example, by tuning and / or adjusting the thresholds n and m of the first and second up-counters 120, 122, so as to adapt the behavior of the clip detection circuit 12 to different applications and / or requirements.

[0145] Without prejudice to the basic principles, details and embodiments may vary even significantly from what is described only by way of example, without departing from the scope of protection.

[0146] The scope of protection is defined by the appended claims.

Claims

1. A clipping detector circuit, comprising: An output terminal; A timer circuit configured to: Monitor an edge of a pulse width modulation signal, Monitor a time period elapsed since the last occurrence of an edge in the pulse width modulation signal, Assert a first signal when the time period has elapsed, and De-assert the first signal and reset the time period due to an edge occurring in the pulse width modulation signal; And A counter circuit configured to: Monitor the pulse width modulation signal and the first signal, Determine the number of pulses in the pulse width modulation signal since the last de-assertion of the first signal, and Assert a second signal when the number of pulses in the pulse width modulation signal since the last de-assertion of the first signal reaches m pulses, where m is a positive integer greater than 1, wherein the clipping detector circuit is configured to generate a clipping detection signal at the output terminal based on the first signal and the second signal, the clipping detection signal indicating whether the pulse width modulation signal is clipped, wherein the clipping detection signal is a digital signal, and wherein the clipping detector circuit is configured to de-assert the clipping detection signal after m pulses of the pulse width modulation signal after the first signal is de-asserted.

2. The clipping detector circuit according to claim 1, wherein m is less than or equal to 3.

3. The clipping detector circuit according to claim 1, wherein the timer circuit includes an additional counter circuit configured to: receive a clock signal and assert the first signal due to n cycles of the clock signal elapsing since the last occurrence of an edge in the pulse width modulation signal, where n is a positive integer greater than 1.

4. The clipping detector circuit according to claim 3, wherein n is less than or equal to 6.

5. The clipping detector circuit according to claim 4, wherein m equals 3 and n equals 6.

6. The clipping detector circuit according to claim 3, wherein the clock signal has the same period as the pulse width modulation signal.

7. The clipping detector circuit according to claim 3, wherein the additional counter circuit is configured to: Receive the pulse width modulation signal at a corresponding reset input and receive the clock signal at a corresponding clock input; Increment a corresponding internal count number at each cycle of the clock signal and reset the corresponding internal count number to zero each time an edge occurs in the pulse width modulation signal; And Assert the first signal due to the corresponding internal count number reaching count n.

8. The clipping detector circuit according to claim 1, wherein the counter circuit is configured to: Receive the first signal at a corresponding reset input and receive the pulse width modulation signal at a corresponding clock input; Each time a pulse appears in the pulse width modulation signal, increment a corresponding internal count number, and reset the corresponding internal count number to zero each time the first signal is asserted; and Assert the second signal when the corresponding internal count number reaches count m.

9. The clipping detector circuit according to claim 1, further comprising an OR logic gate configured to generate the clipping detection signal by performing an OR process on a complementary copy of the second signal and the first signal.

10. An electronic system, comprising: A switched pulse width modulator circuit configured to: generate a pulse width modulation signal by comparing a modulation signal with a periodic carrier signal; A clipping detector circuit configured to produce a clipping detection signal indicating whether the pulse width modulation signal is clipped, wherein the clipping detection signal is a digital signal; And A control unit configured to: receive the clipping detection signal from the clipping detector circuit and, when the clipping detection signal indicates that the pulse width modulation signal is clipped, act on the switched pulse width modulator circuit to count the clipping of the pulse width modulation signal, wherein the clipping detector circuit comprises: A timer circuit configured to: Monitor the edges of the pulse width modulation signal, Monitor the time period elapsed since the last edge appeared in the pulse width modulation signal, Assert a first signal when the time period has elapsed, and De-assert the first signal and reset the time period due to an edge appearing in the pulse width modulation signal; And A counter circuit configured to: Monitor the pulse width modulation signal and the first signal, Determine the number of pulses in the pulse width modulation signal since the last de-assertion of the first signal, and Assert a second signal when the number of pulses in the pulse width modulation signal since the last de-assertion of the first signal reaches m pulses, where m is a positive integer greater than 1, wherein the clipping detector circuit is configured to generate the clipping detection signal based on the first signal and the second signal, and wherein the clipping detector circuit is configured to de-assert the clipping detection signal after m pulses of the pulse width modulation signal after the first signal is de-asserted.

11. The electronic system according to claim 10, wherein the electronic system is a class D amplifier.

12. The electronic system according to claim 10, further comprising an integrator circuit, an output of the integrator circuit being configured to generate the modulation signal based on an input signal.

13. The electronic system according to claim 12, wherein the input signal is an analog audio signal.

14. The electronic system according to claim 12, further comprising: A pulse width modulation output stage configured to receive the pulse width modulation signal; An LC filter, an input of the LC filter being coupled to an output of the pulse width modulation output stage, and the LC filter being configured to generate an amplifier signal based on the input signal; and a feedback network, an input of the feedback network being coupled to the output of the pulse width modulation output stage, and an output of the feedback network being coupled to the integrator circuit.

15. The electronic system according to claim 10, wherein the timer circuit includes an additional counter circuit configured to: receive a clock signal synchronized with the periodic carrier signal; and assert the first signal due to n periods of the clock signal having elapsed since the last occurrence of an edge in the pulse width modulation signal, where n is a positive integer greater than 1.

16. The electronic system according to claim 15, wherein the additional counter circuit includes an output terminal coupled to a reset terminal of the timer circuit.

17. A method for detecting clipping of a pulse width modulation signal, comprising: monitoring edges of the pulse width modulation signal; monitoring a time period elapsed since the last occurrence of an edge in the pulse width modulation signal; asserting a first signal when the time period has elapsed; de-asserting the first signal and resetting the time period due to an edge occurring in the pulse width modulation signal; determining a number of pulses in the pulse width modulation signal since the last de-assertion of the first signal; asserting a second signal when the number of pulses in the pulse width modulation signal since the last de-assertion of the first signal reaches m pulses, where m is a positive integer greater than 1; and generating a clipping detection signal based on the first signal and the second signal, the clipping detection signal indicating whether the pulse width modulation signal is clipped, wherein the clipping detection signal is a digital signal, and wherein the clipping detection signal is de-asserted after m pulses of the pulse width modulation signal after the first signal has been de-asserted.

18. The method according to claim 17, wherein the pulse width modulation signal has a frequency higher than 1 MHz.

19. The method according to claim 17, further comprising: receiving a clock signal; and asserting the first signal due to n periods of the clock signal having elapsed since the last occurrence of an edge in the pulse width modulation signal, where n is a positive integer greater than 1.

20. The method according to claim 19, wherein m is equal to 3 and n is equal to 6.

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