Organic Light-Emitting Diode Display

Abstract

An organic light emitting diode display is described. The organic light emitting diode display includes a substrate having a display area and a non-display area, a metal layer disposed on the non-display area of the substrate, an insulating layer, a voltage line disposed on the gate insulating layer and receiving a driving voltage, a second voltage line disposed on the gate insulating layer and receiving a low driving voltage, an organic insulating layer, and a cathode electrode disposed on the organic insulating layer. The second voltage line and the cathode electrode are electrically connected to each other through an opening formed in the organic insulating layer, and the first voltage line or the second voltage line is electrically connected to the metal layer through an opening formed in the gate insulating layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0026393, filed with the Korean Intellectual Property Office on March 7, 2019, the entire content of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to an organic light - emitting diode (OLED) display, and more particularly, to a wiring structure for applying a driving voltage and a low driving voltage to an OLED display. Background art

[0004] OLEDs can be used in the production of display devices. In an OLED display, a plurality of pixels can be arranged in a matrix form to display an image. Compared with other display technologies, OLED displays have technical advantages. For example, OLED displays have self - emissive characteristics, which avoid the need to use a backlight unit as a light source.

[0005] Each pixel in an OLED display includes a light - emitting device and a pixel driving circuit. It may also include a plurality of thin - film transistors and storage capacitors for independently driving the light - emitting device.

[0006] The light - emitting device may include an organic emission layer located between an anode electrode (pixel electrode) and a cathode electrode. The cathode electrode may include a transparent conductive material and may be formed over the entirety of the pixels of the display panel.

[0007] The driving voltage (ELVDD) is a high - potential voltage supplied to the anode electrode. The low driving voltage (ELVSS) is a low - potential voltage supplied to the cathode electrode. The driving voltage (ELVDD) and the low driving voltage (ELVSS) may be supplied to one side of the display panel of the OLED display and may be supplied from a driving circuit for driving the display panel to each light - emitting device.

[0008] The above information disclosed in the background art section is only for enhancing the understanding of the background of the present invention and thus may include information that does not constitute the prior art known to a person of ordinary skill in the art in this country. Summary of the invention

[0009] Embodiments of the present invention prevent heat from being generated at the lower part of the display panel when current accumulates at the end of the low - driving - voltage (ELVSS) wiring in an organic light - emitting diode (OLED) display.

[0010] Exemplary embodiments of the present invention provide an OLED display, comprising: a substrate including a display area and a non-display area, a metal layer disposed on the non-display area of the substrate, a gate insulating layer covering the metal layer and the substrate (wherein the gate insulating layer includes an inorganic material), a first voltage line disposed on the gate insulating layer and receiving a driving voltage, a second voltage line disposed on the gate insulating layer and receiving a low driving voltage (wherein the low driving voltage is lower than the driving voltage), an organic insulating layer covering the first voltage line and the second voltage line, and a cathode electrode formed on the organic insulating layer, wherein the second voltage line and the cathode electrode are electrically connected to each other through an opening formed in the organic insulating layer, and the first voltage line or the second voltage line is electrically connected to the metal layer through an opening formed in the gate insulating layer.

[0011] The second voltage line may be disposed to surround four sides of the display area.

[0012] The first voltage line may be disposed to partially overlap the second voltage line in the non-display area.

[0013] The organic insulating layer may include: an interlayer insulating layer disposed to cover the first voltage line disposed on the gate insulating layer; a passivation layer disposed to cover the second voltage line disposed on the interlayer insulating layer; and an upper organic layer disposed on the passivation layer.

[0014] The OLED display may further include: a first voltage application connector disposed on the gate insulating layer; and a first voltage application wiring disposed on the interlayer insulating layer, wherein the first voltage application wiring may be electrically connected to the first voltage application connector through an opening formed in the interlayer insulating layer, and the first voltage application connector may be electrically connected to the metal layer through an opening formed in the gate insulating layer.

[0015] The first voltage line may be electrically connected to the metal layer through an opening formed in the gate insulating layer.

[0016] The OLED display may further include: an anode electrode disposed between the passivation layer and the upper organic layer; and an organic emission layer disposed on the anode electrode, wherein the cathode electrode may be disposed on the organic emission layer.

[0017] The OLED display may further include a cathode electrode connector disposed on the passivation layer, wherein the cathode electrode connector may be electrically connected to the cathode electrode through an opening formed in the upper organic layer, and the cathode electrode connector may be electrically connected to the second voltage line through an opening formed in the passivation layer.

[0018] The OLED display may further include a second voltage line auxiliary connector disposed on the gate insulating layer, wherein the second voltage line auxiliary connector may be electrically connected to the second voltage line through an opening formed in the interlayer insulating layer.

[0019] The second voltage line may be disposed around at least three sides of the display area.

[0020] The organic insulating layer may include: an interlayer insulating layer disposed to cover the gate insulating layer; a passivation layer disposed to cover the second voltage line disposed on the interlayer insulating layer; and an upper organic layer disposed on the passivation layer.

[0021] The OLED display may further include a first voltage line auxiliary connector disposed on the gate insulating layer, wherein the first voltage line may be disposed on the interlayer insulating layer and may be electrically connected to the first voltage line auxiliary connector through an opening formed in the interlayer insulating layer.

[0022] The OLED display may further include a second voltage application connector disposed on the gate insulating layer and a second voltage application wiring disposed on the interlayer insulating layer, wherein the second voltage application connector may be electrically connected to the metal layer through an opening formed in the gate insulating layer, and the second voltage application wiring may be electrically connected to the second voltage application connector through an opening formed in the interlayer insulating layer.

[0023] The OLED display may further include a cathode electrode connector disposed on the passivation layer, wherein the cathode electrode connector may be electrically connected to the cathode electrode through an opening formed in the upper organic layer, and the cathode electrode connector may be electrically connected to the second voltage line through an opening formed in the passivation layer.

[0024] The OLED display may further include: a second voltage application connector disposed on the gate insulating layer; and a second voltage application wiring disposed on the interlayer insulating layer, wherein the second voltage application wiring may be electrically connected to the second voltage application connector through an opening formed in the interlayer insulating layer, and the second voltage application connector may be electrically connected to the metal layer through an opening formed in the gate insulating layer.

[0025] The second voltage line may be disposed around three sides of the display area.

[0026] Another embodiment of the present invention provides an OLED display, comprising: a substrate including a display area and a non-display area; a gate insulating layer disposed on the substrate; a first voltage line disposed on the gate insulating layer and receiving a driving voltage; an inorganic insulating layer covering the first voltage line and the gate insulating layer; an interlayer insulating layer disposed on the inorganic insulating layer; a second voltage line disposed on the interlayer insulating layer and receiving a low driving voltage, wherein the low driving voltage is lower than the driving voltage; an organic insulating layer disposed on the second voltage line; and a cathode electrode disposed on the organic insulating layer, wherein the second voltage line and the cathode electrode can be electrically connected to each other through an opening formed in the organic insulating layer, and in a plan view, the first voltage line and the second voltage line can be disposed to partially overlap each other at a lower portion of the non-display area.

[0027] The second voltage line can be disposed to surround four sides of the display area.

[0028] The organic insulating layer can include: a passivation layer disposed to cover the second voltage line disposed on the interlayer insulating layer; and an upper organic layer disposed on the passivation layer.

[0029] The OLED display can further include: an anode electrode disposed between the passivation layer and the upper organic layer; and an organic emission layer disposed on the anode electrode, wherein the cathode electrode can be disposed on the organic emission layer.

[0030] According to an exemplary embodiment, a metal layer can be formed in a lower portion of the non-display area to apply the driving voltage or the low driving voltage, and an inorganic insulating layer can be formed between the driving voltage line and the low driving voltage line to reduce heat generated by a lower portion of the display panel.

[0031] A metal layer can be formed in a lower portion of the non-display area to apply the driving voltage or the low driving voltage, and a low driving voltage wiring can be partially formed in the non-display area to reduce a dead space between a display unit and a pad unit.

[0032] In yet another embodiment, the OLED display can include a metal layer disposed on a non-display area of the substrate; a gate insulating layer including an inorganic material; a first voltage line disposed on the gate insulating layer and configured to receive a driving voltage; and a second voltage line disposed on the gate insulating layer and configured to receive a low driving voltage, wherein the low driving voltage is lower than the driving voltage; wherein the first voltage line or the second voltage line is electrically connected to the metal layer through an opening formed in the gate insulating layer, and wherein the gate insulating layer is configured to prevent current concentration in the second voltage line. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A plan view and an enlarged view of an organic light-emitting diode (OLED) display according to an exemplary embodiment are shown.

[0034] Figure 2 Shows a plan view of an OLED display according to an exemplary embodiment.

[0035] Figure 3 Shows with respect to Figure 1 a cross-sectional view taken along line III-III.

[0036] Figure 4 Shows a plan view of an OLED display according to an exemplary embodiment.

[0037] Figure 5 Shows with respect to Figure 4 a cross-sectional view taken along line IV-IV.

[0038] Figure 6 Shows a plan view of an OLED display according to an exemplary embodiment.

[0039] Figure 7 Shows with respect to Figure 6 a cross-sectional view taken along line VI-VI.

[0040] Figure 8 Shows a plan view of an OLED display according to an exemplary embodiment.

[0041] Figure 9 Shows with respect to Figure 8 a cross-sectional view taken along line VIII-VIII.

[0042] Figure 10 Shows a plan view of an OLED display according to an exemplary embodiment.

[0043] Figure 11 Shows with respect to Figure 10 a cross-sectional view taken along line X-X.

[0044] Figure 12 Shows a circuit diagram of a pixel of an OLED display according to an exemplary embodiment.

[0045] Figure 13 Shows a cross-sectional view of a display area of an OLED display according to an exemplary embodiment. DETAILED DESCRIPTION

[0046] The present disclosure describes an organic light emitting diode (OLED) display in which drive voltage lines and low drive voltage lines are configured to prevent heat generation at a lower portion of a display panel.

[0047] The present invention is described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. Those skilled in the art will recognize that the described embodiments can be modified in various different ways without departing from the spirit or scope of the present invention.

[0048] The drawings and the description are to be regarded as illustrative rather than restrictive, and throughout the specification, like reference numerals indicate like elements.

[0049] For better understanding and ease of description, the dimensions and thicknesses of each structure shown in the drawings are arbitrarily shown, and the present invention is not limited thereto. In the drawings, for clarity, the thicknesses of layers, films, panels, regions, etc. are enlarged. For better understanding and ease of description, the thicknesses of some layers and regions are enlarged.

[0050] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, the element can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements. The terms “on” or “above” refer to being on or under a portion of an object and do not necessarily mean on the upper side based on the direction of gravity of the object portion.

[0051] Unless expressly stated to the contrary, the term “comprises” and variations such as “comprising” are to be understood as implicitly including the stated elements but not excluding any other elements.

[0052] The phrase “in a plane” refers to observing a portion of an object from the top, and the phrase “in a cross-section” refers to a cross-section obtained by vertically cutting a portion of an object from the side.

[0053] Reference will now be made to Figures 1 to 3 describe an OLED display in which a driving voltage line and a low driving voltage line are provided according to an exemplary embodiment.

[0054] Figure 1 A plan view and an enlarged view of an OLED display according to an exemplary embodiment are shown, Figure 2 A plan view of an OLED display according to an exemplary embodiment is shown, and Figure 3 is shown with respect to Figure 1 a cross-sectional view taken along line III-III.

[0055] Reference Figures 1 to 3, the OLED display includes a substrate 100, a second voltage line auxiliary connector 146, a second voltage line 156, a cathode electrode connector 192, and a cathode electrode 270. The second voltage line auxiliary connector 146, the second voltage line 156, the cathode electrode connector 192, and the cathode electrode 270 are sequentially formed on the substrate 100. When the second voltage line auxiliary connector 146, the second voltage line 156, the cathode electrode connector 192, and the cathode electrode 270 are not connected through an opening, these layers are insulated from each other using an insulating layer therebetween. More specifically, the second voltage line auxiliary connector 146, the second voltage line 156, the cathode electrode connector 192, and the cathode electrode 270 are sequentially insulated using an organic insulating layer therebetween. In Figures 1 to 3 , an organic insulating layer including an interlayer insulating layer 160, a passivation layer 180, and an upper organic layer 350 is described.

[0056] Reference Figure 1 and Figure 2 , the substrate 100 includes a display area DA and a non-display area NA. The display area DA is an area for displaying an image, and pixels PX including thin film transistors and OLEDs are formed in the display area DA. The non-display area NA is an area where no image is displayed. A first voltage line 155 and a second voltage line 156 for transmitting voltage and signals to the pixels PX formed in the display area DA and a plurality of pads 300 are formed in the non-display area NA. In an exemplary embodiment, the first voltage line 155 is a wiring for supplying a driving voltage ELVDD (shown in Figure 12 ) to the thin film transistors in the display area DA. The second voltage line 156 is a wiring for supplying a low driving voltage ELVSS (shown in Figure 12 ) to the cathode electrode 270 of the OLED configured with an anode electrode (191 hereinafter Figure 13 ), an organic emission layer (370 hereinafter Figure 13 ), and the cathode electrode 270.

[0057] The first voltage line 155 is a wiring for applying a driving voltage ELVDD to the display area DA and is formed in the non-display area NA. The first voltage line 155 also includes an overlapping portion 155a formed in the lower part (area A) of the non-display area NA. The first voltage application wiring 153 extends from the overlapping portion 155a to a plurality of pads 300, and a plurality of wirings 155b extend from the overlapping portion 155a toward the display area DA. The overlapping portion 155a of the first voltage line 155 overlaps with the second voltage line 156. The first voltage application wiring 153 can be a part of the wiring for receiving the driving voltage ELVDD from the pad 300, and the plurality of wirings 155b are parts that are connected to the display area DA and apply the driving voltage ELVDD. The overlapping portion 155a and the wiring 155b receive the driving voltage ELVDD and apply the driving voltage ELVDD to the pixels PX in the display area DA. Although not shown, the plurality of wirings 155b can be formed to extend in the vertical direction in the display area DA.

[0058] The second voltage line 156 is a wiring for supplying a low driving voltage ELVSS to the cathode electrode 270 of the OLED. The second voltage line 156 is formed to surround the edge of the display area DA. More specifically, the second voltage line 156 is formed in the upper area, lower area, right area, and left area of the non-display area NA surrounding the display area DA. According to an exemplary embodiment, the second voltage line 156 can be formed in one of the upper area, lower area, right area, and left area of the non-display area NA so that the second voltage line 156 can surround at least a part of the display area DA. Specifically, referring to Figure 2 , the second voltage line 156 is formed to surround the lower area, right area, and left area of the non-display area NA.

[0059] The second voltage line 156 is formed to overlap with the first voltage line 155 in the lower part of the non-display area NA and is also formed to surround the four sides of the display area DA. Therefore, the current flowing to the cathode electrode 270 can be prevented from accumulating in any specific area and can flow throughout the area. The second voltage line 156 is electrically connected to the cathode electrode 270 through a plurality of contact holes in the upper area, right area, and left area of the non-display area NA. The connection between the second voltage line 156 and the cathode electrode 270 will be described with reference to Figure 3 described later in this specification.

[0060] The plurality of pads 300 include a first pad for applying the driving voltage ELVDD to the first voltage line 155 and the first voltage application wiring 153 connected to the first voltage line 155. The plurality of pads 300 may also include a second pad for applying the low driving voltage ELVSS to the second voltage line 156 and the second voltage application wiring 154 connected to the second voltage line 156.

[0061] The cathode electrode 270 is an electrode on the other side of the OLED and is formed on the display panel. The cathode electrode 270 is formed to cover the display area DA, and is formed to cover parts of the upper area, lower area, right area, and left area of the non-display area NA. In a plan view, the cathode electrode 270 is formed to completely cover the second voltage line 156 formed in the upper area, right area, and left area of the non-display area NA, and is formed to partially cover the second voltage line 156 formed in the lower area. In an exemplary embodiment, the second voltage application wiring 154 may not be covered by the cathode electrode 270. In a plan view, the cathode electrode 270 is formed to cover the first voltage line 155 formed in the lower area of the non-display area NA. The first voltage application wiring 153 may not be covered by the cathode electrode 270.

[0062] The OLED display may include a substrate 100 having a display area DA and a non-display area NA. The non-display area NA may include a metal layer 111 (shown in Figure 4 ), a gate insulating layer 130 including an inorganic material, a first voltage line 155 disposed on the gate insulating layer 130 and configured to receive a driving voltage ELVDD, and a second voltage line 156 disposed on the gate insulating layer 130 and configured to receive a low driving voltage ELVSS; wherein the first voltage line 155 or the second voltage line 156 is electrically connected to the metal layer through an opening formed in the gate insulating layer 130, and wherein the gate insulating layer 130 is configured to prevent current concentration in the second voltage line 156.

[0063] Figure 1 An enlarged view showing where the cathode electrode 270 contacts the second voltage line 156 is shown in the right inset. Referring to Figure 1 the enlarged view on the right side, the cathode electrode 270 is connected to the cathode electrode connector 192 through an opening 63. The cathode electrode connector 192 is connected to the second voltage line 156 through an opening 62. The second voltage line 156 is connected to the second voltage line auxiliary connector 146 through an opening 61.

[0064] Specifically, referring to Figure 3 , the substrate 100 may be formed of a glass substrate or a flexible substrate including plastic and polyimide (PI).

[0065] The gate insulating layer 130 is formed on the substrate 100. The gate insulating layer 130 includes an inorganic material and may be made of silicon nitride (SiN x ) or silicon oxide (SiO x ). The gate insulating layer 130 may include a first gate insulating layer 131, a second gate insulating layer 132, a third gate insulating layer 133, and a fourth gate insulating layer 134 (as shown in Figure 13 ). In an exemplary embodiment, a barrier layer (in the lower partFigure 5 110) and the buffer layer (below Figure 5 120) can be additionally formed between the substrate 100 and the gate insulating layer 130.

[0066] The second voltage line auxiliary connector 146 is formed on the gate insulating layer 130. The second voltage line auxiliary connector 146 is an island-shaped electrode and is partially formed on the gate insulating layer 130.

[0067] The interlayer insulating layer 160 is formed on the second voltage line auxiliary connector 146. An opening 61 for exposing the second voltage line auxiliary connector 146 is formed in the interlayer insulating layer 160. The interlayer insulating layer 160 can be an organic insulating layer made of an organic material.

[0068] The second voltage line 156 is formed on the interlayer insulating layer 160. The second voltage line 156 is provided to overlap with the second voltage line auxiliary connector 146 and is electrically connected to the second voltage line auxiliary connector 146 through the opening 61.

[0069] The passivation layer 180 is formed on the second voltage line 156. The passivation layer 180 is an organic insulating layer made of an organic material and has the property of removing steps and flattening the steps.

[0070] The cathode electrode connector 192 is formed on the passivation layer 180. The cathode electrode connector 192 applies a low driving voltage ELVSS to the cathode electrode 270 which can be another electrode of the OLED. The cathode electrode connector 192 is provided to overlap with the second voltage line 156 and is electrically connected to the second voltage line 156 through the opening 62.

[0071] The upper organic layer 350 is formed on the cathode electrode connector 192 and can be an organic insulating layer made of an organic material.

[0072] The cathode electrode 270 is formed on the upper organic layer 350 and can overlap with the cathode electrode connector 192 and is electrically connected to the cathode electrode connector 192 through the opening 63. That is, the cathode electrode 270 receives the low driving voltage ELVSS from the second voltage line 156 through the cathode electrode connector 192.

[0073] In an exemplary embodiment, the second voltage line 156 and the cathode electrode 270 have been described as being connected through the cathode electrode connector 192. In some examples, the second voltage line 156 and the cathode electrode 270 can be directly connected through an opening passing through the organic insulating layer instead of by the cathode electrode connector 192.

[0074] In the above, it has been described that the first voltage line 155 overlaps with the second voltage line 156 at the lower part of the non-display area NA, and the cathode electrode 270 is electrically connected to the second voltage line 156.

[0075] In Figures 4 to 9 an exemplary embodiment is described in which the first voltage line 155 overlaps with the second voltage line 156 at the lower part of the non-display area NA of the OLED display and a metal layer 111 is further formed at the lower part of the non-display area NA.

[0076] Figure 4 A plan view of an OLED display according to an exemplary embodiment is shown, and Figure 5 a cross-sectional view taken along line IV-IV with respect to Figure 4 is shown. Figure 6 A plan view of an OLED display according to an exemplary embodiment is shown, and Figure 7 a cross-sectional view taken along line VI-VI with respect to Figure 6 is shown. Figure 8 A plan view of an OLED display according to an exemplary embodiment is shown, and Figure 9 a cross-sectional view taken along line VIII-VIII with respect to Figure 8 is shown.

[0077] Referring to Figure 4 and Figure 5 an OLED display according to an exemplary embodiment includes a substrate 100, a first data wiring layer (143, 146, and 155, and Figure 6 136, 148, and 145 shown in Figure 6 ), a second data wiring layer (153 and 156, and 154, 158, and 155 shown in

[0078] ), a cathode electrode connector 192, and a cathode electrode 270. The first data wiring layer (143, 146, 155, 136, 148, and 145), the second data wiring layer (153, 156, 154, 158, and 155), the cathode electrode connector 192, and the cathode electrode 270 are sequentially formed on the substrate 100. When the first data wiring layer (143, 146, 155, 136, 148, and 145), the second data wiring layer (153, 156, 154, 158, and 155), the cathode electrode connector 192, and the cathode electrode 270 are not connected through openings, these layers are insulated from each other using an insulating layer therebetween. In the exemplary embodiment, the insulating layer includes an inorganic insulating layer or an organic insulating layer, and the organic insulating layer includes an interlayer insulating layer 160, a passivation layer 180, and an upper organic layer 350. The substrate 100 may be formed of a flexible substrate 100 including plastic and polyimide (PI).

[0079] The barrier layer 110 is formed on the substrate 100. The barrier layer 110 may be formed of an inorganic material.

[0080] The metal layer 111 is formed on the barrier layer 110. The metal layer 111 transmits the driving voltage ELVDD. The metal layer 111 includes an overlapping portion 111a formed in the non-display area NA in the horizontal direction and a lower extension 111b extending from the overlapping portion 111a in the vertical direction and connected to the pad 300. The upper region of the overlapping portion 111a overlaps with the end of the first voltage line 155 in the vertical direction and overlaps with the second voltage line 156 in the horizontal direction. The lower extension 111b partially overlaps with the first voltage application connector 143 and the first voltage application wiring 153.

[0081] The buffer layer 120 is formed on the metal layer 111 and covers the substrate 100 and the metal layer 111. The buffer layer 120 may be formed of an inorganic insulating material.

[0082] The gate insulating layer 130 is formed on the buffer layer 120, and the gate insulating layer 130 may be made of an inorganic insulating material.

[0083] The first data wiring layer (143, 146, 155, 136, 148, and 145) is formed on the gate insulating layer 130. The first data wiring layer (143, 146, 155, 136, 148, and 145) includes the first voltage application connector 143, the second voltage line auxiliary connector 146, and the first voltage line 155.

[0084] The first voltage application connector 143 transmits the driving voltage ELVDD to the metal layer 111. The first voltage application connector 143 partially overlaps with the lower extension 111b of the metal layer 111. The first voltage application connector 143 has an island structure and is connected to the lower extension 111b of the metal layer 111 through the opening 71.

[0085] The second voltage line auxiliary connector 146 is an auxiliary electrode for applying the low driving voltage ELVSS to the second voltage line 156. The second voltage line auxiliary connector 146 is formed to overlap with the overlapping portion 111a of the metal layer 111 and the second voltage line 156.

[0086] The first voltage line 155 is a wiring for applying the driving voltage ELVDD to the display area DA and is formed in the non-display area NA. The first voltage line 155 partially overlaps with the upper region of the overlapping portion 111a of the metal layer 111. The first voltage line 155 is electrically connected to the metal layer 111 through the opening 51. Although not shown, a plurality of wirings 155b may be formed to extend in the vertical direction in the display area DA.

[0087] The first data wiring layers 143, 146, 155, 136, 148, and 145, and the gate insulating layer 130 are covered with an interlayer insulating layer 160. The interlayer insulating layer 160 may be formed of an organic material.

[0088] The second data wiring layers 153 and 156, and Figure 6 154, 158, and 155 shown in

[0089] are formed on the interlayer insulating layer 160. The second data wiring layers 154, 158, 153, 155, and 156 include a first voltage application wiring 153 and a second voltage line 156.

[0090] The first voltage application wiring 153 is connected to the pad 300 to transmit a driving voltage ELVDD, and overlaps with the first voltage application connector 143. The first voltage application wiring 153 is electrically connected to the first voltage application connector 143 through an opening 72. The first voltage application wiring 153 and the second voltage line 156 are formed on the same layer.

[0091] Reference Figure 4 , the second voltage line 156 is shown to have an overlapping area with the first voltage line 155 at the lower part of the non-display area NA. Reference Figure 4 and Figure 5, the low driving voltage ELVSS is applied to the second voltage line 156 through the second voltage application wiring 154 formed on the same layer. The first voltage line 155 transmits the driving voltage ELVDD applied by the pad 300 to the first voltage application wiring 153. The first voltage application wiring 153 transmits the driving voltage ELVDD to the first voltage application connector 143 connected through the opening 72. The first voltage application connector 143 transmits the driving voltage ELVDD to the metal layer 111 connected through the opening 71. The first voltage line 155 connected to the metal layer 111 through the opening 51 applies the driving voltage ELVDD to the pixel PX in the display area DA. In an exemplary embodiment, the driving voltage ELVDD and the low driving voltage ELVSS are applied while the gate insulating layer 130 made of an inorganic insulating layer is located therebetween, resulting in a lower possibility of short - circuit between the first voltage line 155 and the second voltage line 156.

[0092] The passivation layer 180 is formed on the second data wiring layers 153 and 156 and the interlayer insulating layer 160. The passivation layer 180 is formed of an organic insulating material, and the passivation layer 180 has the property of removing steps and flattening the steps.

[0093] The cathode electrode connector 192 is formed on the passivation layer 180. The cathode electrode connector 192 can apply the low driving voltage ELVSS to the cathode electrode 270 which can be another electrode of the OLED. The cathode electrode connector 192 is provided to partially overlap with the second voltage line 156. The cathode electrode connector 192 is electrically connected to the second voltage line 156 through the opening 62 and is also electrically connected to the cathode electrode 270.

[0094] The upper organic layer 350 is formed on the cathode electrode connector 192 and the passivation layer 180. The upper organic layer 350 includes an opening 63 for exposing the cathode electrode connector 192. The upper organic layer 350 may further include an opening ( Figure 13 in 91) for exposing the anode electrode ( Figure 13 in 191), and the organic emission layer ( Figure 13 in 370) may be formed in the opening 91.

[0095] The cathode electrode 270 is formed on the upper organic layer 350. The cathode electrode 270 is provided to overlap with the cathode electrode connector 192, and the cathode electrode 270 is electrically connected to the cathode electrode connector 192 through the opening 63. That is, the cathode electrode 270 receives the low driving voltage ELVSS from the second voltage line 156 through the cathode electrode connector 192.

[0096] has been referred to Figure 4 and Figure 5A structure is described in which a driving voltage ELVDD can be applied through a metal layer 111, and now reference will be made to Figures 6 to 9 Describe a structure in which a low driving voltage ELVSS is applied through a metal layer 111.

[0097] Reference Figure 6 And Figure 7 According to an exemplary embodiment, an OLED display includes a substrate 100, a first data wiring layer (136, 146, 155, 143, 148, and 145), a second data wiring layer (153, 156, 154, 158, and 155), a cathode electrode connector 192, and a cathode electrode 270. The first data wiring layer (136, 146, 155, 143, 148, and 145), the second data wiring layer (153, 156, 154, 158, and 155), the cathode electrode connector 192, and the cathode electrode 270 are sequentially formed on the substrate 100. When the first data wiring layer (136, 146, 155, 143, 148, and 145), the second data wiring layer (153, 156, 154, 158, and 155), the cathode electrode connector 192, and the cathode electrode 270 are not connected through an opening, these layers are insulated from each other using an insulating layer therebetween. The insulating layer may include an inorganic insulating layer or an organic insulating layer, and the organic insulating layer includes an interlayer insulating layer 160, a passivation layer 180, and an upper organic layer 350.

[0098] Hereinafter, what is different from the above description will be described while omitting repeated parts.

[0099] A barrier layer 110 is formed on the substrate 100.

[0100] A metal layer 111 is formed on the barrier layer 110. The metal layer 111 is electrically connected to the second voltage line 156 and transmits a low driving voltage ELVSS. The metal layer 111 is formed in a quadrilateral shape in the non-display area NA, and may partially overlap with the first voltage line 155, and partially overlap with the second voltage application connector 136 and the second voltage line auxiliary connector 148.

[0101] The first data wiring layer (136, 143, 146, 148, 155, and 145) is formed on the gate insulating layer 130 and includes a first voltage line auxiliary connector 145, a second voltage application connector 136, and a second voltage line auxiliary connector 148.

[0102] The first voltage line auxiliary connector 145 is an auxiliary electrode for transmitting a driving voltage ELVDD to the first voltage line 155. The first voltage line auxiliary connector 145 is formed to be completely overlapped by the metal layer 111 and has an island structure.

[0103] The second voltage application connector 136 transmits a low driving voltage ELVSS to the metal layer 111 and partially overlaps with a lower region of the metal layer 111. The second voltage application connector 136 may be electrically connected to the metal layer 111 through the opening 81.

[0104] The second voltage line auxiliary connector 148 transmits the low driving voltage ELVSS from the metal layer 111 to the cathode electrode 270. The second voltage line auxiliary connector 148 partially overlaps with an upper region of the metal layer 111. The second voltage line auxiliary connector 148 is electrically connected to the metal layer 111 through the opening 60.

[0105] The second data wiring layer (153, 156, 154, 158, and 155) is formed on the interlayer insulating layer 160. The second data wiring layer (153, 156, 154, 158, and 155) may further include a first voltage line 155, a second voltage application wiring 154, and a second voltage line connector 158.

[0106] The first voltage line 155 is a wiring for applying the driving voltage ELVDD to the display area DA. The first voltage line 155 includes a horizontal unit 155c formed at a lower portion of the non-display area NA in the horizontal direction. The first voltage application wiring 153 extends from the horizontal unit 155c to a plurality of pads 300, and a plurality of wirings 155b extend from the horizontal unit 155c to the display area DA. The first voltage line auxiliary connector 145 completely overlaps with the horizontal unit 155c of the first voltage line 155 and is connected to the first voltage line 155 through the opening 52. The first voltage application wiring 153 receives the driving voltage ELVDD from the pads 300, and the plurality of wirings 155b are connected to the display area DA and apply the driving voltage ELVDD. Although not shown, the plurality of wirings 155b may be formed to extend in the vertical direction in the display area DA. The second voltage line auxiliary connector 148 is formed between the plurality of wirings 155b at a lower portion of the non-display area NA.

[0107] The second voltage application wiring 154 is connected to the pads 300 and transmits the low driving voltage ELVSS. The second voltage application wiring 154 overlaps with the second voltage application connector 136 and is electrically connected to the second voltage application connector 136 through the opening 82. The low driving voltage ELVSS applied by the second voltage application wiring 154 is transmitted to the metal layer 111 through the second voltage application connector 136. The second voltage application wiring 154 is a part of the connection to the second voltage line 156 and the pads 300, and the second voltage application wiring 154 and the second voltage line 156 are formed on the same layer.

[0108] The second voltage line connector 158 transmits the low driving voltage ELVSS to the cathode electrode 270, and is provided to overlap with the second voltage line auxiliary connector 148, and is electrically connected to the second voltage line auxiliary connector 148 through the opening 61.

[0109] The cathode electrode connector 192 is formed on the passivation layer 180, and is provided to partially overlap with the second voltage line connector 158. In addition, the cathode electrode connector 192 is provided to partially overlap with the second voltage line auxiliary connector 148. The cathode electrode connector 192 is electrically connected to the second voltage line connector 158 through the opening 62, and is also electrically connected to the cathode electrode 270.

[0110] The cathode electrode 270 is formed on the upper organic layer 350, and may be provided to overlap with the cathode electrode connector 192, and is electrically connected to the cathode electrode connector 192 through the opening 63. That is, the cathode electrode 270 receives the low driving voltage ELVSS from the second voltage line 156 through the cathode electrode connector 192.

[0111] Reference Figure 6 , the second voltage line 156 is formed to surround the upper region, the right region, and the left region of the display area DA, and is formed in the upper region, the lower region, the right region, and the left region of the non-display area NA. However, the second voltage line 156 is formed to be partially open at the lower part of the non-display area NA. Therefore, the current caused by the low driving voltage ELVSS applied by the pad 300 located on one side may accumulate at the end (region B) where the second voltage line 156 overlaps with the cathode electrode 270. The low driving voltage ELVSS applied through the second voltage application wiring 154 on the pad 300 is applied to the second voltage application connector 136. The second voltage application connector 136 is connected to the second voltage application wiring 154 through the opening 82. The metal layer 111 may be connected to the second voltage application connector 136 through the opening 81.

[0112] In an exemplary embodiment, a low driving voltage ELVSS applied from the metal layer 111 to the second voltage line auxiliary connector 148 through the opening 60 is applied to the second voltage line connector 158. The second voltage line connector 158 may be connected to the second voltage line auxiliary connector 148 through the opening 61. The low driving voltage ELVSS may be applied to the cathode electrode connector 192 connected at the second voltage line connector 158 through the opening 62, and to the cathode electrode 270 to which the cathode electrode connector 192 is connected through the opening 63. Accordingly, the low driving voltage ELVSS applied by the pad 300 may be applied to the cathode electrode 270, thereby dispersing the current concentrated at the end (region B) of the second voltage line 156. Additionally, the driving voltage ELVDD and the low driving voltage ELVSS are applied on both sides of the gate insulating layer 130 made of an inorganic insulating layer. Therefore, the risk of short - circuiting between the first voltage line 155 and the second voltage line 156 may be reduced, and the generation of burnout defects may be correspondingly reduced.

[0113] The above has been referenced Figure 6 and Figure 7 to describe the configuration in which the low driving voltage ELVSS is applied through the metal layer 111. In an exemplary embodiment, the second voltage line 156 is formed in the lower region of the non - display area NA, so that the low driving voltage ELVSS is applied from the pad 300 through the second voltage application wiring 154. A predetermined space may be provided in the non - display area NA so that the second voltage line 156 can be formed in the lower part of the non - display area NA. In some examples, a dead space may be formed.

[0114] Now, exemplary embodiments for reducing the dead space in the case where the second voltage line 156 is not formed in the lower region of the non - display area NA will be described with reference to Figure 8 and Figure 9 and will mainly describe the differences, including the content described with reference to

[0115] Figure 8 and Figure 9 Figure 6 and Figure 7 Therefore, the differences will be mainly described.

[0116]

[0116] Referring to Figure 8 , a barrier layer 110 is formed on the substrate 100.

[0117] The metal layer 111 is formed on the barrier layer 110. The metal layer 111 is electrically connected to the second voltage line 156 and transmits a low driving voltage ELVSS. The metal layer 111 includes an overlapping portion 111a formed in the non-display area NA in the horizontal direction and a lower extension 111b extending from the overlapping portion 111a in the vertical direction and connected to the pad 300. The overlapping portion 111a partially overlaps with the first voltage line 155 and a portion of the second voltage line auxiliary connector 148. The lower extension 111b overlaps with the entire area of the second voltage application connector 136.

[0118] The second voltage application connector 136 transmits the low driving voltage ELVSS to the metal layer 111. The second voltage application connector 136 is electrically connected to the lower extension 111b of the metal layer 111 through the opening 81. The entire area of the second voltage application connector 136 partially overlaps with the lower extension 111b.

[0119] The second voltage application wiring 154 is connected to the pad 300 to transmit the low driving voltage ELVSS. The second voltage application wiring 154 overlaps with the second voltage application connector 136 and is electrically connected to the second voltage application connector 136 through the opening 82. The low driving voltage ELVSS applied by the second voltage application wiring 154 is transmitted to the metal layer 111 through the second voltage application connector 136. In an exemplary embodiment, the second voltage application wiring 154 and the second voltage line 156 are formed on the same layer.

[0120] The second voltage line 156 is formed to surround the upper area, the right area, and the left area of the display area DA and is not formed in the lower part of the non-display area NA. That is, the second voltage line 156 is formed to reach the ends (point C) of the right area and the left area of the non-display area NA. Therefore, in order to apply the low driving voltage ELVSS to the second voltage line 156, the low driving voltage ELVSS is applied from the pad 300 through the second voltage application wiring 154. The low driving voltage ELVSS is also applied to the second voltage application connector 136 to which the second voltage application wiring 154 is connected through the opening 82. The low driving voltage ELVSS is also applied to the metal layer 111 to which the second voltage application connector 136 is connected through the opening 81.

[0121] The low driving voltage ELVSS is applied to the second voltage line auxiliary connector 148 through the opening 60 in the metal layer 111. The low driving voltage ELVSS is applied to the second voltage line connector 158 to which the opening 61 is connected. The low driving voltage ELVSS is applied to the cathode electrode connector 192 connected through the opening 62 on the second voltage line connector 158 and is applied to the cathode electrode 270 to which the cathode electrode connector 192 is connected through the opening 63.

[0122] Reference Figure 6 , Figure 6 the second voltage line 156 shown in Figure 6 is formed in upper, right, left, and a part of the lower regions of the non-display area NA, while Figure 8 the second voltage line 156 shown in Figure 8 is formed in the upper, right, and left portions of the non-display area NA. Figure 8 And Figure 9 the second voltage line 156 shown in Figure 9 is not formed in the lower portion of the non-display area NA, thereby reducing the dead zone between the display area DA and the plurality of pads 300. Further, the driving voltage ELVDD and the low driving voltage ELVSS are applied while the gate insulating layer 130 made of an inorganic insulating layer is located therebetween. Accordingly, the risk that the first voltage line 155 and the second voltage line 156 are short-circuited can be reduced, and heat generation can be correspondingly reduced. This can prevent the generation of burn-out defects.

[0123] Exemplary embodiments in which the first voltage line 155 and the second voltage line 156 partially or entirely overlap each other at the lower portion of the non-display area NA of the OLED display have been described. In some cases, it has been described that a metal layer 111 is further formed at the lower portion of the non-display area NA. When the OLED display includes an inorganic insulating layer between the first voltage line 155 and the second voltage line 156, the OLED display can prevent heat generation at the lower portion of the non-display area NA. Now, reference will be made to Figure 10 and Figure 11 to describe a structure in which an inorganic insulating layer is included between the first voltage line 155 and the second voltage line 156.

[0124] Reference Figure 10 and Figure 11 , an OLED display according to an exemplary embodiment includes a substrate 100, a first voltage line 155, an inorganic insulating layer 135, a second voltage line 156, a cathode electrode connector 192, and a cathode electrode 270. The first voltage line 155, the second voltage line 156, the cathode electrode connector 192, and the cathode electrode 270 are sequentially formed on the substrate 100. In a case where the first voltage line 155, the second voltage line 156, the cathode electrode connector 192, and the cathode electrode 270 are not connected through an opening, these layers are insulated from each other using an insulating layer therebetween. In the exemplary embodiment, the insulating layer includes an inorganic insulating layer or an organic insulating layer, and the organic insulating layer includes an interlayer insulating layer 160, a passivation layer 180, and an upper organic layer 350 to be described.

[0125] A gate insulating layer 130 is formed on the substrate 100. The gate insulating layer 130 may be formed of an inorganic material. An inorganic insulating layer including a barrier layer 110 and a buffer layer 120 may be further formed between the substrate 100 and the gate insulating layer 130.

[0126] The first voltage line 155 is formed on the gate insulating layer 130. The first voltage line 155 includes an overlapping portion 155a formed in the non-display area NA in the horizontal direction. The first voltage application wiring 153 extends from the overlapping portion 155a to a plurality of pads 300, and a plurality of wirings 155b extend from the overlapping portion 155a to the display area DA. The overlapping portion 155a of the first voltage line 155 overlaps with the second voltage line 156. The first voltage application wiring 153 receives the driving voltage ELVDD from the pad 300, and the plurality of wirings 155b are connected to the display area DA to apply the driving voltage ELVDD. The overlapping portion 155a and the plurality of wirings 155b receive the driving voltage ELVDD and apply the driving voltage ELVDD to the pixels PX in the display area DA. Although not shown, the wiring 155b may be formed to extend in the vertical direction in the display area DA.

[0127] The inorganic insulating layer 135 is formed on the first voltage line 155 and the gate insulating layer 130.

[0128] The interlayer insulating layer 160 is formed on the inorganic insulating layer 135, and the interlayer insulating layer 160 is formed of an organic material.

[0129] The second voltage line 156 is formed on the interlayer insulating layer 160. The second voltage line 156 is formed in the upper region, lower region, right region, and left region of the non-display area NA surrounding the display area DA.

[0130] The passivation layer 180 covers the second voltage line 156 and the interlayer insulating layer 160. The passivation layer 180 may be formed of an organic material.

[0131] The cathode electrode connector 192 is formed on the passivation layer 180. The cathode electrode connector 192 is provided to overlap with the second voltage line 156 and is electrically connected to the second voltage line 156 through the opening 62.

[0132] The upper organic layer 350 is formed on the cathode electrode connector 192. The upper organic layer 350 may be formed of an organic material.

[0133] The cathode electrode 270 is formed on the upper organic layer 350. The cathode electrode 270 is provided to overlap with the cathode electrode connector 192 and is electrically connected to the cathode electrode connector 192 through the opening 63. That is, the cathode electrode 270 receives the low driving voltage ELVSS from the second voltage line 156 through the cathode electrode connector 192.

[0134] A large amount of current can flow to the first voltage line 155 and the second voltage line 156 to drive the pixel PX. When an organic insulating layer is provided between the first voltage line 155 and the second voltage line 156 in a portion where the first voltage line 155 overlaps with the second voltage line 156, this may cause the first voltage line 155 and the second voltage line 156 to be short-circuited. However, according to an exemplary embodiment, an inorganic insulating layer 135 is further formed between the first voltage line 155 and the second voltage line 156, so that burn-in defects and generated heat occurring at the lower portion of the non-display area NA can be prevented.

[0135] Exemplary embodiments for solving the drawback of generating heat at the lower portion of the non-display area NA of the OLED display have been described.

[0136] Now, the configuration of the pixel PX in the display area DA of the OLED display will be described.

[0137] Figure 12 A circuit diagram of a pixel of an OLED display according to an exemplary embodiment is shown, and Figure 13 A cross-sectional view of a display area of an OLED display according to an exemplary embodiment is shown.

[0138] Referring to Figure 12 , the pixel PX of the OLED display includes a storage capacitor Cst, an OLED, and a plurality of transistors (T1, T2, T3, T4, T5, T6, and T7) connected to signal lines (127, 151, 152, 155, 156, 157, 159, and 171).

[0139] The plurality of transistors (T1, T2, T3, T4, T5, T6, and T7) includes a driving transistor T1, a second transistor T2 which is a switching transistor connected to the scan line 151, and a third transistor T3. Other transistors (hereinafter, compensation transistors) for performing operations for operating the OLED display may also be included. The compensation transistors T4, T5, T6, and T7 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0140] The plurality of signal lines (127, 151, 152, 155, 156, 157, 159, and 171) may include a scan line 151, a pre-stage scan line 152, an emission control line 157, a bypass control line 159, a data line 171, a first voltage line 155, an initialization voltage line 127, and a second voltage line 156. The bypass control line 159 may be a part of the pre-stage scan line 152, or may be electrically connected to the pre-stage scan line 152.

[0141] The scan line 151 is connected to a gate driver (not shown) and transmits a scan signal Sn to switching transistors, i.e., the second transistor T2 and the third transistor T3. The pre-stage scan line 152 is connected to the gate driver and transmits a pre-stage scan signal Sn-1 applied to a pixel PX provided at the pre-stage to the fourth transistor T4. The fourth transistor T4 includes two transistors connected in series, and thus the pre-stage scan signal Sn-1 is applied to the gate electrodes of the two transistors connected in series included in the fourth transistor T4. The emission control line 157 is connected to an emission controller (not shown), and the emission control line 157 transmits an emission control signal EM for controlling the light emission time of the OLED display to the fifth transistor T5 and the sixth transistor T6. The bypass control line 159 transmits a bypass signal GB to the seventh transistor T7, and according to an exemplary embodiment, the bypass control line 159 may transmit the same signal as the pre-stage scan signal Sn-1.

[0142] The data line 171 is a wiring for transmitting a data voltage Dm generated by a data driver (not shown), and the luminance of the light emitted by the OLED changes according to the data voltage Dm. The first voltage line 155 applies a driving voltage ELVDD, the initialization voltage line 127 transmits an initialization voltage Vint for initializing the driving transistor T1, and the second voltage line 156 applies a low driving voltage ELVSS. A predetermined voltage may be applied to the first voltage line 155, the initialization voltage line 127, and the second voltage line 156.

[0143] A plurality of transistors will now be described.

[0144] The driving transistor T1 controls current output according to the applied data voltage Dm, an output driving current Id is applied to the OLED, and the luminance of the OLED is controlled according to the data voltage Dm. Accordingly, a first electrode S1 of the driving transistor T1 is set to receive the driving voltage ELVDD, and thus the first electrode S1 of the driving transistor T1 is connected to the first voltage line 155 via the fifth transistor T5. Further, the first electrode S1 of the driving transistor T1 is connected to a second electrode D2 of the second transistor T2 to receive the data voltage Dm. The second electrode (D1; the electrode on the output side) is set to output current to the OLED, and the second electrode D1 is connected to the anode electrode of the OLED via the sixth transistor T6. A gate electrode G1 is connected to one electrode (second storage electrode E2) of the storage capacitor Cst. The voltage at the gate electrode G1 changes according to the voltage charged in the storage capacitor Cst, and the driving current Id output by the driving transistor T1 changes accordingly.

[0145] The second transistor T2 supplies a data voltage Dm to the pixel PX. The gate electrode G2 is connected to the scan line 151, and the first electrode S2 is connected to the data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the first electrode S1 of the driving transistor T1.

[0146] The third transistor T3 allows a compensation voltage (Dm + Vth voltage) that can be changed when the data voltage Dm passes through the driving transistor T1 to be transmitted to the second storage electrode E2 of the storage capacitor Cst. The third transistor T3 includes a third-1 transistor T3-1 and a third-2 transistor T3-2 connected in series. The gate electrodes G3-1 and G3-2 of the transistors T3-1 and T3-2 are connected to the scan line 151. The first electrode S3-2 of the third-2 transistor T3-2 is connected to the second electrode D1 of the driving transistor T1. The second electrode D3-1 of the third-1 transistor T3-1 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. In addition, the first electrode S3-1 of the third-1 transistor T3-1 is connected to the second electrode D3-2 of the third-2 transistor T3-2 at the third node N3.

[0147] When the third transistor T3 is a single transistor, the first electrode S3-2 of the third-2 transistor T3-2 can be the first electrode of the third transistor T3, and the second electrode D3-1 of the third-1 transistor T3-1 can be the second electrode of the third transistor T3. The third transistor T3 is turned on by the scan signal Sn provided through the scan line 151 to connect the gate electrode G1 and the second electrode D1 of the driving transistor T1. The third transistor T3 connects the second electrode D1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst.

[0148] The fourth transistor T4 initializes the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 is connected to the previous-stage scan line 152, and the first electrode S4 is connected to the initialization voltage line 127. The second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode of the third transistor T3. The fourth transistor T4 has a structure including two transistors connected in series. The fourth transistor T4 transfers the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst according to the previous-stage scan signal Sn-1 provided through the previous-stage scan line 152. Accordingly, the gate voltage at the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint may have a low voltage value and may turn on the driving transistor T1.

[0149] The fifth transistor T5 transfers the driving voltage ELVDD to the driving transistor T1. The gate electrode G5 is connected to the emission control line 157, and the first electrode S5 is connected to the first voltage line 155. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1.

[0150] The sixth transistor T6 transfers the driving current Id output from the driving transistor T1 to the OLED. The gate electrode G6 is connected to the emission control line 157, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode electrode of the OLED.

[0151] The fifth transistor T5 and the sixth transistor T6 are turned on according to the emission control signal EM provided through the emission control line 157. When the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs the driving current Id according to the voltage at the gate electrode G1 of the driving transistor T1 (i.e., the voltage at the second storage electrode E2 of the storage capacitor Cst). The output driving current Id is transferred to the OLED through the sixth transistor T6. When the current Ioled flows to the OLED, the OLED emits light.

[0152] The seventh transistor T7 initializes the anode electrode of the OLED. The gate electrode G7 is connected to the bypass control line 159, the first electrode S7 is connected to the anode electrode of the OLED, and the second electrode D7 is connected to the initialization voltage line 127. The bypass control line 159 may be connected to the previous scan line 152, and the bypass signal GB is applied using the same timing as the previous scan signal Sn-1. The bypass control line 159 may not be connected to the previous scan line 152 and may transmit a signal different from the previous scan signal Sn-1. When the seventh transistor T7 is turned on according to the bypass signal GB, the bypass current Ibp flows to the first electrode S7 of the seventh transistor T7, and the initialization voltage Vint is applied to the anode electrode of the OLED to be initialized.

[0153] The first storage electrode E1 of the storage capacitor Cst is connected to the first voltage line 155. The second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode of the third transistor T3, and the second electrode D4 of the fourth transistor T4. The second storage electrode E2 can determine the voltage at the gate electrode G1 of the driving transistor T1, can receive the data voltage Dm through the second electrode of the third transistor T3, and can receive the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0154] In addition, the anode electrode of the OLED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7. The cathode electrode is connected to the second voltage line 156 for transmitting the low driving voltage ELVSS.

[0155] In the reference Figure 12 described exemplary embodiment, the pixel circuit includes seven transistors (T1 to T7) and one capacitor Cst, but this exemplary embodiment is not limited thereto, and the number of transistors, the number of capacitors, and their combinations can be modified in various ways.

[0156] Reference Figure 13 , the OLED display according to the exemplary embodiment includes an overlapping metal layer 112, semiconductor layers 140 and 141, first gate electrode layers 121, 122, and 123, second gate electrode layers 125 and 126, first data electrode layers 165, 166, 147, and 176, second data electrode layers 167 and 155, an anode electrode 191, an organic emission layer 370, and a cathode electrode 270 formed on the substrate 100. If one or more of these layers are not connected through the opening, they may be insulated from each other using an insulating layer.

[0157] The substrate 100 may be formed of a flexible substrate 100 including plastic and polyimide (PI).

[0158] The blocking layer 110 is formed on the substrate 100. The blocking layer 110 may be formed of an inorganic material.

[0159] The overlapping metal layer 112 is formed on the blocking layer 110. The overlapping metal layer 112 is formed in the display area DA including pixels and is formed on the same layer as the metal layer 111 formed in the non-display area NA. In an exemplary embodiment, the overlapping metal layer 112 may not be formed in the display area DA, while the metal layer 111 may be formed in the non-display area NA.

[0160] The buffer layer 120 is formed to cover the overlapping metal layer 112 and the blocking layer 110.

[0161] The semiconductor layers 140 and 141 may be provided on the buffer layer 120. The semiconductor layers 140 and 141 may include polysilicon, oxide semiconductor materials, and amorphous silicon. For example, the semiconductor layers 140 and 141 may include oxides of metal elements such as indium (In), zinc (Zn), gallium (Ga), tin (Sn), or germanium (Ge) and materials selected from combinations thereof.

[0162] The first gate insulating layer 131 is formed to cover the semiconductor layers 140 and 141 and the substrate 100.

[0163] The first gate electrode layers 121, 122, and 123 are formed on the first gate insulating layer 131 and include a first gate electrode 121, a second gate electrode 122, and a third gate electrode 123.

[0164] The second gate insulating layer 132 is formed to cover the first gate electrode layers 121, 122, and 123 and the first gate insulating layer 131.

[0165] The second gate electrode layers 125 and 126 are formed on the second gate insulating layer 132 and include an overlapping gate electrode 125 and a storage electrode 126.

[0166] The third gate insulating layer 133 is formed to cover the second gate electrode layers 125 and 126 and the second gate insulating layer 132.

[0167] The first data electrode layers 165, 166, 147, and 176 are formed on the third gate insulating layer 133 and include a source electrode 165, a drain electrode 166, a gate connector 147, and a driving voltage connector 176.

[0168] The source electrode 165 and the drain electrode 166 are connected to the semiconductor layer 140 and form a thin film transistor with the first gate electrode 121.

[0169] The gate connector 147 is provided to overlap with the third gate electrode 123 and can be electrically connected through openings formed in the second gate insulating layer 132 and the third gate insulating layer 133.

[0170] The driving voltage connector 176 partially overlaps with the storage electrode 126 and can be electrically connected to the storage electrode 126 through an opening formed in the third gate insulating layer 133.

[0171] The fourth gate insulating layer 134 is formed to cover the first data electrode layers 165, 166, 147, and 176 and the third gate insulating layer 133. In an exemplary embodiment, the first gate insulating layer 131, the second gate insulating layer 132, the third gate insulating layer 133, and the fourth gate insulating layer 134 may be collectively referred to as the gate insulating layer 130.

[0172] The interlayer insulating layer 160 is formed on the fourth gate insulating layer 134 and may be formed of an organic insulating layer.

[0173] The second data electrode layers 167 and 155 are formed on the interlayer insulating layer 160 and include an anode electrode connector 167 and a first voltage line 155.

[0174] The anode electrode connector 167 supplies a driving current Id to the anode electrode 191. The anode electrode connector 167 partially overlaps with the source electrode 165 of the thin film transistor and is electrically connected to the source electrode 165 through an opening formed in the interlayer insulating layer 160.

[0175] The first voltage line 155 is a wiring for applying a driving voltage ELVDD and may partially overlap with the driving voltage connector 176. The first voltage line 155 is electrically connected to the driving voltage connector 176 through an opening formed in the interlayer insulating layer 160.

[0176] The passivation layer 180 is formed to cover the second data electrode layers 167 and 155 and the interlayer insulating layer 160. The passivation layer 180 may be formed of an organic insulating layer.

[0177] The anode electrode 191 is formed on the passivation layer 180 and may be formed of a transparent conductive material or a reflective metal. The anode electrode 191 can be electrically connected to the anode electrode connector 167 through an opening formed in the passivation layer 180 and may be a pixel electrode of the OLED.

[0178] The upper organic layer 350 is formed to cover the anode electrode 191 and the passivation layer 180. The upper organic layer 350 may be formed of an organic material.

[0179] The organic emission layer 370 is formed in the opening portion of the upper organic layer 350. The organic emission layer 370 may include at least one of an emission layer, a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0180] The cathode electrode 270 is formed on the upper organic layer 350 and the organic emission layer 370. The cathode electrode 270 may be formed of a transparent conductive material or a reflective metal. The cathode electrode 270 may be a common electrode of the OLED. The anode electrode 191, the organic emission layer 370, and the cathode electrode 270 configure the OLED.

[0181] Although the present invention has been described in connection with presently considered practical exemplary embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. An organic light emitting diode display, comprising: a substrate including a display area and a non-display area; a metal layer disposed on the non-display area of the substrate; a gate insulating layer covering the metal layer and the substrate, wherein the gate insulating layer is made of an inorganic material; a first voltage line disposed on the gate insulating layer and receiving a driving voltage; a second voltage line disposed on the gate insulating layer and receiving a low driving voltage, wherein the low driving voltage is lower than the driving voltage; an organic insulating layer covering the first voltage line and the second voltage line; and a cathode electrode disposed on the organic insulating layer, wherein the second voltage line and the cathode electrode are electrically connected to each other through an opening formed in the organic insulating layer, and the first voltage line or the second voltage line is electrically connected to the metal layer through an opening formed in the gate insulating layer.

2. The organic light emitting diode display according to claim 1, wherein: the second voltage line is disposed to surround four sides of the display area, and the first voltage line is disposed to partially overlap with the second voltage line in the non-display area.

3. The organic light emitting diode display according to claim 2, wherein: the organic insulating layer includes: an interlayer insulating layer disposed to cover the first voltage line disposed on the gate insulating layer; a passivation layer disposed to cover the second voltage line disposed on the interlayer insulating layer; and an upper organic layer disposed on the passivation layer.

4. The organic light emitting diode display according to claim 3, further comprising: a first voltage application connector disposed on the gate insulating layer; and a first voltage application wiring disposed on the interlayer insulating layer, wherein the first voltage application wiring is electrically connected to the first voltage application connector through an opening formed in the interlayer insulating layer, the first voltage application connector is electrically connected to the metal layer through an opening formed in the gate insulating layer, and the first voltage line is electrically connected to the metal layer through an opening formed in the gate insulating layer.

5. The organic light emitting diode display according to claim 3, further comprising: a cathode electrode connector disposed on the passivation layer; and a second voltage line auxiliary connector disposed on the gate insulating layer, wherein the cathode electrode connector is electrically connected to the cathode electrode through an opening formed in the upper organic layer, the cathode electrode is disposed on an organic emission layer, and the second voltage line auxiliary connector is electrically connected to the second voltage line through an opening formed in the interlayer insulating layer.

6. The organic light emitting diode display according to claim 1, wherein: the second voltage line is disposed to surround at least three sides of the display area.

7. The organic light emitting diode display according to claim 6, wherein: the organic insulating layer includes: an interlayer insulating layer disposed to cover the gate insulating layer; a passivation layer disposed to cover the second voltage line disposed on the interlayer insulating layer; and an upper organic layer disposed on the passivation layer.

8. The organic light emitting diode display according to claim 7, further comprising: A first voltage line auxiliary connector disposed on the gate insulating layer, wherein the first voltage line is disposed on the interlayer insulating layer and is electrically connected to the first voltage line auxiliary connector through an opening formed in the interlayer insulating layer.

9. The organic light emitting diode display according to claim 7, further comprising: A second voltage application connector disposed on the gate insulating layer, A second voltage application wiring disposed on the interlayer insulating layer, wherein the second voltage application connector is electrically connected to the metal layer through an opening formed in the gate insulating layer, and the second voltage application wiring is electrically connected to the second voltage application connector through an opening formed in the interlayer insulating layer.

10. An organic light emitting diode display, comprising: A substrate including a display area and a non-display area; A gate insulating layer disposed on the substrate; A first voltage line disposed on the gate insulating layer and receiving a driving voltage; An inorganic insulating layer covering the first voltage line and the gate insulating layer; An interlayer insulating layer disposed on the inorganic insulating layer; A second voltage line disposed on the interlayer insulating layer and receiving a low driving voltage, wherein the low driving voltage is lower than the driving voltage; An organic insulating layer disposed on the second voltage line; And A cathode electrode disposed on the organic insulating layer, wherein the second voltage line and the cathode electrode are electrically connected to each other through an opening formed in the organic insulating layer, In a plan view, the first voltage line and the second voltage line are disposed to partially overlap each other at a lower portion of the non-display area, and the second voltage line is not located in the display area but only in the non-display area.

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