An overcurrent protection circuit for a common-anode LED display row driver chip

Abstract

The present invention discloses an overcurrent protection circuit for a common-anode LED display row driving chip, comprising: a power transistor serving as the row driving chip; an overcurrent detection circuit, which is signal-connected to the power transistor and is used for detecting the drain voltage of the power transistor; and a combinational logic circuit, which is signal-connected to the output end of the overcurrent detection circuit and is used for outputting a control signal to control the switching of the power transistor; wherein, the overcurrent detection circuit judges whether the drain voltage is lower than a set reference voltage by detecting the drain voltage of the power transistor and comparing it with the set reference voltage, and outputs an enabling signal to the combinational logic circuit according to the comparison result, so that the combinational logic circuit outputs a control signal to control the switching of the power transistor. The present invention detects and judges whether the current at the output end of the power transistor is too large, outputs an enabling signal to drive the combinational logic circuit to control the switching of the power transistor, protects the chip connected to the output end of the power transistor, has an accurate detection effect, and protects the chip from being damaged.

Description

Technical Field

[0001] The present invention relates to the technical field of LED display driving, and particularly to an over-current protection circuit for a common-anode LED display row driving chip. Background Art

[0002] In order to meet the requirements of a relatively large current at the application end, the size of the power transistor in the LED row driving chip is usually designed to be relatively large. When an abnormality occurs at the application end (for example, a short circuit to the ground appears at the output end of the power transistor), it will cause the current of the power transistor to increase sharply. The excessive current will increase the heat generation, and further cause the chip to be burned out. To avoid damage to the chip due to excessive current in the power transistor, it is necessary to provide a protection circuit to solve the above technical problems. Summary of the Invention

[0003] The purpose of the present invention is to provide an over-current protection circuit for a common-anode LED display row driving chip. By detecting the voltage value at the output end of the power transistor, it is judged whether the current flowing through the power transistor is excessive, and a corresponding enable signal is output to the combinational logic circuit. The combinational logic circuit controls the switch of the power transistor, thereby protecting the chip connected to the output end of the power transistor and preventing the chip from being damaged.

[0004] To solve the above technical problems, the technical solution provided by the present invention is: an over-current protection circuit for a common-anode LED display row driving chip, including: a power transistor PM0 serving as a row driving chip; an over-current detection circuit, which is signal-connected to the power transistor and is used to detect the drain voltage VOUT of the power transistor PM0; and a combinational logic circuit, which is signal-connected to the output end of the over-current detection circuit and is used to output a control signal VCTRL to control the switch of the power transistor PM0; wherein, the over-current detection circuit judges whether the drain voltage VOUT is lower than a set reference voltage VR by detecting the drain voltage VOUT of the power transistor PM0 and comparing it with the reference voltage VR, and the over-current detection circuit outputs an enable signal EN to the combinational logic circuit according to the comparison result, so that the combinational logic circuit outputs a control signal VCTRL to control the switch of the power transistor PM0.

[0005] The present invention adopts the above technical solution. The over-current detection circuit is used to detect the drain voltage value of the power transistor PM0 and compare it with the reference voltage VR. When the drain voltage VOUT is lower than the reference voltage VR, the enable signal EN output by the over-current detection circuit is inverted and becomes an invalid state. After being processed by the combinational logic circuit, the output control signal VCTRL controls the power transistor PM0 to turn off, protecting the chip from being damaged due to excessive current flowing through it.

[0006] Further, an output enable signal OE is respectively input into the combinational logic circuit and the overcurrent detection circuit. The output enable signal OE and the enable signal EN are commonly input into the combinational logic circuit. When both the output enable signal OE and the enable signal EN are valid, the combinational logic circuit outputs a control signal VCTRL at a low level, and at this time, the power transistor PM0 is normally turned on.

[0007] Further, the combinational logic circuit includes an AND gate circuit A6 and an inverter A5. The output enable signal OE and the enable signal EN output from the overcurrent detection circuit are input into the input terminals of the AND gate circuit A6. The AND gate circuit A6 is connected to the inverter A5 in series. The inverter A5 outputs the control signal VCTRL to the gate of the power transistor PM0. The AND gate circuit A6 inputs both the output enable signal OE and the enable signal EN. When both are valid, the AND gate circuit A6 outputs a signal to the inverter A5, and after processing, the output control signal VCTRL controls the switching of the power transistor PM0.

[0008] Furthermore, the overcurrent detection circuit includes a flip-flop DFF, inverters A3, A4, inverters A1, A2, and a current mirror. The output enable signal OE is input into the flip-flop DFF after being processed by the inverters A1 and A2. The input current I0 is input into the current mirror and is input into the flip-flop DFF after being processed by the inverters A3 and A4. The flip-flop DFF outputs the enable signal EN to the combinational logic circuit.

[0009] Still further, the current mirror is composed of a symmetric No. 0 NMOS transistor and a first NMOS transistor connected in series. The current I0 is input into its input stage, and the output stage of the current mirror is connected to the inverter A3 in series.

[0010] Further, a second NMOS transistor is connected in series between the inverters A1 and A2. The second NMOS transistor is connected in parallel with the current mirror, and its drain is connected to the inverter A3.

[0011] Furthermore, the drain of the power transistor PM0 is connected to the gate of the second PMOS transistor. The control signal VCTRL output by the combinational logic circuit is input into the gates of the power transistor PM0 and the first PMOS transistor. The first PMOS transistor is connected to the second PMOS transistor in series, and the second PMOS transistor is connected to the inverter A3. The first PMOS transistor inputs a DC voltage VDD.

[0012] Further, a third NMOS transistor is connected in parallel with the second NMOS transistor. The sources of the zero - numbered NMOS transistor, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected to the common ground terminal VSS of the circuit. When the enable signal OE is at a low level, the control signal VCTRL is at a high potential, and PM0 is in the off state. At this time, the first PMOS transistor is turned off, and the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are in the on state, pulling down the VC potential to VSS.

[0013] The beneficial effects achieved by the present invention are as follows: By detecting the drain - terminal voltage of the power transistor and comparing it with a reference voltage, it is determined whether the drain - terminal voltage is lower than the reference voltage value. According to the characteristics of the power transistor, it is judged whether the current flowing through the power transistor is abnormal. When the current flowing through the power transistor is too large, the over - current detection circuit outputs a corresponding enable signal to the combinational logic circuit. The combinational logic circuit outputs a control signal according to this enable signal and the enable signal OE to control the power transistor to turn off, which can effectively prevent the adverse effects caused by excessive current in the power transistor of the line - driving chip and effectively protect the normal operation of the line - driving chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of the system structure of an embodiment of the present invention;

[0015] Figure 2 is a schematic diagram of the circuit structure of an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The present invention will be further described below in conjunction with the drawings and the detailed description.

[0017] Refer to Figure 1 As shown, an over - current protection circuit for a common - anode LED display line - driving chip includes:

[0018] A power transistor PM0 serving as the line - driving chip;

[0019] An over - current detection circuit 10, which is signal - connected to the power transistor and is used to detect the drain - terminal voltage VOUT of the power transistor PM0; and

[0020] A combinational logic circuit 20, which is signal - connected to the output terminal of the over - current detection circuit 10 and is used to output a control signal VCTRL to control the switching of the power transistor PM0;

[0021] Among them, the over - current detection circuit 10 detects the drain - terminal voltage VOUT of the power transistor PM0 and compares it with a set reference voltage VR, determines whether the drain - terminal voltage VOUT is lower than the reference voltage VR, and the over - current detection circuit 10 outputs an enable signal EN to the combinational logic circuit 20 according to the comparison result, so that the combinational logic circuit 20 outputs a control signal VCTRL to control the switching of the power transistor PM0.

[0022] In this embodiment, the combinational logic circuit 20 and the overcurrent detection circuit 10 are respectively input with an active enable signal OE.

[0023] In the specific implementation process, when the control signal VCTRL is at a low potential, the power transistor PM0 is turned on, and the overcurrent detection circuit 10 continuously detects the drain voltage VOUT of the power transistor PM0. The greater the current flowing through the power transistor PM0, the lower the voltage of its drain voltage VOUT. The active enable signal OE and the enable signal EN output by the overcurrent detection circuit 10 are simultaneously input into the combinational logic circuit 20. When the enable signal EN and the active enable signal OE are both in an active state, the control signal VCTRL is at a low level, and the power transistor PM0 is normally turned on. When the active enable signal OE is invalid, the enable signal EN output by the overcurrent detection circuit 10 is reset to an active state.

[0024] When the active enable signal OE is invalid, the output signal EN of the overcurrent detection circuit 10 is reset to an active state, the control signal VCTRL is at a high potential, and the power transistor PM0 is in an off state.

[0025] When the active enable signal OE changes from invalid to valid, the enable signal EN remains in an active state unchanged, the control signal VCTRL is at a low potential, the power transistor PM0 changes to an on state, and the overcurrent detection circuit 10 starts to detect the drain voltage VOUT.

[0026] When the current flowing through the power transistor PM0 is normal, the potential of the drain voltage VOUT is close to the DC voltage VDD of the circuit operation, the output enable signal EN of the overcurrent detection circuit 10 remains in an active state, the control signal VCTRL remains at a low potential unchanged, and the power transistor PM0 remains in an on state unchanged;

[0027] When the current flowing through the power transistor PM0 is too large, due to the limited current capacity of the power transistor PM0, its drain voltage VOUT drops significantly. When the drain voltage VOUT is lower than the reference voltage VR, the enable signal EN output by the overcurrent detection circuit 10 becomes an invalid state. After receiving the invalid enable signal EN, the combinational logic circuit 20 makes the control signal VCTRL become a high level, controls the power transistor PM0 to turn off, thereby preventing too large current from flowing through the power transistor and the driving chip, and effectively protecting the driving chip. At this time, the driving chip does not work, and when the output active enable signal OE becomes invalid, the output enable signal EN of the overcurrent detection circuit 10 is reset to an active state.

[0028] It should be understood that in the present invention, the active enable signal OE and the enable signal EN are in an active state when the input value is "1", and the active enable signal OE and the enable signal EN are in an invalid state when the input value is "0".

[0029] Further refer toFigure 2 As shown, the combinational logic circuit 20 includes an AND gate circuit A6 and an inverter A5. The active enable signal OE and the enable signal EN output by the overcurrent detection circuit are input to the input terminals of the AND gate circuit A6. The AND gate circuit A6 is connected to the inverter A5 in series, and the inverter A5 outputs a control signal VCTRL to the gate of the power transistor PM0.

[0030] The overcurrent detection circuit 10 includes a flip-flop DFF, inverters A3, A4, inverters A1, A2, and a current mirror. The active enable signal OE is input to the flip-flop DFF after being processed by the inverters A1 and A2. The input current I0 is input to the current mirror and is input to the flip-flop DFF after being processed by the inverters A3 and A4. The flip-flop DFF outputs an enable signal EN to the combinational logic circuit.

[0031] The current mirror is composed of a symmetric zero NMOS transistor and a first NMOS transistor connected in series. The current I0 is input to its input stage, and the output stage of the current mirror is connected to the inverter A3 in series.

[0032] A second NMOS transistor NM2 is connected in series between the inverters A1 and A2. The second NMOS transistor NM2 is connected in parallel with the current mirror, and its drain is connected to the inverter A3 in series. The drain of the power transistor PM0 is connected to the gate of the second PMOS transistor PM2. The control signal VCTRL output by the combinational logic circuit 20 is input to the gates of the power transistor PM0 and the first PMOS transistor PM1. The first PMOS transistor PM1 is connected to the second PMOS transistor PM2 in series. The second PMOS transistor PM2 is connected to the inverter A3. The first PMOS transistor PM1 is input with a DC voltage VDD.

[0033] The second NMOS transistor NM2 is connected in parallel with a third NMOS transistor NM3. The sources of the zero NMOS transistor NM0, the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 are connected to the common ground terminal VSS of the circuit.

[0034] In the specific implementation process of the present invention, when the active enable signal OE is at a low level, the enable signal EN output by the overcurrent detection circuit 10 is reset to a high level, the control signal VCTRL is at a high potential, the power transistor PM0 is in an off state, and the overcurrent detection circuit 10 does not detect the input of the leakage terminal voltage VOUT. At this time, the first PMOS transistor PM1 is turned off, and the first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 are all in an on state, pulling down the VC potential to the common ground terminal VSS of the circuit.

[0035] When the enable signal OE changes from low level to high level, the enable signal EN output by the overcurrent detection circuit 10 remains high level, the control signal VCTRL of the combinational logic circuit 20 is at low potential, the power transistor PM0 is in an on state, and the drain voltage VOUT of the overcurrent detection circuit 10 is input. At this time, the second NMOS transistor NM2 and the third NMOS transistor NM3 are turned off, the first PMOS transistor PM1 is turned on, and the first NMOS transistor NM1 pulls down the VC potential with a mirror current of a current I0.

[0036] When the current flowing through the power transistor PM0 is normal, the potential of the drain voltage VOUT is close to the DC voltage VDD of the circuit operation, the second PMOS transistor PM2 is in an off state, the potential VC is pulled down to the common ground voltage VSS by the first NMOS transistor NM1, and the input terminal CLK connected to the inverter A4 of the flip-flop DFF is at low potential. The enable signal EN output by the overcurrent detection circuit 10 remains high level. At this time, the control signal VCTRL remains at low potential, the power transistor PM0 remains in an on state, and the circuit operates normally.

[0037] When the current flowing through the power transistor PM0 is too large, due to the limited current capacity of the power transistor PM0, the voltage of its drain voltage VOUT drops significantly. When the drain voltage VOUT is lower than the reference voltage VR, the second PMOS transistor PM2 is turned on. The current capacity of the second PMOS transistor is greater than that of the first NMOS transistor, and it pulls up the VC potential to VDD. At this time, there is a rising edge from low potential to high potential at the input terminal CLK of the flip-flop DFF, and the enable signal EN output by the overcurrent detection circuit 10 becomes low level. After being processed by the combinational logic circuit 20, the voltage of the control signal VCTRL becomes high level, controlling the power transistor PM0 to turn off, thereby preventing too large current from flowing through the power transistor and the driver chip, and effectively protecting the driver chip.

[0038] When the enable signal OE becomes low level, the enable signal EN can be reset to high level.

[0039] In summary, the present invention has been made into an actual sample and tested many times as described in the specification and the illustrated content. From the test results of the use, it can be proved that the present invention can achieve its intended purpose, and its practical value is undoubtedly. The above embodiments are only used to conveniently illustrate the present invention, and do not impose any form of limitation on the present invention. Any person with ordinary knowledge in the technical field can, without departing from the technical features of the present invention, make local changes or modified equivalent embodiments by using the technical content disclosed in the present invention, and without departing from the technical feature content of the present invention, still fall within the scope of the technical features of the present invention.

Claims

1. An overcurrent protection circuit for a common anode LED display row driver chip, characterized in that: include: PM0, the power transistor of the row driver chip; An overcurrent detection circuit (10), whose signal is connected to the power tube and is used to detect the drain voltage VOUT of the power tube PM0; and a combination logic circuit (20), which is connected to the output terminal signal of the overcurrent detection circuit (10) and is used to output a control signal VCTRL to control the switch of the power tube PM0; The overcurrent detection circuit (10) detects the drain voltage VOUT of the power tube PM0 and compares it with the set reference voltage VR to determine whether the drain voltage VOUT is lower than the reference voltage VR. (10) Outputting an enable signal EN to the combinational logic circuit (20) according to the comparison result, so that the combinational logic circuit (20) Output control signal VCTRL to control the switch of power tube PM0; The combinational logic circuit (20) and the overcurrent detection circuit (10) respectively input an active enable signal OE; The overcurrent detection circuit (10) includes a trigger DFF, inverters A3, A4, inverters A1, A2 and a current mirror, wherein an enable signal OE is input to the RESET terminal of the trigger DFF after being processed by inverters A1 and A2, a current I0 is input to the current mirror and is input to the CLK terminal of the trigger DFF after being processed by inverters A3 and A4, wherein the trigger DFF outputs an enable signal EN to the combinational logic circuit (20); The drain line of the power tube PM0 is connected to the gate of the second PMOS tube, the control signal VCTRL output by the combinational logic circuit (20) is input to the gate of the power tube PM0 and the gate of the first PMOS tube, the drain of the first PMOS tube is connected to the source of the second PMOS tube, the drain of the second PMOS tube is connected to the input end of the inverter A3, and the source of the first PMOS tube is input with a DC voltage VDD.

2. The overcurrent protection circuit according to claim 1, wherein: The combinational logic circuit (20) includes an AND gate circuit A6 and an inverter A5. The row enable signal OE and the enable signal EN output by the overcurrent detection circuit (10) are input to the input end of the AND gate circuit A6. The AND gate circuit A6 is connected to the inverter A5 line. The inverter A5 outputs a control signal VCTRL to the gate of the power tube PM0.

3. The overcurrent protection circuit according to claim 1, wherein: The current mirror is composed of a symmetrical zero NMOS tube and a first NMOS tube connected in circuit, the current I0 is input into its input stage, and the output stage circuit of the current mirror is connected to the inverter A3.

4. The overcurrent protection circuit according to claim 1, wherein: Connect the first line between inverters A1 and A2. The gate of the second NMOS tube is connected in parallel with the current mirror, and its drain line is connected to the inverter A3.

5. The overcurrent protection circuit according to claim 4, characterized in that: The second NMOS tube is connected in parallel with the third NMOS tube, and the sources of the zero NMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube are connected to the common ground terminal VSS of the circuit.

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