Semiconductor devices

Abstract

The present invention provides a semiconductor device, which comprises: an upper conductive plate, an intermediate conductive plate and a lower conductive plate arranged in a stacked configuration; a first semiconductor element, which is located between the upper conductive plate and the intermediate conductive plate and is electrically connected to the upper conductive plate and the intermediate conductive plate, respectively; and a second semiconductor element, which is located between the intermediate conductive plate and the lower conductive plate and is electrically connected to the intermediate conductive plate and the lower conductive plate, respectively. One of the area of ​​the upper conductive plate and the area of ​​the lower conductive plate is smaller than the area of ​​the intermediate conductive plate, and the other of the area of ​​the upper conductive plate and the area of ​​the lower conductive plate is larger than the area of ​​the intermediate conductive plate.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device. Background Art

[0002] Japanese Patent Application Publication No. 2016-36047 discloses a semiconductor device, which comprises: an upper conductive plate, an intermediate conductive plate, and a lower conductive plate arranged in a stacked manner; a first semiconductor element located between the upper conductive plate and the intermediate conductive plate; a second semiconductor element located between the intermediate conductive plate and the lower conductive plate; and a package that packages the first semiconductor element and the second semiconductor element and integrally holds the upper conductive plate, the intermediate conductive plate, and the lower conductive plate.

[0003] When manufacturing the semiconductor device, it is necessary to join three conductive plates with the semiconductor element interposed therebetween. At this time, in order to manufacture the semiconductor device with high precision, it is necessary to use, for example, a fixture to correctly position the three conductive plates. However, considering that they need to be removed later, it is difficult to hold the three conductive plates in a stacked configuration with a single fixture. Therefore, it is possible to consider using a fixture that can be divided into two or more, but the use of multiple fixtures may result in reduced dimensional accuracy compared to a single fixture. Summary of the invention

[0004] This specification provides a structure in which a semiconductor device having three or more conductive plates stacked on top of each other can be manufactured with high precision.

[0005] The technology disclosed in this specification is embodied as a semiconductor device. The semiconductor device has: an upper conductive plate, an intermediate conductive plate, and a lower conductive plate in a stacked configuration; a first semiconductor element, which is located between the upper conductive plate and the intermediate conductive plate and is electrically connected to the upper conductive plate and the intermediate conductive plate, respectively; and a second semiconductor element, which is located between the intermediate conductive plate and the lower conductive plate and is electrically connected to the intermediate conductive plate and the lower conductive plate, respectively. One of the area of ​​the upper conductive plate and the area of ​​the lower conductive plate is smaller than the area of ​​the intermediate conductive plate. The other of the area of ​​the upper conductive plate and the area of ​​the lower conductive plate is larger than the area of ​​the intermediate conductive plate.

[0006] In the semiconductor device described above, the areas of the three conductive plates gradually increase (or decrease) along the stacking direction. According to this structure, when manufacturing the semiconductor device, the three conductive plates stacked in the same direction can be held by a single fixture. Since a single fixture is used, the semiconductor device can be manufactured with high precision.

[0007] Here, the area of ​​the conductive plate in this specification (i.e., the area of ​​the upper conductive plate, the middle conductive plate, and the lower conductive plate) refers to the area of ​​the conductive plate when viewed from above. In other words, the area of ​​the conductive plate refers to the projected area of ​​the conductive plate when projected onto a plane parallel to the conductive plate.

[0008] The technology disclosed in this specification is also embodied as the following semiconductor device. The semiconductor device has: an upper conductive plate, an intermediate conductive plate, and a lower conductive plate in a stacked configuration; a first semiconductor element, which is located between the upper conductive plate and the intermediate conductive plate and is electrically connected to the upper conductive plate and the intermediate conductive plate, respectively; and a second semiconductor element, which is located between the intermediate conductive plate and the lower conductive plate and is electrically connected to the intermediate conductive plate and the lower conductive plate, respectively. In the semiconductor device, when the upper conductive plate, the intermediate conductive plate, and the lower conductive plate are projected onto a plane parallel to them, at least a first region, a second region, and a third region are divided on the plane. The first region is a region where the upper conductive plate, the intermediate conductive plate, and the lower conductive plate are projected. The second region is a region where only one of the upper conductive plate and the lower conductive plate and the intermediate conductive plate are projected. In addition, the third region is a region where only the other of the upper conductive plate and the lower conductive plate is projected.

[0009] In the above-mentioned semiconductor device, a single jig may be used to hold the three stacked conductive plates from the same direction when manufacturing the semiconductor device. Since a single jig is used, the semiconductor device can be manufactured with high precision. In this case, the areas of the three conductive plates may be the same or different from each other. The area of ​​each conductive plate may be appropriately determined in consideration of, for example, the expected temperature distribution in the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The appearance of the semiconductor device 10 according to the embodiment is shown.

[0011] Figure 2 Show Figure 1 Cross-sectional view at line II-II in FIG.

[0012] Figure 3 Show Figure 1 Cross-sectional view at line III-III in FIG.

[0013] Figure 4 The circuit structure of the semiconductor device 10 according to the embodiment is shown.

[0014] Figure 5 The projection areas P16, P20, and P18 of the three conductive plates 16, 20, and 18 projected onto a plane parallel to them are shown. The projection area P16 in the figure represents the projection area of ​​the upper conductive plate 16, the projection area P20 represents the projection area of ​​the middle conductive plate 20, and the projection area P18 represents the projection area of ​​the lower conductive plate 18.

[0015] Figure 6The case where three conductive plates 16 , 20 , and 18 stacked with semiconductor elements 12 and 14 interposed therebetween are held by a single jig 90 is shown.

[0016] Figure 7 This is a diagram showing a state where the package 30 is molded using a molding die 92 .

[0017] Figure 8 is a cross-sectional view schematically showing the structure of a semiconductor device 10A according to a modified example, corresponding to Figure 2 Cross-sectional view shown.

[0018] Fig. 9 is a cross-sectional view schematically showing the structure of a semiconductor device 10B according to a modified example, corresponding to Figure 2 Cross-sectional view shown.

[0019] Fig.10 a-10c shows Fig. 9 The shapes of the three conductive plates 16, 18, and 20 used in the semiconductor device 10B shown. Fig.10 a is a diagram showing the upper conductive plate 16 from above. Fig.10 b is a top view of the intermediate conductive plate 20, Fig.10 c is a diagram showing the lower conductive plate 18 as seen from above.

[0020] Fig.11 against Fig. 9 The semiconductor device 10B shown in the figure shows projection areas P16, P20, and P18 of the three conductive plates 16, 20, and 18 projected onto a plane parallel to them. The projection area P16 in the figure represents the projection area of ​​the upper conductive plate 16, the projection area P20 represents the projection area of ​​the middle conductive plate 20, and the projection area P18 represents the projection area of ​​the lower conductive plate 18.

[0021] Fig.12 against Fig. 9 The semiconductor device 10B shown in the figure shows a case where three conductive plates 16 , 20 , and 18 stacked with semiconductor elements 12 and 14 interposed therebetween are held by a single jig 90 .

[0022] Fig.13 is a cross-sectional view schematically showing the structure of a semiconductor device 10C according to a modified example, corresponding to Figure 2 Cross-sectional view shown.

[0023] Fig.14 The appearance of a semiconductor device 100 according to Reference Example 1 of the related art is shown.

[0024] Fig.15 Show Fig.14 Cross-sectional view at line XV-XV in FIG.

[0025] Fig.16 Show Fig.14 Cross-sectional view at line XVI-XVI in FIG.

[0026] Fig.17 A circuit configuration of a semiconductor device 100 according to Reference Example 1 is shown.

[0027] Fig.18 The results of calculating the characteristics of the semiconductor device 100 of Reference Example 1 by computer simulation are shown.

[0028] Fig.19 1 is a cross-sectional view schematically showing the structure of a semiconductor device 100A according to a modification example of Reference Example 1.

[0029] Fig. 20 1 is a cross-sectional view schematically showing the structure of a semiconductor device 100B according to another modification example of Reference Example 1.

[0030] Fig.21 1 is a cross-sectional view schematically showing the structure of a semiconductor device 100C according to a modified example of Reference Example 1.

[0031] Fig. 22 The appearance of a semiconductor device 200 according to Reference Example 2 of the related art is shown.

[0032] Fig.23 Show Fig. 22 Cross-sectional view at line XXIII-XXIII in FIG.

[0033] Fig.24 Show Fig. 22 Cross-sectional view at line XXIV-XXIV in FIG.

[0034] Fig.25 A circuit structure of a semiconductor device 200 according to Reference Example 2 is shown.

[0035] Fig.26 1 is a cross-sectional view schematically showing the structure of a semiconductor device 200A according to a modification example of Reference Example 2.

[0036] Fig. 27 1 is a cross-sectional view schematically showing the structure of a semiconductor device 200B according to a modification example of Reference Example 2.

[0037] Fig.28 1 is a cross-sectional view schematically showing the structure of a semiconductor device 200C according to a modified example of Reference Example 2.

[0038] Fig.29 1 is a cross-sectional view schematically showing the structure of a semiconductor device 200D according to a modification example of Reference Example 2.

[0039] Fig.30 1 is a cross-sectional view schematically showing the structure of a semiconductor device 200E according to a modification example of Reference Example 2.

[0040] Fig.31 The appearance of a semiconductor device 300 according to Reference Example 3 of the related art is shown.

[0041] Fig.32 Show Fig.31 Cross-sectional view at line XXXII-XXXII in FIG.

[0042] Fig.33 Show Fig.31 Cross-sectional view at line XXXIII-XXXIII in FIG.

[0043] Fig.34 A circuit structure of a semiconductor device 300 according to Reference Example 3 is shown.

[0044] Fig.35 1 is a cross-sectional view schematically showing the structure of a semiconductor device 300 ′ according to a modification example of Reference Example 3.

[0045] Fig.36 2 is a cross-sectional view schematically showing the structure of a semiconductor device 300 ″ according to a modified example of Reference Example 3.

[0046] Fig.37 A cross-sectional view schematically showing the structure of a semiconductor device 300A according to another modified example of Reference Example 3, corresponding to Fig.32 Cross-sectional view of .

[0047] Fig.38 A cross-sectional view schematically showing the structure of a semiconductor device 300A according to another modification example related to reference example 3 corresponds to Fig.33 Cross-sectional view of .

[0048] Fig.39 Show Fig.37 , 38 1 shows a circuit structure of a semiconductor device 300A according to a modified example. DETAILED DESCRIPTION

[0049] In one embodiment of the present invention, the first semiconductor element and the second semiconductor element may each have a first main electrode and a second main electrode having an area larger than that of the first main electrode. The first semiconductor element may be connected to the upper conductive plate at the first main electrode and to the intermediate conductive plate at the second main electrode. Furthermore, the second semiconductor element may be connected to the intermediate conductive plate at the first main electrode and to the lower conductive plate at the second main electrode. That is, for the first semiconductor element and the second semiconductor element, the first main electrode may be located on the opposite side relative to the second main electrode.

[0050] When the area of ​​the second main electrode is larger than the area of ​​the first main electrode, in each semiconductor element, more heat is released through the second main electrode than through the first main electrode. Therefore, if the area of ​​the conductive plate connected to the second main electrode is made larger than the area of ​​the conductive plate connected to the first main electrode, the heat dissipation performance of the conductive plate connected to the second main electrode can be improved. Based on this viewpoint, in the above embodiment, the area of ​​the upper conductive plate can be smaller than the area of ​​the middle conductive plate, and the area of ​​the lower conductive plate can be larger than the area of ​​the middle conductive plate.

[0051] Alternatively, it can be said that when the area of ​​the second main electrode is larger than the area of ​​the first main electrode, the heat dissipation of the first main electrode is worse than that of the second main electrode. Therefore, when each semiconductor element generates heat due to power-on, the temperature of the first main electrode may be higher than that of the second main electrode. In order to suppress this temperature difference, the area of ​​the conductive plate connected to the first main electrode can be made larger than the area of ​​the conductive plate connected to the second main electrode, thereby improving the heat dissipation performance of the conductive plate connected to the first main electrode. Based on this viewpoint, in the above embodiment, the area of ​​the upper conductive plate can be made larger than the area of ​​the middle conductive plate, and the area of ​​the lower conductive plate can be made smaller than the area of ​​the middle conductive plate.

[0052] In one embodiment of the present invention, each of the first semiconductor element and the second semiconductor element may further include a protective film provided in a frame shape along the periphery of the first main electrode. According to this structure, near the protective film, a plurality of different types of materials having different linear expansion coefficients are concentrated, and deformation due to thermal deformation is likely to increase locally. In order to suppress the increase of this deformation, it is effective to suppress the temperature rise of the first main electrode, and thus the heat dissipation performance of the conductive plate connected to the first main electrode can be improved. In this regard, if the area of ​​the upper conductive plate is larger than the area of ​​the middle conductive plate, and the area of ​​the lower conductive plate is smaller than the area of ​​the middle conductive plate, the temperature rise of the first main electrode can be effectively suppressed.

[0053] In one embodiment of the present invention, the thickness of the conductive plate with a smaller area between the upper conductive plate and the lower conductive plate may be greater than the thickness of the conductive plate with a larger area. According to this structure, the difference in heat capacity between the upper conductive plate and the lower conductive plate can be reduced, thereby reducing the temperature difference that may be generated between the first semiconductor element and the second semiconductor element.

[0054] In one embodiment of the present invention, the semiconductor device may further include a package that packages the first semiconductor element and the second semiconductor element and integrally holds the upper conductive plate, the middle conductive plate, and the lower conductive plate.

[0055] Hereinafter, representative but not limiting examples of the present invention will be described in detail with reference to the accompanying drawings. This detailed description is intended only to show the details of the preferred examples for implementing the present invention to those skilled in the art, and is not intended to limit the scope of protection of the present invention. In addition, the additional features and inventions disclosed below can be used alone or in combination with other features and inventions to provide further improved semiconductor devices, methods of using the same, and methods of manufacturing the same.

[0056] In addition, the combination of features or processes disclosed in the following detailed description is not necessary for implementing the present invention to the maximum extent, and is only recorded for the purpose of specifically describing the representative specific examples of the present invention. In addition, the various features of the above-mentioned and the following representative specific examples, as well as the various features recorded in the independent claims and the dependent claims, do not need to be combined in accordance with the specific examples recorded herein or in the order in which they are listed when providing additional practical embodiments of the present invention.

[0057] The purpose of all features recorded in the scope of this specification and / or claims is to disclose features separately and independently of each other as limitations of the original disclosure of the present invention and the specific contents claimed for protection, in addition to the configurations of the features recorded in the embodiments and / or claims. In addition, the purpose of all numerical ranges, and the relevant descriptions of groups or groups is to disclose intermediate configurations thereof as limitations of the original disclosure of the present invention and the specific contents claimed for protection.

[0058] [Example]

[0059] Reference Figure 1-Figure 5 , the semiconductor device 10 of the embodiment is described. The semiconductor device 10 of the embodiment is used, for example, in a power control device of an electric vehicle, and can constitute a part of a power conversion circuit such as a converter and an inverter. In addition, the electric vehicle in this specification refers to a vehicle having an electric motor for driving wheels in a broad sense, including, for example, an electric vehicle charged by external power, a hybrid vehicle having an engine in addition to an electric motor, and a fuel cell vehicle using a fuel cell as a power source.

[0060] The semiconductor device 10 includes a plurality of semiconductor elements 12 and 14, a plurality of conductive plates 16, 18, and 20, and a package 30. The package 30 packages the plurality of semiconductor elements 12 and 14 and integrally holds the plurality of conductive plates 16, 18, and 20. The package 30 is made of an insulating material. The package 30 in this embodiment is made of a sealing resin material such as epoxy resin, but is not particularly limited.

[0061] The package body 30 is generally plate-shaped and has an upper surface 30a, a lower surface 30b, a first end surface 30c, a second end surface 30d, a first side surface 30e, and a second side surface 30f. The upper surface 30a and the lower surface 30b are located on opposite sides to each other, and the first end surface 30c, the second end surface 30d, the first side surface 30e, and the second side surface 30f are respectively developed between the upper surface 30a and the lower surface 30b. In addition, the first end surface 30c and the second end surface 30d are located on opposite sides to each other, and the first side surface 30e and the second side surface 30f are located on opposite sides to each other.

[0062] The plurality of semiconductor elements 12 and 14 include a first semiconductor element 12 and a second semiconductor element 14. The first semiconductor element 12 and the second semiconductor element 14 are power semiconductor elements and have the same structure. Each semiconductor element 12 and 14 includes a semiconductor substrate 12a and 14a; a first main electrode 12b and 14b; a second main electrode 12c and 14c; and a plurality of signal electrodes 12d and 14d. The semiconductor substrates 12a and 14a are not particularly limited and may be silicon substrates, silicon carbide substrates, or nitride semiconductor substrates.

[0063] The first main electrodes 12b and 14b are located on the surface of the semiconductor substrates 12a and 14a, and the second main electrodes 12c and 14c are located on the back surface of the semiconductor substrates 12a and 14a. The first main electrodes 12b and 14b and the second main electrodes 12c and 14c are electrically connected to each other via the semiconductor substrates 12a and 14a. Each semiconductor element 12 and 14 may be a switching element that can selectively conduct or disconnect between the first main electrode 12b and 14b and the second main electrode 12c and 14c, but is not particularly limited. A plurality of signal electrodes 12d and 14d are located on the first surface of the semiconductor substrates 12a and 14a in the same manner as the first main electrodes 12b and 14b. Each signal electrode 12d and 14d is sufficiently smaller than the first main electrode 12b and 14b and the second main electrode 12c and 14c. However, since both the first main electrodes 12b, 14b and the plurality of signal electrodes 12d, 14d are located on the surface of the semiconductor substrates 12a, 14a, the area of ​​the first main electrodes 12b, 14b is smaller than the area of ​​the second main electrodes 12c, 14c. The first main electrodes 12b, 14b, the second main electrodes 12c, 14c and the signal electrodes 12d, 14d may be formed of a single metal or multiple metals such as aluminum, nickel or gold.

[0064] As an example, Figure 4As shown, each semiconductor element 12, 14 in this embodiment is an RC (Reverse Conducting)-IGBT formed by integrating an IGBT (Insulated Gate Bipolar Transistor) and a diode. The first main electrode 12b, 14b is connected to the emitter of the IGBT and the positive electrode of the diode, and the second main electrode 12c, 14c is connected to the collector of the IGBT and the negative electrode of the diode. In addition, one of the multiple signal electrodes 12d, 14d is connected to the gate of the IGBT. In addition, as another embodiment, the first semiconductor element 12 and / or the second semiconductor element 14 can also be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In this case, the first main electrode 12b, 14b is connected to the source of the MOSFET, and the second main electrode 12c, 14c is connected to the drain of the MOSFET. In addition, one of the multiple signal electrodes 12d, 14d is connected to the gate of the MOSFET.

[0065] The plurality of conductive plates 16, 18, 20 include an upper conductive plate 16, an intermediate conductive plate 20, and a lower conductive plate 18. Each conductive plate 16, 20, 18 is a plate-shaped member having conductivity at least partially. The three conductive plates 16, 20, 18 are stacked and arranged, and a plurality of semiconductor elements 12, 14 are arranged between them. That is, the first semiconductor element 12 is located between the upper conductive plate 16 and the intermediate conductive plate 20, and is electrically connected to the upper conductive plate 16 and the intermediate conductive plate 20, respectively. The second semiconductor element 14 is located between the intermediate conductive plate 20 and the lower conductive plate 18, and is electrically connected to the intermediate conductive plate 20 and the lower conductive plate 18, respectively. In addition, two or more first semiconductor elements 12 may be provided between the upper conductive plate 16 and the intermediate conductive plate 20. In this case, the two or more first semiconductor elements 12 may be semiconductor elements of the same type (i.e., the same structure), or may be semiconductor elements of different types (i.e., different structures). Similarly, two or more second semiconductor elements 14 of the same type or different types may be provided between the intermediate conductive plate 20 and the lower conductive plate 18 .

[0066] The upper conductive plate 16, the intermediate conductive plate 20, and the lower conductive plate 18 are plate-shaped members having conductivity, and at least a portion thereof is made of a conductor. As an example, each of the conductive plates 16, 20, and 18 in the present embodiment is a metal plate made of copper. The upper conductive plate 16 is electrically connected to the first main electrode 12b of the first semiconductor element 12 via the first conductor separator 13. The intermediate conductive plate 20 is electrically connected to the second main electrode 12c of the first semiconductor element 12. The upper conductive plate 16 and the first conductor separator 13, the first conductor separator 13 and the first main electrode 12b of the first semiconductor element 12, and the second main electrode 12c of the first semiconductor element 12 and the intermediate conductive plate 20 are joined to each other via conductive bonding layers 50, 52, and 54 (e.g., solder layers), but are not particularly limited thereto.

[0067] The intermediate conductive plate 20 is also electrically connected to the first main electrode 14b of the second semiconductor element 14 via the second conductor separator 15. Furthermore, the lower conductive plate 18 is electrically connected to the second main electrode 14c of the second semiconductor element 14. The intermediate conductive plate 20 and the second conductor separator 15, the second conductor separator 15 and the first main electrode 14b of the second semiconductor element 14, and the second main electrode 14c of the second semiconductor element 14 and the lower conductive plate 18 are bonded to each other via conductive bonding layers 60, 62, 64 (e.g., solder layers), but are not particularly limited.

[0068] The upper conductive plate 16 is exposed to the outside at the upper surface 30a of the package 30. Thus, the upper conductive plate 16 not only constitutes a part of the circuit of the semiconductor device 10, but also functions as a heat sink for releasing the heat of the semiconductor elements 12 and 14 to the outside. Similarly, the lower conductive plate 18 is exposed to the outside at the lower surface 30b of the package 30. Therefore, the lower conductive plate 18 also not only constitutes a part of the circuit of the semiconductor device 10, but also functions as a heat sink for releasing the heat of the semiconductor elements 12 and 14 to the outside.

[0069] The semiconductor device 10 has a plurality of power terminals 32, 34, 36 and a plurality of signal terminals 40, 42. These terminals 32, 34, 36, 40, 42 are made of metal such as copper, but are not particularly limited. The plurality of power terminals 32, 34, 36 protrude from the second end surface 30d of the package 30. The plurality of signal terminals 40, 42 protrude from the first end surface 30c of the package 30. However, the specific structures such as the positions and shapes of these terminals 32, 34, 36, 40, 42 are not particularly limited.

[0070] The plurality of power terminals 32, 34, 36 include a first power terminal 32, a second power terminal 34, and a third power terminal 36. The first power terminal 32 is electrically connected to the upper conductive plate 16 inside the package 30. Thus, the first main electrode 12b of the first semiconductor element 12 is electrically connected to the first power terminal 32 via the upper conductive plate 16. The first power terminal 32 may be formed integrally with the upper conductive plate 16, but this is not particularly limited.

[0071] The second power terminal 34 is electrically connected to the intermediate conductive plate 20 inside the package 30. Thus, the second main electrode 12c of the first semiconductor element 12 and the first main electrode 14b of the second semiconductor element 14 are electrically connected to the second power terminal 34 via the intermediate conductive plate 20. The second power terminal 34 may be formed integrally with the intermediate conductive plate 20, but the present invention is not particularly limited. The third power terminal 36 is electrically connected to the lower conductive plate 18 inside the package 30. Thus, the second main electrode 14c of the second semiconductor element 14 is electrically connected to the third power terminal 36 via the lower conductive plate 18. The third power terminal 36 may be formed integrally with the lower conductive plate 18, but the present invention is not particularly limited.

[0072] The plurality of signal terminals 40, 42 include a plurality of first signal terminals 40 and a plurality of second signal terminals 42. The plurality of first signal terminals 40 are electrically connected to the plurality of signal electrodes 12d of the first semiconductor element 12 in the interior of the package 30, respectively. The first signal terminals 40 and the signal electrodes 12d are bonded to each other via a conductive bonding layer 56 (e.g., a soldering layer), but the present invention is not particularly limited thereto. Similarly, the plurality of second signal terminals 42 are electrically connected to the plurality of signal electrodes 14d of the second semiconductor element 14 in the interior of the package 30, respectively. The second signal terminals 42 and the signal electrodes 14d are bonded to each other via a conductive bonding layer 66 (e.g., a soldering layer), but the present invention is not particularly limited thereto.

[0073] When manufacturing the semiconductor device 10 of this embodiment, it is necessary to bond three conductive plates 16, 20, and 18 via the semiconductor elements 12 and 14. At this time, in order to manufacture the semiconductor device 10 with high precision, the three conductive plates 16, 20, and 18 need to be correctly positioned. However, considering that they need to be removed later, it is difficult to hold the three conductive plates 16, 20, and 18 in a stacked configuration with a single jig. Therefore, it is possible to consider using a jig that can be divided into two or more, but the use of multiple jigs may result in a decrease in dimensional accuracy compared to a single jig.

[0074] To address this problem, in the semiconductor device 10 of this embodiment, the area of ​​the upper conductive plate 16 is made smaller than the area of ​​the middle conductive plate 20, and the area of ​​the lower conductive plate 18 is made larger than the area of ​​the middle conductive plate 20. That is, the areas of the three conductive plates 16, 20, and 18 are gradually increased (or decreased) along their stacking direction. Figure 5 As shown in FIG. 1 , if the three conductive plates 16, 20, and 18 are projected onto a plane parallel to them, a first region R1, a second region R2, and a third region R3 are divided on the plane. The first region R1 is a region where the upper conductive plate 16, the middle conductive plate 20, and the lower conductive plate 18 are projected. The second region R2 is a region where both the lower conductive plate 18 and the middle conductive plate 20 are projected. Furthermore, the third region R3 is a region where only the lower conductive plate 18 is projected.

[0075] According to the above construction, Figure 6 As shown in FIG. 1 , the three stacked conductive plates 16, 20, and 18 can be held in the same direction by a single jig 90. By using a single jig 90, the semiconductor device 10 can be manufactured with high precision. Figure 7 As shown, when manufacturing the semiconductor device 10, the package 30 is molded (injection molded) using a molding die 92. At this time, if the areas of the three conductive plates 16, 20, and 18 gradually increase (or decrease) along the stacking direction, the material (e.g., resin) of the package 30 can flow smoothly in the molding die 92, and the generation of defects such as voids can be suppressed.

[0076] In the semiconductor device 10 of the present embodiment, each semiconductor element 12, 14 has a first main electrode 12b, 14b and a second main electrode 12c, 14c, and the area of ​​the second main electrode 12c, 14c is larger than the area of ​​the first main electrode 12b, 14b. If the area of ​​the second main electrode 12c, 14c is larger than the area of ​​the first main electrode 12b, 14b, more heat can be released through the second main electrode 12c, 14c than through the first main electrode 12b, 14b in each semiconductor element 12, 14. Therefore, the area of ​​the conductive plate 20, 18 connected to the second main electrode 12c, 14c can be made larger than the area of ​​the conductive plate 16, 20 connected to the first main electrode 12b, 14b, thereby improving the heat dissipation performance of the conductive plate 20, 18 connected to the second main electrode 12c, 14c. Based on this viewpoint, in the semiconductor device 10 of the present embodiment, the area of ​​the upper conductive plate 16 is made smaller than that of the intermediate conductive plate 20 , and the area of ​​the lower conductive plate 18 is made larger than that of the intermediate conductive plate 20 .

[0077] Figure 8 A semiconductor device 10A of a modified example is shown. Figure 8As shown, in the semiconductor device 10A, the area of ​​the lower conductive plate 18 is smaller than the area of ​​the middle conductive plate 20, and the area of ​​the upper conductive plate 16 is larger than the area of ​​the middle conductive plate 20. In this modified example, the areas of the three conductive plates 16, 20, and 18 also gradually increase (or decrease) along the stacking direction. Therefore, when manufacturing the semiconductor device 10A, the three stacked conductive plates 16, 20, and 18 can be easily held in the same direction using a single jig 90, and the semiconductor device 10A can be manufactured with high precision.

[0078] In each semiconductor element 12, 14, since the area of ​​the second main electrode 12c, 14c is larger than the area of ​​the first main electrode 12b, 14b, the heat dissipation performance of the first main electrode 12b, 14b is inferior to the heat dissipation performance of the second main electrode 12c, 14c. Therefore, when each semiconductor element 12, 14 generates heat due to power supply, the temperature at the first main electrode 12b, 14b may be higher than the temperature at the second main electrode 12c, 14c. In order to suppress such a temperature difference, the area of ​​the conductive plate 16, 20 connected to the first main electrode 12b, 14b can be made larger than the area of ​​the conductive plate 20, 18 connected to the second main electrode 12c, 14c, thereby improving the heat dissipation performance of the conductive plate 16, 20 connected to the first main electrode 12b, 14b. Based on this viewpoint, in the semiconductor device 10A of the present modification, the area of ​​the upper conductive plate 16 is made larger than that of the intermediate conductive plate 20 , and the area of ​​the lower conductive plate 18 is made smaller than that of the intermediate conductive plate 20 .

[0079] exist Figure 8 In the semiconductor device 10A of the modified example shown, each of the first semiconductor element 12 and the second semiconductor element 14 may have a protective film (not shown) provided in a frame shape along the periphery of the first main electrode 12b, 14b. It is known that if such a structure is formed, deformation due to thermal deformation is likely to increase locally near the protective film due to the concentration of a plurality of different types of materials having different linear expansion coefficients. In order to suppress the increase of such deformation, it is effective to suppress the temperature rise of the first main electrodes 12b, 14b. For this purpose, the heat dissipation performance of the conductive plates 16, 20 connected to the first main electrodes 12b, 14b can be improved. In this regard, if the area of ​​the upper conductive plate 16 is made larger than the area of ​​the intermediate conductive plate 20, and the area of ​​the lower conductive plate 18 is made smaller than the area of ​​the intermediate conductive plate 20, the temperature rise of the first main electrodes 12b, 14b can be effectively suppressed.

[0080] Fig. 9 , Fig.10 a-10c shows another modified example of a semiconductor device 10B. Fig. 9 As shown in FIG. 1 , in the semiconductor device 10B, the areas of the three conductive plates 16, 20, and 18 are almost equal. Fig.10 As shown in a-10c, the three conductive plates 16, 20, and 18 have different shapes from each other. That is, the upper conductive plate 16 has a substantially rectangular shape, but the four corners are chamfered. The middle conductive plate 20 also has a substantially rectangular shape, but only the two corners located at the diagonal corners are chamfered. In addition, the lower conductive plate 18 has a substantially rectangular shape, and its corners are not chamfered.

[0081] In the above construction, if Fig.11 As shown in FIG. 1 , if the three conductive plates 16, 20, and 18 are projected onto a plane parallel to them, the plane is also divided into a first region R1, a second region R2, and a third region R3. The first region R1 is a region where the upper conductive plate 16, the middle conductive plate 20, and the lower conductive plate 18 are projected. The second region R2 is a region where the lower conductive plate 18 and the middle conductive plate 20 are projected. And the third region R3 is a region where only the lower conductive plate 18 is projected. Therefore, in the structure of this modified example, as shown in FIG. 1 , the first region R1 is a region where the upper conductive plate 16, the middle conductive plate 20, and the lower conductive plate 18 are projected. Fig.12 As shown, the three stacked conductive plates 16, 20, and 18 can also be easily held from the same direction by a single jig 90. By using the single jig 90, the semiconductor device 10B can be manufactured with high precision.

[0082] Furthermore, in order to stably hold the lower conductive plate 18 with the single jig 90, it is sufficient that a triangle can be drawn that surrounds the center of gravity of the lower conductive plate 18 with the three points located in the third region R3 as vertices. Similarly, in order to stably hold the intermediate conductive plate 20 with the single jig 90, it is sufficient that a triangle can be drawn that surrounds the center of gravity of the intermediate conductive plate 20 with the three points located in the second region R2 as vertices. However, the jig 90 may also have, for example, an adsorption mechanism or a clamping mechanism, and in this case, the above limitation is not essential.

[0083] Fig.13 A semiconductor device 10C according to another modified example is shown. Fig.13 As shown in FIG. 1 , in the semiconductor device 10C, the thickness of the upper conductive plate 16 with a smaller area is made larger than the thickness of the lower conductive plate 18 with a larger area. In this way, if the thickness of the conductive plate with a smaller area is made larger than the thickness of the conductive plate with a larger area between the upper conductive plate 16 and the lower conductive plate 18, the difference in heat capacity between the upper conductive plate 16 and the lower conductive plate 18 is reduced. As a result, the difference in heat dissipation performance between the two conductive plates 16 and 18 is also reduced, so that, for example, the temperature difference that may occur between the first semiconductor element 12 and the second semiconductor element 14 can be reduced.

[0084] (Reference Example 1 of Related Art)

[0085] Reference Figure 14-Figure 21, a reference example 1 of the related art is described. In addition, the same reference numerals are given to the components common to or corresponding to the semiconductor device 10 of the above-mentioned embodiment, and repeated descriptions are appropriately omitted. Figure 14-17 As shown, the semiconductor device 100 of reference example 1 also has: an upper conductive plate 16, an intermediate conductive plate 20 and a lower conductive plate 18 arranged in a stacked manner; a first semiconductor element 12, which is located between the upper conductive plate 16 and the intermediate conductive plate 20 and is electrically connected to the upper conductive plate 16 and the intermediate conductive plate 20, respectively; a second semiconductor element 14, which is located between the intermediate conductive plate 20 and the lower conductive plate 18 and is electrically connected to the intermediate conductive plate 20 and the lower conductive plate 18, respectively; and a package body 30, which packages the first semiconductor element 12 and the second semiconductor element 14, and holds the upper conductive plate 16, the intermediate conductive plate 20 and the lower conductive plate 18 as a whole.

[0086] The semiconductor device 100 of Reference Example 1 can be assembled in a power conversion circuit such as a converter or an inverter to form a switch circuit for turning on and off current, similarly to the semiconductor device 10 of the above-mentioned embodiment. When current flows through the first semiconductor element 12 and the second semiconductor element 14, the first semiconductor element 12 and the second semiconductor element 14 each generate heat. When the first semiconductor element 12 and the second semiconductor element 14 generate heat, the temperature of the three conductive plates 16, 18, and 20 adjacent to them also rises, and thermal expansion occurs in each conductive plate 16, 18, and 20. In particular, the middle conductive plate 20 located between the first semiconductor element 12 and the second semiconductor element 14 is more likely to become high temperature than the upper conductive plate 16 and the lower conductive plate 18. In this case, the middle conductive plate 20 generates a larger thermal expansion than the upper conductive plate 16 and the lower conductive plate 18, and as a result, there is a possibility that the deformation generated in the semiconductor device 100 is locally increased.

[0087] Therefore, in the semiconductor device 100 of Reference Example 1, the thickness T20 of the intermediate conductive plate 20 is smaller than the thickness T16 of the upper conductive plate 16 and the thickness T18 of the lower conductive plate 18 (see Fig.15 ). By making the thickness T20 of the intermediate conductive plate 20 smaller, the thermal expansion force that may be generated by the intermediate conductive plate 20 can be made smaller. As described above, the thermal expansion force of the intermediate conductive plate 20 refers to the force that acts from the intermediate conductive plate 20 on other components (such as adjacent bonding layers 54, 60) when the intermediate conductive plate 20 thermally expands. Since the thermal expansion force generated by the intermediate conductive plate 20 is reduced, the thermal expansion of the intermediate conductive plate 20 can be significantly suppressed by using other adjacent components (such as the package 30). As a result, local deformation generated inside the semiconductor device 100 (especially the bonding layers 54, 60) can be reduced.

[0088] Furthermore, as the thickness T20 of the intermediate conductive plate 20 decreases, the distance from the first semiconductor element 12 to the lower conductive plate 18 becomes shorter. As a result, the thermal resistance from the first semiconductor element 12 to the lower conductive plate 18 decreases, so that the heat of the first semiconductor element 12 can also be effectively released from the lower conductive plate 18. Similarly, as the thickness T20 of the intermediate conductive plate 20 decreases, the distance from the second semiconductor element 14 to the upper conductive plate 16 becomes shorter. As a result, the thermal resistance from the second semiconductor element 14 to the upper conductive plate 16 decreases, so that the heat of the second semiconductor element 14 can also be effectively released from the upper conductive plate 16. Therefore, as the thickness T20 of the intermediate conductive plate 20 decreases, the temperature rise of the first semiconductor element 12 and the second semiconductor element 14 can be suppressed.

[0089] In the semiconductor device 100 of Reference Example 1, the thickness T16 of the upper conductive plate 16 is greater than the thickness T18 of the lower conductive plate 18, but this is not particularly limited. In this regard, in each of the semiconductor elements 12 and 14, the area of ​​the second main electrode 12c and 14c is greater than the area of ​​the first main electrode 12b and 14b. Therefore, in each of the semiconductor elements 12 and 14, more heat is released through the second main electrode 12c and 14c than through the first main electrode 12b and 14b. In other words, the heat dissipation performance of the first main electrode 12b and 14b is worse than that of the second main electrode 12c and 14c. In order to improve the unbalanced heat dissipation performance, it is effective to set the thickness T16 of the upper conductive plate 16 connected to the first main electrode 12b to be greater than the thickness T18 of the lower conductive plate 18 connected to the second main electrode 12c. According to this structure, the upper conductive plate 16 has a relatively high heat capacity, thereby promoting heat dissipation from the first main electrode 12 b and improving the heat dissipation performance of the first main electrode 12 b.

[0090] Fig.18 This is the result of a computer simulation performed by the inventors to confirm the above findings. In this computer simulation, the thermal resistance (°C / W) and maximum deformation of the semiconductor device 100 were calculated for each sample (i.e., various combinations of thicknesses T16, T20, T18) while changing the thicknesses T16, T20, T18 of the three conductive plates 16, 20, 18 between 0.5 mm and 2.0 mm, respectively. The results are shown in Figure 2. Fig.18As shown in FIG. 1 , it was confirmed that when the thickness T20 of the middle conductive plate 20 was 0.5 mm, the thickness T16 of the upper conductive plate 16 was 2.0 mm, and the thickness T18 of the lower conductive plate 18 was 1.5 mm, the maximum strain generated in the semiconductor device 100 was minimized. In addition, when the thickness T20 of the middle conductive plate 20 was set within the range of 0.5±0.1 mm, the thickness T16 of the upper conductive plate 16 was set to 2.0 mm, and the thickness T18 of the lower conductive plate 18 was set to 1.5±0.1 mm, it was confirmed that the maximum strain generated in the semiconductor device 100 was sufficiently reduced.

[0091] Fig.19 A semiconductor device 100A according to a modified example is shown. Fig.19 As shown in FIG. 1 , the thickness T16 of the upper conductive plate 16 and the thickness T18 of the lower conductive plate 18 can be made equal to each other. In this modification, since the thickness T20 of the intermediate conductive plate 20 is smaller than the thickness T16 of the upper conductive plate 16 and the thickness T18 of the lower conductive plate 18, the thermal expansion of the intermediate conductive plate 20 is suppressed, thereby reducing the local deformation in the semiconductor device 100A.

[0092] Fig. 20 A semiconductor device 100B of a modified example is shown. Fig. 20 As shown in FIG. 1 , the area of ​​the intermediate conductive plate 20 may be made smaller than the area of ​​the upper conductive plate 16 and the area of ​​the lower conductive plate 18. The heat of the first semiconductor element 12 and the second semiconductor element 14 is released to the outside through the upper conductive plate 16 and the lower conductive plate 18. In contrast, the intermediate conductive plate 20 located between the first semiconductor element 12 and the second semiconductor element 14 is located inside the package 30, where the heat of the first semiconductor element 12 and the second semiconductor element 14 is easily accumulated. Therefore, by increasing the area of ​​the upper conductive plate 16 and the area of ​​the lower conductive plate 18 and reducing the area of ​​the intermediate conductive plate 20, the temperature rise of the first semiconductor element 12 and the second semiconductor element 14 can be effectively suppressed.

[0093] Fig.21 A semiconductor device 100C of a modified example is shown. Fig.21 As shown in FIG. 1 , the area of ​​the intermediate conductive plate 20 may be larger than the area of ​​the upper conductive plate 16 and / or the area of ​​the lower conductive plate 18. According to this structure, the intermediate conductive plate 20 located between the upper conductive plate 16 and the lower conductive plate 18 partially protrudes between the upper conductive plate 16 and the lower conductive plate 18. Therefore, when manufacturing the semiconductor device 100C, for example, the intermediate conductive plate 20 and the upper conductive plate 16 and / or the lower conductive plate 18 can be easily supported by the same jig. In addition, the area of ​​the upper conductive plate 16 and the area of ​​the lower conductive plate 18 may be equal to each other or different from each other.

[0094] (Reference Example 2 of Related Art)

[0095] Reference Figure 22-Figure 30 , a reference example 2 of the related art is described. In addition, the same reference numerals are given to the components common to or corresponding to the semiconductor device 10 of the above-mentioned embodiment, and repeated descriptions are appropriately omitted. Figure 22-Figure 25 As shown, the semiconductor device 200 of reference example 2 also has: an upper conductive plate 16, an intermediate conductive plate 20 and a lower conductive plate 18 arranged in a stacked manner; a first semiconductor element 12, which is located between the upper conductive plate 16 and the intermediate conductive plate 20 and is electrically connected to the upper conductive plate 16 and the intermediate conductive plate 20, respectively; a second semiconductor element 14, which is located between the intermediate conductive plate 20 and the lower conductive plate 18 and is electrically connected to the intermediate conductive plate 20 and the lower conductive plate 18, respectively; and a package body 30, which packages the first semiconductor element 12 and the second semiconductor element 14, and holds the upper conductive plate 16, the intermediate conductive plate 20 and the lower conductive plate 18 as a whole.

[0096] In the semiconductor device 200 of Reference Example 2, the intermediate conductive plate 20 is also exposed to the outside at the side surfaces 30e and 30f of the package 30, similarly to the upper conductive plate 16 and the lower conductive plate 18, and can function as a heat sink. Fig.23 As shown in FIG. 1 , the intermediate conductive plate 20 includes a main body portion 20a bonded to the first semiconductor element 12 and the second semiconductor element 14 inside the package 30, and an exposed portion 20b exposed to the outside from the side surfaces 30e and 30f of the package 30. The thickness Tb of the exposed portion 20b of the intermediate conductive plate 20 is equal to or greater than the thickness Ta of the main body portion 20a of the intermediate conductive plate 20.

[0097] The semiconductor device 200 of Reference Example 2 can also be assembled in a power conversion circuit such as a converter or an inverter to form a switch circuit for turning on and off current. When current flows through the first semiconductor element 12 and the second semiconductor element 14, the first semiconductor element 12 and the second semiconductor element 14 generate heat respectively. When the first semiconductor element 12 and the second semiconductor element 14 generate heat, the temperature of the three conductive plates 16, 18, and 20 adjacent to them also rises, and thermal expansion occurs in each conductive plate 16, 18, and 20. In particular, the middle conductive plate 20 located between the first semiconductor element 12 and the second semiconductor element 14 is more likely to become high temperature than the upper conductive plate 16 and the lower conductive plate 18.

[0098] Therefore, in the semiconductor device 200 of Reference Example 2, the intermediate conductive plate 20 is exposed to the outside at the side surfaces 30e and 30f of the package body 30, so that the heat of the intermediate conductive plate 20 can be easily released to the outside. As a result, it is possible to significantly suppress the temperature rise of the intermediate conductive plate 20. In particular, by arranging a cooler connected to the exposed portion 20b of the intermediate conductive plate 20, it is possible to efficiently cool both the first semiconductor element 12 and the second semiconductor element 14 while suppressing the temperature rise of the intermediate conductive plate 20.

[0099] Fig.26 A semiconductor device 200A according to a modified example of Reference Example 2 is shown. Fig.26 As shown in FIG. 1 , the thickness Tb of the exposed portion 20b of the intermediate conductive plate 20 can be made sufficiently larger than the thickness Ta of the main body portion 20a of the intermediate conductive plate 20. In this case, the thickness Tb of the exposed portion 20b can be made at least twice the thickness Ta of the main body portion 20a. According to this structure, the temperature rise of the intermediate conductive plate 20 can be further suppressed. In addition, the shape of the intermediate conductive plate 20 can also be made in the stacking direction ( Figure 5 According to this structure, the temperature difference between the first semiconductor element 12 and the second semiconductor element 14 can be reduced. The temperature rise of the intermediate conductive plate 20 can be further suppressed.

[0100] Fig. 27 A semiconductor device 200B according to another modification of Reference Example 2 is shown. Fig. 27 As shown, the exposed portion 20b of the intermediate conductive plate 20 may also be exposed to the outside at the upper surface 30a (or the lower surface 30b) of the package body 30. That is, the exposed portion 20b of the intermediate conductive plate 20 may also be exposed from the same surface of the package body 30 together with the upper conductive plate 16 or the lower conductive plate 18. According to this structure, by arranging a cooler along the upper surface 30a or the lower surface 30b of the package body 30, the intermediate conductive plate 20 and the upper conductive plate 16 or the lower conductive plate 18 can be cooled simultaneously.

[0101] Fig.28 A semiconductor device 200C according to another modified example of Reference Example 2 is shown. Fig.28 As shown, the exposed portion 20b of the intermediate conductive plate 20 may be exposed to the outside at two locations, the upper surface 30a and the lower surface 30b of the package 30. According to this structure, by arranging coolers on the upper surface 30a and the lower surface 30b of the package 30, the intermediate conductive plate 20 can be efficiently cooled by two coolers.

[0102] Fig.29 A semiconductor device 200D according to another modification of Reference Example 2 is shown. Fig.29As shown, the exposed portion 20b of the intermediate conductive plate 20 may also be exposed to the outside at the side surfaces 30e, 30f, the upper surface 30a and the lower surface 30b of the package body 30. According to this structure, since the intermediate conductive plate 20 is exposed to the outside over a large area, more heat can be released from the intermediate conductive plate 20 to the outside.

[0103] Fig.30 A semiconductor device 200E according to another modified example of Reference Example 2 is shown. Fig.30 As shown, the package 30 may be divided into a first package 30X and a second package 30Y by the intermediate conductive plate 20. The first package 30X is filled between the upper conductive plate 16 and the intermediate conductive plate 20, and encapsulates the first semiconductor element 12. The second package 30Y is filled between the intermediate conductive plate 20 and the lower conductive plate 18, and encapsulates the second semiconductor element 14. In the semiconductor device 200E, the intermediate conductive plate 20 also has a main body 20a that is bonded to the first semiconductor element 12 and the second semiconductor element 14 inside the package 30, and an exposed portion 20b that is exposed to the outside from the surface of the package 30. In addition, the thickness Tb of the exposed portion 20b of the intermediate conductive plate 20 is equal to or greater than the thickness Ta of the main body 20a of the intermediate conductive plate 20.

[0104] (Reference Example 3 of Related Art)

[0105] Reference Figure 31-Figure 39 , Reference Example 3 of the related art is described. In addition, the same reference numerals are given to the components common to or corresponding to the semiconductor device 10 of the above-mentioned embodiment, and repeated descriptions are appropriately omitted. Figure 31-Figure 34 As shown, the semiconductor device 300 of reference example 3 also has: an upper conductive plate 16, an intermediate conductive plate 20 and a lower conductive plate 18 arranged in a stacked manner; a first semiconductor element 12, which is located between the upper conductive plate 16 and the intermediate conductive plate 20 and is electrically connected to the upper conductive plate 16 and the intermediate conductive plate 20, respectively; a second semiconductor element 14, which is located between the intermediate conductive plate 20 and the lower conductive plate 18 and is electrically connected to the intermediate conductive plate 20 and the lower conductive plate 18, respectively; and a package body 30, which packages the first semiconductor element 12 and the second semiconductor element 14, and holds the upper conductive plate 16, the intermediate conductive plate 20 and the lower conductive plate 18 as a whole.

[0106] The upper conductive plate 16 and the lower conductive plate 18 are metal plates, for example, made of metal such as copper. The upper conductive plate 16 is bonded to the second main electrode 12c of the first semiconductor element 12 via a bonding layer 52. The bonding layer 52 is, for example, a solder layer, which electrically and thermally connects the upper conductive plate 16 to the first semiconductor element 12. The upper conductive plate 16 is exposed on the upper surface 30a of the package 30. Therefore, the upper conductive plate 16 not only constitutes a part of the circuit connected to the first semiconductor element 12, but also acts as a heat sink that releases the heat of the first semiconductor element 12 to the outside. The lower conductive plate 18 is bonded to the second main electrode 14c of the second semiconductor element 14 via a bonding layer 62. The bonding layer 62 is also, for example, a solder layer, which electrically and thermally connects the lower conductive plate 18 to the second semiconductor element 14. The lower conductive plate 18 is exposed on the lower surface 30b of the package 30. Therefore, the lower conductive plate 18 not only constitutes a part of the circuit connected to the second semiconductor element 14 but also functions as a heat sink that releases the heat of the second semiconductor element 14 to the outside.

[0107] The intermediate conductive plate 20 has a laminated structure including an insulating substrate 22, a first metal layer 24, and a second metal layer 26. The insulating substrate 22 is a substrate made of an insulator, and may be, for example, a ceramic substrate. The first metal layer 24 is made of a metal such as copper, and is disposed on the upper surface of the insulating substrate 22. The second metal layer 26 is also made of a metal such as copper, and is disposed on the lower surface of the insulating substrate 22. The first metal layer 24 is electrically connected to the first semiconductor element 12, and the second metal layer 26 is electrically connected to the second semiconductor element 14. The intermediate conductive plate 20 may be a DBC (Direct Bonded Cupper) substrate, a DBA (Direct Bonded Aluminum) substrate, or an AMC (Active Metal Brazed Cupper) substrate, without particular limitation.

[0108] The first metal layer 24 of the intermediate conductive plate 20 includes a first main circuit portion 24a and a plurality of first signal circuit portions 24b. The first main circuit portion 24a and the plurality of first signal circuit portions 24b are separated from each other and electrically insulated from each other. The first main circuit portion 24a is bonded to the first main electrode 12b of the first semiconductor element 12 via a bonding layer 50. The bonding layer 50 is, for example, a soldering layer, and electrically and thermally connects the first main circuit portion 24a to the first main electrode 12b of the first semiconductor element 12. The plurality of first signal circuit portions 24b are respectively bonded to the plurality of signal electrodes 12d of the first semiconductor element 12 via bonding layers 54. These bonding layers 54 are also, for example, soldering layers, and electrically and thermally connect the plurality of first signal circuit portions 24b to the plurality of signal electrodes 12d of the first semiconductor element 12.

[0109] Similarly, the second metal layer 26 of the intermediate conductive plate 20 includes a second main circuit portion 26a and a plurality of second signal circuit portions 26b. The second main circuit portion 26a and the plurality of second signal circuit portions 26b are separated from each other and electrically insulated from each other. The second main circuit portion 26a is bonded to the first main electrode 14b of the second semiconductor element 14 via a bonding layer 60. The bonding layer 60 is, for example, a soldering layer, and electrically and thermally connects the second main circuit portion 26a to the first main electrode 14b of the second semiconductor element 14. The plurality of second signal circuit portions 26b are respectively bonded to the plurality of signal electrodes 14d of the second semiconductor element 14 via bonding layers 64. These bonding layers 64 are also, for example, soldering layers, and electrically and thermally connect the plurality of second signal circuit portions 26b to the plurality of signal electrodes 14d of the second semiconductor element 14.

[0110] The semiconductor device 300 includes a plurality of power terminals 32, 34, 36, 38 and a plurality of signal terminals 40, 42. The terminals 32, 34, 36, 38, 40, 42 are not particularly limited, and are made of, for example, metal such as copper. The plurality of power terminals 32, 34, 36, 38 protrude from the second end surface 30d of the package 30. The plurality of signal terminals 40, 42 protrude from the first end surface 30c of the package 30. However, the specific structures such as the positions and shapes of the terminals 32, 34, 36, 38, 40, 42 are not particularly limited.

[0111] The plurality of power terminals 32, 34, 36, 38 include a first power terminal 32, a second power terminal 34, a third power terminal 36, and a fourth power terminal 38. The first power terminal 32 is electrically connected to the upper conductive plate 16 inside the package 30. Thus, the second main electrode 12c of the first semiconductor element 12 is electrically connected to the first power terminal 32 via the upper conductive plate 16. The first power terminal 32 may be formed integrally with the upper conductive plate 16, without particular limitation. The second power terminal 34 is electrically connected to the first main circuit portion 24a of the first metal layer 24 of the intermediate conductive plate 20 inside the package 30. Thus, the first main electrode 12b of the first semiconductor element 12 is electrically connected to the second power terminal 34 via the first main circuit portion 24a of the intermediate conductive plate 20. The second power terminal 34 may be bonded to the first main circuit portion 24a via a bonding layer 56 such as a solder layer, without particular limitation.

[0112] The third power terminal 36 is electrically connected to the second main circuit portion 26a of the second metal layer 26 of the intermediate conductive plate 20 inside the package 30. Thus, the first main electrode 14b of the second semiconductor element 14 is electrically connected to the third power terminal 36 via the second main circuit portion 26a of the intermediate conductive plate 20. The third power terminal 36 may be bonded to the second main circuit portion 26a via a bonding layer 66 such as a solder layer, without particular limitation. The fourth power terminal 38 is electrically connected to the lower conductive plate 18 inside the package 30. Thus, the second main electrode 14c of the second semiconductor element 14 is electrically connected to the fourth power terminal 38 via the lower conductive plate 18. The fourth power terminal 38 may be formed integrally with the lower conductive plate 18, without particular limitation.

[0113] The plurality of signal terminals 40 and 42 include a plurality of first signal terminals 40 and a plurality of second signal terminals 42. The plurality of first signal terminals 40 are electrically connected to the plurality of first signal circuit portions 24b of the first metal layer 24 of the intermediate conductive plate 20 in the interior of the package 30. Thus, each signal electrode 12d of the first semiconductor element 12 is electrically connected to a corresponding first signal terminal 40 via the first signal circuit portion 24b. The plurality of first signal terminals 40 may be bonded to the plurality of first signal circuit portions 24b via a bonding layer 58 such as a solder layer, without being particularly limited. Similarly, the plurality of second signal terminals 42 are electrically connected to the plurality of second signal circuit portions 26b of the second metal layer 26 of the intermediate conductive plate 20 in the interior of the package 30. Thus, each signal electrode 14d of the second semiconductor element 14 is electrically connected to a corresponding second signal terminal 42 via the second signal circuit portion 26b. The plurality of second signal terminals 42 may be respectively joined to the plurality of second signal circuit portions 26 b via a joining layer 68 such as a solder layer, and the method is not particularly limited.

[0114] According to the above structure, the semiconductor device 300 of Reference Example 3 can be assembled in a power conversion circuit such as a converter or an inverter to form a switch circuit that turns on and off current. At this time, if the second power terminal 34 and the fourth power terminal 38 are connected to each other, the first semiconductor element 12 and the second semiconductor element 14 can be connected in series. In addition, if the first power terminal 32 and the fourth power terminal 38 are connected to each other and the second power terminal 34 and the third power terminal 36 are connected to each other, the first semiconductor element 12 and the second semiconductor element 14 can be connected in parallel.

[0115] When current flows through the first semiconductor element 12 and the second semiconductor element 14, the first semiconductor element 12 and the second semiconductor element 14 each generate heat. When the first semiconductor element 12 and the second semiconductor element 14 generate heat, the temperature of the three conductive plates 16, 18, and 20 adjacent thereto also rises, and thermal expansion occurs in each of the conductive plates 16, 18, and 20. In particular, the middle conductive plate 20 located between the first semiconductor element 12 and the second semiconductor element 14 is more likely to become high temperature than the upper conductive plate 16 and the lower conductive plate 18.

[0116] Therefore, in the semiconductor device 300 of Reference Example 3, in contrast to the case where the upper conductive plate 16 and the lower conductive plate 18 are metal plates, the intermediate conductive plate 20 has a laminated structure including an insulator substrate 22. The insulator substrate 22 is, for example, a ceramic substrate, and the material constituting the insulator substrate 22 has a smaller linear expansion coefficient than the material constituting the first metal layer 24 and the material constituting the second metal layer 26. As a result, the linear expansion coefficient in the in-plane direction of the intermediate conductive plate 20 is smaller than the linear expansion coefficient in the in-plane direction of the upper conductive plate 16 and the linear expansion coefficient in the in-plane direction of the lower conductive plate 18. Therefore, even if the temperature of the intermediate conductive plate 20 is higher than the temperature of the upper conductive plate 16 and the temperature of the lower conductive plate 18, it is possible to suppress the occurrence of unbalanced thermal expansion in the three conductive plates 16, 18, and 20.

[0117] Here, the intermediate conductive plate 20 is not limited to a laminated structure including the insulator substrate 22, and its structure and material can be appropriately changed. The upper conductive plate 16 and the lower conductive plate 18 are not limited to metal plates, and their structures and materials can be appropriately changed. As long as the linear expansion coefficient in the plane direction of the intermediate conductive plate 20 is smaller than the linear expansion coefficient in the plane direction of the upper conductive plate 16 and the linear expansion coefficient in the plane direction of the lower conductive plate 18, the structures and materials of the three conductive plates 16, 18, and 20 can be variously changed.

[0118] In the semiconductor device 300 of Reference Example 3, the area of ​​the middle conductive plate 20 is smaller than the area of ​​the upper conductive plate 16 and the area of ​​the lower conductive plate 18. In other words, the area of ​​the upper conductive plate 16 and the area of ​​the lower conductive plate 18 are larger than the area of ​​the middle conductive plate 20. As described above, the upper conductive plate 16 and the lower conductive plate 18 are exposed on the upper surface 30a or the lower surface 30b of the package body 30, and function as heat sinks. Therefore, if the area of ​​the upper conductive plate 16 and the area of ​​the lower conductive plate 18 are larger, the heat of each semiconductor element 12, 14 is efficiently released to the outside of the semiconductor device 300 via the upper conductive plate 16 and the lower conductive plate 18. However, it is also possible as shown in FIG. Fig.35As shown, in a semiconductor device 300' of a modified example according to Reference Example 3, the area of ​​the intermediate conductive plate 20 is larger than the area of ​​the upper conductive plate 16 and the area of ​​the lower conductive plate 18. According to this structure, since the heat capacity of the intermediate conductive plate 20 increases, the temperature rise of the intermediate conductive plate 20 can be suppressed.

[0119] In the semiconductor device 300 of Reference Example 3, both the first semiconductor element 12 and the second semiconductor element 14 are electrically connected to the intermediate conductive plate 20 at the first main electrodes 12b and 14b, and are electrically connected to the upper conductive plate 16 or the lower conductive plate 18 at the second main electrodes 12c and 14c. As described above, the area of ​​the second main electrodes 12c and 14c is larger than the area of ​​the first main electrodes 12b and 14b. Therefore, the heat released to the outside by each semiconductor element 12 and 14 through the second main electrodes 12c and 14c is larger than the heat released through the first main electrodes 12b and 14b. In addition, since the intermediate conductive plate 20 receives heat from both the first semiconductor element 12 and the second semiconductor element 14, its temperature tends to rise. Therefore, if both the first semiconductor element 12 and the second semiconductor element 14 are connected to the intermediate conductive plate 20 at the first main electrodes 12b and 14b where the heat dissipation is small, the temperature rise of the intermediate conductive plate 20 can be suppressed. In addition, you can Fig.36 As shown in another modified example of the semiconductor device 300 ″, only the second semiconductor element 14 (or the first semiconductor element 12 ) is connected to the intermediate conductive plate 20 at the first main electrodes 12 b and 14 b.

[0120] Reference Figure 37-Figure 39 , describing a semiconductor device 300A of a variation of reference example 3. The semiconductor device 300A of this variation also has two connecting components 70, which is different from the semiconductor device 300 of reference example 3 described above. In addition, the semiconductor device 300A of this variation does not have a second power terminal 34, which is also different from the semiconductor device 300 of reference example 3. The other structures of the semiconductor device 300A of this variation are common to or correspond to the semiconductor device 300 of reference example 3. Therefore, in Figure 37-Figure 39 In the figure, the same reference numerals are used for the structures that are common to or correspond to the semiconductor device 300 of reference example 3, and repeated descriptions are appropriately omitted here.

[0121] Each connecting member 70 is located inside the package 30 and is made of a conductor such as metal. One end of the connecting member 70 is connected to the first main circuit portion 24a of the first metal layer 24 of the intermediate conductive plate 20. The other end of the connecting member 70 is connected to the lower conductive plate 18. Thus, the first main circuit portion 24a of the intermediate conductive plate 20 is electrically connected to the lower conductive plate 18 via each connecting member 70. According to this structure, Fig.39As shown, the first semiconductor element 12 and the second semiconductor element 14 can be connected in series inside the package 30. Therefore, the second power terminal 34 is omitted. In addition, the fourth power terminal 38 may be omitted without omitting the second power terminal 34.

[0122] The semiconductor device 300A of this modification has two connection components 70, but the number of connection components 70 is not limited to 2. The semiconductor device 300A may have a single connection component 70 or three or more connection components 70. In addition, the first semiconductor element 12 and the second semiconductor element 14 may be connected in parallel inside the package 30 by changing the position connected by the connection component 70.

Claims

1. A semiconductor device comprising: An upper conductive plate, a middle conductive plate and a lower conductive plate arranged in a stacked configuration; a first semiconductor element, which is entirely located between the upper conductive plate and the intermediate conductive plate and is electrically connected to the upper conductive plate and the intermediate conductive plate, respectively; and The second semiconductor element is entirely located between the intermediate conductive plate and the lower conductive plate and is electrically connected to the intermediate conductive plate and the lower conductive plate, respectively. One of the area of ​​the upper conductive plate and the area of ​​the lower conductive plate is smaller than the area of ​​the middle conductive plate, The other of the area of ​​the upper conductive plate and the area of ​​the lower conductive plate is larger than the area of ​​the middle conductive plate. The first semiconductor element and the second semiconductor element each have a first main electrode and a second main electrode having a larger area than the first main electrode. The first semiconductor element is connected to the upper conductive plate at the first main electrode and is connected to the intermediate conductive plate at the second main electrode. The second semiconductor element is connected to the intermediate conductive plate at the first main electrode and is connected to the lower conductive plate at the second main electrode. The upper conductive plate, the middle conductive plate, and the lower conductive plate are each a metal plate.

2. The semiconductor device according to claim 1, wherein The area of ​​the upper conductive plate is smaller than that of the middle conductive plate, and the area of ​​the lower conductive plate is larger than that of the middle conductive plate.

3. The semiconductor device according to claim 1, wherein The area of ​​the upper conductive plate is larger than that of the middle conductive plate, and the area of ​​the lower conductive plate is smaller than that of the middle conductive plate.

4. The semiconductor device according to any one of claims 1 to 3, wherein: A thickness of one of the upper conductive plate and the lower conductive plate is greater than a thickness of the other of the upper conductive plate and the lower conductive plate.

5. The semiconductor device according to any one of claims 1 to 3, wherein: A package is further provided, which packages the first semiconductor element and the second semiconductor element and integrally holds the upper conductive plate, the intermediate conductive plate, and the lower conductive plate.

6. A semiconductor device, It has: An upper conductive plate, a middle conductive plate and a lower conductive plate arranged in a stacked configuration; a first semiconductor element, which is entirely located between the upper conductive plate and the intermediate conductive plate and is electrically connected to the upper conductive plate and the intermediate conductive plate, respectively; and The second semiconductor element is entirely located between the intermediate conductive plate and the lower conductive plate and is electrically connected to the intermediate conductive plate and the lower conductive plate, respectively. When the upper conductive plate, the middle conductive plate, and the lower conductive plate are projected onto a plane parallel to them, at least a first region, a second region, and a third region are divided on the plane. The first area is an area where the upper conductive plate, the middle conductive plate and the lower conductive plate are projected. The second area is an area where only two conductive plates, namely, one of the upper conductive plate and the lower conductive plate, and the middle conductive plate are projected. The third area is an area where only one of the upper conductive plate and the lower conductive plate is projected. The first semiconductor element and the second semiconductor element each have a first main electrode and a second main electrode having a larger area than the first main electrode. The first semiconductor element is connected to the upper conductive plate at the first main electrode and is connected to the intermediate conductive plate at the second main electrode. The second semiconductor element is connected to the intermediate conductive plate at the first main electrode and is connected to the lower conductive plate at the second main electrode. The upper conductive plate, the middle conductive plate, and the lower conductive plate are each a metal plate.

7. The semiconductor device according to claim 6, wherein: At least two of the upper conductive plate, the middle conductive plate, and the lower conductive plate have equal areas.

8. The semiconductor device according to claim 6 or 7, wherein: A package is further provided, which packages the first semiconductor element and the second semiconductor element and integrally holds the upper conductive plate, the intermediate conductive plate, and the lower conductive plate.

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