Detection device, detection method and radar system

Abstract

The present invention relates to the field of radar technology, and in particular to a detection device, a detection method and a radar system. The detection device provided by the present invention includes: an input circuit, connected to a synthesizer to receive a frequency modulated continuous wave signal, and down-converting and shaping the frequency modulated continuous wave signal to generate a first clock signal; a ring register link, used to update the value of the corresponding data bit in the indication data according to the clock edge of the first clock signal; a processing circuit, based on the second clock signal, samples the indication data to obtain a measurement value, and provides detection result data based on the measurement value to indicate whether the frequency of the frequency modulated continuous wave signal is normal. Among them, the frequency of the first clock signal changes linearly within the detection interval, the frequency of the second clock signal is less than the frequency of the first clock signal, and the measurement value is controlled by the number of clock edges of the first clock signal within the detection interval. The radar system, detection device and detection method provided by the present disclosure can be used to determine whether the frequency of the frequency modulated continuous wave signal is normal.

Description

Technical Field

[0001] The present invention relates to the field of radar technology, and more specifically, to a detection device, a detection method and a radar system. Background Art

[0002] In the radar system, the frequency difference between the echo signal and the transmitted signal can be obtained by transmitting and receiving frequency modulated continuous wave (Frequency Modulated Continuous Wave, referred to as FMCW), so as to obtain the distance, speed and other information of the target according to the frequency difference. This modulation method using frequency modulated continuous wave has outstanding advantages such as simple structure, simple signal processing process, low cost and low power, so it has been widely used in the fields of vehicle-mounted radar.

[0003] Since the frequency of the FM continuous wave changes continuously during the operation of the radar system, the frequency state of the FM continuous wave can be used to determine whether modules such as the phase-locked loop in the radar system are in a normal working state.

[0004] Based on this, it is expected to provide a frequency detection scheme of a frequency modulated continuous wave to determine whether the radar system and the synthesizer are in normal operation. Summary of the invention

[0005] In order to solve the problems existing in the above-mentioned prior art, the present invention provides a radar system, a detection method and a detection device, which can monitor the frequency of a frequency modulated continuous wave signal in real time, so as to determine whether the frequency change of the frequency modulated continuous wave signal is in a normal state.

[0006] According to a first aspect of an embodiment of the present invention, a detection device of a synthesizer is provided, wherein the synthesizer is used to output a frequency modulated continuous wave signal, and the detection device includes: an input circuit connected to the synthesizer to receive the frequency modulated continuous wave signal, and down-converting and shaping the frequency modulated continuous wave signal to generate a first clock signal in a square wave form, wherein the frequency of the first clock signal changes linearly within a detection interval; a ring register link connected to the input circuit to receive the first clock signal, and used to provide indication data, and update the value of the corresponding data bit in the indication data according to each clock edge of the first clock signal; and a processing circuit connected to the ring register link, and used to: sample the indication data based on a second clock signal to obtain a measurement value, and provide detection result data according to the measurement value, wherein the detection result data characterizes whether the frequency of the frequency modulated continuous wave signal is normal, wherein the frequency of the second clock signal is less than the frequency of the first clock signal, and the measurement value is controlled by the number of clock edges of the first clock signal occurring in the detection interval.

[0007] Optionally, for each of the detection intervals, the ring register link is suitable for: cyclically updating the values ​​of each data bit of the indication data in sequence under the triggering of each of the clock edges; and updating the value of a corresponding data bit in the indication data under the triggering of each of the clock edges.

[0008] Optionally, the processing circuit includes: a sampling unit connected to the ring register link, and used to: sample the indication data based on the second clock signal to obtain the starting value and the ending value of the indication data within the detection interval, and the detection interval corresponds to one or more sampling cycles of the second clock signal; a storage unit, used to pre-store a relationship lookup table to indicate the sequence numbers corresponding to multiple state values ​​of the indication data under the output logic order of the ring register link, the multiple state values ​​include the starting value and the ending value, and the sequence number includes a first sequence number corresponding to the starting value and a second sequence number corresponding to the ending value; and a first judgment unit, used to obtain the measurement value according to the difference between the first sequence number and the second sequence number, and to judge whether the offset between the measurement value and the preset expected value of the detection interval is greater than a first threshold value, if so, the first judgment unit sets the first bit result value of the detection result data to a valid state to indicate that the average value of the frequency of the frequency modulated continuous wave signal within the detection interval does not meet the expected range, if not, the first judgment unit sets the first bit result value to an invalid state to indicate that the average value of the frequency of the frequency modulated continuous wave signal within the detection interval meets the expected range.

[0009] Optionally, the preset expected value is: the obtained data value is calculated based on the total number of the multiple state values ​​and the expected number of occurrences of the clock edge of the first clock signal in the detection interval.

[0010] Optionally, for each detection interval: the measured value is equal to the difference, the preset expected value is equal to the remainder obtained by dividing twice the set value corresponding to the detection interval by the total number of the multiple state values, and the set value is equal to the product of the expected average value of the frequency of the first clock signal within the detection interval and the duration of the detection interval.

[0011] Optionally, the processing circuit also includes: a counter, used to provide a count value according to the first-bit result value, the counter responds to the first-bit result value in a valid state to add 1 to the count value, and responds to the first-bit result value in an invalid state to reset the count value to an initial value; and a comparator, used to determine whether the count value is greater than a second threshold value, if so, the comparator sets the second-bit result value of the detection result data to a valid state to characterize that the frequency change of the frequency modulated continuous wave signal is in an abnormal state, if not, the comparator sets the second-bit result value to an invalid state to characterize that the frequency change of the frequency modulated continuous wave signal is in a normal state.

[0012] Optionally, the synthesizer includes: a phase-locked loop structure, including a voltage-controlled oscillator, the voltage-controlled oscillator generates the frequency-modulated continuous wave signal according to a frequency control voltage, and the frequency of the frequency-modulated continuous wave signal varies with the voltage value of the frequency control voltage.

[0013] For example, when the calculated offset is less than / equal to the first threshold, the detection device disclosed in the embodiment of the present invention can determine that the phase-locked loop structure is in a normal working state, otherwise it is in an abnormal working state; and in order to improve the accuracy of the judgment, the detection device disclosed in the embodiment of the present invention can perform judgment processing for multiple detection intervals respectively, and only in all or a preset proportion of the detection intervals, the offset is less than / equal to the above-mentioned first threshold, and at the same time shows a certain regular change or the change amplitude is small, the phase-locked loop structure is judged to be in a normal working state. Among them, the judgment of the change amplitude can be set based on the actual accuracy requirements.

[0014] In addition, for a phase-locked loop structure in an abnormal working state, the detection device provided in an embodiment of the present invention can also determine whether the phase-locked loop structure is in a locked state or an unstable state (that is, in the embodiment of the present application, the abnormal working state may include a locked state and an unstable state) by further analyzing and judging the change law of the offset obtained in different detection intervals. For example, when the offset obtained in adjacent sampling periods (corresponding to adjacent detection intervals) changes randomly or changes by a large amplitude, it can be determined that the phase-locked loop structure is in an unstable state in an abnormal state at this time, that is, it can be considered that some components in the phase-locked loop structure may be damaged at this time; otherwise, it can be considered that the phase-locked loop structure is in a locked state in an abnormal state at this time.

[0015] According to a second aspect of an embodiment of the present invention, a radar system is provided, including any one of the detection devices and synthesizers provided in the embodiments of the present invention; and a radar transceiver, which provides a transmission signal and / or processes an echo signal based on the frequency modulated continuous wave signal.

[0016] According to a third aspect of an embodiment of the present invention, a detection method for a synthesizer is also provided, wherein the synthesizer is used to output a frequency modulated continuous wave signal, and the detection method includes: performing frequency reduction and shaping processing on the frequency modulated continuous wave signal to generate a first clock signal in a square wave form, wherein the frequency of the first clock signal changes linearly within a detection interval; providing indication data having multiple data bits, and updating corresponding data bits in the indication data according to the clock edge of the first clock signal; sampling the indication data based on a second clock signal to obtain a measurement value; and providing detection result data according to the measurement value, wherein the detection result data characterizes whether the frequency of the frequency modulated continuous wave signal is normal, wherein the frequency of the second clock signal is less than the frequency of the first clock signal, and the measurement value is controlled by the number of clock edges of the first clock signal occurring in the detection interval.

[0017] Optionally, the step of updating the corresponding data bits in the indication data according to the clock edge of the first clock signal includes: cyclically updating the values ​​of each data bit of the indication data in sequence under the triggering of each clock edge; and updating the value of a corresponding data bit in the indication data under the triggering of each clock edge.

[0018] Optionally, the steps of sampling the indication data based on the second clock signal to obtain the measurement value, and providing the detection result data according to the measurement value include: sampling the indication data based on the second clock signal to obtain the starting value and the ending value of the indication data within the detection interval, and the detection interval corresponds to one or more sampling periods of the second clock signal; obtaining a relationship lookup table, the relationship lookup table indicating the sequence numbers corresponding to multiple state values ​​of the indication data in the output logical order, the multiple state values ​​include the starting value and the ending value, and the sequence number includes a first sequence number corresponding to the starting value and a second sequence number corresponding to the ending value; obtaining the measurement value according to the difference between the first sequence number and the second sequence number; judging whether the offset between the measurement value and the preset expected value of the detection interval is greater than a first threshold value, and if so, setting the first bit result value of the detection result data to a valid state to indicate that the average value of the frequency of the frequency modulated continuous wave signal within the detection interval does not meet the expected range, and if not, setting the first bit result value to an invalid state to indicate that the average value of the frequency of the frequency modulated continuous wave signal within the detection interval meets the expected range.

[0019] Optionally, the detection method further includes: calculating the preset expected value based on the total number of the multiple state values ​​and the expected number of occurrences of the clock edge of the first clock signal within the detection interval.

[0020] Optionally, for each detection interval: the measured value is equal to the difference, the preset expected value is equal to the remainder obtained by dividing twice the set value corresponding to the detection interval by the total number of the multiple state values, and the set value is equal to the product of a preset frequency average value of the first clock signal in the detection interval and the duration of the detection interval.

[0021] Optionally, the step of sampling the indication data based on the second clock signal to obtain the measurement value, and providing the detection result data according to the measurement value also includes: providing a count value according to the first-bit result value, and adding 1 to the count value when the first-bit result value is in a valid state, and restoring the count value to an initial value when the first-bit result value is in an invalid state; and judging whether the count value is greater than a second threshold value, if so, setting the second-bit result value of the detection result data to a valid state to characterize that the frequency change of the frequency modulated continuous wave signal is in an abnormal state, if not, setting the second-bit result value to an invalid state to characterize that the frequency change of the frequency modulated continuous wave signal is in a normal state.

[0022] According to the radar system, detection device and detection method provided by the embodiment of the present invention, a first clock signal in the form of a square wave is obtained by downconverting and shaping the frequency modulated continuous wave signal, the value of the corresponding data bit in the indication data is updated according to each clock edge of the first clock signal, and the indication data is sampled based on the second clock signal to obtain a measurement value of the number of clock edges controlled by the first clock signal, so that the detection result data can be obtained according to the measurement value to characterize whether the frequency of the frequency modulated continuous wave signal is normal, thereby realizing the detection of the frequency of the frequency modulated continuous wave signal. In the radar system of the embodiment of the present invention, since the frequency of the frequency modulated continuous wave signal is controlled by the synthesizer, the detection result data provided by the detection device can indicate whether the synthesizer is working abnormally and whether the radar system is working abnormally. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0024] Figure 1 A schematic diagram showing the structure of a radar system according to an embodiment of the present invention is shown;

[0025] Figure 2 Show Figure 1 A schematic structural diagram of an embodiment of a synthesizer;

[0026] Figure 3 A schematic diagram showing waveforms of a frequency modulated continuous wave signal, a first clock signal and a frequency control voltage in an embodiment of the present invention is shown;

[0027] Figure 4A schematic block diagram showing a detection device according to an embodiment of the present invention;

[0028] Figure 5 A schematic diagram showing the structure of a ring register link according to an embodiment of the present invention;

[0029] Figure 6 Show Figure 5 Schematic diagram of the circuit structure of each register in;

[0030] Figure 7 Show Figure 4 A schematic block diagram of an implementation of a processing circuit in FIG.

[0031] Figure 8 Show Figure 4 A schematic block diagram of another implementation of the processing circuit;

[0032] Fig. 9 A schematic flow chart showing a detection method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0034] System Overview

[0035] Figure 1 A schematic structural diagram of a radar system according to an embodiment of the present invention is shown. Figure 2 Show Figure 1 A schematic structural diagram of an embodiment of a synthesizer in FIG. Figure 3 A schematic diagram showing waveforms of a frequency modulated continuous wave signal, a first clock signal and a frequency control voltage in an embodiment of the present invention is shown.

[0036] like Figure 1 As shown, the radar system of the embodiment of the present invention includes: a transceiver antenna, a receiving channel, a transmitting channel, a synthesizer, a signal processing module and a detection device. Among them, the transceiver antenna, the receiving channel, the transmitting channel and the signal processing module serve as a radar transceiver, and the radar transceiver provides a transmitting signal and / or processes an echo signal according to the frequency modulated continuous wave signal provided by the synthesizer.

[0037] The following will be based on Figures 1 to 3 The various parts of the radar system based on the frequency modulated continuous wave system in this embodiment are described. However, the embodiment of the present invention is not limited thereto, and one / some unmentioned conventional structures or modules may also be included in the radar system in the embodiment of the present invention.

[0038] (1) Transceiver antenna

[0039] The transceiver antenna includes a transmitting antenna 1 and a receiving antenna 2. The transmitting antenna 1 provides a spatially radiated electromagnetic wave based on the transmitting signal, and the electromagnetic wave is reflected on the surface of the target object. The reflected electromagnetic wave is captured by the receiving antenna, so that the receiving antenna 2 obtains an echo signal. Since in the radar system 100 of the embodiment of the present invention, the transmitting signal is a frequency modulated continuous wave with a continuously changing frequency, the radar system 100 of the frequency modulated continuous wave system can obtain information such as the distance and speed of the target object based on the frequency difference between the transmitting signal and the echo signal, wherein the speed of the target object can be obtained, for example, by calculating multiple distance measurements.

[0040] (2) Synthesizer

[0041] The synthesizer 6 is used to generate a frequency modulated continuous wave signal S with a continuously changing frequency. FM The frequency of the frequency modulated continuous wave signal changes in a trend such as a triangular wave or a sawtooth wave, and has a linear change trend within the detection interval. FM It can be a periodic signal or a non-periodic signal, and this application does not impose any limitation on this.

[0042] As an optional embodiment, the synthesizer 6 is, for example, Figure 2 The phase-locked loop structure (Phase Locked Loop, PLL for short) shown includes a charge pump (Charge Pump, CP for short) 610, a loop filter (Loop Filter, LP for short) 620, a voltage-controlled oscillator (Voltage Controlled Oscillator, VCO for short) 630, a feedback divider 640, and a phase frequency detector (PFD for short) 650 and other modules.

[0043] The frequency detector 650, the charge pump 610, the loop filter 620 and the voltage controlled oscillator 630 are connected in cascade in sequence, and the output end of the voltage controlled oscillator 630 provides an output frequency modulated continuous wave signal S FM The feedback divider 640 receives the frequency modulated continuous wave signal S output by the voltage controlled oscillator 630. FM , for the frequency modulated continuous wave signal S FM The frequency is divided to obtain the down-frequency scanning signal S FM_div , and the down-conversion scanning signal S FM_div It is provided to the phase frequency detector 650, thereby forming a feedback control loop in the phase locked loop structure.

[0044] The feedback divider 640 is, for example, a multi-modulus divider (MMD), which can divide the frequency modulated continuous wave signal S according to the frequency division ratio set by the mode control signal. FM The frequency is divided to obtain the down-frequency scanning signal S FM_div , thus realizing the programmable frequency division function. When the frequency division ratio set by the mode control signal changes continuously, the frequency modulated continuous wave signal S FM The frequency can be varied continuously.

[0045] The frequency and phase detector 650 detects the frequency and phase of the reference signal Fref and the down-converted scanning signal S FM_div The frequency and phase of the reference signal Fref are compared to generate a first state signal Qa and a second state signal Qb representing the comparison result. As an example, the reference signal Fref may be provided by a crystal oscillator, or by other circuits or modules, and the present application does not limit this.

[0046] The charge pump 610 generates an analog voltage signal Vo according to the received first state signal Qa and second state signal Qb. The first state signal Qa and the second state signal Qb are used to increase and decrease the voltage value of the analog voltage signal Vo, respectively.

[0047] The analog voltage signal Vo is filtered by the loop filter 620 to obtain a frequency control voltage Vc, so that the voltage controlled oscillator 630 generates a frequency modulated continuous wave signal S under the control of the frequency control voltage Vc. FM , the frequency modulated continuous wave signal S FM The frequency of corresponds to the voltage value of the frequency control voltage Vc. Under the control of the above phase-locked loop structure, Figure 3 As shown, the voltage value of the frequency control voltage Vc has a linear change trend in each linear interval Tchrip_up. For example, the frequency control voltage Vc increases linearly from a preset voltage at the start time of each linear interval. The frequency modulated continuous wave signal provided by the voltage controlled oscillator 630 under the action of the preset voltage has a minimum frequency F L At the end of each linear interval, the frequency control voltage Vc reaches the maximum voltage, and the frequency modulated continuous wave signal provided by the voltage controlled oscillator 630 under the action of the maximum voltage has a maximum frequency F H In the waiting interval between every two adjacent linear intervals, the frequency control voltage Vc is reset to a preset voltage. Therefore, the frequency modulated continuous wave signal S provided by the voltage controlled oscillator 630 is FM The frequency changes linearly with the frequency control voltage Vc in each linear interval.

[0048] In some optional embodiments, the duration of each linear interval Tchrip_up is equal and the duration of each waiting interval is equal, and each linear interval and each waiting interval are alternately distributed in the time domain, so that the frequency control voltage Vc has a frame period and presents a triangular wave or a sawtooth wave within each frame period.

[0049] This embodiment describes the synthesizer 6 by taking the above-mentioned phase-locked loop structure as an example. However, the synthesizer of the embodiment of the present invention is not limited thereto. The synthesizer 6 may also be implemented by other circuits capable of generating a frequency-modulated continuous wave signal.

[0050] When the radar system is working, it must be ensured that the phase-locked loop structure including the voltage-controlled oscillator is in a normal working state. Therefore, how to detect the working state of the phase-locked loop structure (or synthesizer of other structures) is the key to ensure the normal operation of the radar system. The present invention monitors the working state of the phase-locked loop structure by detecting the frequency-modulated continuous wave signal after amplitude reduction and shaping, so as to judge whether the synthesizer and the radar system are in a normal working state.

[0051] (3) Receiving channel and transmitting channel

[0052] The transmitting channel 3 and the receiving channel 4 are coupled to the transmitting antenna 1 and the receiving antenna 2 respectively. The transmitting channel 3 is connected to the synthesizer 6 to receive the frequency modulated continuous wave signal S FM , and the transmitting channel 3 is based on the frequency modulated continuous wave signal S FM Provide a frequency modulated continuous wave transmission signal to the transmitting antenna 1, and FM The receiving channel 4 is connected to the receiving antenna 2 to receive the echo signal, and performs filtering and other processing on the echo signal to generate the second signal S2.

[0053] (4) Mixing unit

[0054] The frequency mixing unit 5 is connected to the transmitting channel 3 and the receiving channel 4 to receive the first signal S1 and the second signal S2, so as to obtain the beat signal S according to the first signal S1 and the second signal S2. D The beat signal S D The frequency of is the difference between the frequency of the first signal S1 and the frequency of the second signal S2, which can represent the difference between the time when the echo signal is received and the time when the transmission signal is transmitted. This difference is related to the distance, speed and other information of the target. D The frequency is proportional to the distance between the target and the radar.

[0055] (5) Signal processing module

[0056] The signal processing module 8 receives the beat signal S provided by the mixing unit 5 D , so that according to the beat signal SD The detection result Sdata includes information such as the distance and speed of the target object relative to the radar system.

[0057] The signal processing module 8 includes, for example, a D Modules such as an analog-to-digital converter that generates a corresponding digital signal and a calculation unit used to perform calculations on the digital signal.

[0058] (6) Detection device

[0059] The radar system of the embodiment of the present invention further comprises a detection device 7, which detects the frequency modulated continuous wave signal S provided by the synthesizer 6. FM Conduct testing.

[0060] like Figure 2 As shown, the detection device 7 can be coupled to the output end of the synthesizer 6 to receive the frequency modulated continuous wave signal S FM , used for the frequency modulated continuous wave signal S FM The frequency modulated continuous wave signal S is down-converted and shaped to obtain the first clock signal Sclk. FM The frequency of the first clock signal Sclk is in a set ratio N div , and the first clock signal Sclk has a frequency less than the frequency modulated continuous wave signal S FM The square wave signal, thus the detection result data obtained by the detection device 7 detecting the frequency of the first clock signal Sclk can also represent the frequency modulated continuous wave signal S FM The frequency of the synthesizer 6 generates a frequency modulated continuous wave signal S FM In practical applications, the frequency is usually relatively high (for example, in the frequency range of 30 GHz to 300 GHz). Therefore, the detection device 7 can detect the frequency of the detector according to the set ratio N. div The first clock signal Sclk obtained by frequency reduction is detected to indirectly realize the frequency modulated continuous wave signal S FM The frequency of the detection device 7 is monitored, thereby improving the detection accuracy and making the working frequency range of the detection device 7 unnecessary, that is, reducing the performance requirements of the detection device 7; on the other hand, the frequency modulated continuous wave signal S FM The detection device 7 converts the frequency modulated continuous wave signal S into a sine wave signal. FM The first clock signal Sclk shaped into a square wave form further enables the detection device 7 to achieve more accurate frequency detection.

[0061] In addition, the detection device 7 is also used to provide indication data Dstate, and update the indication data Dstate according to each clock edge of the first clock signal Sclk (that is, the level change edge of the first clock signal Sclk, which may include each rising edge and / or each falling edge) within the detection interval, so that the frequency modulated continuous wave signal S in the detection interval can be determined according to the indication data Dstate. FM For example, the detection device 7 may update the corresponding data bit in the indication data Dstate at each rising edge and each falling edge of the first clock signal Sclk, or may update the corresponding data bit in the indication data Dstate only at each rising edge or each falling edge of the first clock signal Sclk.

[0062] It should be noted that, in the embodiments of the present invention, Figure 3 The linear interval Tchrip_up shown can be directly used as the detection interval. However, the embodiment of the present invention is not limited thereto, and in other embodiments, the detection interval can also be a part of the linear interval Tchrip_up.

[0063] Figure 4 A schematic block diagram of a detection device according to an embodiment of the present invention is shown below. Figure 4 The detection device 7 of this embodiment is described in detail.

[0064] like Figure 4 As shown, the detection device 7 includes an input circuit 7300 , a ring register link 7100 and a processing circuit 7200 .

[0065] The input circuit 7300 is used to input the frequency modulated continuous wave signal S FM The shaping process and the frequency reduction process are performed to generate the first clock signal Sclk. The shaping process can be implemented by a circuit structure such as a buffer and an inverter so that the first clock signal Sclk has a square wave waveform; the frequency reduction process can be implemented by a frequency divider with a fixed frequency division ratio or an adjustable frequency division ratio so that the frequency modulated continuous wave signal S FM The frequency of the first clock signal Sclk is in a set ratio N div , and the first clock signal Sclk satisfies the operating frequency of the ring register link 7100. It should be noted that the frequency reduction process can be performed before the shaping process or after the shaping process, and this application does not limit this.

[0066] The ring register link 7100 is used to provide indication data Dstate having multiple data bits, and update each data bit D1-Dn in the indication data Dstate according to the clock edge of the first clock signal Sclk, where n is a natural number greater than 1.

[0067] For example, when a rising edge appears in the first clock signal Sclk, the logic state of a corresponding data bit Di in the indication data Dstate changes (from 1 to 0 or from 0 to 1, referred to as the i-th update), and then, when a falling edge appears in the first clock signal Sclk, the logic state of another data bit Dj in the indication data Dstate after the i-th update changes (referred to as the j-th update), and so on, it can be known that: in each frame period, the first clock signal Sclk has a rising edge and a falling edge, and the indication data Dstate can be updated twice, that is, the indication data Dstate has two corresponding data bits updated. Wherein, i and j are non-zero natural numbers less than or equal to n, respectively.

[0068] In some optional embodiments, when i is less than n, j is equal to i+1, and when i is equal to n, j is equal to 1, so that each data bit D1 to Dn in the indication data Dstate can be cyclically updated according to the clock edge of the first clock signal Sclk.

[0069] In the above description, the i-th update of the indication data Dstate occurs when the first clock signal Sclk has a rising edge. It should be noted that in some other equivalent embodiments, the i-th update of the indication data Dstate may occur when the first clock signal Sclk has a falling edge, and accordingly, the j-th update of the indication data Dstate may occur when the first clock signal Sclk has a rising edge. In addition, in the description of the various embodiments of the present invention, the update of a data bit in the indication data Dstate refers to the update of the logic value of the data bit from 1 to 0 or from 0 to 1.

[0070] In this document, various data values ​​that may be provided by the indication data Dstate during the continuous updating process are referred to as various state values ​​of the indication data Dstate.

[0071] The processing circuit 7200 is connected to the output end of the ring register link 7100 to receive the indication data Dstate. The processing circuit 7200 is used to obtain the preset expected value of the indication data Dstate corresponding to each detection interval, and determine whether the average value of the frequency of the first clock signal Sclk in the detection interval meets the expected range according to the starting value and the end value of the indication data Dstate in each detection interval and the preset expected value corresponding to the detection interval.

[0072] In the linear interval, the processing circuit 7200 can sample the indication data Dstate under the triggering of the clock edge (rising edge or falling edge) of the second clock signal clk_cs to obtain the starting value and the ending value of the indication data Dstate in each detection interval. In this case, each detection interval corresponds to a corresponding sampling period in the second clock signal clk_cs, and the starting time and the ending time of each detection interval correspond to two adjacent and co-directional clock edges of the second clock signal clk_cs. The second clock signal clk_cs is set to have a frequency less than the first clock signal Sclk. This embodiment will be described in detail below, however, the embodiment of the present invention is not limited thereto, and each detection interval is not limited to corresponding to a sampling period of the second clock signal, but may also correspond to multiple consecutive sampling periods.

[0073] Specifically, in each detection interval, the processing circuit 7200 can sample and obtain the starting value of the indication data Dstate at the starting time of the detection interval. With the appearance of the clock edge of the first clock signal Sclk, each data bit D1-Dn in the indication data Dstate is cyclically updated; the processing circuit 7200 obtains the ending value of the indication data Dstate at the end time of the detection interval. It can be seen that the difference between the ending value and the starting value is related to the number of times the indication data Dstate is updated, that is, related to the total number of clock edges that appear in the first clock signal Sclk in the detection interval. Therefore, the difference between the starting value and the ending value of the indication data Dstate in the detection interval is related to the average frequency of the first clock signal Sclk in the detection interval. Based on this, the processing circuit 7200 can obtain a measurement value according to the difference between the starting value and the ending value of the indication data Dstate in each detection interval, and provide the detection result data Sout according to the preset expected value corresponding to the measurement value and the sampling period, so that the detection result data Sout can characterize whether the average value of the frequency of the first clock signal Sclk in each detection interval meets the expected range. If so, it means that the frequency modulated continuous wave signal S FM The frequency of the detection interval is in a normal state. If not, it means that the frequency modulated continuous wave signal S FM The frequency is abnormal within the detection range.

[0074] It should be noted that the "start value" disclosed herein refers to the data value indicating the data Dstate at the start time of the detection interval; the "end value" refers to the data value indicating the data Dstate at the end time of the detection interval. The start value and the end value are respectively one of the state values ​​indicating the data Dstate.

[0075] In some optional embodiments, the preset expected value can represent the expected number of occurrences of the clock edge of the first clock signal Sclk in the detection interval, for example, the expected average value of the frequency of the first clock signal Sclk in the detection interval. Based on this, the processing circuit 7200 can calculate the predicted end value of the indication data Dstate in the detection interval according to the starting value of the indication data in the detection interval, the preset expected value corresponding to the detection interval, and the duration of the detection interval; then, the processing circuit 7200 can compare the end value obtained by sampling with the predicted end value obtained by calculation. If the two are consistent within the allowable error range, it means that the average value of the frequency of the first clock signal Sclk in the detection interval meets the expected range. If the two are inconsistent within the allowable error range, it means that the average value of the frequency of the first clock signal Sclk in the detection interval does not meet the expected range. The synthesizer 6 (such as Figure 1 as shown) and the radar system is not functioning properly.

[0076] In some other optional embodiments, the preset expected value may be a value calculated based on the total number of state values ​​that may be provided by the specified data Dstate and the expected number of occurrences of the clock edge of the first clock signal Sclk in the detection interval. Based on this, for each detection interval, the processing circuit 7200 may determine whether the average value of the frequency of the first clock signal Sclk in the detection interval satisfies the expected range based on the difference between the starting value and the ending value of the first clock signal Sclk in the detection interval and the preset expected value corresponding to the detection interval. This embodiment will be described in detail later and will not be described here.

[0077] exist Figure 4 In the illustrated embodiment, the ring register link 7100 has a clock terminal, which directly receives the first clock signal Sclk, so that the ring register link uses the first clock signal Sclk as the clock signal clk. As mentioned above, since the first clock signal Sclk is a frequency modulated continuous wave signal S FM The frequency-modulated continuous wave signal S FM The known set ratio N between the frequency of the first clock signal Sclk div And the detection result data Sout provided by the processing circuit 7200 is used to obtain the frequency modulated continuous wave signal S FM Whether the average value of the frequency in the detection interval meets the expected frequency range, that is, the detection result data Sout provided by the processing circuit 7200 can also characterize the frequency modulated continuous wave signal S FM When the detection result data Sout indicates that the average value of the frequency of the first clock signal Sclk in the detection interval meets the expected range, it means that the synthesizer works normally and the frequency modulated continuous wave signal SFM The frequency change is correct, and the radar system can work normally at this time; when the detection result data Sout indicates that the average value of the frequency of the first clock signal Sclk in the detection interval does not meet the expected range, it means that the synthesizer is working abnormally and the frequency modulated continuous wave signal S FM The frequency change does not conform to the expected range, and the radar system works abnormally.

[0078] The ring register link 7100 and the processing circuit 7200 of the embodiment of the present invention are described in detail below.

[0079] Ring register link

[0080] Figure 5 A schematic diagram showing the structure of a ring register link according to an embodiment of the present invention is shown. Figure 6 Show Figure 5 The circuit structure diagram of each register in the following table is shown in Figure 1. Figure 5 and Figure 6 The ring register link of the embodiment of the present invention is described in detail.

[0081] like Figure 5 As shown, the ring register chain 7100 includes a plurality of registers 7110 cascaded in sequence, and the last stage of registers is cascaded before the first stage of registers to form a ring chain.

[0082] Each level of register 7110 generates the output signal DOUT of this level and the corresponding data bits in the indication data Dstate according to the clock signal clk, the inverted clock signal clkb and the input signal DIN of this level. Each level of register 7110 corresponds to different data bits in the indication data Dstate.

[0083] The ring register chain 7100 further includes an odd number of inverters INV1 cascaded between the first-stage register and the last-stage register, so that the first-stage register can obtain the input signal of the current stage according to the inverted signal of the output signal provided by the last-stage register. Each stage register other than the first-stage register obtains the input signal of the current stage according to the output signal provided by the register cascaded in the previous stage.

[0084] The ring register chain 7100 further includes an odd number of inverters INV0 for generating an inverted clock signal clkb according to the clock signal clk, so that the inverted clock signal clkb is an inverted signal of the clock signal clk.

[0085] In an optional embodiment, if Figure 5As shown, the number of data bits n indicating the data Dstate is a non-zero even number, and each level of register 7110 corresponds to two corresponding adjacent data bits in the indication data Dstate. For example, the first level register 7110 is used to output the data bit D1 and the data bit D2 in the indication data Dstate, and the second level register 7110 is used to output the data bit D3 and the data bit D4 in the indication data Dstate, and so on.

[0086] As an example, each level of register 7110 can update the corresponding first data bit Dk in the indication data Dstate (output by the DF1 terminal of the register of this level) according to the rising edge of the clock signal clk, and update the corresponding second data bit Dp in the indication data Dstate (output by the DF2 terminal of the register of this level) according to the falling edge of the clock signal clk. Wherein, k and p are non-zero natural numbers less than or equal to n, and p is preferably equal to k+1.

[0087] In other embodiments, each level of register 7110 can update the corresponding first data bit Dk in the indication data Dstate according to the falling edge of the clock signal clk, and update the corresponding second data bit Dp in the indication data Dstate according to the rising edge of the clock signal clk. The principle is the same as the above embodiment and will not be repeated.

[0088] It should be noted that “updating a certain data bit” mentioned in this article refers to resetting the corresponding data bit according to the current state of each related signal, that is, updating the corresponding data bit in the indication data Dstate may or may not change the logical state of the data bit.

[0089] As an optional embodiment, Figure 6 As shown, each level of register 7110 includes at least two levels of sampling and holding modules. The number of cascaded sampling and holding modules in each level of register 7110 can be the same as the number of bits of the indication data corresponding to each level of register. In this embodiment, each level of register corresponds to 2 data bits, and each level of register includes a first level of sampling and holding module and a second level of sampling and holding module as an example for description, but the embodiment of the present application is not limited thereto.

[0090] like Figure 6 As shown, the first stage sampling and holding module 7111 samples the input signal DIN of the register at this stage in the sampling state to generate the transfer signal DZ, and the second stage sampling and holding module 7112 samples the transfer signal DZ in the sampling state to generate the output signal DOUT of the register at this stage.

[0091] The first stage sampling and holding module 7111 has a sampling state and a holding state, and enters the sampling state and the holding state alternately according to the clock signal clk. In the sampling state, the first stage sampling and holding module 7111 updates the transfer signal DZ according to the input signal DIN of the register of this stage; in the holding state, the first stage sampling and holding module 7111 keeps the transfer signal unchanged.

[0092] As an optional embodiment, the first-stage sampling and holding module 7111 may include a transmission gate controlled by the clock signal clk. The transmission gate includes, for example, field effect transistors M11 and M12, the sources of which are connected and receive the input signal DIN of the register 7110 at this stage, the drains of which are connected and provide the transfer signal DZ; the gates of the field effect transistors M11 and M12 receive the clock signal clk and the inverted clock signal clkb, respectively.

[0093] The first stage sampling and holding module 7111 may further include an even number of inverters (NOT gates) for buffering the input signal DIN input to the transmission gate and / or buffering the transfer signal DZ output by the transmission gate.

[0094] The second-stage sampling and holding module 7112 may have the same circuit structure as the first-stage sampling and holding module 7111. The second-stage sampling and holding module 7112 may include, for example, a transmission gate composed of field effect transistors M21 and M22. The sources of the field effect transistors M21 and M22 are connected and receive the transmission signal DZ provided by the first-stage sampling and holding module 7111. The drains of the field effect transistors M21 and M22 are connected and provide the output signal DOUT of the register at this stage. The gates of the field effect transistors M21 and M22 receive the clock signal clk and the inverted clock signal clkb, respectively. The second-stage sampling and holding module 7112 may also include an even number of inverters for buffering the transmission signal DZ input to the transmission gate and / or buffering the output signal DOUT provided by the register at this stage.

[0095] In an optional embodiment, the transmission gate in the first stage sampling and holding module 7111 is cascaded between two inverters, and the transmission gate in the second stage sampling and holding module 7112 is cascaded between another two inverters, so that a precise sampling and holding function can be achieved with a simple circuit structure.

[0096] In order to make the working states of the second-stage sampling and holding module 7112 and the first-stage sampling and holding module 7111 different at the same time, that is, the first-stage sampling and holding module 7112 and the first-stage sampling and holding module 7111 alternately enter the sampling state and alternately enter the holding state, the transmission gate in the second-stage sampling and holding module 7112 and the transmission gate in the first-stage sampling and holding module 7111 are alternately turned on under the control of the clock signal clk.

[0097] As an optional embodiment, the gates of the field effect transistors M12 and M21 receive the inverted clock signal clkb, the gates of the field effect transistors M11 and M22 receive the clock signal clk, the field effect transistors M11 and M21 are, for example, PMOS transistors, and the field effect transistors M12 and M22 are, for example, NMOS transistors. Thus, when the clock signal clk is at a low level, the transmission gate in the first-stage sampling and holding module 7111 is turned on, so that the transfer signal DZ is the same as the input signal DIN received by the register of this stage, at which time the first-stage sampling and holding module 7111 works in a sampling state, and the second-stage sampling and holding module 7112 works in a holding state; when the clock signal clk is at a high level, the transmission gate in the second-stage sampling and holding module 7112 is turned on, so that the output signal DOUT provided by the register of this stage is the same as the transfer signal DZ provided by the first-stage sampling and holding module 7111, at which time the first-stage sampling and holding module 7111 works in a holding state, and the second-stage sampling and holding module 7112 works in a sampling state.

[0098] like Figure 6 As shown, each level of register 7110 also includes a first-level buffer module 7113 and a second-level buffer module 7114. The first-level buffer module 7113 buffers the transfer signal DZ output by the first-level sampling and holding module 7111 to drive / shape to obtain the first data bit Dk corresponding to the register of this level in the indication data Dstate, and the second-level buffer module 7114 buffers the output signal DOUT provided by the second-level sampling and holding module 7112 to drive / shape to obtain the second data bit Dp corresponding to the register of this level in the indication data Dstate. The first-level buffer module 7113 and the second-level buffer module 7114, for example, respectively include an even number of cascaded inverters (not gates).

[0099] In the above embodiment, each level of sampling and holding module and each level of buffer module receive, for example, the same power supply voltage, such as a high-level power supply voltage VDD and a low-level voltage VSS.

[0100] Processing circuit

[0101] Figure 7 Show Figure 4 A schematic block diagram of an implementation of a processing circuit in FIG.

[0102] The following is based on Figure 7 The implementation method shown describes and illustrates the processing circuit of the embodiment of the present invention, but the embodiment of the present invention is not limited to this. Other implementation principles of the processing circuit are described above, and those skilled in the art may also use other judgment methods to determine whether the average values ​​of the frequency of the first clock signal and the frequency of the frequency modulated continuous wave signal in the detection interval are within the expected range.

[0103] like Figure 7 As shown, the processing circuit 7200 includes a sampling unit 7210 , a storage unit 7220 and a first determination unit 7230 .

[0104] The sampling unit 7210 is used to sample the indication data Dstate provided by the ring register link 7100 at the start time of the detection interval to obtain the starting value Dstate_ini of the indication data in the detection interval, and to sample the indication data Dstate provided by the ring register link 7100 at the end time of the detection interval to obtain the ending value Dstate_end of the indication data in the detection interval. The sampling unit 7210 receives the second clock signal clk_cs, the frequency of the second clock signal clk_cs is less than the frequency of the clock signal clk of the ring register link 7100, and the sampling period Tsample of the second clock signal clk_cs corresponds to one detection interval, so that the sampling unit 7210 can sample and obtain the starting value Dstate_ini and the ending value Dstate_end under the control of the second clock signal clk_cs.

[0105] The storage unit 7220 is used to pre-store various possible state values ​​Dstate_1 to Dstate_2n of the indication data, and store the sequence numbers corresponding to the state values ​​of the indication data in the output logic order of the ring register link, so as to establish a relationship lookup table between different state values ​​and each sequence number. The storage unit 7220 can be set at Figure 1 The signal processing module 8 shown may also be an independently arranged memory, or may be arranged in the same module as other circuits.

[0106] The storage unit 7220 stores, for example, a relationship lookup table as shown in Table 1 below.

[0107] Table 1 Pre-stored relationship lookup table between different status values ​​and sequence numbers

[0108]

[0109]

[0110] In each detection interval, the first judgment unit 7230 is used to obtain the difference Δa between the sequence number a2 corresponding to the end value Dstate_end of the indication data in the detection interval and the sequence number a1 corresponding to the starting value Dstate_ini of the indication data in the detection interval according to the above-mentioned relationship lookup table, and obtain the measurement value of the detection interval according to the difference Δa. Further, the first judgment unit 7230 can be used to determine whether the offset a_os between the measurement value of the detection interval and the preset expected value a_ref is greater than the first threshold value. If so, the first bit result value Sout[0] of the detection result data Sout is set to a valid state (for example, 1, or 0 in other embodiments). If not, the first bit result value Sout[0] of the detection result data is set to an invalid state (for example, 0, or 1 in other embodiments), so that the first bit result value Sout[0] can represent whether the average value of the frequency of the first clock signal Sclk in the detection interval meets the expected range, for the following reasons:

[0111] As described above, the clock signal clk of the ring register chain 7100 is the first clock signal Sclk, so the frequency modulated continuous wave signal S provided by the synthesizer FM The frequency of the clock signal clk has a set ratio N div , the set ratio is usually a positive real number greater than or equal to 1.

[0112] Fake FM continuous wave signal S FM The frequency in the detection interval is fixed to f0, and the duration of the detection interval is equal to a sampling period Tsample of the second clock signal clk_cs. Then, in the detection interval, the frequency of the clock signal clk is f0 / N div , the number of times the indication data Dstate provided by the ring register link 7100 is updated within the detection interval is equal to:

[0113] 2*Tsample / [1 / (f0 / N div )]

[0114] However, due to the frequency modulated continuous wave signal S FM In fact, it increases linearly in each detection interval, so between every two adjacent sampling points, the expected number of times the indication data Dstate output by the ring register link 7100 is updated is equal to:

[0115] {2*Tsample / [1 / (F y-1 / N div )]+2*Tsample / [1 / (F y / N div )]} / 2

[0116] Right now:

[0117] Tsample*(F y-1 +F y ) / N div

[0118] Where y is a natural number greater than or equal to 1, F y and F y-1 are the frequency modulated continuous wave signal S corresponding to the current sampling point (the current clock edge of the second clock signal clk_cs) FM The desired frequency and the frequency modulated continuous wave signal S corresponding to the adjacent previous sampling point (the next clock edge of the second clock signal clk_cs) FM The expected frequency. F y-1 and F y For example, they correspond to Figure 3 The frequency F shown 1 and F 2 .

[0119] Table 1 shows 16 (i.e., 2n) state values ​​of the ring register chain 7100, taking 8-bit indication data Dstate (i.e., n=8) as an example. In this example, the ring register chain may include 4 levels of registers, and each level of registers corresponds to 2 data bits in the indication data. The ring register chain 7100 outputs 16 times as a cycle and cyclically outputs 16 state values ​​of the indication data Dstate in an output logic sequence, and these 16 state values ​​correspond to sequence numbers 1 to 16 in sequence according to the output logic sequence of the ring register chain 7100.

[0120] According to the above analysis, two adjacent clock edges in the second clock signal clk_cs can define a detection interval, and the remainder obtained by dividing the expected number of times the indication data Dstate is updated within the detection interval by 16 can be used to calculate the preset expected value a_ref corresponding to the detection interval. The preset expected value represents the ideal value of the difference Δa calculated by the first judgment unit 7230.

[0121] Based on this, the first judgment unit 7230 can judge whether the offset a_os between the difference Δa (i.e., the measured value) and the preset expected value a_ref is greater than the first threshold. If so, it means that the deviation between the difference Δa and the preset expected value a_ref is too large and exceeds the allowable range determined by the first threshold. At this time, the first judgment unit 7230 can set the first bit result value Sout[0] of the detection result data Sout to a valid state to indicate that the first clock signal Sclk and the frequency modulated continuous wave signal S FMThe average value of the frequency in the detection interval does not meet the expected range, so that the synthesizer and the radar system can be known to be in an abnormal working state according to the first bit result value Sout[0] of the valid state; if not, it means that the deviation between the difference Δa and the preset expected value a_ref is within the allowable range determined by the first threshold value. At this time, the first judgment unit 7230 can set the first bit result value Sout[0] of the detection result data Sout to an invalid state to indicate that the first clock signal Sclk and the frequency modulated continuous wave signal S FM The average value of the frequency in the detection interval meets the expected range, so that it can be known that the synthesizer and the radar system are in normal working condition according to the first bit result value Sout[0] of the invalid state.

[0122] As an optional embodiment, the first judgment unit 7230 may include: a search module, used to search for corresponding sequence numbers a1 and a2 in the storage unit 7220 according to the start value and end value provided by the sampling unit 7210; a calculation module, used to calculate the difference Δa according to the sequence numbers a1 and a2, and calculate the offset between the difference Δa and the preset expected value a_ref; a comparison module, used to compare the offset with the first threshold to generate a first bit result value Sout[0].

[0123] Figure 8 Show Figure 4 A schematic block diagram of another implementation of the processing circuit in FIG.

[0124] As a further optimized embodiment, Figure 8 As shown, in addition to the sampling unit 7210, the storage unit 7220 and the first judgment unit 7230 described in the above embodiment, the processing circuit 7200 may further include a second judgment unit 7240. The second judgment unit 7240 is used to provide a second bit result value Sout[1] in the detection result data Sout, so as to further provide detection result information of the frequency modulated continuous wave signal.

[0125] like Figure 8 As shown, the second judgment unit 7240 is used to generate a second result value Sout[1] according to the first result value Sout[0]. The second judgment unit 7240 includes a counter 7241 and a comparator 7242.

[0126] The counter 7241 is used to provide a count value num according to the first result value Sout[0]. When the first result value Sout[0] is in a valid state, the counter 7241 adds 1 to the count value num; and when the first result value Sout[0] received by the counter 7241 is in an invalid state, the counter 7241 resets the count value num to an initial value. Thus, the count value num can represent the number of sampling cycles during which the first result value Sout[0] continuously represents the abnormal working state, that is, the frequency modulated continuous wave signal S FM The number of sampling cycles during which the frequency does not meet the preset frequency continuously.

[0127] The comparator 7242 is used to compare the count value num provided by the counter 7241 with the second threshold value max_ref to obtain a second result value Sout[1]. When the count value num is greater than the second threshold value max_ref, the comparator 7242 will output a valid second result value Sout[1] to indicate that the first clock signal Sclk and the frequency modulated continuous wave signal S FM The average value of the frequency in a plurality of consecutive detection intervals / sampling periods exceeding the expected number does not meet the expected range, which indicates that the synthesizer and the radar system are in an abnormal working state for a long time and are not easy to recover to normal by themselves; and when the count value num is less than / equal to the second threshold value max_ref, the comparator 7242 outputs the second bit result value Sout[1] of the invalid state to represent the first clock signal Sclk and the frequency modulated continuous wave signal S FM The frequency variation is as expected.

[0128] In an optional embodiment, the subsequent circuit connected to the comparator 7242 may be triggered by the valid second result value Sout[1] to initiate an early warning prompt, and the early warning prompt includes but is not limited to a sound prompt, a pop-up prompt, an optical prompt, etc. When the second result value Sout[1] is in an invalid state, the subsequent circuit does not need to initiate an early warning prompt.

[0129] The present invention also provides a detection device as described in the above embodiments, for determining whether the first clock signal Sclk and the frequency modulated continuous wave signal S FM Whether the average value of the frequency in each detection interval meets the expected range.

[0130] According to the radar system and detection device provided by the embodiment of the present invention, a first clock signal in the form of a square wave is obtained by down-converting and shaping the frequency modulated continuous wave signal, the value of the corresponding data bit in the indication data is updated according to each clock edge of the first clock signal, and the indication data is sampled based on the second clock signal to obtain a measurement value of the number of clock edges controlled by the first clock signal, so that the detection result data can be obtained according to the measurement value to characterize whether the frequency of the frequency modulated continuous wave signal is normal, thereby realizing the detection of the frequency of the frequency modulated continuous wave signal. In the radar system of the embodiment of the present invention, since the frequency of the frequency modulated continuous wave signal is controlled by the synthesizer, the detection result data provided by the detection device can indicate whether the synthesizer is working abnormally and whether the radar system is working abnormally.

[0131] For example, for a synthesizer with a phase-locked loop structure, when the calculated offset is less than / equal to the first threshold, the detection device and radar system provided by the embodiment of the present invention can determine that the phase-locked loop structure is in a normal working state, otherwise it is in an abnormal working state; and in order to improve the accuracy of the judgment, judgment processing can be performed separately for multiple detection intervals, and only when the offset is less than / equal to the above-mentioned first threshold in all or a preset proportion of the detection intervals, and at the same time shows a certain regular change or the change amplitude is small, the phase-locked loop structure is judged to be in a normal working state. Among them, the judgment of the change amplitude can be set based on the actual accuracy requirements.

[0132] In addition, for a phase-locked loop structure in an abnormal working state, the detection device and radar system provided by the embodiment of the present invention can also determine whether the phase-locked loop structure is in a locked state or an unstable state by further analyzing and judging the change law of the offset obtained in different detection intervals (that is, in the embodiment of the present application, the abnormal working state may include a locked state and an unstable state). For example, when the offset obtained in adjacent sampling periods (corresponding to adjacent detection intervals) changes randomly or the change amplitude is large, it can be determined that the phase-locked loop structure is in an unstable state in an abnormal state at this time, that is, it can be considered that some components in the phase-locked loop structure may be damaged at this time; otherwise, it can be considered that the phase-locked loop structure is in a locked state in an abnormal state at this time.

[0133] Fig. 9 The flowchart of the detection method of the embodiment of the present invention is shown, which includes steps S810 to S850. The method is applied to the detection device and radar system of the above-mentioned embodiments, for example.

[0134] In step S810, the frequency modulated continuous wave signal is down-converted and shaped to generate a first clock signal in the form of a square wave, and the frequency of the frequency modulated continuous wave signal is in a set ratio with the frequency of the first clock signal. The frequency of the frequency modulated continuous wave signal changes linearly within the detection interval, so the frequency of the first clock signal also changes linearly within the detection interval.

[0135] In step S820, indication data having a plurality of data bits is provided, and corresponding data bits in the indication data are updated according to a clock edge of a first clock signal.

[0136] As an optional embodiment, each rising edge and / or each falling edge of the first clock signal can be used as a clock edge for updating the indication data. Step S820 can include: cyclically updating the value of each data bit of the indication data in turn under the triggering of each clock edge; and updating the value of a corresponding data bit in the indication data under the triggering of each clock edge.

[0137] In step S830, the indication data is sampled based on the second clock signal to obtain a measurement value, and the detection result data is provided according to the measurement value. The measurement value is controlled by the number of clock edges of the first clock signal that appear in the detection interval, and the detection result data indicates whether the frequency of the frequency modulated continuous wave signal and the frequency of the first clock signal are normal, and the frequency of the second clock signal is less than the frequency of the first clock signal.

[0138] As an optional embodiment, step S830 may include: sampling the indication data based on the second clock signal to obtain the starting value and the ending value of the indication data within the detection interval, and the detection interval may correspond to one or more sampling periods of the second clock signal; obtaining a relationship lookup table, the relationship lookup table being used to provide sequence numbers corresponding to multiple state values ​​of the indication data in the output logical order, the multiple state values ​​of the indication data including the above-mentioned starting value and ending value, and the sequence numbers including a first sequence number corresponding to the starting value and a second sequence number corresponding to the ending value; obtaining a measurement value according to the difference between the first sequence number and the second sequence number; judging whether the offset between the measurement value and the preset expected value of the detection interval is greater than a first threshold value, and if so, setting the first bit result value of the detection result data to a valid state to indicate that the average value of the frequency of the frequency modulated continuous wave signal within the detection interval does not meet the expected range, and if not, setting the first bit result value to an invalid state to indicate that the average value of the frequency of the frequency modulated continuous wave signal within the detection interval meets the expected range.

[0139] As an optional embodiment, step S830 may further include: calculating and obtaining a preset expected value based on the total number of multiple state values ​​indicating the data and the expected number of occurrences of the clock edge of the first clock signal within the detection interval.

[0140] As an optional embodiment, for each detection interval, the measured value may be equal to the difference between the first sequence number and the second sequence number, and the preset expected value is equal to the remainder obtained by dividing twice the set value corresponding to the detection interval by the total number of multiple state values ​​indicating the data, where the set value is equal to the product of the preset frequency average value of the first clock signal in the detection interval and the duration of the detection interval.

[0141] As an optional embodiment, in step S830, the step of providing detection result data according to the measurement value may also include: providing a count value according to the first result value, and adding 1 to the count value when the first result value is in a valid state, and restoring the count value to an initial value when the first result value is in an invalid state; judging whether the count value is greater than a second threshold value, and if so, setting the second result value of the detection result data to a valid state to characterize that the frequency change of the frequency modulated continuous wave signal is in an abnormal state, and if not, setting the second result value to an invalid state to characterize that the frequency change of the frequency modulated continuous wave signal is in a normal state.

[0142] It should be noted that the detection method provided in the embodiment of the present invention may include the technical details and features proposed in the above description of the detection device and radar system of each embodiment, and the same parts will not be repeated here.

[0143] According to the radar system, detection device and detection method provided by the embodiment of the present invention, a first clock signal in the form of a square wave is obtained by downconverting and shaping the frequency modulated continuous wave signal, the value of the corresponding data bit in the indication data is updated according to each clock edge of the first clock signal, and the indication data is sampled based on the second clock signal to obtain a measurement value of the number of clock edges controlled by the first clock signal, so that the detection result data can be obtained according to the measurement value to characterize whether the frequency of the frequency modulated continuous wave signal is normal, thereby realizing the detection of the frequency of the frequency modulated continuous wave signal. In the radar system of the embodiment of the present invention, since the frequency of the frequency modulated continuous wave signal is controlled by the synthesizer, the detection result data provided by the detection device can indicate whether the synthesizer is working abnormally and whether the radar system is working abnormally.

[0144] It should be noted that, in this article, the term "comprises", "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0145] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A radar system, for obtaining a beat signal according to a frequency modulated continuous wave signal and an echo signal, and obtaining a detection result according to the frequency of the beat signal, It is characterized in that The radar system includes a transmitting channel, a synthesizer, and a detection device for the synthesizer, wherein the synthesizer is used to output the frequency modulated continuous wave signal, the transmitting channel provides a transmitting signal to the antenna according to the frequency modulated continuous wave signal, and the detection device includes: An input circuit connected to the synthesizer to receive the frequency modulated continuous wave signal, and to perform frequency reduction and shaping processing on the frequency modulated continuous wave signal to generate a first clock signal in the form of a square wave, wherein the frequency of the first clock signal changes linearly within a detection interval; a ring register link connected to the input circuit to receive the first clock signal, for providing indication data, and updating the value of a corresponding data bit in the indication data according to each clock edge of the first clock signal; and a processing circuit connected to the ring register link, and configured to: sample the indication data based on the second clock signal to obtain a measurement value, and provide detection result data according to the measurement value, wherein the detection result data indicates whether the frequency of the frequency modulated continuous wave signal is normal, The frequency of the second clock signal is less than the frequency of the first clock signal, and the measurement value is controlled by the number of clock edges of the first clock signal occurring within the detection interval.

2. The radar system according to claim 1, It is characterized in that For each of the detection intervals, the ring register chain is adapted to: cyclically updating the value of each data bit of the indication data in sequence under the triggering of each clock edge; and The value of a corresponding data bit in the indication data is updated under the triggering of each clock edge.

3. The radar system according to claim 1, It is characterized in that The processing circuit comprises: a sampling unit connected to the ring register link, and configured to: sample the indication data based on the second clock signal to obtain a start value and an end value of the indication data within the detection interval, wherein the detection interval corresponds to one or more sampling periods of the second clock signal; a storage unit, configured to pre-store a relational lookup table to indicate sequence numbers corresponding to a plurality of state values ​​of the indication data in an output logic order of the ring register link, the plurality of state values ​​including the start value and the end value, the sequence numbers including a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; and a first judging unit, configured to obtain the measurement value according to a difference between the first sequence number and the second sequence number, and to judge whether an offset between the measurement value and a preset expected value of the detection interval is greater than a first threshold value, If yes, the first judgment unit sets the first result value of the detection result data to a valid state to indicate that the average value of the frequency of the FMCW signal in the detection interval does not meet the expected range. If not, the first determination unit sets the first bit result value to an invalid state to indicate that the average value of the frequency of the FMCW signal within the detection interval satisfies the expected range.

4. The radar system according to claim 3, It is characterized in that The preset expected value is: a data value obtained by calculating based on the total number of the plurality of state values ​​and the expected number of occurrences of the clock edge of the first clock signal within the detection interval.

5. The radar system according to claim 4, It is characterized in that For each of the detection intervals: The measured value is equal to the difference, The preset expected value is equal to the remainder obtained by dividing twice the set value corresponding to the detection interval by the total number of the multiple state values, The set value is equal to the product of an expected average value of the frequency of the first clock signal in the detection interval and a duration of the detection interval.

6. The radar system according to claim 4, It is characterized in that The processing circuit further comprises: a counter for providing a count value according to the first-bit result value, the counter being responsive to the first-bit result value in a valid state to increase the count value by 1, and being responsive to the first-bit result value in an invalid state to reset the count value to an initial value; and a comparator, configured to determine whether the count value is greater than a second threshold, If yes, the comparator sets the second bit result value of the detection result data to a valid state to indicate that the frequency change of the FMCW signal is in an abnormal state. If not, the comparator sets the second bit result value to an invalid state to indicate that the frequency change of the FMCW signal is in a normal state.

7. The radar system according to claim 1, It is characterized in that The synthesizer comprises: The phase-locked loop structure comprises a voltage-controlled oscillator, which generates the frequency-modulated continuous wave signal according to the frequency control voltage, and the frequency of the frequency-modulated continuous wave signal varies with the voltage value of the frequency control voltage.

8. A method for detecting a synthesizer, It is characterized in that The synthesizer is used to output a frequency modulated continuous wave signal, and the detection method includes: Performing frequency reduction and shaping processing on the frequency modulated continuous wave signal to generate a first clock signal in the form of a square wave, wherein the frequency of the first clock signal changes linearly within a detection interval; providing indication data having a plurality of data bits, and updating corresponding data bits in the indication data according to a clock edge of the first clock signal; sampling the indication data based on a second clock signal to obtain a measurement value; Providing detection result data according to the measured value, wherein the detection result data indicates whether the frequency of the FMCW signal is normal, The frequency of the second clock signal is less than the frequency of the first clock signal, and the measurement value is controlled by the number of clock edges of the first clock signal occurring within the detection interval.

9. The detection method according to claim 8, It is characterized in that The step of updating corresponding data bits in the indication data according to the clock edge of the first clock signal comprises: cyclically updating the value of each data bit of the indication data in sequence under the triggering of each clock edge; and The value of a corresponding data bit in the indication data is updated under the triggering of each clock edge.

10. The detection method according to claim 8, It is characterized in that The steps of sampling the indication data based on the second clock signal to obtain the measurement value, and providing the detection result data according to the measurement value include: sampling the indication data based on the second clock signal to obtain a start value and an end value of the indication data within the detection interval, wherein the detection interval corresponds to one or more sampling periods of the second clock signal; Obtaining a relational lookup table, the relational lookup table indicating sequence numbers corresponding to a plurality of state values ​​of the indication data in an output logical order, the plurality of state values ​​including the start value and the end value, the sequence numbers including a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; Obtaining the measurement value according to the difference between the first sequence number and the second sequence number; Determine whether the offset between the measured value and the preset expected value of the detection interval is greater than a first threshold, If yes, then the first result value of the detection result data is set to a valid state to indicate that the average value of the frequency of the FMCW signal in the detection interval does not meet the expected range. If not, the first bit result value is set to an invalid state to indicate that the average value of the frequency of the FMCW signal within the detection interval meets the expected range.

11. The detection method according to claim 10, It is characterized in that Also includes: The preset expected value is calculated based on the total number of the multiple state values ​​and the expected number of occurrences of the clock edge of the first clock signal in the detection interval.

12. The detection method according to claim 11, It is characterized in that For each of the detection intervals: The measured value is equal to the difference, The preset expected value is equal to the remainder obtained by dividing twice the set value corresponding to the detection interval by the total number of the multiple state values, The set value is equal to the product of a preset frequency average value of the first clock signal in the detection interval and a duration of the detection interval.

13. The detection method according to claim 10, It is characterized in that The step of sampling the indication data based on the second clock signal to obtain the measurement value, and providing the detection result data according to the measurement value also includes: Providing a count value according to the first result value, and adding 1 to the count value when the first result value is in a valid state, and restoring the count value to an initial value when the first result value is in an invalid state; and determining whether the count value is greater than a second threshold, If yes, then the second bit result value of the detection result data is set to a valid state to indicate that the frequency change of the FMCW signal is in an abnormal state. If not, the second bit result value is set to an invalid state to indicate that the frequency change of the FMCW signal is in a normal state.

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