Timing analysis method, circuit, device and storage medium

Abstract

The present invention discloses a timing analysis method, circuit, device and storage medium. The method comprises: constructing a clock tree based on a plurality of first inverter pair units; the clock tree is used to provide an input clock to a component to be analyzed; wiring the clock tree and the component to be analyzed; analyzing the timing of the input clock of the component to be analyzed after wiring to obtain an analysis result; the analysis result indicates that the minimum pulse width of the input clock is greater than or equal to a preset threshold.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and in particular to a timing analysis method, circuit, device and storage medium. Background Art

[0002] With the continuous advancement of technology, the performance of chip units in intelligent electronic devices is gradually improving. For example, the clock frequency of chip units is getting higher and higher. Faced with higher and higher clock frequencies, timing convergence in chip physical design implementation will be a big challenge, especially for the minimum pulse width of the clock. The requirements will be extremely strict. In the related technology, during the chip back-end design process, the minimum pulse width of the clock can be checked using a timing check tool. When the minimum pulse width is found to be violated, the minimum pulse width of the clock needs to be repaired, resulting in a longer back-end design time.

[0003] Therefore, it is urgent to find a technical solution to ensure that the minimum pulse width of the clock is not violated. Summary of the invention

[0004] In view of this, embodiments of the present invention are intended to provide a timing analysis method, circuit, device, and storage medium.

[0005] The technical solution of the present invention is achieved in this way:

[0006] An embodiment of the present invention provides a timing analysis method, the method comprising:

[0007] Based on the plurality of first inverter pair units, a clock tree is constructed; the clock tree is used to provide an input clock to the components to be analyzed;

[0008] Routing the clock tree and the components to be analyzed;

[0009] The timing of the input clock of the component to be analyzed after wiring is analyzed to obtain an analysis result; the analysis result indicates that the minimum pulse width of the input clock is greater than or equal to a preset threshold.

[0010] In the above solution, the analyzing the timing of the input clock of the component to be analyzed after wiring includes:

[0011] Determine a period of an original clock input into the clock tree, and determine a first rise time and a first fall time of the original clock passing through each first inverter pair unit in the clock tree;

[0012] Based on the period, the first rising time and the first falling time, the timing of the input clock reaching the component to be analyzed after routing is analyzed.

[0013] In the above scheme, the timing of the input clock arriving at the component to be analyzed after routing is analyzed based on the period, the first rise time and the first fall time, including:

[0014] Based on the cycle of the original clock, determine the high level pulse width and the low level pulse width of the original clock;

[0015] Analyzing the minimum pulse width of the high-level pulse based on the high-level pulse width, and a first rising time and a first falling time corresponding to the high-level pulse;

[0016] Based on the low level pulse width, and a first rising time and a first falling time corresponding to the low level pulse, the minimum pulse width of the low level pulse is analyzed.

[0017] In the above scheme, the method further comprises:

[0018] Determine whether the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse are both greater than or equal to a preset threshold;

[0019] When it is determined that the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse are both greater than or equal to the preset threshold, it is determined that the minimum pulse width of the input clock is greater than or equal to the preset threshold.

[0020] In the above scheme, the method further comprises:

[0021] When it is determined that at least one of the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse is less than the preset threshold, adjusting the clock parameter of the first inverter pair unit of the last stage in the clock tree;

[0022] The clock tree is reconstructed based on the adjusted first inverter pair unit.

[0023] In the above scheme, the method further comprises:

[0024] Determine at least one second inverter pair unit having a driving capability level greater than or equal to a level threshold; wherein the driving capability level of the second inverter pair unit is greater than the driving capability level of the first inverter pair unit;

[0025] The at least one second inverter pair unit is arranged at a clock port of the memory; the clock port is used to input an input clock provided by the clock tree.

[0026] An embodiment of the present invention provides a timing analysis circuit, including:

[0027] A clock tree circuit, composed of a plurality of first inverter pair units, for providing an input clock to the component to be analyzed;

[0028] The component to be analyzed is connected to the clock tree circuit for wiring, and is used to analyze the timing of the input clock of the component to be analyzed after wiring; the analysis result indicates that the minimum pulse width of the input clock is greater than or equal to a preset threshold.

[0029] In the above solution, the component to be analyzed is a memory; the circuit further includes:

[0030] The driving circuit is composed of at least one second inverter pair unit and is used to be connected to a clock port of the memory; the clock port is used to input an input clock provided by the clock tree.

[0031] An embodiment of the present invention provides a timing analysis device, including:

[0032] A clock tree unit, comprising a plurality of first inverter pair units, wherein the clock tree is used to provide an input clock to a component to be analyzed;

[0033] A wiring unit, used for wiring the clock tree and the components to be analyzed;

[0034] The timing analysis unit is used to analyze the timing of the input clock of the component to be analyzed after wiring to obtain an analysis result; the analysis result is used to make the minimum pulse width of the input clock of the component to be analyzed greater than or equal to a preset threshold.

[0035] In the above solution, the timing analysis unit is specifically used for:

[0036] Determine a period of an original clock input into the clock tree, and determine a first rise time and a first fall time of the original clock passing through each first inverter pair unit in the clock tree;

[0037] Based on the period, the first rising time and the first falling time, the timing of the input clock reaching the component to be analyzed after routing is analyzed.

[0038] In the above solution, the timing analysis unit is specifically used for:

[0039] Based on the cycle of the original clock, determine the high level pulse width and the low level pulse width of the original clock;

[0040] Analyzing the minimum pulse width of the high-level pulse based on the high-level pulse width, and a first rising time and a first falling time corresponding to the high-level pulse;

[0041] Based on the low level pulse width, and a first rising time and a first falling time corresponding to the low level pulse, the minimum pulse width of the low level pulse is analyzed.

[0042] In the above solution, the device further comprises:

[0043] A judgment unit is used to judge whether the minimum pulse width of the high-level pulse and the minimum pulse width of the low-level pulse are both greater than or equal to a preset threshold; when it is determined that the minimum pulse width of the high-level pulse and the minimum pulse width of the low-level pulse are both greater than or equal to the preset threshold, it is determined that the minimum pulse width of the input clock is greater than or equal to the preset threshold.

[0044] In the above solution, the judging unit is further used for:

[0045] When it is determined that at least one of the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse is less than the preset threshold, adjusting the clock parameter of the first inverter pair unit of the last stage in the clock tree;

[0046] The clock tree is reconstructed based on the adjusted first inverter pair unit.

[0047] In the above solution, the component to be analyzed is a memory; the device further comprises:

[0048] A determination unit is used to determine at least one second inverter pair unit whose driving capability level is greater than or equal to a level threshold; wherein the driving capability level of the second inverter pair unit is greater than the driving capability level of the first inverter pair unit; the at least one second inverter pair unit is set at a clock port of the memory; the clock port is used to input an input clock provided by the clock tree.

[0049] An embodiment of the present invention provides a timing analysis device, comprising: a processor and a memory for storing a computer program that can be run on the processor,

[0050] Wherein, when the processor is used to run the computer program, the steps of any of the above methods are implemented when the program is executed.

[0051] An embodiment of the present invention provides a storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0052] The timing analysis method, circuit, device and storage medium provided in the embodiment of the present invention construct a clock tree based on multiple first inverter pair units; the clock tree is used to provide input clocks to the components to be analyzed; the clock tree and the components to be analyzed are wired; the timing of the input clocks of the components to be analyzed after wiring is analyzed to obtain analysis results; the analysis results characterize that the minimum pulse width of the input clock is greater than or equal to a preset threshold. By adopting the technical solution of the embodiment of the present invention, the buffer unit is replaced with the first inverter pair unit, and a clock tree is constructed based on multiple first inverter pair units, which can eliminate the occurrence of minimum pulse width violations caused by the buffer unit, thereby ensuring that the minimum pulse width of the clock input by the clock tree to the components to be analyzed is not violated, thereby avoiding the chip back-end design taking up a long time. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A schematic diagram of performing timing analysis on the clock of components for related technologies;

[0054] Figure 2 A waveform diagram of a clock in the related art;

[0055] Figure 3 A schematic diagram of the delay of the rising edge and the delay of the falling edge of a clock passing through a buffer in the related art;

[0056] Figure 4 A schematic diagram of a waveform of a clock after passing through a buffer in the related art;

[0057] Figure 5 A schematic diagram of detecting the minimum pulse width of a clock signal of a register in the related art;

[0058] Figure 6 Schematic diagram of the implementation flow of the timing analysis method according to an embodiment of the present invention;

[0059] Figure 7 A schematic diagram of an implementation flow of analyzing the timing of an input clock of a component to be analyzed according to an embodiment of the present invention;

[0060] Figure 8 A schematic diagram of a clock tree constructed according to an embodiment of the present invention;

[0061] Fig. 9 A schematic diagram of a clock constraint file according to an embodiment of the present invention;

[0062] Fig.10 A schematic diagram of the structure of a timing analysis circuit according to an embodiment of the present invention;

[0063] Fig.11 It is a structural schematic diagram of a timing analysis circuit corresponding to a memory according to an embodiment of the present invention;

[0064] Fig.12 The structure diagram of the timing analysis device according to the embodiment of the present invention is shown in FIG. Figure 1 ;

[0065] Fig.13 The structure diagram of the timing analysis device according to the embodiment of the present invention is shown in FIG. Figure 2 . DETAILED DESCRIPTION

[0066] Before describing the technical solution of the embodiment of the present invention in detail, the related technology is first introduced.

[0067] In related technologies, with the continuous advancement of technology, the performance of chips has gradually improved. The clock frequency of processors (CPUs) of mobile terminals has already reached more than 2.0GHz. For example, the Cortex-A78 architecture released by ARM can reach 3.0GHz under the 5nm process. Faced with such a high clock frequency, the timing convergence in the implementation of chip physical design will be a great challenge, especially the requirements for clock pulse width will be extremely strict. Figure 1 This is a schematic diagram of the timing analysis of the clock of components by related technologies, such as Figure 1 As shown, the method to repair the minimum pulse width violation in the chip back-end design is mainly to analyze the results reported by the timing checking tool (such as PT or Tempus) when the engineering change order (eco) of the timing is performed after the layout and routing (PR) is completed. The repair method is generally to eco the clock tree. At this time, the clock tree of the chip has been completed and stable. Once the clock tree is changed, it will have a very large impact on the timing of the chip, especially when the violation occurs at the clock port of the memory. The impact will be immeasurable and may even require starting over and re-entering the PR stage. At this time, the design process (schedule) of the project will be greatly tested.

[0068] Figure 2 It is a waveform diagram of a clock in the related art, such as Figure 2 As shown, the period of the clock is 10 ns, and ideally the duty cycle of the clock is 50%, that is, the high pulse width and the low pulse width are both 5 ns. Figure 3 It is a schematic diagram of the delay of the rising edge and the delay of the falling edge of the clock passing through the buffer in the related art, such as Figure 3As shown, after the clock passes through an ordinary buffer, the delay of the rising edge is equal to 0.7ns, and the delay of the falling edge is equal to 0.5ns. Obviously, the delay of the rising edge (rise delay) is inconsistent with the delay of the falling edge (fall delay), and the delay of the rising edge is greater than the delay of the falling edge. Figure 4 This is a schematic diagram of the waveform of the clock after passing through the buffer in the related technology, such as Figure 4 As shown in the figure, when the rise delay of the buffer cell is greater than the fall delay, the pulse width of the high level of the clock signal will become smaller. When the clock tree contains a large number of buffer cells, the pulse width of the clock signal will continue to decrease when the clock signal passes through a series of similar buffer cells, and may eventually fail to meet the minimum pulse width requirement.

[0069] For example, if Figure 5 As shown in the figure, the clock signal of a register arrives through the clock root CLK through 4 levels of common buffers. The rise time and fall time of each buffer are different, and the rise time is greater than the fall time. Assuming the clock period is 1ns, the uncertainty is 100ps, and the register required min pulse width is 0.4ns, we can calculate the clock port of the register:

[0070] High pulse width=0.5+(0.051-0.054)+(0.039-0.043)+(0.045-0.048)+(0.056-0.060)-0.1=0.386ns

[0071] Low pulse width=0.5+(0.054-0.051)+(0.043-0.039)+(0.048-0.045)+(0.060-0.056)-0.1=0.414ns

[0072] Since High pulse width = 0.386ns < required min pulse width = 0.4ns, the minimum pulse width of the register clock signal is detected to be violated. For registers, if the minimum pulse width is violated, it must be fixed, otherwise the function of the timing device may fail.

[0073] In summary, the technical defects existing in the related technology are: during the chip back-end design process, the timing check tool can be used to check the minimum pulse width of the clock. When the check finds that the minimum pulse width is violated, the minimum pulse width of the clock needs to be repaired, resulting in the back-end design taking a long time.

[0074] Based on this, in various embodiments of the present invention, a clock tree is constructed based on multiple first inverter pair units; the clock tree is used to provide an input clock to the components to be analyzed; the clock tree and the components to be analyzed are wired; the timing of the input clock of the components to be analyzed after wiring is analyzed to obtain an analysis result; the analysis result characterizes that the minimum pulse width of the input clock is greater than or equal to a preset threshold.

[0075] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0076] The embodiment of the present invention provides a timing analysis method. Figure 6 FIG. 1 is a schematic diagram of the implementation flow of the timing analysis method according to an embodiment of the present invention; Figure 6 As shown, the method includes:

[0077] Step 601: constructing a clock tree based on a plurality of first inverter pair units; the clock tree is used to provide an input clock to a component to be analyzed;

[0078] Step 602: routing the clock tree and the components to be analyzed;

[0079] Step 603: Analyze the timing of the input clock of the component to be analyzed after routing to obtain an analysis result; the analysis result indicates that the minimum pulse width of the input clock is greater than or equal to a preset threshold.

[0080] Here, in step 601, the first inverter pair unit may refer to a basic unit (cell) composed of two inverters. The clock tree may refer to a mesh structure constructed by a plurality of first inverter pair units, wherein a plurality of first inverter pair units may construct an N-level clock tree, where N is a positive integer. In practical applications, when a clock tree is constructed by a buffer unit (buffer), since the mobility of the PMOS in the buffer is less than the mobility of the NMOS, the time required for charging is greater than the time for discharging, that is, the fall time (fall time) of the clock after passing through the buffer will be faster than the rise time (rise time). The buffer is replaced with the first inverter pair unit (represented by a clock inverter pair). Since the rise time and fall time of the clockinverter pair will compensate each other, the final minimum pulse width (minpulse width) of the clock will not change, so it is easier to avoid the occurrence of the min pulse width violation problem.

[0081] Here, in step 602, in actual application, in order to provide input clocks to the components to be analyzed through the clock tree, and to facilitate the subsequent inspection of the minimum pulse width of the input clocks of the components to be analyzed, the clock tree constructed based on the first inverter pair unit and the components to be analyzed can be routed (Route). Before routing the clock tree and the components to be analyzed, the clock tree can also be synthesized (CTS, Clock Tree Synthesis) to constrain the relevant parameters of the clock signal of the clock tree.

[0082] Here, in step 603, the minimum pulse width is a measure of the minimum width of the high level pulse and the low level pulse of the signal, and is a hard rule in the STA stage. For sequential devices or memories, if there is a violation of the minimum pulse width, it must be repaired, otherwise the function of the sequential device may fail. The STA refers to checking the min pulse width of the clock path in the clock tree. The minimum pulse width of the input clock is greater than or equal to the preset threshold value, which means that the minimum pulse width of the high level pulse of the input clock is greater than the preset threshold value and the minimum pulse width of the low level pulse of the input clock is greater than the preset threshold value.

[0083] In practical applications, it is considered that after the clock signal passes through the first inverter pair unit of the clock tree, there will be a "delay" on the rising edge and the falling edge of the clock signal. In this way, the clock signal will have a rise time and a fall time. Therefore, based on the rise time, the fall time of the clock signal passing through each first inverter pair unit in the clock tree and the period of the clock signal, the minimum pulse width of the clock signal reaching the component to be analyzed can be analyzed.

[0084] Based on this, in one embodiment, analyzing the timing of the input clock of the component to be analyzed after wiring includes:

[0085] Determine a period of an original clock input into the clock tree, and determine a first rise time and a first fall time of the original clock passing through each first inverter pair unit in the clock tree;

[0086] Based on the period, the first rising time and the first falling time, the timing of the input clock reaching the component to be analyzed after routing is analyzed.

[0087] Here, when the clock signal input to the first inverter pair unit is a low-level pulse signal, the first inverter in the first inverter pair unit outputs a high-level pulse signal, so the time required for the input low-level pulse signal to reach 50% to the output high-level pulse signal to reach 50% can be called the first rise time. When the clock signal input to the first inverter pair unit is a high-level pulse signal, the first inverter in the first inverter pair unit outputs a low-level pulse signal, so the time required for the input high-level pulse signal to reach 50% to the output low-level pulse signal to reach 50% can be called the first fall time.

[0088] In practical application, since the input clock provided by the clock tree to the component to be analyzed may consist of high-level pulses and low-level pulses, the minimum pulse width of the high-level pulse and the minimum pulse width of the low-level pulse may be analyzed respectively.

[0089] Based on this, in one embodiment, analyzing the timing of the input clock that reaches the component to be analyzed after routing based on the period, the first rise time, and the first fall time includes:

[0090] Based on the cycle of the original clock, determine the high level pulse width and the low level pulse width of the original clock;

[0091] Analyzing the minimum pulse width of the high-level pulse based on the high-level pulse width, and a first rising time and a first falling time corresponding to the high-level pulse;

[0092] Based on the low level pulse width, and a first rising time and a first falling time corresponding to the low level pulse, the minimum pulse width of the low level pulse is analyzed.

[0093] Here, the minimum pulse width of the high-level pulse can be calculated according to formula (1).

[0094] Width H =T H +(T fall1 T rise1 )+(T fall2 -T rise2 )+...(T falln -T risen ) (1)

[0095] Among them, Width H Indicates the minimum pulse width of the high level pulse, T H Indicates the high level pulse width of the original clock input to the clock tree, T fall1 It represents the falling time of the high level pulse of the original clock when it passes through the first inverter pair unit, T rise1 It represents the rise time of the high level pulse of the original clock when it passes through the first inverter pair unit, and so on, T falln It represents the falling time of the high level pulse of the original clock when it passes through the nth inverter pair unit, T risen It represents the rising time of the high level pulse of the original clock when passing through the nth inverter pair unit.

[0096] Here, the minimum pulse width of the low-level pulse can be calculated according to formula (2).

[0097] Width L =T L +(T rise1 -T fall1 )+(T rise2 -T fall2 )+...(T risen -T falln ) (2)

[0098] Among them, Width L Indicates the minimum pulse width of the low level pulse, T L Indicates the low level pulse width of the original clock input to the clock tree, T fall1 It represents the falling time of the low level pulse of the original clock when it passes through the first inverter pair unit, T rise1 It represents the rise time of the low level pulse of the original clock when it passes through the first inverter pair unit, and so on, T fallnIt represents the falling time of the low level pulse of the original clock when it passes through the nth inverter pair unit, T risen It represents the rising time of the low level pulse of the original clock when passing through the nth inverter pair unit.

[0099] In actual application, when the minimum pulse width of the high level pulse of the input clock is greater than or equal to a preset threshold, and the minimum pulse width of the low level pulse of the input clock is greater than or equal to the preset threshold, it is determined that the minimum pulse width of the input clock is not violated.

[0100] Based on this, in one embodiment, the method further includes:

[0101] Determine whether the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse are both greater than or equal to a preset threshold;

[0102] When it is determined that the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse are both greater than or equal to the preset threshold, it is determined that the minimum pulse width of the input clock is greater than or equal to the preset threshold.

[0103] In actual application, when analyzing the timing of the input clock provided by the clock tree to the device to be analyzed, if it is found that the minimum pulse width of the high-level pulse of the input clock is less than the preset threshold and / or the minimum pulse width of the low-level pulse of the input clock is less than the preset threshold, the clock parameters of the first inverter unit in the clock tree can be adjusted; the clock parameters may refer to the transmission time (transition time) of the clock signal input by the clock tree.

[0104] Based on this, in one embodiment, the method further includes:

[0105] When it is determined that at least one of the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse is less than the preset threshold, adjusting the clock parameter of the first inverter pair unit of the last stage in the clock tree;

[0106] The clock tree is reconstructed based on the adjusted first inverter pair unit.

[0107] Here, the clock parameters may refer to the rise time and the fall time. Since the first inverter unit of the last stage is closest to the position of the component to be analyzed, the clock parameters of the first inverter unit of the last stage are adjusted first, which can ensure that the minimum pulse width of the clock is not violated with the highest probability, that is, the minimum pulse width of the clock is greater than or equal to the preset threshold.

[0108] For example, assuming that the minimum pulse width of the high-level pulse is 0.38ns and the preset threshold is 0.4ns, since 0.38ns is less than 0.4ns, the difference between the fall time and the rise time of the first inverter pair unit of the last stage can be reduced to ensure that the value of the final calculated minimum pulse width becomes larger, so that the minimum pulse width of the high-level pulse is greater than or equal to 0.4ns.

[0109] It should be noted that if the minimum pulse width of the clock is still violated after the clock parameters of the first inverter pair unit of the last stage are adjusted, the clock parameters of the first inverter pair unit of the previous stage of the last stage can be adjusted, and so on, ultimately ensuring that the minimum pulse width of the input clock reaching the component to be analyzed is not violated.

[0110] In actual application, when the component to be analyzed is a memory, considering that the memory has strict requirements on the minimum pulse width of the input clock and the clock network signal of the memory is prone to crosstalk, before building the clock tree of the memory, an inverter pair unit with a stronger driving capability level can be placed at the clock input port of the memory to ensure that the minimum pulse width of the clock signal reaching the memory is not violated and to reduce the crosstalk of the clock signal.

[0111] Based on this, in one embodiment, the component to be analyzed is a memory; before replacing the buffer unit with the first inverter pair unit, the method further includes:

[0112] Determine at least one second inverter pair unit having a driving capability level greater than or equal to a level threshold; wherein the driving capability level of the second inverter pair unit is greater than the driving capability level of the first inverter pair unit;

[0113] The at least one second inverter pair unit is arranged at a clock port of the memory; the clock port is used to input an input clock provided by the clock tree.

[0114] For example, assuming that the threshold is 3, a second inverter pair unit with a driving capability level of 4 may be firstly set at the clock port of the memory, and then a plurality of first inverter pair units with a driving capability level of 1 may be used to construct a clock tree of the memory.

[0115] Here, when the component to be analyzed is a memory, in addition to using the first clock inverter pairs, it is also necessary to insert at least one second inverter pair with stronger driving capability close to the clock port of the memory. In this way, the clock transition time reaching the memory clock port can be kept short and the crosstalk of the clock net can be reduced to a very low level, making it easier to meet the minpulse width requirement.

[0116] In one example, if Figure 7 As shown in the figure, the process of analyzing the timing of the input clock of the component to be analyzed is described, including:

[0117] Step 701: Replace the buffer unit with a first inverter pair unit, and construct a clock tree based on a plurality of the first inverter pair units; perform clock tree synthesis (CTS).

[0118] here, Figure 8 is a schematic diagram of a constructed clock tree. The clock tree is used to provide input clocks to the components to be analyzed.

[0119] Here, before step 701, the clock tree, components to be analyzed, etc. in the circuit may be arranged (FLOORPLAN) and laid out (PLACE).

[0120] Here, when the component to be wired is a memory, in order to meet the strict requirement of the memory on the minimum pulse width, at least one second inverter pair unit with a larger driving capability level is first set at the clock port of the memory, and then a plurality of first inverter pair units are used to construct the clock tree of the memory.

[0121] Step 702: Routing the clock tree and the components to be analyzed.

[0122] Step 703: Perform static timing analysis (STA) on the input clock provided by the clock tree to the component to be analyzed after routing to obtain an analysis result.

[0123] The analysis result indicates that the minimum pulse width of the input clock is greater than or equal to a preset threshold.

[0124] Here, the clock constraint file can be used to perform timing analysis on the input clock provided by the clock tree to the component to be analyzed after routing. Fig. 9 This is a schematic diagram of the clock constraint file, such as Fig. 9As shown, the clock constraint file may include check contents, namely, timing_type is "min_pulse_width", rise time constraint, namely, rise_constraint, fall time constraint, namely, fall_constraint, and so on.

[0125] Here, the clock tree of the components to be analyzed is constructed based on multiple first inverter pair units, which has the following advantages:

[0126] (1) An improved solution is proposed to repair the minimum pulse width violation in the chip back-end design, that is, when constructing the clock tree, multiple first inverter pair units (clock inverter cells) are used to construct the clock tree to eliminate the minimum pulse width violation. Compared with the method of modifying the clock tree in the related art, it can avoid affecting the chip timing and shorten the chip timing signoff time.

[0127] (2) When checking the minimum pulse width of the memory clock, a clock inverter pair with a stronger driving capability level is inserted into the memory clock port in advance to eliminate the violation of the minimum pulse width and meet the strict requirement of the memory for the minimum pulse width.

[0128] (3) Achieve the following goals without introducing additional chip design workload: improve the clock structure of registers and memories; reduce the possibility of back-end design rework; reduce the time of back-end timing eco; and improve chip performance and robustness.

[0129] (4) A solution to adjust the clock tree synthesis is proposed. The clock tree of the full inverter pair cell and the inverter pair plugged into the memory in advance are adopted to improve the minpulse width violation in the chip back-end design, reduce the possibility of chip rework, and accelerate the timing convergence of the chip. This solution can be applied to subsequent advanced processes to improve the time for chip design convergence.

[0130] By adopting the technical solution of the embodiment of the present invention, the buffer unit is replaced by the first inverter pair unit, and a clock tree is constructed based on multiple of the first inverter pair units. This can eliminate the occurrence of minimum pulse width violations caused by the buffer unit, thereby ensuring that the minimum pulse width of the clock input by the clock tree to the component to be analyzed is not violated, thereby avoiding the chip back-end design taking up a long time.

[0131] In order to implement the timing analysis method of the embodiment of the present invention, the embodiment of the present invention also provides a timing analysis circuit. Fig.10 FIG. 1 is a schematic diagram of the structure of a timing analysis circuit according to an embodiment of the present invention; Fig.10 As shown, the circuit comprises:

[0132] The clock tree circuit 101 is composed of a plurality of first inverter pair units and is used to provide an input clock to the component to be analyzed;

[0133] The component to be analyzed 102 is connected to the clock tree circuit for routing and analyzing the timing of the input clock of the component to be analyzed after routing; the analysis result indicates that the minimum pulse width of the input clock is greater than or equal to a preset threshold.

[0134] In actual application, when the component to be analyzed is a memory, considering that the memory has strict requirements on the minimum pulse width of the input clock and the clock network signal of the memory is prone to crosstalk, before building the clock tree of the memory, an inverter pair unit with a stronger driving capability level can be placed at the clock input port of the memory to ensure that the minimum pulse width of the clock signal reaching the memory is not violated and to reduce the crosstalk of the clock signal.

[0135] Based on this, in one embodiment, the component to be analyzed is a memory; and the circuit further includes:

[0136] The driving circuit is composed of at least one second inverter pair unit and is used to be connected to a clock port of the memory; the clock port is used to input an input clock provided by the clock tree.

[0137] For example, Fig.11 It is a schematic diagram of the structure of the timing analysis circuit corresponding to the memory, such as Fig.11 As shown, the timing analysis circuit includes a clock tree circuit, components to be analyzed (memory), and a driving circuit. The driving capability level of the inverter in the driving circuit to the unit is higher than the driving capability level of the inverter in the clock tree circuit to the unit.

[0138] In order to implement the timing analysis method of the embodiment of the present invention, the embodiment of the present invention also provides a timing analysis device. Fig.12 FIG. 1 is a schematic diagram of the structure of a timing analysis device according to an embodiment of the present invention; Fig.12 As shown, the device comprises:

[0139] The clock tree unit 121 includes a plurality of first inverter pair units, and is used to construct a clock tree based on the plurality of first inverter pair units; the clock tree is used to provide an input clock to the components to be analyzed;

[0140] A wiring unit 122, used for wiring the clock tree and the components to be analyzed;

[0141] The timing analysis unit 123 is used to analyze the timing of the input clock of the component to be analyzed after wiring to obtain an analysis result; the analysis result is used to make the minimum pulse width of the input clock of the component to be analyzed greater than or equal to a preset threshold.

[0142] In one embodiment, the timing analysis unit 123 is specifically used for:

[0143] Determine the period of the original clock input to the clock tree, and determine the first rise time and the first fall time of the original clock passing through each first inverter pair unit in the clock tree; based on the period, the first rise time and the first fall time, analyze the timing of the input clock arriving at the component to be analyzed after routing.

[0144] In one embodiment, the timing analysis unit 123 is specifically used for:

[0145] Determine the high level pulse width and the low level pulse width of the original clock based on the cycle of the original clock; analyze the minimum pulse width of the high level pulse based on the high level pulse width, and the first rise time and the first fall time corresponding to the high level pulse;

[0146] Based on the low level pulse width, and a first rising time and a first falling time corresponding to the low level pulse, the minimum pulse width of the low level pulse is analyzed.

[0147] In one embodiment, the device further comprises:

[0148] A judgment unit is used to judge whether the minimum pulse width of the high-level pulse and the minimum pulse width of the low-level pulse are both greater than or equal to a preset threshold; when it is determined that the minimum pulse width of the high-level pulse and the minimum pulse width of the low-level pulse are both greater than or equal to the preset threshold, it is determined that the minimum pulse width of the input clock is greater than or equal to the preset threshold.

[0149] In one embodiment, the determining unit is further configured to:

[0150] When it is determined that at least one of the minimum pulse width of the high-level pulse and the minimum pulse width of the low-level pulse is less than the preset threshold, the clock parameters of the first inverter pair unit of the last level in the clock tree are adjusted; and the clock tree is reconstructed based on the adjusted first inverter pair unit.

[0151] In one embodiment, the component to be analyzed is a memory; the device further comprises:

[0152] A determination unit, configured to determine at least one second inverter pair unit having a driving capability level greater than or equal to a level threshold; wherein the driving capability level of the second inverter pair unit is greater than the driving capability level of the first inverter pair unit;

[0153] The at least one second inverter pair unit is arranged at a clock port of the memory; the clock port is used to input an input clock provided by the clock tree.

[0154] In actual application, the clock tree unit 121, the wiring unit 122, the timing analysis unit 123, the judgment unit, and the determination unit can be implemented by a processor in the device; the processor can be a central processing unit (CPU), a digital signal processor (DSP), a microcontroller unit (MCU) or a programmable gate array (FPGA).

[0155] It should be noted that: when the device provided in the above embodiment performs timing analysis, only the division of the above program modules is used as an example. In actual application, the above processing can be assigned to different program modules as needed, that is, the internal structure of the terminal is divided into different program modules to complete all or part of the processing described above. In addition, the device provided in the above embodiment and the timing analysis method embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0156] Based on the hardware implementation of the above device, the embodiment of the present invention also provides a timing analysis device, Fig.13 FIG. 1 is a schematic diagram of the hardware structure of the timing analysis device according to an embodiment of the present invention. Fig.13 As shown, the timing analysis device 130 includes a memory 133, a processor 132, and a computer program stored in the memory 133 and executable on the processor 132; when the processor 132 executes the program, the method provided by one or more of the above technical solutions is implemented.

[0157] It should be noted that the specific steps implemented when the processor 132 executes the program have been described in detail above and will not be repeated here.

[0158] It can be understood that the timing analysis device 130 also includes a communication interface 131, and the communication interface 131 is used to exchange information with other devices; at the same time, the various components in the timing analysis device 130 are coupled together through a bus system 134. It can be understood that the bus system 134 is configured to achieve connection and communication between these components. In addition to the data bus, the bus system 134 also includes a power bus, a control bus, and a status signal bus.

[0159] It can be understood that the memory 133 in this embodiment can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAM bus random access memory (DRRAM, Direct Rambus Random Access Memory).The memories described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memories.

[0160] The method disclosed in the above embodiment of the present invention can be applied to the processor 132, or implemented by the processor 132. The processor 132 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 132 or the instruction in the form of software. The above processor 132 may be a general-purpose processor, a DSP, or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 132 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present invention can be directly embodied as a hardware decoding processor to execute, or the hardware and software modules in the decoding processor can be combined to execute. The software module can be located in a storage medium, which is located in a memory. The processor 132 reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0161] The embodiment of the present invention further provides a storage medium, specifically a computer storage medium, more specifically a computer readable storage medium, on which computer instructions, namely a computer program, are stored, and when the computer instructions are executed by a processor, the method provided by one or more of the above technical solutions is implemented.

[0162] In the several embodiments provided by the present invention, it should be understood that the disclosed methods and intelligent devices can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0163] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0164] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0165] A person of ordinary skill in the art can understand that: all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium, which, when executed, executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, disks or optical disks.

[0166] Alternatively, if the above-mentioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention can be essentially or partly reflected in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

[0167] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0168] In addition, the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0169] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A timing analysis method, characterized in that: The method comprises: Based on the plurality of first inverter pair units, a clock tree is constructed; the clock tree is used to provide an input clock to the components to be analyzed; Routing the clock tree and the components to be analyzed; Analyzing the timing of the input clock of the component to be analyzed after wiring to obtain an analysis result; the analysis result indicates that the minimum pulse width of the input clock is greater than or equal to a preset threshold; The step of analyzing the timing of the input clock of the component to be analyzed after wiring to obtain the analysis result includes: Determine whether the minimum pulse width of the input clock is greater than or equal to a preset threshold; the minimum pulse width of the input clock includes the minimum pulse width of a high level pulse and the minimum pulse width of a low level pulse; When it is determined that at least one of the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse is less than the preset threshold, adjusting the clock parameter of the first inverter pair unit of the last stage in the clock tree; The clock tree is reconstructed based on the adjusted first inverter pair unit.

2. The method according to claim 1, characterized in that The step of analyzing the timing of the input clock of the components to be analyzed after wiring also includes: Determine a period of an original clock input into the clock tree, and determine a first rise time and a first fall time of the original clock passing through each first inverter pair unit in the clock tree; Based on the period, the first rising time and the first falling time, the timing of the input clock reaching the component to be analyzed after routing is analyzed.

3. The method according to claim 2, characterized in that The step of analyzing the timing of the input clock that reaches the component to be analyzed after routing based on the period, the first rise time, and the first fall time includes: Based on the cycle of the original clock, determine the high level pulse width and the low level pulse width of the original clock; Analyzing the minimum pulse width of the high-level pulse based on the high-level pulse width, and a first rising time and a first falling time corresponding to the high-level pulse; Based on the low level pulse width, and a first rising time and a first falling time corresponding to the low level pulse, the minimum pulse width of the low level pulse is analyzed.

4. The method according to claim 3, characterized in that The method further comprises: When it is determined that the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse are both greater than or equal to the preset threshold, it is determined that the minimum pulse width of the input clock is greater than or equal to the preset threshold.

5. The method according to claim 1, characterized in that The method further comprises: Determine at least one second inverter pair unit having a driving capability level greater than or equal to a level threshold; wherein the driving capability level of the second inverter pair unit is greater than the driving capability level of the first inverter pair unit; The at least one second inverter pair unit is arranged at a clock port of the component to be analyzed; the clock port is used to input an input clock provided by the clock tree.

6. A timing analysis circuit, characterized in that: include: A clock tree circuit, composed of a plurality of first inverter pair units, for providing an input clock to the components to be analyzed; The components to be analyzed are connected to the clock tree circuit for wiring, and the timing of the input clock of the components to be analyzed after wiring is analyzed to obtain analysis results; The analysis result indicates that the minimum pulse width of the input clock is greater than or equal to a preset threshold; The components to be analyzed are also used to determine whether the minimum pulse width of the input clock is greater than or equal to a preset threshold; the minimum pulse width of the input clock includes the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse; When it is determined that at least one of the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse is less than the preset threshold, adjusting the clock parameter of the first inverter pair unit of the last stage in the clock tree; The clock tree is reconstructed based on the adjusted first inverter pair unit.

7. The circuit according to claim 6, characterized in that The component to be analyzed is a memory; the circuit further includes: The driving circuit is composed of at least one second inverter pair unit and is used to be connected to a clock port of the memory; the clock port is used to input an input clock provided by the clock tree.

8. A timing analysis device, characterized in that: include: A clock tree unit, comprising a plurality of first inverter pair units, wherein the clock tree is used to provide an input clock to a component to be analyzed; A wiring unit, used for wiring the clock tree and the components to be analyzed; A timing analysis unit, used to analyze the timing of the input clock of the component to be analyzed after wiring, and obtain an analysis result; The analysis result is used to make the minimum pulse width of the input clock of the component to be analyzed greater than or equal to a preset threshold; A judging unit, used to judge whether the minimum pulse width of the input clock is greater than or equal to a preset threshold; The minimum pulse width of the input clock includes the minimum pulse width of a high level pulse and the minimum pulse width of a low level pulse; When it is determined that at least one of the minimum pulse width of the high level pulse and the minimum pulse width of the low level pulse is less than the preset threshold, adjusting the clock parameter of the first inverter pair unit of the last stage in the clock tree; The clock tree is reconstructed based on the adjusted first inverter pair unit.

9. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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