DRAM testing method, device, readable storage medium and electronic device
By using preset burst length and masking technology for bitwise access in DRAM testing, the problem of low fault coverage in the prior art is solved, and more efficient fault detection and more reliable test results are achieved.
Patent Information
- Application Number
- CN202011136998.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-10-22
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2040-10-22
AI Technical Summary
Existing DRAM testing methods are difficult to fully detect bridge faults, coupling faults and other faults between memory cells, resulting in low fault coverage.
A DRAM test method is adopted to write data from both ends of the DRAM reading and writing units to the middle by preset burst length as units, and use mask strobes and mask bits during the writing process to achieve bitwise access. Incites faults between memory units.
It improves the fault coverage during DRAM testing, can be closer to the user's usage environment, detects hard-to-discover chip defects, and improves the reliability and comprehensiveness of the test.
Smart Images
Figure CN112216339B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of DRAM chip testing, and in particular to a DRAM testing method, device, readable storage medium and electronic equipment. Background Art
[0002] Dynamic Random Access Memory (DRAM) is an indispensable component of modern computer systems. Different platforms include DDR modules used in personal computers or servers and LPDDR chips used in embedded ARM architecture.
[0003] The basic storage unit of DRAM is cell. Computers and embedded systems store and read data by writing high or low levels in cells. However, due to the influence of process technology, the storage cell may cause data storage failure when reading and writing.
[0004] At present, DRAM adopts burst read and write mode for efficient access rate, that is, read and write operations are performed in burst length (BL) units in a storage array, and multiple bits (such as 8 or 16 bits) of column addresses are read and written at a time, and data consisting of 0 and 1 is accessed in each burst length. For example, if the address is located at row 0 and the burst length is 8 bits, then 1 bit of data is written to each bit in the space from row 0, column 0 to row 0, column 7, for a total of 8 bits. The second burst length is from row 0, column 8 to column 15, and so on. When all the storage locations of a row are written, the memory controller (MC) locates the address of the next row and continues the same operation.
[0005] Although the burst read / write method makes data access more efficient, it is difficult to stimulate bridging faults (BF), coupling faults (CF), and other cell faults between storage cells when performing memory testing through the burst read / write access method. Therefore, it is impossible to fully detect the fault problems between cells in the DRAM. Summary of the invention
[0006] The technical problem to be solved by the present invention is to provide a DRAM testing method, device, readable storage medium and electronic equipment to improve the coverage of faults when testing DRAM.
[0007] In order to solve the above technical problems, a technical solution adopted by the present invention is:
[0008] A DRAM testing method includes the following steps:
[0009] Writing data from both ends of each first preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and performing data reading corresponding to the data writing process, comparing the read data with the corresponding written data, and obtaining a first comparison result;
[0010] Writing data from both ends of each second preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and performing data reading corresponding to the data writing process, comparing the read data with the corresponding written data, and obtaining a second comparison result;
[0011] In the process of writing data in units of the preset burst length, the preset write bits of the preset burst length are sequentially selected by masking and the remaining bits are masked until data is written to each bit corresponding to the preset burst length;
[0012] The first preset read-write unit is different from the second preset read-write unit;
[0013] A test result of the DRAM to be tested is obtained according to the first comparison result and the second comparison result.
[0014] In order to solve the above technical problems, another technical solution adopted by the present invention is:
[0015] A DRAM testing device, comprising:
[0016] A first data reading and writing module is used to write data from both ends of each first preset reading and writing unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and to read data corresponding to the data writing process, and compare the read data with the corresponding written data to obtain a first comparison result;
[0017] A second data reading and writing module is used to write data from both ends of each second preset reading and writing unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and to read data corresponding to the data writing process, and compare the read data with the corresponding written data to obtain a second comparison result;
[0018] The first preset read-write unit is different from the second preset read-write unit;
[0019] A testing module is used to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.
[0020] In order to solve the above technical problems, another technical solution adopted by the present invention is:
[0021] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, each step in the above DRAM testing method is implemented.
[0022] In order to solve the above technical problems, another technical solution adopted by the present invention is:
[0023] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements each step of the above-mentioned DRAM testing method when executing the computer program.
[0024] The beneficial effect of the present invention is that: the DRAM to be tested is first subjected to a burst read / write access operation based on a first preset read / write unit in units of a preset burst length, and then subjected to a burst read / write access operation based on a second preset read / write unit. The first preset read / write unit is different from the second preset read / write unit. Since the read / write access of the preset read / write unit is performed from both ends of the preset read / write unit to the middle at the same time, and the preset write bits of the preset burst length are selected in sequence through a mask and the remaining bits are shielded until data is written to each bit corresponding to the preset burst length. Therefore, it is closer to the user's use environment, and compared with the existing burst access test, by using a mask to achieve bit-by-bit access within a burst length, it is more capable of stimulating faults between cells, thereby improving the fault coverage rate when testing DRAM. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A flowchart of a DRAM testing method according to an embodiment of the present invention;
[0026] Figure 2 A schematic diagram of the structure of a DRAM testing device according to an embodiment of the present invention;
[0027] Figure 3 A schematic diagram of the structure of an electronic device according to an embodiment of the present invention;
[0028] Figure 4 A schematic diagram of data writing of a first model in a DRAM testing method according to an embodiment of the present invention;
[0029] Figure 5 A schematic diagram of data reading of a first model in a DRAM testing method according to an embodiment of the present invention;
[0030] Figure 6A schematic diagram of a first round of burst data writing of a first segment column address of a second model in a DRAM testing method according to an embodiment of the present invention;
[0031] Figure 7 A schematic diagram of a second round of burst data writing of a first segment column address of a second model in a DRAM test method according to an embodiment of the present invention;
[0032] Figure 8 A schematic diagram of writing burst data of the second column address of the second model in the DRAM test method according to an embodiment of the present invention;
[0033] Fig. 9 A schematic diagram of data reading of a second model in a DRAM testing method according to an embodiment of the present invention;
[0034] Fig.10 Another structural schematic diagram of a DRAM testing device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0035] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.
[0036] like Figure 1 As shown, an embodiment of the present invention provides a DRAM testing method, comprising the steps of:
[0037] Writing data from both ends of each first preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and performing data reading corresponding to the data writing process, comparing the read data with the corresponding written data, and obtaining a first comparison result;
[0038] Writing data from both ends of each second preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and performing data reading corresponding to the data writing process, comparing the read data with the corresponding written data, and obtaining a second comparison result;
[0039] In the process of writing data in units of the preset burst length, the preset write bits of the preset burst length are sequentially selected by masking and the remaining bits are masked until data is written to each bit corresponding to the preset burst length;
[0040] The first preset read-write unit is different from the second preset read-write unit;
[0041] A test result of the DRAM to be tested is obtained according to the first comparison result and the second comparison result.
[0042] From the above description, it can be seen that the beneficial effect of the present invention is that: the DRAM to be tested is first subjected to a burst read / write access operation based on a first preset read / write unit in units of a preset burst length, and then a burst read / write access operation based on a second preset read / write unit is performed. The first preset read / write unit is different from the second preset read / write unit. Since the read / write access of the preset read / write unit is performed from both ends of the preset read / write unit to the middle at the same time, and the preset write bits of the preset burst length are selected in turn through a mask and the remaining bits are masked until data is written to each bit corresponding to the preset burst length. Therefore, it is closer to the user's environment, and compared with the existing burst access test, by using a mask to achieve bit-by-bit access within a burst length, it is more capable of stimulating cell-to-cell faults, thereby improving the fault coverage rate when testing DRAM.
[0043] Further, the first preset read-write unit is a row, and the second preset read-write unit is a column;
[0044] Writing data from both ends of each first preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data includes:
[0045] Starting from the first column and the last column of each row of the DRAM to be tested, data is simultaneously written to the middle of each row in units of the preset burst length until data is written to each column of each row.
[0046] From the above description, it can be seen that for each row of the DRAM to be tested, data is written to the middle simultaneously in preset burst length units starting from the first column and the last column until data is written to each column of each row. This method can well simulate the actual user's use environment of the DRAM chip, ensure the reliability of the test, and have low time complexity.
[0047] Furthermore, in the process of writing data to each row in units of the preset burst length:
[0048] For a first preset burst length located in the first half of each row, each bit of the first preset burst length is selected in ascending order of the sequence number corresponding to each bit in the first preset burst length by masking, and the remaining bits are masked until data is written to each bit corresponding to the first preset burst length;
[0049] For the corresponding second preset burst length located in the second half of each row and written with data simultaneously with the first preset burst length, each bit of the second preset burst length is selected in sequence from large to small in the order of the serial number corresponding to each bit in the second preset burst length through a mask, and the remaining bits are masked until data is written to each bit corresponding to the second preset burst length.
[0050] From the above description, it can be seen that in the process of writing from the first half and the second half of each row to the middle at the same time in units of preset burst length, the masks are used to select them in sequence, so that the bit-by-bit selection test mode can be implemented within a burst length, which can better stimulate the faults between cells and improve the fault coverage when testing DRAM.
[0051] Further, the first preset read-write unit is a column, and the second preset read-write unit is a row;
[0052] The step of writing data from both ends of each first preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data comprises:
[0053] Starting from the first row and the last row of each column of the DRAM to be tested, data is simultaneously written to the middle of each column in units of the preset burst length until data is written to each row of each column.
[0054] From the above description, it can be seen that starting from the first row and the last row of each column of the DRAM to be tested, data is written to the middle of each column at the same time in units of burst length until data is written to each row of each column. This method can well simulate the user's actual usage environment of the DRAM chip, ensure the reliability of the test, and have low time complexity.
[0055] Furthermore, in the process of writing data to each column in units of a preset burst length:
[0056] For a third preset burst length located in the first half of each column, two bits located at both ends of the third preset burst length are selected in sequence from both ends to the middle through a mask, and the remaining bits are masked until data is written to each bit corresponding to the third preset burst length;
[0057] For the fourth preset burst length corresponding to the second half of each column and in which data is written simultaneously with the third preset burst length, the two bits located at both ends of the fourth preset burst length are selected simultaneously from both ends to the middle through a mask and the remaining bits are masked until data is written to each bit corresponding to the fourth preset burst length.
[0058] From the above description, it can be seen that in the process of writing from the first half and the second half of each column to the middle at the same time in units of preset burst length, the masks are used to select them in sequence, so that the bit-by-bit selection test mode can be implemented within a burst length, which can better stimulate the faults between cells and improve the fault coverage when testing DRAM.
[0059] Further, a corresponding number of columns are sequentially selected based on the preset burst length to form an array;
[0060] Data is written in units of the array until all columns of the DRAM to be tested are traversed.
[0061] From the above description, it can be seen that the corresponding number of columns are selected in turn to form an array for write operation based on the preset burst length, which is closer to the write operation of the burst access test mode. This method can well simulate the user's actual usage environment of the DRAM chip and improve the fault coverage when testing DRAM.
[0062] Further, the data reading corresponding to the data writing process includes:
[0063] Performing data reading corresponding to the data writing process in units of the preset burst length;
[0064] In the process of reading data in units of the preset burst length, all data within the preset burst length are directly read.
[0065] From the above description, it can be seen that the method of reading data in units of a burst length can well simulate the actual usage environment of the user for the DRAM chip, reduce time complexity, and facilitate mass production.
[0066] Another embodiment of the present invention provides a DRAM testing device, comprising:
[0067] A first data reading and writing module is used to write data from both ends of each first preset reading and writing unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and to read data corresponding to the data writing process, and compare the read data with the corresponding written data to obtain a first comparison result;
[0068] A second data reading and writing module is used to write data from both ends of each second preset reading and writing unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and to read data corresponding to the data writing process, and compare the read data with the corresponding written data to obtain a second comparison result;
[0069] In the process of writing data in units of the preset burst length, the preset write bits of the preset burst length are sequentially selected by masking and the remaining bits are masked until data is written to each bit corresponding to the preset burst length;
[0070] The first preset read-write unit is different from the second preset read-write unit;
[0071] A testing module is used to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.
[0072] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program implements each step of the above DRAM testing method.
[0073] Another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements each step of the above-mentioned DRAM testing method when executing the computer program.
[0074] Another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements each step of the above-mentioned DRAM testing method when executing the computer program.
[0075] The DRAM testing method, device, computer-readable storage medium and electronic device of the present invention can be applied to various generations of DDR and LPDDR products, and are described below through specific implementation methods:
[0076] Embodiment 1
[0077] Please refer to Figure 1 , a DRAM testing method, comprising the steps of:
[0078] S1, writing data from both ends of each first preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and performing data reading corresponding to the data writing process, comparing the read data with the corresponding written data, and obtaining a first comparison result;
[0079] S2, writing data from both ends of each second preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and performing data reading corresponding to the data writing process, comparing the read data with the corresponding written data, and obtaining a second comparison result;
[0080] In the process of writing data in units of the preset burst length, the preset write bits of the preset burst length are sequentially selected by masking and the remaining bits are masked until data is written to each bit corresponding to the preset burst length;
[0081] The first preset read-write unit is different from the second preset read-write unit;
[0082] S3, obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result;
[0083] Specifically, the read data is compared with the corresponding expected data in the read operation in turn. If the data is inconsistent, it can be judged as FAIL. If the data in all address spaces are correct, it is judged as PASS.
[0084] The first preset read-write unit and the second preset read-write unit can be combined in different ways and implemented through different models:
[0085] In this embodiment, the first preset read-write unit is a row, and the second preset read-write unit is a column;
[0086] The step of writing data from both ends of each first preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data comprises:
[0087] Starting from the first column and the last column of each row of the DRAM to be tested, data is simultaneously written to the middle of each row in units of the preset burst length until data is written to each column of each row.
[0088] Specifically, for the first preset burst length located in the first half of each row, each bit of the first preset burst length is selected in ascending order of the sequence number corresponding to each bit in the first preset burst length through a mask, and the remaining bits are masked until data is written to each bit corresponding to the first preset burst length;
[0089] For the corresponding second preset burst length located in the second half of each row and written with data simultaneously with the first preset burst length, each bit of the second preset burst length is selected in sequence from large to small in the order of the serial number corresponding to each bit in the second preset burst length through a mask, and the remaining bits are masked until data is written to each bit corresponding to the second preset burst length.
[0090] The burst length (BL) is determined by the JEDEC standard and can also be set freely, that is, multiple bits (such as 8 bits or 16 bits) are operated at one time for corresponding reading and writing. For example, when writing data based on rows, if the address is row 0 and the burst length is 8 bits, the first 8 bits of the data to be written are written at the same time starting from the position of row 0 and column 0, and then the second burst length is used to write bits 9-16 of the data to be written. The writing is continued until all the storage locations of row 0 are written, and then the address of the next row is relocated, and the operation of the previous row is continued until the data is written to the entire disk. The reading of data is also a similar operation.
[0091] In this embodiment, the specific Figure 4 As shown, first, a burst access write operation is performed on the row:
[0092] The default burst access length is BL = 8 bits. Assuming that each row has 1024 bits, the data content to be written is defined as DX, and the mask is defined as DM, such as:
[0093] DX=11111111;
[0094] DM = 01111111;
[0095] The DM value of 0 indicates that the bit is written, and 1 indicates that the bit is masked.
[0096] First, in the first round of burst access, the first address to be written in the first half and the second half of the first row is determined, and the number of pre-written bits is determined based on the burst length. The pre-written addresses of this round are: columns 0-7 of the first half of the first row and columns 1016-1023 of the second half.
[0097] In the first write operation in this round, the mask corresponding to the storage cells in columns 0-7 of the first half of the first row is set to DM=01111111, and the mask corresponding to the storage cells in columns 1016-1023 of the second half of the first row is set to DM=11111110, that is, the first column 0 of the first half and the first column 1023 of the second half are selected as the write bits for this time, and the remaining bits are masked for the first write;
[0098] During the second write operation in this round, the mask corresponding to the storage cells in columns 0-7 of the first half of the first row is set to DM=10111111, and the mask corresponding to the storage cells in columns 1016-1023 of the second half of the first row is set to DM=11111101, that is, the second column 1 of the first half and the second column 1022 of the second half are selected as the write bits this time, and the remaining bits are masked for the second write;
[0099] Similarly, the first half and the second half are written at the same time, and eight write operations are completed, so that the entire 8-bit burst length storage unit is written with data, and this round of burst access write operation ends;
[0100] Next, when performing the second round of burst access, the first address to be written in the first half and the second half of the first row is first determined, and the number of pre-written bits is determined based on the burst length, and the pre-written addresses of this round are obtained as follows: columns 8-15 of the first half of the first row and columns 1008-1015 of the second half;
[0101] Then, according to the method of the first round of burst access write operation, the first half is written in the order of columns 8 to 15, and the second half is written in the order of columns 1015 to 1008, and the two parts are written simultaneously to complete the write operation of this round of burst access, and so on to write data to all columns of this row;
[0102] Finally, switch to the next row and repeat the same operation until all the memory cells of the DRAM to be tested are written with data;
[0103] After the write operation is completed, the data read operation corresponding to the data write is performed. In each round of burst read operation, all 8 bits of data within the burst length are directly read, such as Figure 5 As shown:
[0104] The data reading corresponding to the data writing process includes:
[0105] Performing data reading corresponding to the data writing process in units of the preset burst length;
[0106] In the process of reading data in units of the preset burst length, all data within the preset burst length are directly read.
[0107] In the first round of burst read operation, the read operation process directly reads all 8 bits of data within the burst length, that is, the data in the storage cells of columns 0-7 in the first half and columns 1016-1023 in the second half of the first row, and compares them with the data DX written in the first round of burst write operation;
[0108] In the second round of burst access, the data in the storage cells of columns 8-15 in the first half and columns 1008-1015 in the second half of the first row are read and compared with the data DX written in the corresponding second round of burst write operation;
[0109] Similarly, the first half and the second half perform read operations simultaneously until all storage cells in the first row are written with data, switch to the next row, and repeat the same operation until all storage cells of the DRAM to be tested are read and compared with the corresponding written data to obtain a first comparison result.
[0110] After performing a burst access write and read operation on the row, a burst access write and read operation is then performed on the column. Specifically:
[0111] First perform a column-based burst access write operation:
[0112] Starting from the first row and the last row of each column of the DRAM to be tested, writing data to the middle of each column simultaneously in units of the preset burst length until data is written to each row of each column;
[0113] Specifically, in the process of writing data to each column in units of the preset burst length:
[0114] For a third preset burst length located in the first half of each column, two bits located at both ends of the third preset burst length are selected in sequence from both ends to the middle through a mask, and the remaining bits are masked until data is written to each bit corresponding to the third preset burst length;
[0115] For the fourth preset burst length corresponding to the second half of each column and to which data is written simultaneously with the third preset burst length, two bits at both ends of the fourth preset burst length are selected in sequence from both ends to the middle through a mask and the remaining bits are masked until data is written to each bit corresponding to the fourth preset burst length;
[0116] Taking the preset burst length as a unit, sequentially selecting a corresponding number of columns to form an array;
[0117] Writing data in units of the array until all columns of the DRAM to be tested are traversed;
[0118] In this embodiment, specifically, Figure 6 , 7 As shown, first, a burst access write operation is performed on the column:
[0119] First, in the first round of burst access, the first address of the first column of the array is determined, and the corresponding number of columns are selected in sequence to form an array based on the burst length, and the number of pre-written bits is determined, and the array is obtained as follows: 0-7 columns, 0-16383 rows; the pre-written addresses of this round are obtained as follows: 0-7 columns of the first row and 0-7 columns of the last row;
[0120] like Figure 6 As shown, in the first write operation in this round, by setting the mask corresponding to the storage cells of columns 0-7 pre-written in this round to: DM=01111110, the first column and the eighth column in a burst length unit, that is, the 0th column and the 7th column of the first row and the 0th column and the 7th column of the last row 16383rd row, are selected, and the remaining bits are masked for the first write;
[0121] like Figure 7 As shown, during the second write operation in this round, the mask corresponding to the storage cells of columns 0-7 pre-written in this round is set to: DM=10111101, the second column and the sixth column in a burst length unit are selected, that is, the first column and the sixth column of the first row and the first column and the sixth column of the 16383rd row of the last row, and the remaining bits are masked for the second write;
[0122] Similarly, the first half and the second half are written at the same time, and four write operations are completed, so that the entire 8-bit burst length storage unit is written with data, and this round of burst access write operation ends;
[0123] Next, the second round of burst access is performed. First, the first position of the second row in the first half of the array and the second row in the second half are determined. The number of bits to be written is determined based on the burst length. The pre-written addresses for this round are obtained as follows: 0-7 columns of the second row and 0-7 columns of the 16382nd row.
[0124] Then, according to the method of the first round of write operation, data is written from the 0th column and the 7th column to the middle at the same time to complete the write operation of this round of burst access, and so on to write data to all storage cells of the array;
[0125] Further, a write operation is performed on the second array, such as Figure 8 As shown:
[0126] First, when the array is accessed in the first round of burst, the first address of the first column of the array is determined, and the corresponding number of columns are selected in sequence in units of burst length to form an array, and the number of pre-written bits is determined, and the array is obtained as follows: 8-15 columns, 0-16383 rows; the pre-written addresses of this round are obtained as follows: 8-15 columns of the first row and 8-15 columns of the last row;
[0127] In the first write operation in this round, the mask corresponding to the 8-15 column storage cells pre-written in this round is set to: DM = 01111110, the first column and the eighth column in a burst length unit, that is, the 8th and 15th columns of the first row and the 8th and 15th columns of the last row are selected, and the remaining bits are masked for the first write;
[0128] During the second write operation in this round, the mask corresponding to the 8-15 columns of storage cells pre-written in this round is set to: DM=10111101, the second column and the seventh column in a burst length unit, that is, the 9th and 14th columns of the first row and the 9th and 14th columns of the last row, are selected, and the remaining bits are masked for the second write;
[0129] Similarly, the front and back parts are written at the same time, and four write operations are completed, so that the entire 8-bit burst length storage unit is written with data, and this round of burst access write operation ends;
[0130] Next, the second round of burst access is performed. First, the first position of the second row in the first half of the array and the second row in the second half are determined, and the number of bits to be written is determined in units of burst length. The pre-write addresses of this round are obtained as follows: 8-15 columns of the 2nd row and 8-15 columns of the 16382nd row.
[0131] Then, according to the method of the first round of write operation, data is written to the middle from the 8th column and the 15th column at the same time to complete the write operation of this round of burst access, and so on to write data to all storage cells of the array;
[0132] Finally, switch to the next array and repeat the same operation until all the memory cells of the DRAM to be tested are written with data;
[0133] After the write operation is completed, the data read operation corresponding to the data write is performed, such as Fig. 9 As shown;
[0134] In the first round of burst read operation, the read operation process directly reads all 8 bits of data within the burst length, that is, the data in the storage cells of columns 0-7 of the first row of the first half and columns 0-7 of the last row of the second half, and compares them with the data DX written in the first round of burst write operation;
[0135] In the second round of burst access, the data in the storage cells of columns 0-7 of the second row of the first half and columns 0-7 of the second row of the second half are read and compared with the data DX written in the second round of burst write operation;
[0136] Similarly, the first half and the second half perform read operations simultaneously until all storage cells in the first array have read data, switch to the next array, and repeat the same operation until all storage cells in the DRAM to be tested have been read and compared with the corresponding written data to obtain a second comparison result.
[0137] Obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result;
[0138] Specifically, if the comparison result shows that the data is inconsistent, it can be judged as FAIL. If the data in all address spaces are correct after comparison, it can be judged as PASS.
[0139] Embodiment 2
[0140] In this embodiment, the first preset read-write unit is a column, and the second preset read-write unit is a row;
[0141] The step of writing data from both ends of each first preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data comprises:
[0142] Starting from the first row and the last row of each column of the DRAM to be tested, data is simultaneously written to the middle of each column in units of the preset burst length until data is written to each row of each column.
[0143] Specifically, Figure 6-Figure 8As shown, first, a burst access write operation is performed on the column;
[0144] After the data is written, Fig. 9 As shown, a burst access read operation of the column is then performed, and all data in the burst length unit is directly read in sequence according to the writing order and compared to obtain a first comparison result;
[0145] After the burst access write and read operation is performed based on the column, the burst access write and read operation is then performed based on the row;
[0146] Specifically, Figure 4 ,First, a burst access write operation is performed on the row;
[0147] After the data is written, Figure 5 As shown, a burst access read operation of the row is then performed, and all data in the burst length unit is directly read in sequence according to the writing order and compared to obtain a second comparison result;
[0148] Finally, a test result of the DRAM to be tested is obtained according to the first comparison result and the second comparison result;
[0149] Specifically, the read data and the corresponding expected written data are compared in sequence through the comparison link in the read operation. If the data is inconsistent, it can be determined as FAIL. If the data in the entire address space is correct after comparison, it is determined as PASS.
[0150] Embodiment 3
[0151] Please refer to Figure 2 , a DRAM testing device, comprising:
[0152] A first data reading and writing module is used to write data from both ends of each first preset reading and writing unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and to read data corresponding to the data writing process, and compare the read data with the corresponding written data to obtain a first comparison result;
[0153] A second data reading and writing module is used to write data from both ends of each second preset reading and writing unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and to read data corresponding to the data writing process, and compare the read data with the corresponding written data to obtain a second comparison result;
[0154] In the process of writing data in units of the preset burst length, the preset write bits of the preset burst length are sequentially selected by masking and the remaining bits are masked until data is written to each bit corresponding to the preset burst length;
[0155] The first preset read-write unit is different from the second preset read-write unit;
[0156] A testing module is used to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.
[0157] Further, such as Fig.10 As shown, the first data reading and writing module can be subdivided into:
[0158] A first data writing module, used for writing data from both ends of each first preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data;
[0159] A first data reading module, used for reading corresponding data according to the data writing process of the first data writing module;
[0160] A first comparison module, configured to compare the data written by the first data writing module with the data read by the first data reading module to obtain a first comparison result;
[0161] The second data reading and writing module is subdivided into:
[0162] A second data writing module is used to write data from both ends of each second preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data;
[0163] A second data reading module, used to read corresponding data according to the data writing process of the second data writing module;
[0164] The second comparison module is used to compare the data written by the second data writing module with the data read by the second data reading module to obtain a second comparison result.
[0165] Embodiment 4
[0166] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the computer program implements each step of a DRAM testing method in the first or second embodiment.
[0167] Embodiment 5
[0168] Please refer to Figure 3, an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, each step in a DRAM testing method in the first or second embodiment is implemented.
[0169] In summary, the present invention provides a DRAM test method, device, computer-readable storage medium and electronic device, which first perform a burst access read-write operation based on a first preset read-write unit, and then perform a burst access read-write operation based on a second preset read-write unit. The first preset read-write unit is different from the second preset read-write unit, and can be accessed by column priority first and then row priority, or by row priority first and then column priority. The test flexibility is high, and in the process of writing data in units of a preset burst length, the preset write bits of the preset burst length are selected in sequence by a mask and the remaining bits are masked until data is written to each bit corresponding to the preset burst length. In the case of being close to the user's use environment, multiple writing modes, especially the bit-by-bit writing mode, are realized. Compared with the existing test mode of writing all data at once in units of burst length used for burst access testing, it is easier to stimulate cell faults such as bridge faults and coupling faults between cells, thereby covering the previous test blind area and detecting chip defects that were previously difficult to find, improving the yield, making the DRAM test more reliable and comprehensive, and achieving the purpose of low time complexity, suitability for mass production testing, and reducing production costs.
[0170] In the above embodiments provided in the present application, it should be understood that the disclosed methods, devices, computer-readable storage media, and electronic devices can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple components or modules can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or components or modules, which can be electrical, mechanical or other forms.
[0171] The components described as separate components may or may not be physically separated, and the components shown as components may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the components may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0172] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each component may exist physically separately, or two or more modules may be integrated into one module. The above integrated modules may be implemented in the form of hardware or in the form of software functional modules.
[0173] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.
[0174] It should be noted that, for the convenience of description, the aforementioned method embodiments are all described as a series of action combinations, but those skilled in the art should be aware that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.
[0175] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0176] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A DRAM testing method, characterized in that: Includes steps: Writing data from both ends of each first preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and performing data reading corresponding to the data writing process, comparing the read data with the corresponding written data, and obtaining a first comparison result; Writing data from both ends of each second preset read / write unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and performing data reading corresponding to the data writing process, comparing the read data with the corresponding written data, and obtaining a second comparison result; In the process of writing data in units of the preset burst length, the preset write bits of the preset burst length are sequentially selected by masking and the remaining bits are masked until data is written to each bit corresponding to the preset burst length; The first preset read-write unit is different from the second preset read-write unit; Obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result; The first preset read / write unit is a row, and the second preset read / write unit is a column; or The first preset read-write unit is a column, and the second preset read-write unit is a row.
2. A DRAM testing method according to claim 1, characterized in that: If the first preset read / write unit is a row and the second preset read / write unit is a column; then writing data from both ends to the middle of each first preset read / write unit of the DRAM to be tested in units of a preset burst length until all storage units of the DRAM to be tested are written with data includes: Starting from the first column and the last column of each row of the DRAM to be tested, data is simultaneously written to the middle of each row in units of the preset burst length until data is written to each column of each row.
3. A DRAM testing method according to claim 2, characterized in that: In the process of writing data to each row in units of the preset burst length: For a first preset burst length located in the first half of each row, each bit of the first preset burst length is selected in ascending order of the sequence number corresponding to each bit in the first preset burst length by masking, and the remaining bits are masked until data is written to each bit corresponding to the first preset burst length; For the corresponding second preset burst length located in the second half of each row and written with data simultaneously with the first preset burst length, each bit of the second preset burst length is selected in sequence from large to small in the order of the serial number corresponding to each bit in the second preset burst length through a mask, and the remaining bits are masked until data is written to each bit corresponding to the second preset burst length.
4. A DRAM testing method according to claim 1, characterized in that: If the first preset read / write unit is a column and the second preset read / write unit is a row; then writing data from both ends to the middle of each first preset read / write unit of the DRAM to be tested in units of a preset burst length until all storage units of the DRAM to be tested are written with data includes: Starting from the first row and the last row of each column of the DRAM to be tested, data is simultaneously written to the middle of each column in units of the preset burst length until data is written to each row of each column.
5. A DRAM testing method according to claim 4, characterized in that: In the process of writing data to each column in units of the preset burst length: For a third preset burst length located in the first half of each column, two bits located at both ends of the third preset burst length are selected in sequence from both ends to the middle through a mask, and the remaining bits are masked until data is written to each bit corresponding to the third preset burst length; For the fourth preset burst length corresponding to the second half of each column and in which data is written simultaneously with the third preset burst length, the two bits located at both ends of the fourth preset burst length are selected simultaneously from both ends to the middle through a mask and the remaining bits are masked until data is written to each bit corresponding to the fourth preset burst length.
6. A DRAM testing method according to claim 4 or 5, characterized in that: Taking the preset burst length as a unit, sequentially selecting a corresponding number of columns to form an array; Data is written in units of the array until all columns of the DRAM to be tested are traversed.
7. A DRAM testing method according to any one of claims 1 to 5, characterized in that: The data reading corresponding to the data writing process includes: Performing data reading corresponding to the data writing process in units of the preset burst length; In the process of reading data in units of the preset burst length, all data within the preset burst length are directly read.
8. A DRAM testing device, characterized in that: include: A first data reading and writing module is used to write data from both ends of each first preset reading and writing unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and to read data corresponding to the data writing process, and compare the read data with the corresponding written data to obtain a first comparison result; A second data reading and writing module is used to write data from both ends of each second preset reading and writing unit of the DRAM to be tested to the middle in units of a preset burst length until all storage units of the DRAM to be tested are written with data, and to read data corresponding to the data writing process, and compare the read data with the corresponding written data to obtain a second comparison result; In the process of writing data in units of the preset burst length, the preset write bits of the preset burst length are sequentially selected by masking and the remaining bits are masked until data is written to each bit corresponding to the preset burst length; The first preset read-write unit is different from the second preset read-write unit; A testing module, configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result; The first preset read / write unit is a row, and the second preset read / write unit is a column; or The first preset read-write unit is a column, and the second preset read-write unit is a row.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, each step in a DRAM testing method as described in any one of claims 1 to 7 is implemented.
10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, each step of the DRAM testing method as described in any one of claims 1 to 7 is implemented.