Wafer testing circuit unit and method, wafer testing circuit, wafer

Abstract

The present disclosure relates to a wafer test circuit unit and method, a wafer test circuit, and a wafer. The wafer test circuit unit is used for wafer testing. The wafer includes a grain area and a scribe line. The grain area includes at least one grain. The wafer test circuit unit includes a test pad, a control pad, and a parasitic resistance simulation circuit. The test pad is arranged on the scribe line for inputting a test signal. The control pad is arranged on the scribe line for inputting a control signal. The parasitic resistance simulation circuit is respectively connected to the test pad, the control pad, and the grain for simulating the external parasitic resistance of the grain, and transmitting the test signal to the grain in response to the control signal.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a wafer testing circuit unit and method, a wafer testing circuit, and a wafer. Background Art

[0002] With the development and advancement of technology, chips are used more and more widely in various electronic products. Chips are usually set on printed circuit boards. The die packaged inside the chip are electrically connected to external pins through package leads, and the external pins are connected to electrical signal contact points on the printed circuit board through printed circuit board routing.

[0003] The package leads and printed circuit board (PCB) traces have a certain resistance value, that is, the die packaged in the chip has external parasitic resistance. This external parasitic resistance will change the signal of the input die and affect the accuracy of the signal, such as changing the current and frequency of the input signal, thereby affecting the normal operation of the chip.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a wafer test circuit unit and method, a wafer test circuit, and a wafer, thereby solving the problem of abnormal chip operation due to external parasitic resistance of the grain in the related art to a certain extent.

[0006] According to a first aspect of the present disclosure, a wafer test circuit unit is provided for wafer testing, wherein the wafer comprises a grain region and a scribe line, the grain region comprises at least one grain, and the wafer test circuit unit comprises:

[0007] A test pad, disposed on the scribe line, for inputting a test signal;

[0008] A control pad, disposed on the scribe line, for inputting a control signal;

[0009] The parasitic resistance simulation circuit is arranged in the dicing road, connected to the test pad, the control pad and the crystal grain respectively, and is used for simulating the external parasitic resistance of the crystal grain, and transmitting the test signal to the crystal grain in response to the control signal.

[0010] According to an embodiment of the present disclosure, the parasitic resistance simulation circuit includes:

[0011] A first switch element has a first end connected to the test pad, a second end connected to the die, and a control end connected to the control pad.

[0012] According to one embodiment of the present disclosure, the control pad includes:

[0013] A first control pad, used for inputting a first control signal;

[0014] A second control pad, used for inputting a second control signal;

[0015] The parasitic resistance simulation circuit also includes:

[0016] A second switch element, a first end of which is connected to the test pad, and a second end of which is connected to the die;

[0017] A third switch element, a first end of which is connected to the test pad, and a second end of which is connected to the die;

[0018] A test mode selection circuit has two input terminals and multiple output terminals, wherein the first input terminal is connected to the first control pad, the second input terminal is connected to the second control pad, the first output terminal is connected to the control terminal of the first switch element, the second output terminal is connected to the control terminal of the second switch element, and the third output terminal is connected to the control terminal of the third switch element.

[0019] According to an embodiment of the present disclosure, the test mode selection circuit includes:

[0020] A first inverter, an input end of which is connected to the first control pad;

[0021] A second inverter, an input end of which is connected to the second control pad;

[0022] A first AND gate, having a first input terminal connected to the output terminal of the first inverter, a second input terminal connected to the second control pad, and an output terminal connected to the control terminal of the first switch element;

[0023] A second AND gate, having a first input terminal connected to the output terminal of the second inverter, a second input terminal connected to the first control pad, and an output terminal connected to the control terminal of the second switch element;

[0024] The third AND gate has a first input terminal connected to the first control pad, a second terminal connected to the second control pad, and an output terminal connected to the control terminal of the third switch element.

[0025] According to an embodiment of the present disclosure, the parasitic resistance simulation circuit further includes:

[0026] A fourth switch element has a first end connected to the test pad, a second end connected to the die, and a control end connected to a fourth output end of the test mode selection circuit.

[0027] According to an embodiment of the present disclosure, the test mode selection circuit further includes:

[0028] A fourth AND gate has a first input terminal connected to the output terminal of the first inverter, a second input terminal connected to the output terminal of the second inverter, and an output terminal connected to the control terminal of the fourth switch element.

[0029] According to an embodiment of the present disclosure, the on-resistance of the first switching element, the on-resistance of the second switching element, the on-resistance of the third switching element, and the impedance of the fourth switching element are all different.

[0030] According to an embodiment of the present disclosure, the parasitic resistance simulation circuit further includes:

[0031] a first resistor connected between the second end of the first switch element and the die;

[0032] a second resistor connected between the second end of the second switch element and the die;

[0033] a third resistor connected between the second end of the third switch element and the die;

[0034] a fourth resistor connected between the second end of the fourth switch element and the die;

[0035] The first resistor, the second resistor, the third resistor and the fourth resistor are all different.

[0036] According to an embodiment of the present disclosure, the parasitic resistance simulation circuit further includes:

[0037] The first resistor is connected between the test pad and the die.

[0038] According to a second aspect of the present disclosure, a test method for a wafer test circuit unit is provided, which is used for the above-mentioned wafer test circuit unit, and the test method includes:

[0039] Use the test pad to input the test signal;

[0040] Use the control pad to input the control signal;

[0041] According to the control signal, the test signal is transmitted to the die through a parasitic resistance simulation circuit.

[0042] According to a third aspect of the present disclosure, a wafer test circuit is provided, wherein the wafer test circuit includes the above-mentioned wafer test circuit unit.

[0043] According to an embodiment of the present disclosure, at least one die pad is provided on the die, and the test pad corresponds to the die pad one-to-one, and the wafer test circuit unit is provided between the corresponding test pad and the die pad.

[0044] According to an embodiment of the present disclosure, the parasitic resistance simulation circuits in a plurality of the wafer test circuit units share a control pad.

[0045] According to a fourth aspect of the present disclosure, a wafer is provided, wherein the wafer includes the above-mentioned wafer test circuit.

[0046] The wafer test circuit unit provided by the present invention inputs a test signal through a test pad, inputs a control signal through a control pad, and the parasitic resistance simulation circuit transmits the test signal to the grain in response to the control signal. On the one hand, the grain can be detected; on the other hand, the influence of the external parasitic resistance on the input signal of the grain in the chip is simulated by the parasitic resistance simulation circuit, and the influence of the parasitic resistance simulation circuit on the input signal is detected. The detection result can provide guidance for adjusting the external input signal to make the external input signal adapt to the external parasitic resistance, thereby solving the problem of abnormal chip operation caused by the influence of the external parasitic resistance on the signal of the input chip grain.

[0047] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0049] Figure 1 A schematic diagram of a wafer provided for an exemplary embodiment of the present disclosure;

[0050] Figure 2 A schematic diagram of a first wafer test circuit unit provided for an exemplary embodiment of the present disclosure;

[0051] Figure 3 A schematic diagram of a second wafer test circuit unit provided for an exemplary embodiment of the present disclosure;

[0052] Figure 4 A schematic diagram of a third wafer test circuit unit provided for an exemplary embodiment of the present disclosure;

[0053] Figure 5 A schematic diagram of a first test mode selection circuit provided for an exemplary embodiment of the present disclosure;

[0054] Figure 6 A schematic diagram of a fourth wafer test circuit unit provided for an exemplary embodiment of the present disclosure;

[0055] Figure 7 A schematic diagram of a fifth wafer test circuit unit provided for an exemplary embodiment of the present disclosure;

[0056] Figure 8A schematic diagram of a second test mode selection circuit provided for an exemplary embodiment of the present disclosure;

[0057] Fig. 9 A flow chart of a test method of a wafer test circuit unit provided in an exemplary embodiment of the present disclosure;

[0058] Fig.10 A schematic diagram of a wafer testing circuit provided according to an exemplary embodiment of the present disclosure.

[0059] In the figure:

[0060] 10. Wafer; 11. Grain area; 12. Slice road; 100. Test pad; 200. Control pad; 210. First control pad; 220. Second control pad; 300. Parasitic resistance simulation circuit; 310. First switch element; 320. Second switch element; 330. Third switch element; 340. Fourth switch element; 350. Test mode selection circuit; 351. First inverter; 352. Second inverter; 353. First AND gate; 354. Second AND gate; 355. Third AND gate; 356. Fourth AND gate; 360. Fifth resistor; 400. Grain; 410. Grain pad. DETAILED DESCRIPTION

[0061] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0062] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, devices, steps, etc. may be adopted. In other cases, known structures, methods, devices, implementations, materials or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0063] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or these functional entities or parts of functional entities may be implemented in one or more software hardened modules, or these functional entities may be implemented in different networks and / or processor devices and / or microcontroller devices.

[0064] In the related technology, wafer-level testing (Wafer Probe) is a necessary process for chips from manufacturing to packaging. This step is to use automatic test equipment (Automatic Test Equipment, ATE) to perform probe testing on the die on the wafer (Wafer) to preliminarily screen out the die whose electrical parameters (Electric Parameters) meet the design requirements.

[0065] After the die is cut from the wafer, it needs to be packaged, such as QFN type packaging. This step will connect the pads on the die to the pins on the package shell through metal wires. The packaged body after packaging is called a chip. Chips are generally used on PCBs. There are also metal wires on the PCB to connect chips to chips, chips to batteries, chips to sensors, etc., to form an electronic device with complete functions.

[0066] During the packaging process, the package leads and PCB traces are actually resistors with a certain resistance value, which are called external parasitic resistances for the crystal grains. These resistors will affect the performance of the chip under conditions such as high current and high frequency. For example, high current will cause voltage drop, which may cause the voltage at the battery end to meet the requirements, but the voltage at the pad end of the crystal grain in the chip cannot meet the requirements; for example, external parasitic resistance and external parasitic capacitance will form a filter, and high-frequency signals will be attenuated during transmission. The above-mentioned effects are sometimes not taken into account during wafer-level testing. If the influence of external parasitic resistance can be considered during wafer-level testing, then not only can more robust crystal grains be screened out to reduce packaging costs, but the PCB-level application of chips can also be guided to reduce application risks.

[0067] The exemplary embodiment of the present disclosure first provides a wafer test circuit unit for wafer test, such as Figure 1 As shown, the wafer 10 includes a grain region 11 and a scribe line 12, and the grain region 11 includes at least one grain 400. Figure 2 As shown, the wafer test circuit unit includes a test pad 100, a control pad 200 and a parasitic resistance simulation circuit 300; the test pad 100 is arranged on the dicing lane 12 for inputting a test signal; the control pad 200 is arranged on the dicing lane 12 for inputting a control signal; the parasitic resistance simulation circuit 300 is respectively connected to the test pad 100, the control pad 200 and the grain 400, for simulating the external parasitic resistance of the grain 400, and transmitting the test signal to the grain 400 in response to the control signal.

[0068] The wafer test circuit unit provided in the embodiment of the present disclosure inputs a test signal through the test pad 100, inputs a control signal through the control pad 200, and the parasitic resistance simulation circuit 300 transmits the test signal to the grain 400 in response to the control signal. On the one hand, the grain can be detected to screen out grains with stronger robustness; on the other hand, the parasitic resistance simulation circuit 300 simulates the influence of external parasitic resistance on the input signal of the grain 400 in the chip, and detects the influence of the parasitic resistance simulation circuit 300 on the input signal. The detection result can provide guidance for adjusting the external input signal to make the external input signal adapt to the external parasitic resistance, thereby solving the problem of abnormal chip operation caused by the influence of external parasitic resistance on the signal of the input chip grain 400.

[0069] The components of the wafer test circuit unit provided by the embodiment of the present disclosure are described in detail below:

[0070] like Figure 3 As shown, the parasitic resistance simulation circuit 300 includes a first switch element 310, a first end of the first switch element 310 is connected to the test pad 100, a second end of the first switch element 310 is connected to the die 400, and a control end is connected to the control pad 200. Among them, a die pad 410 is provided on the die 400, and the second end of the first switch element 310 is connected to the die pad 410. The first switch element 310 is turned on in response to a control signal to transmit a test signal to the die 400. The first switch element 310 has an impedance when it is turned on, so the external parasitic resistance of the chip can be simulated by the first switch element 310. When the test signal passes through the first switch element 310, it will change due to the influence of the conduction impedance. At this time, by detecting the response result of the die 400 after receiving the changed test signal, the influence of the external parasitic resistance on the response result is judged, and then the input signal is adjusted so that the die 400 obtains the expected response result in response to the input signal.

[0071] For example, the test signal will experience a voltage drop, current change, or frequency change when passing through the first switching element 310. When the die pad 410 is a power signal receiving pad, the voltage of the power signal transmitted to the die pad 410 will be insufficient due to the on-resistance of the first switching element 310. At this time, the power voltage received by the die 400 can be detected to determine the error between the power voltage and the expected power voltage, and then adjust the voltage of the external input power signal to ensure that the power voltage transmitted to the die 400 meets the expected value.

[0072] like Figure 4As shown, the control pad 200 may include a first control pad 210 and a second control pad 220 . The first control pad 210 is used to input a first control signal; the second control pad 220 is used to input a second control signal. The first control pad 210 and the second control pad 220 are both arranged on the dicing lane 12 .

[0073] On this basis, the parasitic resistance simulation circuit 300 further includes a second switch element 320, a third switch element 330 and a test mode circuit. The first end of the second switch element 320 is connected to the test pad 100, and the second end of the second switch element 320 is connected to the die 400; the first end of the third switch element 330 is connected to the test pad 100, and the second end of the third switch element 330 is connected to the die 400; the test mode selection circuit 350 has two input ends and multiple output ends, the first input end is connected to the first control pad 210, the second input end is connected to the second control pad 220, the first output end of the test mode selection circuit 350 is connected to the control end of the first switch element 310, the second output end of the test mode selection circuit 350 is connected to the control end of the second switch element 320, and the third output end of the test mode selection circuit 350 is connected to the control end of the third switch element 330.

[0074] like Figure 5 As shown, the test mode selection circuit 350 includes a first inverter 351 , a second inverter 352 , a first AND gate 353 , a second AND gate 354 and a third AND gate 355 . The input end of the first inverter 351 is connected to the first control pad 210; the input end of the second inverter 352 is connected to the second control pad 220; the first input end of the first AND gate 353 is connected to the output end of the first inverter 351, the second input end of the first AND gate 353 is connected to the second control pad 220, and the output end of the first AND gate 353 is connected to the control end of the first switch element 310; the first input end of the second AND gate 354 is connected to the output end of the second inverter 352, the second input end of the second AND gate 354 is connected to the first control pad 210, and the output end of the second AND gate 354 is connected to the control end of the second switch element 320; the first input end of the third AND gate 355 is connected to the first control pad 210, the second end of the third AND gate 355 is connected to the second control pad 220, and the output end of the third AND gate 355 is connected to the control end of the third switch element 330. The output of the first AND gate 353 is the first output of the test mode selection circuit 350 , the output of the second AND gate 354 is the second output of the test mode selection circuit 350 , and the output of the third AND gate 355 is the third output of the test mode selection circuit 350 .

[0075] It can be noted that the first control signal input to the first control pad 210 is A, and the second control signal input to the second control pad 220 is B. Then, the signal output from the output end of the test mode selection circuit 350 is: the first output signal Second output signal The third output signal is AB.

[0076] The control signals input to and output from the test mode selection circuit 350 are shown in Table 1.

[0077] Table 1

[0078]

[0079] According to the above table, the test mode selection circuit 350 outputs a control signal to control the first switch element 310, the second switch element 320 and the third switch element 330 to be turned on under different control signals to simulate different external parasitic resistances and provide different test environments.

[0080] Further, such as Figure 7 As shown, the parasitic resistance simulation circuit 300 may also include a fourth switch element 340, the first end of the fourth switch element 340 is connected to the test pad 100, the second end of the fourth switch element 340 is connected to the grain 400, and the control end of the fourth switch element 340 is connected to the fourth output end of the test mode selection circuit 350.

[0081] On this basis, if Figure 8 As shown, the test mode selection circuit 350 further includes a fourth AND gate 356, a first input end of the fourth AND gate 356 is connected to the output end of the first inverter 351, a second input end of the fourth AND gate 356 is connected to the output end of the second inverter 352, and an output end of the fourth AND gate 356 is connected to the control end of the fourth switch element 340. When the first control signal inputted by the first control pad 210 is A and the second control signal inputted by the second control pad 220 is B, the signal outputted by the output end of the fourth AND gate 356 and the fourth output end of the test mode selection circuit 350 is At this time, the control signal input to and the control signal output from the test mode selection circuit 350 are shown in Table 2.

[0082] Table 2

[0083]

[0084] According to the above table, the test mode selection circuit 350 outputs a control signal to control the first switch element 310, the second switch element 320, the third switch element 330 and the fourth switch element 340 to be turned on under different control signals to simulate different external parasitic resistances and provide different test environments.

[0085] In order to simulate various external parasitic resistances, the on-resistance of the first switch element 310, the on-resistance of the second switch element 320, the on-resistance of the third switch element 330, and the impedance of the fourth switch element 340 are all different. Since the on-resistances of the multiple switch elements are different, when the multiple switch elements are turned on respectively, the impact on the input signal is different, so that the wafer test circuit has better adaptability and is suitable for various test scenarios.

[0086] Of course, in practical applications, the on-resistances of multiple switch elements may also be the same, so as to facilitate the manufacture of switch elements. In this case, the parasitic resistance simulation circuit 300 may also include: a first resistor, a second resistor, a third resistor and a fourth resistor. The first resistor is connected between the second end of the first switch element 310 and the die 400; the second resistor is connected between the second end of the second switch element 320 and the die 400; the third resistor is connected between the second end of the third switch element 330 and the die 400; the fourth resistor is connected between the second end of the fourth switch element 340 and the die 400; wherein the first resistor, the second resistor, the third resistor and the fourth resistor are all different. Optionally, resistors may be connected to some switch elements, and the remaining switch elements are not connected to resistors, for example, the second end of the first switch element 310 is connected to the die pad 410, the second end of the second switch element 320 is connected to the second resistor, the second end of the third switch element 330 is connected to the third resistor, and the second end of the fourth switch element 340 is connected to the fourth resistor.

[0087] like Figure 6 As shown, the parasitic resistance simulation circuit 300 may further include a fifth resistor 360, which is connected between the test pad 100 and the die 400. That is, the fifth resistor 360 is connected in parallel with each switch element, and the fifth resistor 360 can work under the condition that multiple switch elements are all turned off, thereby increasing the adaptability of the wafer test circuit.

[0088] In this example implementation, the first to fourth switch units may correspond to the first to fourth transistors, respectively, and each transistor has a control terminal, a first terminal, and a second terminal. Each transistor may be an N-type transistor, a P-type transistor, or a transmission gate. Specifically, the control terminal of each transistor may be a gate, the first terminal may be a source, and the second terminal may be a drain; or, the control terminal of each transistor may be a gate, the first terminal may be a drain, and the second terminal may be a source. In addition, each transistor may also be an enhancement transistor or a depletion transistor, which is not specifically limited in this example implementation. The on-resistance of the first to fourth transistors provided in the embodiment of the present disclosure may be in the milliohm level, the resistance of the first to fifth resistors may be in the milliohm level, and each resistor may be a metal resistor or a polysilicon resistor.

[0089] The first transistor has a first end connected to the test pad 100 , a second end connected to the die pad 410 on the die 400 , and a control end connected to a first output end of the test mode selection circuit 350 .

[0090] The second transistor has a first end connected to the test pad 100 , a second end connected to the die pad 410 on the die 400 , and a control end connected to the second output end of the test mode selection circuit 350 .

[0091] The third transistor has a first end connected to the test pad 100 , a second end connected to the die pad 410 on the die 400 , and a control end connected to the third output end of the test mode selection circuit 350 .

[0092] The fourth transistor has a first end connected to the test pad 100 , a second end connected to the die pad 410 on the die 400 , and a control end connected to the fourth output end of the test mode selection circuit 350 .

[0093] The wafer test circuit unit provided by the embodiment of the present disclosure inputs a test signal through the test pad 100, inputs a control signal through the control pad 200, and the parasitic resistance simulation circuit 300 transmits the test signal to the grain 400 in response to the control signal. The parasitic resistance simulation circuit 300 simulates the influence of the external parasitic resistance on the input signal of the grain 400 in the chip, and detects the influence of the parasitic resistance simulation circuit 300 on the input signal. The detection result can provide guidance for adjusting the external input signal to make the external input signal adapt to the external parasitic resistance, thereby solving the problem of abnormal chip operation caused by the influence of the external parasitic resistance on the signal of the input chip grain 400.

[0094] The exemplary embodiment of the present disclosure also provides a test method of a wafer test circuit unit, which is used for the above-mentioned wafer test circuit unit, such as Fig. 9 As shown, the testing method comprises the following steps:

[0095] Step S910, inputting a test signal using the test pad 100;

[0096] Step S920, inputting a control signal using the control pad 200;

[0097] Step S930 , transmitting the test signal to the die 400 through the parasitic resistance simulation circuit 300 according to the control signal.

[0098] The test method of the wafer test circuit unit provided in the embodiment of the present disclosure inputs a test signal through the test pad 100, inputs a control signal through the control pad 200, the parasitic resistance simulation circuit 300 transmits the test signal to the grain 400 in response to the control signal, simulates the influence of the external parasitic resistance on the input signal of the grain 400 in the chip through the parasitic resistance simulation circuit 300, and detects the influence of the parasitic resistance simulation circuit 300 on the input signal. The detection result can provide guidance for adjusting the external input signal to make the external input signal adapt to the external parasitic resistance, thereby solving the problem of abnormal chip operation caused by the influence of the external parasitic resistance on the signal of the input chip grain 400.

[0099] In step S910, a test signal may be inputted through the test pad 100. The test pad 100 is disposed on the scribe line 12, and the test signal may be a voltage signal or a current signal.

[0100] In step S920, a control signal may be inputted using the control pad 200. When the control pad 200 includes a first control pad 210 and a second control pad 220, the control signal includes a first control signal and a second control signal.

[0101] In step S930 , the test signal may be transmitted to the die 400 through the parasitic resistance simulation circuit 300 according to the control signal.

[0102] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0103] Under the control of the control signal, the test signal is transmitted to the die 400 via the parasitic resistance simulation circuit 300. The parasitic resistance simulation circuit 300 simulates the external parasitic resistance of the chip, and the test signal changes. The die 400 responds to the changed test signal, detects the die 400, compares the detection structure with the expected result, and then provides feedback to guide the adjustment of the test signal to obtain the expected test result. That is, the test signal corresponding to the expected test result is obtained, so as to input the correct input signal in actual application and solve the problem of abnormal chip operation caused by external parasitic circuits.

[0104] The specific details of each test method mentioned above have been described in detail in the corresponding wafer test circuit unit, so they will not be repeated here.

[0105] The exemplary embodiment of the present disclosure also includes a wafer test circuit, wherein the wafer test circuit includes the above-mentioned wafer test circuit unit. Fig.10 As shown, the wafer die area 11 includes a plurality of die 400, each die 400 is provided with at least one die pad 410, the test pad 100 corresponds to the die pad 410 one by one, and the wafer test circuit unit is provided between the test pad 100 and the die pad 410. The test pad 100 may be distributed in an array after being cut.

[0106] Multiple die pads 410 can be arranged at the edge area of ​​the die 400, the parasitic resistance simulation circuit 300 connected to the die pad 410 is arranged in an area close to the dicing lane 12 and close to the die pad 410, and the test pad 100 is arranged on the side of the parasitic resistance simulation circuit 300 away from the die 400.

[0107] The parasitic resistance simulation circuits 300 in the plurality of wafer test circuit units share the control pad 200. The control pad 200 can provide control signals to the plurality of parasitic resistance simulation circuits 300 at the same time, or provide control signals to the plurality of parasitic resistance simulation circuits 300 separately.

[0108] In a feasible implementation of the present disclosure, a plurality of parasitic resistance simulation circuits 300 are connected to the control pad 200. When the parasitic resistance simulation circuit 300 includes a test mode selection circuit 350, the control pad 200 includes a first control pad 210 and a second control pad 220, and the first input terminals of the plurality of test mode selection circuits 350 are connected to the same first control pad 210, and the second input terminals of the plurality of test mode selection circuits 350 are connected to the same second control pad 220.

[0109] The wafer test circuit provided by the embodiment of the present disclosure inputs a test signal through the test pad 100, inputs a control signal through the control pad 200, and the parasitic resistance simulation circuit 300 transmits the test signal to the grain 400 in response to the control signal. The parasitic resistance simulation circuit 300 simulates the influence of the external parasitic resistance on the input signal of the grain 400 in the chip, and detects the influence of the parasitic resistance simulation circuit 300 on the input signal. The detection result can provide guidance for adjusting the external input signal to make the external input signal adapt to the external parasitic resistance, thereby solving the problem of abnormal chip operation caused by the influence of the external parasitic resistance on the signal of the input chip grain 400.

[0110] The exemplary embodiments of the present disclosure also include a wafer, wherein the wafer includes the wafer test circuit described above.

[0111] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0112] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A wafer test circuit unit, used for wafer testing, wherein the wafer comprises a grain area and a scribe line, wherein the grain area comprises at least one grain, characterized in that: The wafer testing circuit unit comprises: A test pad, disposed on the scribe line, for inputting a test signal; A control pad, disposed on the scribe line, for inputting a control signal; A parasitic resistance simulation circuit is provided in the scribe line, connected to the test pad, the control pad and the die respectively, for simulating the external parasitic resistance of the die, and transmitting the test signal to the die in response to the control signal; Wherein, the control pad includes: A first control pad, used for inputting a first control signal; A second control pad, used for inputting a second control signal; The parasitic resistance simulation circuit also includes: A first switch element, a first end of which is connected to the test pad, a second end of which is connected to the die, and a control end of which is connected to the control pad; A second switch element, a first end of which is connected to the test pad, and a second end of which is connected to the die; A third switch element, a first end of which is connected to the test pad, and a second end of which is connected to the die; A test mode selection circuit has two input terminals and multiple output terminals, wherein the first input terminal is connected to the first control pad, the second input terminal is connected to the second control pad, the first output terminal is connected to the control terminal of the first switch element, the second output terminal is connected to the control terminal of the second switch element, and the third output terminal is connected to the control terminal of the third switch element.

2. The wafer testing circuit unit according to claim 1, characterized in that: The test mode selection circuit comprises: A first inverter, an input end of which is connected to the first control pad; A second inverter, an input end of which is connected to the second control pad; A first AND gate, having a first input terminal connected to the output terminal of the first inverter, a second input terminal connected to the second control pad, and an output terminal connected to the control terminal of the first switch element; A second AND gate, having a first input terminal connected to the output terminal of the second inverter, a second input terminal connected to the first control pad, and an output terminal connected to the control terminal of the second switch element; The third AND gate has a first input terminal connected to the first control pad, a second terminal connected to the second control pad, and an output terminal connected to the control terminal of the third switch element.

3. The wafer testing circuit unit according to claim 2, characterized in that: The parasitic resistance simulation circuit also includes: A fourth switch element has a first end connected to the test pad, a second end connected to the die, and a control end connected to a fourth output end of the test mode selection circuit.

4. The wafer testing circuit unit according to claim 3, characterized in that: The test mode selection circuit also includes: A fourth AND gate has a first input terminal connected to the output terminal of the first inverter, a second input terminal connected to the output terminal of the second inverter, and an output terminal connected to the control terminal of the fourth switch element.

5. The wafer testing circuit unit according to claim 4, characterized in that: The on-resistance of the first switching element, the on-resistance of the second switching element, the on-resistance of the third switching element, and the impedance of the fourth switching element are all different.

6. The wafer testing circuit unit according to claim 4, characterized in that: The parasitic resistance simulation circuit also includes: a first resistor connected between the second end of the first switch element and the die; a second resistor connected between the second end of the second switch element and the die; a third resistor connected between the second end of the third switch element and the die; a fourth resistor connected between the second end of the fourth switch element and the die; The first resistor, the second resistor, the third resistor and the fourth resistor are all different.

7. The wafer testing circuit unit according to any one of claims 1 to 6, characterized in that: The parasitic resistance simulation circuit also includes: A fifth resistor is connected between the test pad and the die.

8. A method for testing a wafer test circuit unit, characterized in that: For the wafer testing circuit unit according to any one of claims 1 to 7, the testing method comprises: Use the test pad to input the test signal; Use the control pad to input the control signal; According to the control signal, the test signal is transmitted to the die through a parasitic resistance simulation circuit.

9. A wafer testing circuit, characterized in that: The wafer testing circuit comprises the wafer testing circuit unit described in any one of claims 1-7.

10. The wafer testing circuit according to claim 9, characterized in that: At least one die pad is arranged on the die, the test pads correspond to the die pads one by one, and the wafer test circuit unit is arranged between the corresponding test pads and the die pads.

11. The wafer testing circuit according to claim 10, characterized in that: The parasitic resistance simulation circuits in the plurality of wafer test circuit units share a control pad.

12. A wafer, characterized in that: The wafer includes the wafer testing circuit described in any one of claims 9-11.

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