Display device and method of driving a display panel of the same

Abstract

The present invention relates to a display device and a method for driving a display panel of the display device. The display device includes a display panel, a gate driver, a data driver, and a drive controller. The display panel displays an image based on input image data. The gate driver outputs a gate signal to the gate lines of the display panel. The data driver outputs a data voltage to the data lines of the display panel. The drive controller controls the operation of the gate driver and the data driver, and drives a still image display area and a video image display area in a display area of ​​the display panel at different drive frequencies. The drive controller includes a still image determiner that divides the input image data into a plurality of still image determination blocks, determines whether the still image determination blocks represent a still image or a video image, and determines a boundary between the still image display area and the video image display area.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to a display device and a method of driving a display panel of the display device. More particularly, exemplary embodiments of the present invention relate to a display device with reduced power consumption and a method of driving a display panel of the display device. Background Art

[0002] Methods of minimizing power consumption of portable electronic devices such as tablet personal computers ("PCs") and laptop computers have been studied.

[0003] In order to minimize the power consumption of portable electronic devices that generally include a display panel, the power consumption of the display panel can be minimized. When the display panel displays a still image, the display panel can be driven at a relatively low frequency so that the power consumption of the display panel can be reduced. Summary of the Invention

[0004] When a portion of a display panel of an electronic device displays a video image and another portion of the display panel displays a still image, the display panel may be driven at a relatively high frequency, so that power consumption of the display panel may not be effectively reduced.

[0005] In addition, when the display panel is driven at a relatively low frequency, flickering may occur, so that display quality may be degraded.

[0006] Exemplary embodiments of the present invention provide a display device with reduced power consumption and enhanced display quality.

[0007] Exemplary embodiments of the present invention also provide a method of driving a display panel of the display device.

[0008] In an exemplary embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver, a data driver, and a drive controller. In such an embodiment, the display panel includes gate lines, data lines, and pixels, and the display panel displays an image based on input image data. In such an embodiment, the gate driver outputs a gate signal to the gate line, the data driver outputs a data voltage to the data line, and the drive controller controls the operation of the gate driver and the operation of the data driver, and drives the still image display area and the video image display area in the display area of ​​the display panel at different drive frequencies. In such an embodiment, the drive controller includes a still image determiner that divides the input image data into a plurality of still image determination blocks, determines whether the still image determination blocks represent a still image or a video image, and determines the boundary between the still image display area and the video image display area.

[0009] In an exemplary embodiment, the still image determiner may generate a flag signal indicating whether the still image determination block indicates a still image or a video image.

[0010] In an exemplary embodiment, the driving controller may further include a driving frequency determiner that divides the still image display area into a plurality of driving frequency determination blocks and determines the driving frequencies of the driving frequency determination blocks respectively based on flicker values ​​corresponding to grayscale values ​​of input image data for the driving frequency determination blocks.

[0011] In an exemplary embodiment, the size of the still image determination block may be different from the size of the driving frequency determination block.

[0012] In an exemplary embodiment, the size of the still image determination block may be smaller than the size of the driving frequency determination block.

[0013] In an exemplary embodiment, the size of the driving frequency determination block may be fixed regardless of the size of the still image display area. In such an embodiment, when the size of the still image display area increases according to the input image data, the number of driving frequency determination blocks may increase.

[0014] In an exemplary embodiment, the number of driving frequency determination blocks may be fixed regardless of the size of the still image display area. In such an embodiment, when the size of the still image display area increases according to the input image data, the size of the driving frequency determination block may increase.

[0015] In an exemplary embodiment, the driving controller may further include a fixed frequency determiner that determines whether the input frequency of the input image data is of a normal type by counting the number of pulses of the horizontal synchronization signal between the first pulse and the second pulse of the vertical synchronization signal, or by counting the number of pulses of the data enable signal between the first pulse and the second pulse of the vertical synchronization signal.

[0016] In an exemplary embodiment, the fixed frequency determiner may generate a frequency flag indicating whether the input frequency of the input image data has a normal type. In such an embodiment, the driving frequency determiner may determine the driving frequency of the display panel.

[0017] In an exemplary embodiment, the driving controller may further include a compensation frame inserter that inserts a compensation frame between a frame of the first frequency and a frame of the second frequency when the driving frequency of the driving frequency determination block is changed from the first frequency to the second frequency by the driving frequency determiner.

[0018] In an exemplary embodiment, the display panel may include a plurality of segments. The driving controller may determine a driving frequency of the display panel based on a driving frequency determined according to a flicker value corresponding to a grayscale value of the input image data for the segment.

[0019] In an exemplary embodiment, each of the driving frequency determination blocks may include a plurality of segments. In such an embodiment, the driving frequency determiner may determine the driving frequency of each of the driving frequency determination blocks based on a driving frequency determined based on a flicker value corresponding to a grayscale value of input image data for the segments in the driving frequency determination block.

[0020] In an exemplary embodiment of a method for driving a display panel, the method includes: dividing input image data into a plurality of still image determination blocks; determining whether the still image determination blocks represent a still image or a video image; determining a boundary between a still image display area and a video image display area in a display area of ​​a display panel; determining a driving frequency for the still image display area; determining a driving frequency for the video image display area; outputting a gate signal to a gate line of the display panel based on the driving frequency of the still image display area and the driving frequency of the video image display area; and outputting a data voltage to a data line of the display panel based on the driving frequency of the still image display area and the driving frequency of the video image display area. In such an embodiment, the still image display area and the video image display area in the display area can be driven at different driving frequencies.

[0021] In an exemplary embodiment, the method may further include generating a flag signal indicating whether the still image determination block indicates a still image or a video image.

[0022] In an exemplary embodiment, the method may further include dividing the still image display area into a plurality of driving frequency determination blocks, and respectively determining driving frequencies of the driving frequency determination blocks based on flicker values ​​corresponding to grayscale values ​​of input image data for the driving frequency determination blocks.

[0023] In an exemplary embodiment, the size of the still image determination block may be smaller than the size of the driving frequency determination block.

[0024] In an exemplary embodiment, the method may further include inserting a compensation frame between a frame of the first frequency and a frame of the second frequency when the driving frequency of the driving frequency determination block is changed from the first frequency to the second frequency.

[0025] In an exemplary embodiment, each of the driving frequency determination blocks may include a plurality of segments. In such an embodiment, the driving frequency of each of the driving frequency determination blocks may be determined based on a driving frequency determined based on a flicker value corresponding to a grayscale value of input image data for the segment in the driving frequency determination block.

[0026] In an exemplary embodiment, the method may further include determining whether the input frequency of the input image data is of a normal type by counting the number of pulses of the horizontal synchronization signal between the first pulse and the second pulse of the vertical synchronization signal, or by counting the number of pulses of the data enable signal between the first pulse and the second pulse of the vertical synchronization signal.

[0027] In an exemplary embodiment, the method may further include generating a frequency flag indicating whether the input frequency of the input image data is of a normal type. In such an embodiment, the driving frequency of the still image display area may be determined based on the frequency flag.

[0028] According to exemplary embodiments of a method for driving a display panel and a display device including the same, a driving frequency is determined based on an image displayed on the display panel, thereby reducing power consumption of the display device. In such an embodiment, when input image data includes a still image display area and a video image display area, the still image display area and the video image display area can be driven at different frequencies, further reducing power consumption of the display device.

[0029] In an exemplary embodiment, the still image determiner may divide the input image data into a plurality of still image determination blocks and determine whether each of the still image determination blocks represents a still image or a video image to determine a boundary between the still image display area and the video image display area, so that the power consumption of the display device can be further reduced.

[0030] In an exemplary embodiment, the driving frequency determiner may divide the still image display area into a plurality of driving frequency determination blocks, and determine the driving frequencies of the driving frequency determination blocks respectively based on flicker values ​​corresponding to grayscale values ​​of the input image data for the driving frequency determination blocks, so that the power consumption of the display device may be further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0032] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention;

[0033] Figure 2 It is an icon Figure 1 The block diagram of the drive controller;

[0034] Figure 3 It is an icon Figure 2 A timing diagram of the operation of the fixed frequency determiner;

[0035] Figure 4 It is an icon Figure 2 A conceptual diagram of the operation of a still image determiner;

[0036] Figure 5 It is an icon Figure 2 a signal timing diagram of an output signal of a still image determiner;

[0037] Figure 6 It is an icon Figure 2 A conceptual diagram of the operation of a still image determiner;

[0038] Figure 7 It is an icon Figure 2 a signal timing diagram of an output signal of a still image determiner;

[0039] Figure 8 It is an icon Figure 2 A conceptual diagram of the operation of a driving frequency determiner;

[0040] Figure 9 It is an icon Figure 2 A table of values ​​of a flash value memory;

[0041] Figure 10 It is an icon Figure 2 A conceptual diagram of the operation of a driving frequency determiner;

[0042] Figure 11 It is an icon Figure 2 A signal timing diagram of an output signal of a driving frequency determiner;

[0043] Figure 12 is a conceptual diagram illustrating a display panel of a display device according to an exemplary embodiment of the present invention; and

[0044] Figure 13 It is an icon Figure 12 A block diagram of a driving controller of a display device. DETAILED DESCRIPTION

[0045] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention will be fully conveyed to those skilled in the art. Like reference numerals refer to like elements throughout.

[0046] It will be understood that when an element is referred to as being "on" another element, the element can be directly on the other element or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0047] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, the "first element," "first component," "first region," "first layer," or "first portion" discussed below may be referred to as a second element, second component, second region, second layer, or second portion without departing from the teachings herein.

[0048] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the content clearly indicates otherwise, the singular forms of "a" and "the" are intended to include plural forms including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the items listed in the relevant list. When following a list of elements, expressions such as "at least one of..." modify the list of the entire elements and do not modify the individual elements of the list. For example, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] It will be further understood that when used in this specification, the terms “include” or “comprising” specify the presence of stated features, regions, integers, steps, operations, elements and / or parts, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, parts and / or combinations thereof.

[0050] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used to describe the relationship of one element to another element as illustrated in the accompanying drawings. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one of the drawings is turned over, the element described as being on the "lower" side of the other elements will then be positioned on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the exemplary term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device in one of the drawings is turned over, the element described as being "below" or "beneath" the other elements will be positioned "above" the other elements. Therefore, the exemplary terms "below" or "below" can cover both "upper" and "lower" orientations.

[0051] As used herein, “about” or “approximately” are inclusive of the stated value and mean within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with measurement of the particular quantity (i.e., limitations of the measurement system).

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0053] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

[0055] See also Figure 1 , an exemplary embodiment of a display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0056] In one exemplary embodiment, for example, the driving controller 200 and the data driver 500 may be integrally formed into, for example, a single integrated circuit. In one exemplary embodiment, for example, the driving controller 200, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed into, for example, a single integrated circuit. A driving module including at least the integrally formed driving controller 200 and the data driver 500 may be referred to as a timing controller embedded data driver ("TED").

[0057] The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 crossing the first direction D1.

[0058] In one exemplary embodiment, for example, the display panel 100 may be an organic light emitting display panel including an organic light emitting element.

[0059] The display panel 100 may be driven in a normal driving mode in which the display panel 100 is driven at a normal driving frequency and in a low-frequency driving mode in which the display panel 100 is driven at a frequency less than the normal driving frequency.

[0060] In one exemplary embodiment, for example, when the input image data represents a video image, the display panel 100 may be driven in a normal driving mode. In one exemplary embodiment, for example, when the input image data represents a still image, the display panel 100 may be driven in a low-frequency driving mode. In one exemplary embodiment, for example, when the display device operates in a normally-on mode, the display panel 100 may be driven in a low-frequency driving mode.

[0061] In such an embodiment, a portion of the input image data representing a video image may be driven in the normal driving mode, and another portion of the input image data representing a still image may be driven in the low-frequency driving mode.

[0062] The display panel 100 may be driven in units of frames. In the normal driving mode, the display panel 100 may be refreshed in each frame. Therefore, the normal driving mode includes only a writing frame in which data is written into pixels.

[0063] In the low frequency driving mode, the display panel 100 may be refreshed at a frequency of the low frequency driving mode. Therefore, the low frequency driving mode includes a write frame in which data is written into pixels and a hold frame in which written data is maintained without writing data into pixels.

[0064] The drive controller 200 receives input image data IMG and an input control signal CONT from an external device (not shown). In an exemplary embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may further include white image data. Alternatively, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0065] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0066] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may further include a vertical start signal and a gate clock signal.

[0067] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0068] The driving controller 200 generates a data signal DATA based on the input image data IMG and outputs the data signal DATA to the data driver 500 .

[0069] In one exemplary embodiment, for example, the driving controller 200 may adjust the driving frequency of the display panel 100 based on the input image data IMG.

[0070] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0071] See later Figures 2 to 11 The structure and operation of the driving controller 200 are described in detail.

[0072] The gate driver 300 generates a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 outputs the gate signal to the gate line GL. In one exemplary embodiment, for example, the gate driver 300 may sequentially output the gate signal to the gate line GL. In one exemplary embodiment, for example, the gate driver 300 may be mounted on the display panel 100. In one exemplary embodiment, for example, the gate driver 300 may be integrated on the display panel 100.

[0073] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0074] In exemplary embodiments, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500 .

[0075] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into an analog data voltage using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0076] Figure 2 It is an icon Figure 1 1 is a block diagram of the driving controller 200. Figure 3 It is an icon Figure 2 1 is a timing diagram of the operation of the fixed frequency determiner 210.

[0077] See also Figures 1 to 3 , an exemplary embodiment of the driving controller 200 may include a still image determiner 220, a driving frequency determiner 230, and a flicker value memory 240. The driving controller 200 may further include a fixed frequency determiner 210. The driving controller 200 may further include a compensation frame interpolator 250.

[0078] The fixed frequency determiner 210 may determine whether the input frequency of the input image data IMG is of a normal type. In one exemplary embodiment, for example, the fixed frequency determiner 210 may determine whether the input frequency of the input image data IMG is of a normal type by counting the number of pulses of the horizontal synchronization signal HSYNC between the first pulse and the second pulse of the vertical synchronization signal VSYNC, or by counting the number of pulses of the data enable signal DE between the first pulse and the second pulse of the vertical synchronization signal VSYNC.

[0079] The duration between the first pulse and the second pulse of the vertical synchronization signal VSYNC may be defined as one frame. When the input frequency of the input image data IMG is 120 Hz, the number of pulses of the horizontal synchronization signal HSYNC between the first pulse and the second pulse of the vertical synchronization signal VSYNC may be 120. When the input frequency of the input image data IMG is 120 Hz, the number of pulses of the data enable signal DE between the first pulse and the second pulse of the vertical synchronization signal VSYNC may be 120.

[0080] When the number of pulses of the horizontal synchronization signal HSYNC or the number of pulses of the data enable signal DE between the first pulse and the second pulse of the vertical synchronization signal VSYNC is equal to the input frequency, the fixed frequency determiner 210 may determine that the input frequency of the input image data IMG is of the normal type. When the number of pulses of the horizontal synchronization signal HSYNC or the number of pulses of the data enable signal DE between the first pulse and the second pulse of the vertical synchronization signal VSYNC is not equal to the input frequency, the fixed frequency determiner 210 may determine that the input frequency of the input image data IMG is not of the normal type.

[0081] The fixed frequency determiner 210 may generate a frequency flag FF indicating whether the input frequency of the input image data IMG is of a normal type. The fixed frequency determiner 210 may output the frequency flag FF to the driving frequency determiner 230. The driving frequency determiner 230 may determine the driving frequency of the display panel 100 based on the frequency flag FF. In one exemplary embodiment, for example, when the input frequency of the input image data IMG is not of a normal type, the driving frequency determiner 230 may drive the switching elements in the pixels at a normal driving frequency (e.g., 120 Hz) instead of a low driving frequency. When the input frequency of the input image data IMG is not of a normal type and the display panel 100 is driven at a low driving frequency, the display panel 100 may produce display defects. In addition, because the driving frequency is fixed to the normal driving frequency when the input frequency of the input image data IMG is not of a normal type, the still image determiner 220 may not operate when the input frequency of the input image data IMG is not of a normal type.

[0082] Figure 4 It is an icon Figure 2 A conceptual diagram of the operation of the still image determiner 220 is shown. Figure 5 It is an icon Figure 2 FIG. 1 is a signal timing diagram of an output signal of the still image determiner 220 . Figure 6 It is an icon Figure 2 A conceptual diagram of the operation of the still image determiner 220 is shown. Figure 7 It is an icon Figure 2 FIG. 1 is a signal timing diagram of an output signal of the still image determiner 220 .

[0083] See also Figures 1 to 7 In an exemplary embodiment, the still image determiner 220 may divide the input image data IMG into a plurality of still image determination blocks SR1 to SRM. In an exemplary embodiment, for example, each of the still image determination blocks SR1 to SRM may extend in a direction perpendicular to a scanning direction of a gate signal (e.g., the second direction D2). Each of the still image determination blocks SR1 to SRM may extend in the first direction D1.

[0084] exist Figure 4 , for convenience of illustration and description, the input image data IMG includes fourteen still image determination blocks SR1 to SR14, but the present invention is not limited thereto.

[0085] The still image determiner 220 may determine whether each of the still image determination blocks SR1 to SR14 represents or displays a still image or a video image. The still image determiner 220 may determine a boundary BMS between a still image display area and a video image display area.

[0086] In an exemplary embodiment, as Figure 4 As shown in , for example, the first to fifth still image determination blocks SR1 to SR5 may represent video images, and the sixth to fourteenth still image determination blocks SR6 to SR14 may represent still images.

[0087] The still image determiner 220 may generate a flag signal SF indicating whether the still image determination blocks SR1 to SR14 indicate a still image or a video image. The still image determiner 220 may output the flag signal SF to the driving frequency determiner 230. In one exemplary embodiment, for example, when the still image determination block indicates a still image, the still image determiner 220 may output the flag signal SF having a value of 1 to the driving frequency determiner 230. When the still image determination block indicates a video image, the still image determiner 220 may output the flag signal SF having a value of 0 to the driving frequency determiner 230. When the display panel 100 is operated in the always-on mode, the still image determiner 220 may output the flag signal SF having a value of 1 to the driving frequency determiner 230. In one exemplary embodiment, for example, the still image determiner 220 may generate the flag signal SF for each of the still image determination blocks SR1 to SR14.

[0088] exist Figure 5 , the input vertical synchronization signal IVS, the input data enable signal IDE, and the flag signal SF in the first to third frames 1F, 2F, and 3F are illustrated.

[0089] like Figure 4 and Figure 5 As shown in , the first to fifth still image determination blocks SR1 to SR5 include video images, and the sixth to fourteenth still image determination blocks SR6 to SR14 include still images, and the flag signal SF has an invalid level (e.g., 0) corresponding to the first to fifth still image determination blocks SR1 to SR5 and a valid level (e.g., 1) corresponding to the sixth to fourteenth still image determination blocks SR6 to SR14.

[0090] In addition, the still image determiner 220 may determine the boundary between the fifth still image determination block SR5 and the sixth still image determination block SR6 as a boundary BMS between the still image display area (corresponding to the still image determination blocks SR6 to SR14) and the video image display area (corresponding to the still image determination blocks SR1 to SR5).

[0091] Although the input image data IMG may include a single boundary BMS between the still image display area and the video image display area, as shown in FIG. Figure 4 When the input image data IMG includes a plurality of video image display areas spaced apart from each other, the input image data IMG may include a plurality of boundaries BMS between the still image display area and the video image display area.

[0092] Although the video image display area may be provided in the upper portion of the display panel 100 and the still image display area may be provided in the lower portion of the display panel 100, the present invention may not be limited thereto. Operations in the case where the video image display area is provided in the lower portion of the display panel 100 and the still image display area is provided in the upper portion of the display panel 100 may be substantially the same as the operations in the case where the video image display area is provided in the upper portion of the display panel 100 and the still image display area is provided in the lower portion of the display panel 100 as described above.

[0093] In an exemplary embodiment, as Figure 6 As shown in , for example, the first to seventh still image determination blocks SR1 to SR7 may represent video images, and the eighth to fourteenth still image determination blocks SR8 to SR14 may represent still images.

[0094] The still image determiner 220 may generate a flag signal SF indicating whether the still image determination blocks SR1 to SR14 indicate a still image or a video image.

[0095] like Figure 6 and Figure 7 As shown in , when the first to seventh still image determination blocks SR1 to SR7 include video images and the eighth to fourteenth still image determination blocks SR8 to SR14 include still images, Figure 7 The flag signal SF has an inactive level (eg, 0) corresponding to the first to seventh still image determination blocks SR1 to SR7 and an active level (eg, 1) corresponding to the eighth to fourteenth still image determination blocks SR8 to SR14.

[0096] In addition, the still image determiner 220 can determine the boundary between the seventh still image determination block SR7 and the eighth still image determination block SR8 as the boundary BMS between the still image display area (corresponding to the still image determination blocks SR8 to SR14) and the video image display area (corresponding to the still image determination blocks SR1 to SR7).

[0097] Figure 8 It is an icon Figure 2 A conceptual diagram of the operation of the driving frequency determiner 230. Figure 9 It is an icon Figure 2 A table of values ​​of the flicker value memory 240. Figure 10 It is an icon Figure 2 A conceptual diagram of the operation of the driving frequency determiner 230. Figure 11 It is an icon Figure 2 1 and 2. A signal timing diagram of an output signal of the driving frequency determiner 230 is shown in FIG.

[0098] See also Figures 1 to 11 , an exemplary embodiment of the driving frequency determiner 230 may divide the still image display area into a plurality of driving frequency determining blocks DR1 to DRN, and determine the driving frequencies RDATA1 to RDATAN of the driving frequency determining blocks DR1 to DRN, respectively, based on flicker values ​​corresponding to grayscale values ​​of the input image data IMG for the driving frequency determining blocks DR1 to DRN.

[0099] The size of the still image determination block (e.g., the first still image determination block SR1) may be different from the size of the driving frequency determination block (e.g., the first driving frequency determination block DR1). In one exemplary embodiment, for example, the size of the still image determination block (e.g., the first still image determination block SR1) may be smaller than the size of the driving frequency determination block (e.g., the first driving frequency determination block DR1).

[0100] When the number of still image determination blocks SR1 to SRM is large, the resolution for finding the boundary BMS between the still image display area and the video image display area can be high. Therefore, when the size of each of the still image determination blocks SR1 to SRM is reduced and the number of still image determination blocks SR1 to SRM is increased, the boundary BMS between the still image display area and the video image display area can be accurately determined, making it possible to further effectively reduce the power consumption of the display device.

[0101] In addition, when the number of the driving frequency determination blocks DR1 to DRN is large, the still image display area can be driven at an appropriate low driving frequency corresponding to the flicker value.

[0102] The still image determiner 220 may determine the still image display area. The driving frequency determiner 230 may divide the still image display area into a plurality of driving frequency determination blocks DR1 to DRN.

[0103] In one exemplary embodiment, for example, the sizes of the driving frequency determination blocks DR1 to DRN may be fixed regardless of the size of the still image display area. In such an embodiment, when the sizes of the driving frequency determination blocks DR1 to DRN are fixed, the number of the driving frequency determination blocks DR1 to DRN may increase when the size of the still image display area increases according to the input image data IMG.

[0104] In an alternative exemplary embodiment, for example, the number of the driving frequency determination blocks DR1 to DRN may be fixed regardless of the size of the still image display area. In such an embodiment, when the number of the driving frequency determination blocks DR1 to DRN is fixed, when the size of the still image display area increases according to the input image data IMG, the size of the driving frequency determination blocks DR1 to DRN may increase. In an exemplary embodiment, for example, Figures 8 to 10 As shown in , the number of driving frequency determination blocks DR1 to DRN may be fixed to seven. In such an embodiment, Figure 10 The size of the still image display area in the Figure 8 The size of the still image display area in Figure 10 The size of a single drive frequency determination block in Figure 8 The individual drive frequencies in determine the block size.

[0105] In one exemplary embodiment, for example, when the flag signal SF is 0, the driving frequency determiner 230 may drive the switching elements of the pixels in the video image display area at a normal driving frequency. In one exemplary embodiment, for example, when the flag signal SF is 0, the driving frequency determiner 230 may drive the video image display area at 120 Hz.

[0106] In one exemplary embodiment, for example, when the flag signal SF is 1, the driving frequency determiner 230 may drive the switching elements of the pixels in the still image display area at a low driving frequency. In one exemplary embodiment, for example, when the flag signal SF is 1, the driving frequency determiner 230 may drive the still image display area at a frequency between 1 Hz and 120 Hz.

[0107] The driving frequency determiner 230 may refer to the flicker value memory 240 to determine the low driving frequency of the driving frequency determination blocks DR1 to DRN. The flicker value memory 240 may include flicker values ​​representing flicker degrees corresponding to grayscale values ​​of the input image data IMG.

[0108] The flicker value memory 240 may store grayscale values ​​of the input image data IMG and flicker values ​​corresponding to the grayscale values ​​of the input image data IMG. The flicker values ​​may be used to determine the driving frequency of the display panel 100. The flicker value memory 240 may be a lookup table ("LUT") type.

[0109] exist Figure 9In the embodiment of the present invention, the input grayscale value of the input image data IMG may be 8 bits, the minimum grayscale value of the input image data IMG may be 0, and the maximum grayscale value of the input image data IMG may be 255. The number of flicker setting levels of the flicker value memory 240 may be 64. When the number of flicker setting levels increases, flicker can be effectively eliminated, but the logical size of the driving controller 200 may increase. Therefore, the number of flicker setting levels may be limited.

[0110] Despite Figure 9 The input grayscale value has an 8-bit value, but the present invention is not limited thereto.

[0111] exist Figure 9 In the example, the number of grayscale values ​​of the input image data IMG is 256, and the number of flicker setting levels is 64, so that a single flicker value in the flicker value memory 240 can correspond to four grayscale values. In one exemplary embodiment, for example, the first flicker setting level stores a flicker value of 0 for grayscale values ​​0 to 3. In such an embodiment, a flicker value of 0 can represent a driving frequency of 1 Hz. In one exemplary embodiment, for example, the second flicker setting level stores a flicker value of 0 for grayscale values ​​4 to 7. In such an embodiment, a flicker value of 0 can represent a driving frequency of 1 Hz. In one exemplary embodiment, for example, the third flicker setting level stores a flicker value of 40 for grayscale values ​​8 to 11. In such an embodiment, a flicker value of 40 can represent a driving frequency of 2 Hz. In one exemplary embodiment, for example, the fourth flicker setting level stores a flicker value of 80 for grayscale values ​​12 to 15. In such an embodiment, a flicker value of 80 can represent a driving frequency of 5 Hz. In one exemplary embodiment, for example, the fifth flicker setting level stores a flicker value of 120 for grayscale values ​​16 to 19. In such an embodiment, a flicker value of 120 may represent a driving frequency of 10 Hz. In one exemplary embodiment, for example, the sixth flicker setting level stores a flicker value of 160 for grayscale values ​​20 to 23. In such an embodiment, a flicker value of 160 may represent a driving frequency of 30 Hz. In one exemplary embodiment, for example, the seventh flicker setting level stores a flicker value of 200 for grayscale values ​​24 to 27. Here, a flicker value of 200 may represent a driving frequency of 60 Hz. In one exemplary embodiment, for example, the sixty-second flicker setting level stores a flicker value of 0 for grayscale values ​​244 to 247. In such an embodiment, a flicker value of 0 may represent a driving frequency of 1 Hz. In one exemplary embodiment, for example, the sixty-third flicker setting level stores a flicker value of 0 for grayscale values ​​248 to 251. In such an embodiment, a flicker value of 0 may represent a driving frequency of 1 Hz. In one exemplary embodiment, for example, the sixty-fourth flicker setting level stores a flicker value of 0 for grayscale values ​​252 to 255. In such an embodiment, a flicker value of 0 may represent a driving frequency of 1 Hz.

[0112] In one exemplary embodiment, for example, the drive frequency may be 120 Hz. Figure 8 In an exemplary embodiment, for example, based on the video image display area MOVIE for Figure 8 The driving frequency determiner 230 determines the flicker value of the grayscale value of the input image data IMG corresponding to the first driving frequency determining block DR1. Figure 8 The driving frequency of the first driving frequency determination block DR1 in the embodiment is determined to be 10 Hz. In one exemplary embodiment, for example, based on the Figure 8 The second driving frequency determining block DR2 in the drive frequency determining unit 230 determines the flicker value of the grayscale value of the input image data IMG corresponding to the flicker value of the grayscale value of the input image data IMG. Figure 8 The driving frequency of the second driving frequency determination block DR2 in the embodiment is determined to be 10 Hz. In an exemplary embodiment, for example, based on the Figure 8 The driving frequency determiner 230 determines the flicker value of the grayscale value of the input image data IMG corresponding to the third driving frequency determining block DR3. Figure 8 The driving frequency of the third driving frequency determination block DR3 in the embodiment is determined to be 5 Hz. In an exemplary embodiment, for example, based on the Figure 8 The driving frequency determiner 230 determines the flicker value of the grayscale value of the input image data IMG corresponding to the fourth driving frequency determining block DR4. Figure 8 The driving frequency of the fourth driving frequency determination block DR4 in the embodiment is determined to be 1 Hz. In an exemplary embodiment, for example, based on the Figure 8 The driving frequency determiner 230 determines the flicker value of the grayscale value of the input image data IMG corresponding to the fifth driving frequency determining block DR5. Figure 8 The driving frequency of the fifth driving frequency determination block DR5 in the embodiment is determined to be 1 Hz. In an exemplary embodiment, for example, based on the Figure 8 The driving frequency determiner 230 determines the flicker value of the grayscale value of the input image data IMG corresponding to the sixth driving frequency determining block DR6. Figure 8 The driving frequency of the sixth driving frequency determination block DR6 in the embodiment is determined to be 1 Hz. In an exemplary embodiment, for example, based on the Figure 8 The driving frequency determiner 230 determines the flicker value of the grayscale value of the input image data IMG corresponding to the seventh driving frequency determining block DR7. Figure 8 The driving frequency of the seventh driving frequency determination block DR7 in is determined to be 1 Hz.

[0113] In one exemplary embodiment, for example, the drive frequency may be 120 Hz. Figure 10The driving frequency of the driving frequency determination block is determined according to the grayscale value of the input image data IMG, so that Figure 10 The driving frequencies of the driving frequency determination blocks DR1 to DR7 in the Figure 8 In one exemplary embodiment, for example, based on the driving frequency of the blocks DR1 to DR7, Figure 10 The driving frequency determiner 230 determines the flicker value of the grayscale value of the input image data IMG corresponding to the first driving frequency determining block DR1. Figure 10 The driving frequency of the first driving frequency determination block DR1 in the embodiment is determined to be 10 Hz. In one exemplary embodiment, for example, based on the Figure 10 The driving frequency determiner 230 determines the flicker value of the grayscale value of the input image data IMG corresponding to the second driving frequency determining block DR2, the third driving frequency determining block DR3 and the fourth driving frequency determining block DR4. Figure 10 The driving frequencies of the second driving frequency determination block DR2, the third driving frequency determination block DR3 and the fourth driving frequency determination block DR4 in the embodiment are determined to be 5 Hz. In one exemplary embodiment, for example, based on the Figure 10 The driving frequency determiner 230 determines the flicker value of the grayscale value of the input image data IMG corresponding to the fifth driving frequency determining block DR5, the sixth driving frequency determining block DR6 and the seventh driving frequency determining block DR7. Figure 10 The driving frequency of the fifth driving frequency determination block DR5, the sixth driving frequency determination block DR6 and the seventh driving frequency determination block DR7 in FIG.

[0114] exist Figure 11 , an input vertical synchronization signal IVS, an input data enable signal IDE, and an output data enable signal ODE are illustrated. The input vertical synchronization signal IVS and the input data enable signal IDE may be input to the driving controller 200 and synchronized with the input image data IMG.

[0115] The driving frequency determiner 230 may generate an output data enable signal ODE based on the driving frequencies RDATA1 to RDATAN of the driving frequency determination blocks DR1 to DRN. Figure 11 As shown in , the driving frequency of the video image display area MOVIE may be 120 Hz, for example, the driving frequency of the first group of driving frequency determination blocks STILL(1) may be 10 Hz, the driving frequency of the second group of driving frequency determination blocks STILL(2) may be 5 Hz, and the driving frequency of the third group of driving frequency determination blocks STILL(3) may be 1 Hz. In such an embodiment, as Figure 11 As shown in , 1 second can be divided into 120 frames.

[0116] The output data enable signal ODE of the video image display area MOVIE may be the same as the input data enable signal IDE of the video image display area MOVIE. The output data enable signal ODE may be activated in the first frame to the 120th frame corresponding to the video image display area MOVIE.

[0117] The output data enable signal ODE of the first group driving frequency determination block STILL(1) may be generated by masking a portion of the input data enable signal IDE of the first group driving frequency determination block STILL(1). In one exemplary embodiment, for example, the output data enable signal ODE of the first group driving frequency determination block STILL(1) may be activated every 12 frames (e.g., in the 1st frame 1F, the 13th frame 13F, the 25th frame 25F, ..., the 121st frame 121F) to indicate a driving frequency of 10 Hz.

[0118] The output data enable signal ODE of the second group driving frequency determination block STILL(2) can be generated by masking a portion of the input data enable signal IDE of the second group driving frequency determination block STILL(2). In one exemplary embodiment, for example, the output data enable signal ODE of the second group driving frequency determination block STILL(2) can be activated every 24 frames to indicate a driving frequency of 5 Hz.

[0119] The output data enable signal ODE of the third group driving frequency determination block STILL(3) can be generated by masking a portion of the input data enable signal IDE of the third group driving frequency determination block STILL(3). In one exemplary embodiment, for example, the output data enable signal ODE of the third group driving frequency determination block STILL(3) can be activated every 120 frames to indicate a driving frequency of 1 Hz.

[0120] In one exemplary embodiment, for example, the waveform of the output data enable signal ODE in the 121st to 240th frames may be the same as the waveform of the output data enable signal ODE in the first to 120th frames.

[0121] When the driving frequency of the driving frequency determination block is changed from the first frequency to the second frequency by the driving frequency determiner 230 , the compensation frame inserter 250 may insert the compensation frame between the frame of the first frequency and the frame of the second frequency.

[0122] In one exemplary embodiment, for example, the compensation frame inserter 250 may operate independently in units of driving frequency determination blocks. In one exemplary embodiment, for example, when the driving frequency of the first driving frequency determination block DR1 changes from the first frequency to the second frequency, the compensation frame inserter 250 may insert a compensation frame between the frame of the first frequency and the frame of the second frequency corresponding to the first driving frequency determination block DR1. In one exemplary embodiment, for example, when the driving frequency of the second driving frequency determination block DR2 changes from the third frequency to the fourth frequency, the compensation frame inserter 250 may insert a compensation frame between the frame of the third frequency and the frame of the fourth frequency corresponding to the second driving frequency determination block DR2.

[0123] The compensation frame inserter 250 may determine the frequency of the compensation frames and the number of compensation frames. In one exemplary embodiment, for example, when the driving frequency of the first driving frequency determination block DR1 changes from a first frequency to a second frequency, the frequency of the compensation frame may be determined to be a value between the first frequency and the second frequency. In one exemplary embodiment, for example, when the driving frequency changes from 60 Hz to 10 Hz, the frequency of the first compensation frame may be determined to be one of 30 Hz, 20 Hz, and 15 Hz. In one exemplary embodiment, for example, when the first driving frequency of the first driving frequency determination block DR1 changes from 60 Hz to 1 Hz, the frequency of the compensation frame may be determined to be one of 30 Hz, 20 Hz, 15 Hz, 10 Hz, 5 Hz, and 2 Hz. The compensation frame inserter 250 may determine the frequencies of multiple compensation frames.

[0124] The compensation frame inserter 250 may determine the number of compensation frames based on the difference between the first frequency and the second frequency. In an exemplary embodiment, for example, when the difference between the first frequency and the second frequency is small, the number of compensation frames may be small. In such an embodiment, when the difference between the first frequency and the second frequency is large, the number of compensation frames may be large.

[0125] According to an exemplary embodiment, the driving frequency is determined based on the image displayed on the display panel 100, so that the power consumption of the display device can be reduced. In such an embodiment, when the input image data IMG includes a still image display area and a video image display area, the still image display area and the video image display area can be driven at different frequencies, so that the power consumption of the display device can be further reduced.

[0126] In such an embodiment, the still image determiner 220 can divide the input image data IMG into multiple still image determination blocks SR1 to SRM, and determine whether each of the still image determination blocks SR1 to SRM represents a still image or a video image to determine the boundary BMS between the still image display area and the video image display area, so that the power consumption of the display device can be further reduced.

[0127] In such an embodiment, the driving frequency determiner 230 can divide the still image display area into a plurality of driving frequency determination blocks DR1 to DRN, and determine the driving frequencies RDATA1 to RDATAN of the driving frequency determination blocks DR1 to DRN respectively based on the flicker values ​​corresponding to the grayscale values ​​of the input image data IMG, so that the power consumption of the display device can be further reduced while effectively preventing flicker.

[0128] Figure 12 is a conceptual diagram illustrating a display panel 100 of a display device according to an exemplary embodiment of the present invention. Figure 13 It is an icon Figure 12 1 is a block diagram of a driving controller 200 of a display device.

[0129] In addition to the display panel 100 being divided into a plurality of segments, Figure 12 and Figure 13 The display device and the method of driving the display panel 100 shown in FIG. Figures 1 to 11 The display device and the method of driving the display panel 100 are substantially the same. Figure 12 and Figure 13 In the present invention, the same reference numerals will be used to refer to the Figures 1 to 11 The elements described are identical or similar elements, and any repeated detailed description of the elements will be omitted.

[0130] See also Figure 1 and Figures 3 to 13 , an exemplary embodiment of a display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0131] In such an embodiment, Figure 13 As shown in FIG, the driving controller 200 may include a still image determiner 220, a driving frequency determiner 230, and a flicker value memory 240A. The driving controller 200 may further include a fixed frequency determiner 210. The driving controller 200 may further include a compensation frame interpolator 250.

[0132] The fixed frequency determiner 210 may determine whether the input frequency of the input image data IMG is of a normal type. In one exemplary embodiment, for example, the fixed frequency determiner 210 may determine whether the input frequency of the input image data IMG is of a normal type by counting the number of pulses of the horizontal synchronization signal HSYNC between the first pulse and the second pulse of the vertical synchronization signal VSYNC, or by counting the number of pulses of the data enable signal DE between the first pulse and the second pulse of the vertical synchronization signal VSYNC.

[0133] The still image determiner 220 may divide the input image data IMG into a plurality of still image determination blocks SR1 to SRM. In one exemplary embodiment, for example, each of the still image determination blocks SR1 to SRM may extend in a direction perpendicular to a scanning direction of a gate signal (e.g., the second direction D2). Each of the still image determination blocks SR1 to SRM may extend in the first direction D1.

[0134] The driving frequency determiner 230 may divide the still image display area into a plurality of driving frequency determining blocks DR1 to DRN and respectively determine driving frequencies RDATA1 to RDATAN of the driving frequency determining blocks DR1 to DRN based on flicker values ​​corresponding to grayscale values ​​of the input image data IMG for the driving frequency determining blocks DR1 to DRN.

[0135] The driving frequency determiner 230 may refer to the flicker value memory 240A and information of the segments of the display panel 100 to determine the low driving frequencies of the driving frequency determination blocks DR1 to DRN.

[0136] The display panel 100 may include a plurality of segments SEG11 to SEG85. Although exemplary embodiments of the display panel 100 include Figure 12 , but the present invention is not limited thereto. Although for ease of illustration and description, in Figure 12 , the segments are illustrated in an eight by five matrix, but the actual number of segments of the display panel 100 may be different from Figure 12 The number of segments shown in Figure 12 The number of segments shown in is much larger.

[0137] When the flicker value is determined in units of pixels and only one pixel has a high flicker value, the entire display panel 100 may be driven at a high driving frequency to prevent flicker in the one pixel. In this case, when flicker of only one pixel is prevented at a driving frequency of 30 Hz and flicker is not generated in other pixels at a driving frequency of 1 Hz, the display panel 100 may be driven at a driving frequency of 30 Hz, and the power consumption of the display device may become higher than desired.

[0138] In an exemplary embodiment, the display panel 100 is divided into segments, and the flicker value is determined in units of segments, so that the power consumption of the display device can be effectively reduced.

[0139] The driving controller 200 may determine optimal driving frequencies of the segments determined based on the flicker values ​​of the segments, and may determine a maximum driving frequency among the optimal driving frequencies of the segments as a low driving frequency of the display panel 100 .

[0140] In an exemplary embodiment, Figure 8 and Figure 10 Each of the driving frequency determination blocks DR1 to DRN may include a plurality of segments. The driving frequency determiner 230 may determine the driving frequencies RDATA1 to RDATAN of the driving frequency determination blocks DR1 to DRN based on the optimal driving frequencies of the segments in the driving frequency determination blocks DR1 to DRN.

[0141] The driving frequency determiner 230 may generate an output data enable signal ODE based on the driving frequencies RDATA1 to RDATAN of the driving frequency determination blocks DR1 to DRN.

[0142] When the driving frequency of the driving frequency determination blocks DR1 to DRN is changed from the first frequency to the second frequency by the driving frequency determiner 230 , the compensation frame inserter 250 may insert the compensation frame between the frame of the first frequency and the frame of the second frequency.

[0143] According to an exemplary embodiment, the driving frequency is determined according to the image to be displayed on the display panel 100, so that the power consumption of the display device can be reduced. In such an embodiment, when the input image data IMG includes a still image display area and a video image display area, the still image display area and the video image display area can be driven at different frequencies, so that the power consumption of the display device can be further reduced.

[0144] In such an embodiment, the still image determiner 220 can divide the input image data IMG into multiple still image determination blocks SR1 to SRM, and determine whether each of the still image determination blocks SR1 to SRM represents a still image or a video image to determine the boundary BMS between the still image display area and the video image display area, so that the power consumption of the display device can be further reduced.

[0145] In such an embodiment, the driving frequency determiner 230 can divide the still image display area into a plurality of driving frequency determination blocks DR1 to DRN, and determine the driving frequencies RDATA1 to RDATAN of the driving frequency determination blocks DR1 to DRN respectively based on the flicker values ​​corresponding to the grayscale values ​​of the input image data IMG, so that the power consumption of the display device can be further reduced.

[0146] According to the present invention as explained above, the power consumption of the display device can be reduced, and the display quality of the display panel 100 can be improved.

[0147] The present invention should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and the concept of the present invention will be fully conveyed to those skilled in the art.

[0148] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made in the exemplary embodiments without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device comprising: A display panel including gate lines, data lines, and pixels, wherein the display panel displays an image based on input image data; A gate driver, outputting a gate signal to the gate line; a data driver, outputting a data voltage to the data line; and a driving controller that controls the operation of the gate driver and the operation of the data driver and drives a still image display area and a video image display area in a display area of ​​the display panel at different driving frequencies; wherein the drive controller includes a still image determiner that divides the input image data into a plurality of still image determination blocks, determines whether the still image determination blocks represent a still image or a video image, and determines a boundary between the still image display area and the video image display area, wherein the driving controller further includes a driving frequency determiner that divides the still image display area into a plurality of driving frequency determination blocks and determines driving frequencies of the driving frequency determination blocks respectively based on flicker values ​​corresponding to grayscale values ​​of the input image data for the driving frequency determination blocks, and in: The size of the driving frequency determination block is fixed regardless of the size of the still image display area, and When the size of the still image display area increases according to the input image data, the number of the driving frequency determination blocks increases. 2 . The display device according to claim 1 , wherein the still image determiner generates a flag signal indicating whether the still image determination block indicates the still image or the video image. 3 . The display device according to claim 1 , wherein a size of the still image determination block is different from a size of the driving frequency determination block. 4 . The display device according to claim 3 , wherein the size of the still image determination block is smaller than the size of the driving frequency determination block.

5. The display device according to claim 1, wherein the driving controller further comprises a compensation frame inserter that inserts a compensation frame between a frame of the first frequency and a frame of the second frequency when the driving frequency of the driving frequency determination block is changed from a first frequency to a second frequency by the driving frequency determiner.

6. The display device according to claim 1, wherein: The display panel includes a plurality of segments, and The driving controller determines a driving frequency of the display panel based on a driving frequency determined according to a flicker value corresponding to a grayscale value of the input image data for the segment.

7. The display device according to claim 6, wherein: Each of the driving frequency determination blocks includes a plurality of segments, and The driving frequency determiner determines the driving frequency of each of the driving frequency determination blocks based on a driving frequency determined according to a flicker value corresponding to a grayscale value of the input image data for the segment in the driving frequency determination block.

8. A display device comprising: A display panel including gate lines, data lines, and pixels, wherein the display panel displays an image based on input image data; A gate driver, outputting a gate signal to the gate line; a data driver, outputting a data voltage to the data line; and a driving controller that controls the operation of the gate driver and the operation of the data driver and drives a still image display area and a video image display area in a display area of ​​the display panel at different driving frequencies; wherein the drive controller includes a still image determiner that divides the input image data into a plurality of still image determination blocks, determines whether the still image determination blocks represent a still image or a video image, and determines a boundary between the still image display area and the video image display area, wherein the driving controller further includes a driving frequency determiner that divides the still image display area into a plurality of driving frequency determination blocks and determines driving frequencies of the driving frequency determination blocks respectively based on flicker values ​​corresponding to grayscale values ​​of the input image data for the driving frequency determination blocks, and in: The number of the driving frequency determination blocks is fixed regardless of the size of the still image display area, and When the size of the still image display area increases according to the input image data, the size of the driving frequency determination block increases.

9. A display device comprising: A display panel including gate lines, data lines, and pixels, wherein the display panel displays an image based on input image data; A gate driver, outputting a gate signal to the gate line; a data driver, outputting a data voltage to the data line; and a driving controller that controls the operation of the gate driver and the operation of the data driver and drives a still image display area and a video image display area in a display area of ​​the display panel at different driving frequencies; wherein the drive controller includes a still image determiner that divides the input image data into a plurality of still image determination blocks, determines whether the still image determination blocks represent a still image or a video image, and determines a boundary between the still image display area and the video image display area, and The drive controller further includes a fixed frequency determiner, which determines whether the input frequency of the input image data is of a normal type by counting the number of pulses of the horizontal synchronization signal between the first pulse and the second pulse of the vertical synchronization signal, or by counting the number of pulses of the data enable signal between the first pulse and the second pulse of the vertical synchronization signal.

10. The display device according to claim 9, wherein: The fixed frequency determiner generates a frequency flag indicating whether the input frequency of the input image data has the normal type, and The driving frequency determiner determines a driving frequency of the display panel.

11. A method for driving a display panel, the method comprising: determining whether an input frequency of input image data is of a normal type by counting the number of pulses of a horizontal synchronization signal between a first pulse and a second pulse of a vertical synchronization signal, or by counting the number of pulses of a data enable signal between the first pulse and the second pulse of the vertical synchronization signal; dividing the input image data into a plurality of still image determination blocks; respectively determining whether the still image determination block represents a still image or a video image; determining a boundary between a still image display area and a video image display area in a display area of ​​the display panel; determining a driving frequency of the still image display area; determining a driving frequency of the video image display area; outputting a gate signal to a gate line of the display panel based on the driving frequency of the still image display area and the driving frequency of the video image display area; and outputting a data voltage to a data line of the display panel based on the driving frequency of the still image display area and the driving frequency of the video image display area, The still image display area and the video image display area in the display area are driven at different driving frequencies from each other.

12. The method according to claim 11, further comprising: A flag signal indicating whether the still image determination block indicates the still image or the video image is generated.

13. The method according to claim 11, further comprising: dividing the still image display area into a plurality of driving frequency determination blocks; and The driving frequencies of the driving frequency determination blocks are respectively determined based on flicker values ​​corresponding to grayscale values ​​of the input image data for the driving frequency determination blocks. 14 . The method of claim 13 , wherein a size of the still image determination block is smaller than a size of the driving frequency determination block.

15. The method according to claim 13, further comprising: When the driving frequency of the driving frequency determination block is changed from a first frequency to a second frequency, a compensation frame is inserted between a frame of the first frequency and a frame of the second frequency.

16. The method according to claim 13, wherein Each of the driving frequency determination blocks includes a plurality of segments, and The driving frequency of each of the driving frequency determination blocks is determined based on a driving frequency determined according to a flicker value corresponding to a grayscale value of the input image data for the segment in the driving frequency determination block.

17. The method according to claim 11, further comprising: generating a frequency flag indicating whether the input frequency of the input image data has the normal type, The driving frequency of the still image display area is determined based on the frequency flag.

Images