Display device

Abstract

A display device is provided. The display device includes a pixel connected to a scan line and a data line intersecting the scan line, wherein the pixel includes: a light emitting element; a driving transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line; and a first switching transistor configured to apply the data voltage of the data line to the driving transistor according to a scan signal applied to the scan line. The driving transistor includes: a first active layer including an oxide semiconductor; and a first oxide layer disposed on the first active layer and including the oxide semiconductor. The first switching transistor includes a second active layer including the oxide semiconductor, and the first oxide layer is not disposed on the second active layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0093003 filed on Jul. 31, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more aspects of an embodiment of the present disclosure relate to a display device, and more particularly, to a display device including a thin film transistor having an oxide layer. Background Art

[0003] With the development of multimedia, the importance of display devices has increased. Therefore, various suitable display devices such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs) have been used.

[0004] Devices for displaying images in a display device include display panels such as an OLED panel and an LCD panel. The display device may include a light-emitting element as a light-emitting display panel. Examples of light-emitting diodes (LEDs) include organic LEDs using organic materials as fluorescent materials and inorganic LEDs using inorganic materials as fluorescent materials.

[0005] The example display device includes a display panel, a gate drive circuit, a data drive circuit and a timing controller. The display panel includes a data line, a gate line and a pixel formed at the intersection (cross point) of the data line and the gate line. Each pixel uses a thin film transistor as a switching device and receives a data voltage from the data line when a gate signal is supplied to the gate line. Each pixel can emit light with a set or predetermined brightness according to the data voltage applied to the pixel.

[0006] Recently, display devices capable of displaying images at high resolution, for example, at ultra high definition (UHD), have been released, and display devices capable of displaying images at high resolution of 8K UHD have been developed. UHD means a resolution of 3840×2160, and 8K UHD means a resolution of 7680×4320.

[0007] In a high-resolution display device, the driving current for each pixel may decrease as the number of pixels increases, thereby reducing the driving voltage range of the driving transistor of each pixel. Summary of the invention

[0008] One or more aspects of an embodiment of the present disclosure are directed to a display device including a driving transistor and a switching transistor, the driving transistor including an oxide layer including an oxide semiconductor, and the switching transistor not including (the) oxide layer.

[0009] It should be noted that the objects of the present disclosure are not limited to the objects described above, and other objects of the present disclosure will become apparent to those skilled in the art from the following description.

[0010] One or more exemplary embodiments of the present disclosure provide a display device including a pixel connected to a scan line and a data line intersecting or crossing the scan line, wherein the pixel includes: a light emitting element; a driving transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line; and a first switching transistor configured to apply the data voltage of the data line to the driving transistor according to a scan signal applied to the scan line. The driving transistor includes: a first active layer including an oxide semiconductor; and a first oxide layer disposed on the first active layer and including the oxide semiconductor, the first switching transistor includes a second active layer including the oxide semiconductor, wherein the first oxide layer is not disposed on the second active layer.

[0011] In example embodiments, the oxide semiconductor of the first active layer and the oxide semiconductor of the second active layer may include at least one selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf).

[0012] In example embodiments, the oxide semiconductor of the first oxide layer may include at least one selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf).

[0013] In example embodiments, the first active layer may have a lower hydrogen content than the second active layer, and the first active layer may have a higher oxygen content than the second active layer.

[0014] In example embodiments, the driving transistor may include: a first gate insulating layer disposed on the first active layer; and a first gate electrode disposed on the first gate insulating layer and overlapping the first active layer, wherein the first oxide layer is disposed between the first gate electrode and the first gate insulating layer.

[0015] In example embodiments, a width of the first oxide layer measured in one direction may be substantially equal to a width of the first gate electrode measured in the one direction.

[0016] In example embodiments, a width of the first oxide layer measured in one direction may be smaller than a width of the first gate electrode measured in the one direction, and both side surfaces of the first oxide layer may (eg, simultaneously) contact the first gate electrode.

[0017] In example embodiments, the first active layer may include a first conductive region, a second conductive region, and a channel region disposed between the first conductive region and the second conductive region, and the first oxide layer may be disposed to overlap the channel region of the first active layer.

[0018] In example embodiments, the driving transistor may include a first source electrode contacting the first conductive region through a first contact hole passing through an interlayer insulating layer disposed on the first active layer, and a first drain electrode contacting the second conductive region through a second contact hole passing through the interlayer insulating layer.

[0019] In example embodiments, the driving transistor may further include a first light blocking layer disposed under the first active layer, and the first source electrode may contact the first light blocking layer.

[0020] In example embodiments, the first gate insulating layer may be disposed on the second active layer, and the first switching transistor may include a second gate electrode disposed on the first gate insulating layer and overlapping the second active layer.

[0021] In example embodiments, at least a partial region of a lower surface of the first gate electrode may be in contact with the first oxide layer, and a lower surface of the second gate electrode may not be in contact with the first oxide layer.

[0022] One or more example embodiments of the present disclosure provide a display device, the display device comprising: a substrate comprising a display area and a non-display area; a buffer layer disposed on the substrate; a first semiconductor layer disposed on the buffer layer and comprising an oxide semiconductor, wherein the first semiconductor layer comprises a first active layer and a second active layer disposed in the display area; a gate insulating layer disposed on the first semiconductor layer to cover the first active layer and the second active layer; a second semiconductor layer disposed on the gate insulating layer and comprising an oxide semiconductor, wherein the second semiconductor layer comprises a first oxide layer disposed on the first active layer; a first conductive layer disposed on the second semiconductor layer and comprising a gate electrode; an interlayer insulating layer disposed on the first conductive layer and covering the gate electrode; and a second conductive layer disposed on the interlayer insulating layer and comprising a source electrode and a drain electrode, wherein the first oxide layer is not disposed on the second active layer.

[0023] In example embodiments, the oxide semiconductor of the first semiconductor layer and the oxide semiconductor of the second semiconductor layer may include at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf).

[0024] In example embodiments, the first active layer may have a lower hydrogen content than the second active layer, and the first active layer may have a higher oxygen content than the second active layer.

[0025] In example embodiments, the first conductive layer includes a first gate electrode disposed on the first active layer and including a lower surface contacting the first oxide layer; and a second gate electrode disposed on the second active layer and including a lower surface contacting the gate insulating layer.

[0026] In example embodiments, a width of the first gate electrode measured in one direction may be at least substantially equal to a width of the first oxide layer measured in the one direction.

[0027] In example embodiments, the second conductive layer includes a first source electrode contacting one end of the first active layer, a first drain electrode contacting an opposite end of the first active layer, a second source electrode contacting one end of the second active layer, and a second drain electrode contacting an opposite end of the second active layer.

[0028] In example embodiments, the display device may further include a third conductive layer disposed between the substrate and the buffer layer and including a first light blocking layer overlapped with the first active layer, wherein the first source electrode may contact the first light blocking layer.

[0029] In example embodiments, the third conductive layer may further include a second light blocking layer stacked with the second active layer, and the second gate electrode may contact the second light blocking layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent through the following exemplary embodiments of the present disclosure being described in more detail with reference to the accompanying drawings, in which:

[0031] Figure 1 is a perspective view showing a display device according to an example embodiment;

[0032] Figure 2 is a schematic plan view of a display device according to an example embodiment;

[0033] Figure 3 It is shown Figure 2 Circuit diagram of a pixel;

[0034] Figure 4 It is shown Figure 2 Circuit diagram of a pixel;

[0035] Figure 5 is a plan view showing a driving transistor according to an example embodiment;

[0036] Figure 6 is a plan view showing a first switching transistor according to an example embodiment;

[0037] Figure 7 It is along Figure 5 The line I-I' and Figure 6 A cross-sectional view taken along line II-II';

[0038] Figure 8 is a graph showing a driving current according to a gate voltage of a driving transistor according to an example embodiment;

[0039] Fig. 9 is a graph showing a driving current according to a gate voltage of a switching transistor according to an example embodiment;

[0040] Fig.10 is a flow chart showing a manufacturing process of a display device according to an example embodiment;

[0041] Figures 11 to 22 is a cross-sectional view showing a manufacturing process of a display device according to an example embodiment;

[0042] Fig.23 is a cross-sectional view showing a portion of a manufacturing process of a display device according to another example embodiment;

[0043] Fig.24 is a plan view showing a driving transistor according to another example embodiment;

[0044] Fig.25 It is along Fig.24 The line I-I' and Figure 6 A cross-sectional view taken along line II-II';

[0045] Fig.26 is a plan view showing a driving transistor according to still another example embodiment;

[0046] Fig. 27 It is along Fig.26 The line I-I' and Figure 6 A cross-sectional view taken along line II-II';

[0047] Fig.28 and Fig.29 It is shown that Fig.26 A cross-sectional view of a portion of a manufacturing process of a display device of a driving transistor;

[0048] Fig.30 is a plan view showing a first switching transistor according to another example embodiment;

[0049] Fig.31 It is along Fig.26 The line I-I' and Fig.30 A cross-sectional view taken along line III-III'; and

[0050] Fig.32 is a cross-sectional view illustrating a second switching transistor according to another example embodiment. DETAILED DESCRIPTION

[0051] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings in which disclosed embodiments are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0052] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. When an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements. Throughout the specification, the same reference numerals refer to the same components, and redundant descriptions thereof may be omitted.

[0053] It will be understood that although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below can be named as the second element. Similarly, the second element can also be named as the first element.

[0054] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0055] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0056] Figure 1 is a perspective view showing a display device according to an example embodiment.

[0057] Reference Figure 1 , the display device 1 displays a moving picture or a still image. The display device 1 may refer to any suitable electronic device provided with a display screen. For example, the display device 1 may include a television, a laptop computer, a monitor, a digital signage, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, a game console, a digital camera and / or a portable video camera, etc., all of which include a display screen.

[0058] The display device 1 includes a display panel provided with a display screen. Non-limiting examples of the display panel include a light emitting diode (LED) display panel, an organic light emitting display (OLED) panel, a quantum dot light emitting display (QLED) panel, a plasma display panel, and a field emission display (FED) panel, etc. Hereinafter, an embodiment including an LED display panel is shown as an example of a display panel, but the present disclosure is not limited thereto, and other display panels may be applied within the same technical spirit.

[0059] The display device 1 may be modified to have any suitable shape or form. For example, the display device 1 may have a rectangular shape with a long width, a rectangular shape with a long length, a square shape, a quadrilateral shape with one or more rounded corners (vertices), any other polygonal shape, and / or a circular (round) shape, etc. In some embodiments, the shape of the display area DA of the display device 1 may be different from that of the display area DA of the display device 1. Figure 1 The overall shape of the display device 1 is similar. Figure 1 An embodiment is shown in which the display device 1 and the display area DA have a rectangular shape with a long width.

[0060] The display device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where an image can be displayed, and the non-display area NDA is an area where no image is displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as an inactive area.

[0061] Typically, the display area DA may occupy a central area or a central portion of the display device 1. The display area DA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix form. When viewed in a plan view, each pixel PX may have a rectangular shape or a square shape, but the present disclosure is not limited thereto, for example, each pixel PX may have a diamond shape (e.g., wherein each side is inclined relative to the first direction DR1).

[0062] Figure 2 is a schematic plan view of a display device according to an example embodiment.

[0063] Reference Figure 2 The display device 1 includes a display panel 10, an integrated driver 20 and a scan driver SDR. The integrated driver 20 may include a timing controller and a data driver.

[0064] The display panel 10 may include a display area DA in which pixels PX are formed to display an image and a non-display area NDA outside the display area DA. When the display panel 10 includes a curved portion, the display area DA may be disposed in the curved portion. For example, an image of the display panel 10 may also be viewed on the curved portion.

[0065] Pixels PX and scan lines SCL (indexed as SCL1 to SCLk, where k is an integer of 2 or more), data lines DTL (indexed as DTL1 to DTLj, where j is an integer of 2 or more), and power lines connected to the pixels PX may be disposed in the display area DA. The scan lines SCL may be formed parallel to a first direction DR1, and the data lines DTL may be formed parallel to a second direction DR2 intersecting the first direction DR1. Each pixel PX may be connected to at least one of the scan lines SCL and one of the data lines DTL.

[0066] Each pixel PX may include a driving transistor, at least one switching transistor, a light emitting element, and a capacitor. The switching transistor may be turned on when at least one scanning signal is applied to it from the scanning line SCL (for example, a current may be transferred from the source electrode to the drain electrode), so that at least one data voltage of the data line DTL is applied to the gate electrode of the driving transistor. The driving transistor supplies a driving current to the light emitting element according to the data voltage applied to the gate electrode, and the light emitting element may then emit light. The driving transistor and at least one switching transistor may both be thin film transistors. The light emitting element may emit light according to (depending on) the driving current of the driving transistor. The light emitting element may be formed by an organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode. The capacitor may be used to constantly (substantially) maintain the data voltage applied to the gate electrode of the driving transistor.

[0067] The non-display area NDA may be defined as an area from the outermost portion (periphery) of the display area DA to the outer edge of the display panel 10. A scan driver SDR (configured to apply a scan signal to a scan line SCL) and a data voltage distribution circuit DMUX that connects a data line DTL to a routine line RL may both (e.g., simultaneously) be disposed in the non-display area NDA. A pad (or referred to as a "pad") DP electrically connected to the integrated driver 20 may also be disposed in the non-display area NDA. In this case, the integrated driver 20 and the pad DP may be disposed at or near one side edge of the display panel 10.

[0068] The integrated driver 20 is connected to the pad DP and receives digital video data and timing signals. The integrated driver 20 converts the digital video data into analog positive / negative data voltages, and supplies the analog positive / negative data voltages to the data lines DTL through the wiring RL and the data voltage distribution circuit DMUX. In addition, the integrated driver 20 generates a scan control signal for controlling the scan driver SDR, and supplies the scan control signal through the scan control line SL. The pixel PX to which the data voltage is supplied is selected by the scan signal of the scan driver SDR, and the data voltage is supplied to the selected pixel PX. In some embodiments, the integrated driver 20 may supply a power voltage to the power line.

[0069] The integrated driver 20 may be formed of an integrated circuit (IC) and may be mounted on the display panel 10 in a pad region using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but the present disclosure is not limited thereto. In some embodiments, for example, the integrated driver 20 may be mounted on a separate circuit board.

[0070] The pad DP may be electrically connected to the integrated driver 20. The circuit board may be attached to the pad DP using an anisotropic conductive film. As a result, the leads of the circuit board may be electrically connected to the pad DP. The circuit board may be a printed circuit board such as a flexible printed circuit board or a flexible film such as a chip-on-chip film. The circuit board may be bent toward the lower portion of the display panel 10. In this case, one side of the circuit board may be attached to one side edge of the display panel 10, and the other side of the circuit board may be disposed on the lower portion of the display panel 10 and connected to a system board on which a host system is mounted.

[0071] The scan driver SDR may be connected to the integrated driver 20 through at least one scan control line SL to receive a scan control signal. The scan driver SDR may generate a scan signal according to the scan control signal and sequentially output the scan signal to the scan lines SCL. Figure 2 The scan driver SDR is shown as being formed at one side of the display area DA, for example, formed in the non-display area NDA on the left side of the display area DA, but the present disclosure is not limited thereto. For example, the scan driver SDR may be formed at both sides of the display area DA, for example, formed in the non-display area NDA on the left and right sides of the display area DA.

[0072] The data voltage distribution circuit DMUX may be connected between the wiring RL and the data line DTL (for example, the wiring RL and the data line DTL may be connected). The number of wirings RL connected to the data voltage distribution circuit DMUX and the number of data lines DTL connected to the data voltage distribution circuit DMUX may be in a ratio of 1:q (where q is an integer greater than or equal to 2). The data voltage distribution circuit DMUX may distribute a data voltage applied to one wiring RL to a plurality of data lines DTL.

[0073] The power supply circuit may generate a voltage required to drive the display panel 10 through the main power applied from the system board, and may supply the generated voltage to the display panel 10. For example, the power supply circuit may generate a first power voltage and a second power voltage (the first power voltage and the second power voltage are used to drive the light emitting element EL of the display panel 10) through the main power. Figure 3 ), and the first power voltage and the second power voltage are respectively supplied to the first power line VDD ( Figure 3 ) and the second power line VSS ( Figure 3 In some embodiments, the power supply circuit may generate a driving voltage for driving the integrated driver 20 and the scan driver SDR through the main power and supply the generated driving voltage to the integrated driver 20 and the scan driver SDR.

[0074] The power circuit may be formed of an IC and mounted on a circuit board, but the present disclosure is not limited thereto. For example, the power circuit may be integrated into the integrated driver 20.

[0075] Figure 3 It is shown Figure 2 Circuit diagram of a pixel.

[0076] Reference Figure 3 , each pixel PX may include a driving transistor DRT, a first switching transistor SCT, a light emitting element EL, and a capacitor Cst. Figure 3 , each pixel PX is shown to have a 2T1C (2-transistor-1 capacitor) structure including one driving transistor DRT, one first switching transistor SCT, and one capacitor Cst, but the present disclosure is not limited thereto. Each pixel PX may include a greater number of transistors and a plurality of capacitors.

[0077] Each of the driving transistor DRT and the first switching transistor SCT may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode.

[0078] Each of the driving transistor DRT and the first switching transistor SCT may be formed of (formed as) a thin film transistor. Figure 3 In the figure, each of the driving transistor DRT and the first switching transistor SCT is shown as being formed by an n-type metal oxide semiconductor field effect transistor (MOSFET) (formed as an n-type metal oxide semiconductor field effect transistor (MOSFET)), but the present disclosure is not limited to this. The driving transistor DRT and the first switching transistor SCT may be formed by a p-type MOSFET (formed as a p-type MOSFET). In this case, the positions of the source electrode and the drain electrode in each of the driving transistor DRT and the first switching transistor SCT may be interchanged. In the following, a case in which the driving transistor DRT and the first switching transistor SCT are both formed by an n-type MOSFET (formed as an n-type MOSFET) will be described as an example.

[0079] The driving transistor DRT supplies a driving current to the light emitting element EL according to the data voltage applied to the gate electrode, so that the light emitting element EL can emit light. For example, the driving transistor DRT can be used as a driving transistor. The gate electrode of the driving transistor DRT can be connected to the source electrode of the first switching transistor SCT, the source electrode of the driving transistor DRT can be connected to the first electrode of the light emitting element EL, and the drain electrode of the driving transistor DRT can be connected to the first power line VDD to which the first power voltage is applied.

[0080] When a scan signal is applied via the kth (k is a positive integer) scan line SCLk, the first switch transistor SCT may be turned on so that the data voltage of the jth (j is a positive integer) data line DTLj is applied to the gate electrode of the drive transistor DRT. For example, the first switch transistor SCT may be used as a switch transistor. The gate electrode of the first switch transistor SCT may be connected to the kth scan line SCLk, the source electrode of the first switch transistor SCT may be connected to the gate electrode of the drive transistor DRT, and the drain electrode of the first switch transistor SCT may be connected to the jth data line DTLj.

[0081] The capacitor Cst may be connected between the gate electrode and the source electrode of the driving transistor DRT. As a result, the capacitor Cst may serve to constantly (substantially) maintain the data voltage applied to the gate electrode of the driving transistor DRT.

[0082] The light emitting element EL may emit light according to the driving current of the driving transistor DRT. The light emitting element EL may be formed by an organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode. The first electrode of the light emitting element EL may be connected to the source electrode of the driving transistor DRT, and the second electrode of the light emitting element EL may be connected to a second power line VSS to which a second power voltage lower than the first power voltage is applied.

[0083] Figure 4 It is shown Figure 2Circuit diagram of a pixel.

[0084] Reference Figure 4 , each pixel PX may include a driving transistor DRT, a first switching transistor SCT, a sensing transistor SST, a light emitting element EL, and a capacitor Cst. Figure 4 , each pixel PX is shown to have a 3T1C (3-transistor-1 capacitor) structure including one driving transistor DRT, one first switching transistor SCT, one sensing transistor SST, and one capacitor Cst, but the present disclosure is not limited thereto. Figure 3 Compared with the circuit diagram, in addition to Figure 4 The circuit diagram also includes a sensing transistor SST and a reference line Vref. Figure 4 The circuit diagram and Figure 3 The circuit diagram is the same.

[0085] Figure 4 The circuit diagram of FIG. 4 may further include a compensation circuit including a sensing transistor SST and a reference line Vref. The compensation circuit is a circuit added to each pixel PX to compensate for a threshold voltage of a driving transistor DRT, etc.

[0086] The source electrode of the sensing transistor SST may be connected between the source electrode of the driving transistor DRT and the first electrode of the light emitting element EL. The gate electrode of the sensing transistor SST may be connected to the kth sensing signal line SSLk, the drain electrode of the sensing transistor SST may be connected to the reference line Vref, and the source electrode of the sensing transistor SST may be connected to one end of the capacitor Cst. The sensing transistor SST may be turned on by the sensing signal of the kth sensing signal line SSLk and may supply a reference voltage transmitted through the reference line Vref to the source electrode of the driving transistor DRT, or may sense the voltage or current of the source electrode of the driving transistor DRT.

[0087] The reference line Vref may be connected to a scan driver SDR. In this case, the scan driver SDR may sense the source electrode of the drive transistor DRT of each pixel PX in real time during the non-display period of the image or the N frame period, and generate a sensing result. At the same time, the first switch transistor SCT (used as a switch transistor) and the sensing transistor SST (used as a sensing transistor) may be turned on at the same time. In this case, the sensing operation of the reference line Vref and the data output operation (wherein the data signal is output) are divided from each other by the time division method of the scan driver SDR.

[0088] The sensing result may facilitate compensation of an object such as a digital data signal, an analog data signal, a gamma signal, etc. A compensation circuit that generates a compensation signal based on the sensing result may be implemented in the scan driver SDR or in the timing controller, or as a separate circuit.

[0089] However, the present disclosure is not limited thereto. Figure 3 and Figure 4 In the present invention, pixels PX having a 2T1C structure and a 3T1C structure, respectively, have been described as examples, but other embodiments of the present disclosure may include a greater number of transistors or capacitors.

[0090] Hereinafter, the structure and arrangement of transistors provided in each pixel PX will be described.

[0091] Figure 5 is a plan view showing a driving transistor according to an example embodiment. Figure 6 is a plan view showing a first switching transistor according to an example embodiment. Figure 7 It is along Figure 5 The line I-I' and Figure 6 A cross-sectional view taken along line II-II'.

[0092] Reference Figures 5 to 7 The display panel 10 may include a plurality of conductive layers and a plurality of semiconductor layers. The display panel 10 may include a first substrate 110, a buffer layer 120, a first gate insulating layer 130, a driving transistor DRT, a first switching transistor SCT, a first interlayer insulating layer 160, a first protective film 170, a first planarizing film 180, a first electrode 191, an organic light emitting layer 192, a second electrode 193, a pixel defining film 195, and an encapsulation layer 196.

[0093] exist Figures 5 to 7 In the embodiment, the driving transistor DRT and the first switching transistor SCT of the pixel PX are shown to have a coplanar structure (e.g., positioned on the same plane). The coplanar structure has a top gate structure in which (each) gate electrode is formed above (each) active layer (e.g., formed in a plane above a layer or plane containing a source region and a drain region). However, the present disclosure is not limited thereto, and the driving transistor DRT and the first switching transistor SCT of each pixel PX may have a bottom gate structure in which the gate electrode is formed below the active layer. Hereinafter, the driving transistor DRT and the first switching transistor SCT will be described in more detail.

[0094] According to an example embodiment, a plurality of pixels PX are disposed in a display area DA of a display panel 10, and each pixel PX may include a driving transistor DRT and a first switching transistor SCT. The driving transistor DRT of each pixel PX includes a first active layer 350, a first oxide layer 370, a first gate electrode 310, a first source electrode 330, and a first drain electrode 340. The first switching transistor SCT of the pixel PX includes a second active layer 450, a second gate electrode 410, a second source electrode 430, and a second drain electrode 440.

[0095] The display device 1 may include a first semiconductor layer and a second semiconductor layer each including an oxide semiconductor. The first semiconductor layer may include a first active layer 350 and a second active layer 450, and the second semiconductor layer may include a first oxide layer 370. The first oxide layer 370 may include an oxide semiconductor different from the oxide semiconductors of the first active layer 350 and the second active layer 450, and may be selectively disposed only on the first active layer 350. Hereinafter, a plurality of components of the display device 1 will be described in more detail.

[0096] The first substrate 110 may provide a region in which the driving transistor DRT and the first switching transistor SCT are formed. The first substrate 110 may be made of plastic and / or glass.

[0097] The buffer layer 120 is disposed on the first substrate 110. The buffer layer 120 may protect the driving transistor DRT and the first switching transistor SCT of the pixel PX from moisture that penetrates through the first substrate 110. The buffer layer 120 may be formed of a plurality of inorganic layers alternately stacked. For example, the buffer layer 120 may be formed as a layer in which silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layers and silicon oxynitride (SiON) layers are alternately stacked.

[0098] Meanwhile, in some example embodiments, a conductive layer may be further disposed between the first substrate 110 and the buffer layer 120 of the display device 1. The conductive layer may include a light blocking layer disposed to overlap with the first active layer 350 of the driving transistor DRT and the second active layer 450 of the first switching transistor SCT, which will be described below. This will also be described in more detail below with reference to other example embodiments.

[0099] The first semiconductor layer including an oxide semiconductor is disposed on the buffer layer 120. The first semiconductor layer may include a first active layer 350 of the driving transistor DRT and a second active layer 450 of the first switching transistor SCT.

[0100] The first active layer 350 and the second active layer 450 may be disposed on the buffer layer 120. According to an example embodiment, the first active layer 350 and the second active layer 450 may include an oxide semiconductor. In an example embodiment, the first active layer 350 and the second active layer 450 may each independently include indium tin oxide (ITO), indium tin gallium oxide (ITGO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO). However, the present disclosure is not limited thereto.

[0101] The first active layer 350 and the second active layer 450 may be formed of substantially the same material, and as described below, the first active layer 350 and the second active layer 450 may have different compositions due to an oxide layer deposited thereon (e.g., such as an oxide layer existing on the first active layer 350 but not on the second active layer 450). A first oxide layer 370 including an oxide semiconductor may be provided on the first active layer 350, while the first oxide layer 370 may not be provided on the second active layer 450. The first oxide layer 370 may serve as an oxygen supply layer for injecting oxygen into the first active layer 350 during a manufacturing process of the display device 1. In the finally manufactured display device 1, the oxygen content of the first active layer 350 may be different from that of the second active layer 450. A description thereof will be given below.

[0102] The first active layer 350 may include a first conductive region 350a, a second conductive region 350b, and a channel region 350c, and the second active layer 450 may include a first conductive region 450a, a second conductive region 450b, and a channel region 450c. The channel region 350c may be disposed between the first conductive region 350a and the second conductive region 350b, and the channel region 450c may be disposed between the first conductive region 450a and the second conductive region 450b. The first conductive region 350a and the second conductive region 350b may contact the first source electrode 330 and the first drain electrode 340, respectively, and the first conductive region 450a and the second conductive region 450b may contact the second source electrode 430 and the second drain electrode 440, respectively, which will be described below.

[0103] The first gate insulating layer 130 is disposed on the first semiconductor layer. The first gate insulating layer 130 is disposed on the first active layer 350 and the second active layer 450. The first gate insulating layer 130 may be made of a material such as silicon oxide (SiO x ) layer or silicon nitride (SiN x ) layer, or a single layer structure such as silicon oxide (SiO x ) layer and silicon nitride (SiN x ) layers are alternately stacked to form a multilayer structure.

[0104] Meanwhile, the first gate insulating layer 130 is shown in the drawings as being disposed only between the first gate electrode 310 and the first active layer 350 and between the second gate electrode 410 and the second active layer 450, but the present disclosure is not limited thereto. For example, the first gate insulating layer 130 may be formed on the upper surface and the side surface of the first active layer 350 and the upper surface and the side surface of the second active layer 450, and may be disposed on the entire surface of the buffer layer 120 in some embodiments.

[0105] A second semiconductor layer including an oxide semiconductor may be disposed on the first gate insulating layer 130. According to one example embodiment, the second semiconductor layer may include a first oxide layer 370 disposed on the first active layer 350.

[0106] The second semiconductor layer may include an oxide semiconductor, and the driving transistor DRT according to an example embodiment may include a first active layer 350 and a first oxide layer 370 having an oxide semiconductor. The oxide semiconductor of the second semiconductor layer and the oxide semiconductor of the first semiconductor layer may be the same material, but are not limited thereto, and in some embodiments the oxide semiconductor of the second semiconductor layer and the oxide semiconductor of the first semiconductor layer may be different oxide semiconductor materials. The first oxide layer 370 of the driving transistor DRT may be disposed on the first gate insulating layer 130 to overlap with the first active layer 350. The first oxide layer 370 is disposed to overlap at least the channel region 350c of the first active layer 350, and in some embodiments, the width of the first oxide layer 370 measured in one direction may be smaller than the width of the first active layer 350 measured in the one direction, but may be larger than the width of the channel region 350c of the first active layer 350 measured in the one direction. In the drawings, the width of the first oxide layer 370 is shown to be substantially equal to or only slightly smaller than the width of the channel region 350c of the first active layer 350, but the present disclosure is not limited thereto.

[0107] Oxygen vacancy regions may be partially formed in the first semiconductor layer including an oxide semiconductor according to the oxygen partial pressure set in the deposition process. When an insulating layer is deposited on the first semiconductor layer including an oxide semiconductor, hydrogen (H) may be injected into the oxygen vacancy regions, which may increase the mobility of the oxide semiconductor. The number of oxygen vacancy regions may be large, so that the first active layer 350 and the second active layer 450 having an oxide semiconductor may have high mobility. However, in this case, due to the excessive carrier concentration, the driving transistor DRT may be difficult to ensure the driving voltage for driving each pixel PX.

[0108] However, according to an example embodiment, the first oxide layer 370 may be used as an oxygen supply layer to inject oxygen (O) into the channel region 350c of the first active layer 350. The first oxide layer 370 may supply excess oxygen (O) to another adjacent layer (e.g., an insulating layer). The excess oxygen (O) supplied to the insulating layer may then be injected into the channel region 350c of the oxide semiconductor, and the hydrogen (H) that penetrates into the oxygen vacancy region may be released back to the insulating layer. In this case, the number of carriers contained in the oxide semiconductor may be reduced, and the driving voltage range of the driving transistor DRT may be ensured or appropriately maintained. In contrast, in the case of the first switching transistor SCT, an oxygen supply layer (oxide layer) is not provided on the second active layer 450, so that the first switching transistor SCT may have a high mobility.

[0109] According to an example embodiment, the driving transistor DRT may include a first oxide layer 370 disposed on the first active layer 350, thereby improving device characteristics. The driving transistor DRT including the first oxide layer 370 may have a relatively small curve slope in a driving voltage-driving current graph, thereby ensuring a wide range of driving voltages to drive the light emitting element EL of the pixel PX. In addition, in the first switching transistor SCT, the second gate electrode 410 is disposed on the second active layer 450 without having an oxide layer disposed on the second active layer 450, so that high mobility of electrons can be ensured in the channel region 450c.

[0110] Figure 8 is a graph showing a relationship between a driving current and a gate voltage of a driving transistor according to an example embodiment. Fig. 9 is a graph showing the relationship between the driving current and the gate voltage of a switching transistor according to an example embodiment. For example, Figure 8 is a graph showing a driving current (Id) according to a gate voltage (Vg) of a driving transistor DRT including a first oxide layer 370 according to an example embodiment. For example, Fig. 9 is a graph showing a driving current (Id) according to a gate voltage (Vg) of a first switching transistor SCT in which the first oxide layer 370 is not provided, according to an example embodiment.

[0111] like Figure 8As shown in , when the driving transistor DRT further includes an oxide layer, the slope of the curve in the graph of the driving current (Id) according to the gate voltage (Vg) may have a gentle shape (for example, dy / dx is relatively gradually reduced in the shoulder area of ​​the drawn curve). Therefore, in the driving transistor DRT, the range of the gate voltage (Vg) required for the setting or predetermined range of the driving current (Id) can be widened. For example, the driving transistor DRT according to an example embodiment can ensure a wide range of driving voltages for driving the pixel PX. Specifically, in order to realize a high-resolution display device 1 by making the display device 1 have a larger number of pixels PX, the width of the channel region 350c of the driving transistor DRT may be narrowed. When the driving transistor DRT includes a first oxide layer 370, the driving transistor DRT according to an example embodiment can ensure a wide range of driving voltages even with a narrow channel region 350c.

[0112] At the same time, Fig. 9 As shown in FIG. 1 , in the case of a switching transistor that does not include an oxide layer, the slope of the curve may be relatively large, and the curve may have a larger slope (eg, in a shoulder region) than that of the switching transistor. Figure 8 The shape of the curve (eg, in the shoulder region) may be steeper. The active layer of the switching transistor may have high electron mobility in the channel region, and the switching transistor may exhibit a high response speed when a gate voltage (Vg) is applied.

[0113] The first oxide layer 370 according to an example embodiment may include an oxide including at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf). In some example embodiments, the first oxide layer 370 may be formed of tin zinc oxide (TZO), tin gallium oxide (TGO), indium tin zinc oxide (ITZO), indium tin gallium oxide (ITGO), or indium tin zinc gallium oxide (ITZGO). However, the present disclosure is not limited thereto.

[0114] The first oxide layer 370 may be formed to overlap at least the channel region 350c of the first active layer 350 so that excess oxygen (O) is injected into the channel region 350c of the first active layer 350. In some embodiments, the first oxide layer 370 disposed on the first gate insulating layer 130 may have a width greater than that of the channel region 350c of the first active layer 350, for example, may overlap the entire region of the channel region 350c. However, the present disclosure is not limited thereto, and the width of the first oxide layer 370 may be substantially equal to the width of the channel region 350c of the first active layer 350.

[0115] Meanwhile, according to an example embodiment, the first active layer 350 of the driving transistor DRT and the second active layer 450 of the first switching transistor SCT may have the same oxide semiconductor but different composition ratios. When the first oxide layer 370 is disposed on the first active layer 350, excess oxygen (O) of the first oxide layer 370 may be injected into the first active layer 350, and hydrogen (H) present in the oxygen vacancy region may be released. Therefore, the first active layer 350 may have an oxygen content higher than that of the first oxide layer 370, and the first oxide layer 370 may have a hydrogen content higher than that of the first active layer 350. However, the present disclosure is not limited thereto.

[0116] According to an example embodiment, the first active layer 350 may have an oxygen (O) content higher than that of the second active layer 450. In addition, the first active layer 350 may have a hydrogen (H) content lower than that of the second active layer 450. The first active layer 350 has a first oxide layer 370 disposed thereon so that oxygen may be injected therein and hydrogen may be released therefrom during a manufacturing process. On the other hand, since the second active layer 450 does not have the first oxide layer 370 disposed thereon, the second active layer 450 may have almost (substantially) no oxygen injection and hydrogen release. The first active layer 350 and the second active layer 450 may be formed of the same material during the same process, but may have different compositions according to differential deposition of the first oxide layer 370 in a subsequent process. The driving transistor DRT according to an example embodiment includes the first active layer 350 having a high content of oxygen (O), thereby ensuring a wide range of driving voltages. The first switching transistor SCT includes the second active layer 450 having a high content of hydrogen (H), and thus may have high electron mobility. However, the present disclosure is not limited thereto.

[0117] Refer again Figures 5 to 7 The first conductive layer is disposed on the second semiconductor layer. The first conductive layer may include a first gate electrode 310 disposed on the first oxide layer 370 and a second gate electrode 410 disposed on the second active layer 450 .

[0118] The first gate electrode 310 is disposed on the first oxide layer 370. The first gate electrode 310 may overlap the first active layer 350, wherein the first oxide layer 370 and the first gate insulating layer 130 are interposed between the first gate electrode 310 and the first active layer 350. For example, the first gate electrode 310 may overlap the channel region 350c of the first active layer 350. The second gate electrode 410 is disposed on the first gate insulating layer 130.

[0119] The second gate electrode 410 may overlap the second active layer 450 with the first gate insulating layer 130 interposed therebetween. For example, the second gate electrode 410 may overlap the channel region 450c of the second active layer 450.

[0120] When the first gate electrode 310 and the second gate electrode 410 have a sufficient width to overlap the channel region 350c of the first active layer 350 and the channel region 450c of the second active layer 450, respectively, the range of the width is not particularly limited. The first gate electrode 310 and the second gate electrode 410 may each be formed as a single-layer structure or a multi-layer structure made of one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0121] According to an example embodiment, the first gate electrode 310 of the first conductive layer is disposed on the first oxide layer 370 at a position overlapping the first active layer 350, and the second gate electrode 410 of the first conductive layer is disposed on the first gate insulating layer 130 at a position overlapping the second active layer 450. For example, the first conductive layer may include the first gate electrode 310 having a lower surface in contact with the first oxide layer 370 and the second gate electrode 410 having a lower surface in contact with the first gate insulating layer 130. As described above, the driving transistor DRT may include the first oxide layer 370 disposed between the first active layer 350 and the first gate electrode 310, thereby ensuring a wide range of driving voltages. Compared to the driving transistor DRT, in the first switching transistor SCT, the first oxide layer 370 is not disposed between the second active layer 450 and the second gate electrode 410, and a large amount of hydrogen (H) is included, thereby ensuring electron mobility.

[0122] Furthermore, according to an example embodiment, the width of the first gate electrode 310 may be at least substantially equal to the width of the first oxide layer 370. Figure 5 , the width of the first gate electrode 310 is shown to be smaller than the width of the first oxide layer 370, but in some embodiments, the widths of the first gate electrode 310 and the first oxide layer 370 may be substantially the same. As will be described below, the first gate electrode 310 and the first oxide layer 370 may be formed to have the same width by being patterned in the same process. Therefore, according to an example embodiment, the upper surface of the first oxide layer 370 may be in contact with the first gate electrode 310, but the side surface of the first oxide layer 370 may be exposed without contacting the first gate electrode 310. The exposed side surface of the first oxide layer 370 may be in contact with the first interlayer insulating layer 160 to be described below.

[0123] However, the present disclosure is not limited thereto, and in some cases, the width of the first gate electrode 310 may be greater than the width of the first oxide layer 370, so that the first gate electrode 310 is disposed to cover the first oxide layer 370. In this case, a side surface of the first oxide layer 370 may be in contact with the first gate electrode 310. This will be described in more detail below with reference to other example embodiments.

[0124] The first interlayer insulating layer 160 is disposed on the first conductive layer. The first interlayer insulating layer 160 is disposed on the first gate electrode 310 and the second gate electrode 410 and may be made of silicon oxide (SiO x ), silicon nitride (SiN x ) of inorganic materials or their stacked structures.

[0125] The first interlayer insulating layer 160 may be formed with (e.g., formed to include) a first contact hole CT1 that passes through the first interlayer insulating layer 160 to expose a portion of the upper surface of the first active layer 350, and a second contact hole CT2 that passes through the first interlayer insulating layer 160 to expose another portion of the upper surface of the first active layer 350. For example, the first contact hole CT1 may be formed to expose the first conductive region 350a of the first active layer 350, and the second contact hole CT2 may be formed to expose the second conductive region 350b of the first active layer 350.

[0126] In addition, the first interlayer insulating layer 160 may be formed with (e.g., formed to include) a fourth contact hole CT4 that passes through the first interlayer insulating layer 160 to expose a portion of the upper surface of the second active layer 450, and a fifth contact hole CT5 that passes through the first interlayer insulating layer 160 to expose another portion of the upper surface of the second active layer 450. For example, the fourth contact hole CT4 may be formed to expose the first conductive region 450a of the second active layer 450, and the fifth contact hole CT5 may be formed to expose the second conductive region 450b of the second active layer 450.

[0127] The number of contact holes formed in the first interlayer insulating layer 160 is not limited thereto. In some example embodiments, a greater number (eg, additional) of contact holes may be formed in the first interlayer insulating layer 160. A description thereof will be given below.

[0128] The second conductive layer is disposed on the first interlayer insulating layer 160. The second conductive layer may include a first source electrode 330 and a first drain electrode 340 of the driving transistor DRT and a second source electrode 430 and a second drain electrode 440 of the first switching transistor SCT.

[0129] The first source electrode 330 contacts the first conductive region 350a formed at one side or one end of the first active layer 350 through the first contact hole CT1. The first drain electrode 340 contacts the second conductive region 350b formed at the opposite side or opposite end of the first active layer 350 through the second contact hole CT2. The second source electrode 430 contacts the first conductive region 450a formed at one side or one end of the second active layer 450 through the fourth contact hole CT4. The second drain electrode 440 contacts the second conductive region 450b formed at the opposite side or opposite end of the second active layer 450 through the fifth contact hole CT5.

[0130] The first protective film 170 is disposed on the second conductive layer. The first protective film 170 is disposed on the first source electrode 330 and the first drain electrode 340 of the driving transistor DRT and the second source electrode 430 and the second drain electrode 440 of the first switching transistor SCT. The first protective film 170 may be made of silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer, or a single layer structure such as silicon oxide (SiO x ) layer and silicon nitride (SiN x ) layers are alternately stacked to form a multilayer structure.

[0131] The first planarization film 180 is disposed on the first protection film 170. The first planarization film 180 may planarize steps caused by thin film transistors such as the driving transistor DRT and the first switching transistor SCT. The first planarization film 180 may be formed of an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0132] A pixel defining film 195 and a light emitting element EL including a first electrode 191 , an organic light emitting layer 192 , and a second electrode 193 may be formed on the first planarization film 180 .

[0133] The first electrode 191 may be formed on the first planarization film 180 . The first electrode 191 may be connected to the first source electrode 330 of the driving transistor DRT through an electrode contact hole CNTD passing through the first protection film 170 and the first planarization film 180 .

[0134] In order to divide (define) pixels, a pixel defining film 195 may be formed on the first planarization film 180 to cover the edge of the first electrode 191. For example, the pixel defining film 195 serves as a pixel defining film that defines pixels. Here, each pixel represents a region in which the first electrode 191, the organic light emitting layer 192, and the second electrode 193 are sequentially stacked so that holes from the first electrode 191 and electrons from the second electrode 193 are combined with each other in the organic light emitting layer 192 to emit light.

[0135] The organic light emitting layer 192 may be disposed on the first electrode 191 and the pixel defining film 195. The organic light emitting layer 192 may include a hole transport layer, a light emitting layer, and an electron transport layer. In some embodiments, the organic light emitting layer 192 may be formed as a stacked structure having two or more stacked members. In this case, a charge generating layer may be formed between the stacked members. In the accompanying drawings, the organic light emitting layer 192 is shown as being formed throughout the entire display area DA, but the present disclosure is not limited thereto. In some example embodiments, the organic light emitting layer 192 may be formed only in a partial region corresponding to the first electrode 191 of each pixel PX.

[0136] The second electrode 193 may be formed on the organic light emitting layer 192. The second electrode 193 may be a common layer commonly formed in (eg, common to) a plurality of pixels PX.

[0137] The light emitting element EL may be formed as a top emission type in which light is emitted upward. In this case, the first electrode 191 may be made of a metal material having a high reflectivity, for example, a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), a silver-palladium-copper (APC) alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO). In some embodiments, the second electrode 193 may be made of a transparent conductive (metal) material (TCO) such as ITO or IZO that can transmit light, or may be made of a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 193 is made of a semi-transmissive conductive (metal) material, the light extraction efficiency may be improved due to the microcavity.

[0138] An encapsulation layer 196 configured to prevent or reduce oxygen or moisture penetration may be formed on the second electrode 193. The encapsulation layer 196 may include at least one inorganic film. The inorganic film may be made of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. In some embodiments, the encapsulation layer 196 may include at least one organic film to prevent or reduce particles from penetrating the encapsulation layer 196 and being introduced into the organic light emitting layer 192 and the second electrode 193. The organic film may be formed of epoxy resin, acrylate, or polyurethane acrylate.

[0139] The display device 1 according to an example embodiment may include a driving transistor DRT having a plurality of oxide semiconductors and a first switching transistor SCT having one oxide semiconductor. The driving transistor DRT may include a first active layer 350 and a first oxide layer 370, and the first switching transistor SCT may include a second active layer 450. In the driving transistor DRT, the first oxide layer 370 is disposed between the first active layer 350 and the first gate electrode 310 to ensure a wide range of driving voltages. In contrast, in the first switching transistor SCT, the first oxide layer 370 is not disposed between the second active layer 450 and the second gate electrode 410, so that high electron mobility can be ensured in the channel region 450c.

[0140] Meanwhile, the scan driver SDR may further include a plurality of transistors, each of which may be formed to be substantially the same as the first switch transistor SCT of each pixel PX. Such second switch transistors included in the above-described scan driver SDR and the data voltage distribution circuit DMUX of the non-display area NDA may each be formed to be substantially the same as the first switch transistor SCT of each pixel PX. Figure 6 and Figure 7 The first switching transistor SCT shown in FIG. 1 is substantially the same.

[0141] For example, in each of the pull-up transistor and the pull-down transistor of the scan driver SDR, an oxide layer may not be provided between the active layer and the gate electrode. Figure 6 and Figure 7 The third active layer, third gate electrode, third source electrode and third drain electrode of each second switching transistor of the scan driver SDR are applied in substantially the same manner as the second active layer 450, second gate electrode 410, second source electrode 430 and second drain electrode 440 of the first switching transistor SCT described.

[0142] In addition, an oxide layer may not be provided between the active layer and the gate electrode in each of the first distribution transistor and the second distribution transistor of the data voltage distribution circuit DMUX. Figure 6 and Figure 7 The fourth active layer, fourth gate electrode, fourth source electrode and fourth drain electrode of each of the first distribution transistor and the second distribution transistor of the data voltage distribution circuit DMUX are applied in substantially the same manner as the second active layer 450, the second gate electrode 410, the second source electrode 430 and the second drain electrode 440 of the described first switching transistor SCT.

[0143] Hereinafter, a method of manufacturing the display device 1 including the driving transistor DRT and the first switching transistor SCT described above will be described.

[0144] Fig.10is a flowchart illustrating a manufacturing process of a display device according to an example embodiment.

[0145] Reference Fig.10 , a manufacturing process of the display device 1 according to an example embodiment may include an action or sub-process of forming a first oxide layer 370 (S104) overlapping the first initial active layer 350' on the gate insulating film. The first oxide layer 370 may include an oxide semiconductor different from the oxide semiconductors of the first active layer 350 and the second active layer 450, and may be disposed only on the first active layer 350. Therefore, oxygen may be selectively supplied only to the first active layer 350, and the first active layer 350 and the second active layer 450 may have different compositions. Hereinafter, the manufacturing process of the display device 1 will be described in more detail with reference to other drawings.

[0146] Figures 11 to 22 is a cross-sectional view illustrating a manufacturing process of a display device according to an example embodiment.

[0147] First, refer to Fig.11 , a buffer layer 120 is formed on the first substrate 110. For example, an embodiment of the manufacturing process includes an action or sub-process of forming a buffer film (S101) on a substrate. The buffer layer 120 can be formed on the entire surface of the first substrate 110. The buffer layer 120 can be formed by a chemical vapor deposition method, but the present disclosure is not limited thereto. In this example embodiment, the process of forming multiple conductive layers and multiple semiconductor layers including the following components is not specifically limited, as long as it can be generally applied. Hereinafter, the formation order and structure of each component will be described in more detail.

[0148] Next, a first semiconductor layer is formed on the buffer layer 120. For example, an embodiment of the manufacturing process includes an action or sub-process of forming a first initial active layer 350' and a second initial active layer 450' on the buffer film (S102). The first semiconductor layer includes a first initial active layer 350' and a second initial active layer 450'. The first initial active layer 350' and the second initial active layer 450' may be formed by a patterning process using a photoresist after forming one layer by a sputtering method. However, the present disclosure is not limited thereto, and in some cases, the first initial active layer 350' and the second initial active layer 450' may be formed by an atomic layer deposition method. Fig.11 It is shown that the conductive region and the channel region are not formed in the first preliminary active layer 350' and the second preliminary active layer 450'. Some regions of the first preliminary active layer 350' and the second preliminary active layer 450' may become conductive in a subsequent process to form the conductive region and the channel region.

[0149] Next, refer to Fig.12, a first insulating layer IL1 is formed on the first semiconductor layer, and an oxide semiconductor layer OXL' is formed on the first insulating layer IL1. For example, as described above, an embodiment of the manufacturing process includes an action or sub-process of forming a gate insulating film (S103) on the first initial active layer 350' and the second initial active layer 450', and an action or sub-process of forming a first oxide layer (S104) overlapping the first initial active layer 350' on the gate insulating film. The first insulating layer IL1 and the oxide semiconductor layer OXL' may be disposed on the entire surface of the buffer layer 120, and may be disposed to overlap each of the first initial active layer 350' and the second initial active layer 450' of the first semiconductor layer. The first insulating layer IL1 may be patterned in a subsequent process to form a first gate insulating layer 130, and the oxide semiconductor layer OXL' may form a first oxide layer 370.

[0150] Next, refer to Fig.12 and Fig.13 , the oxide semiconductor layer OXL′ is thermally treated (H) to form the oxide layer OXL. The oxide semiconductor layer OXL′ may implant oxygen into the first insulating layer IL1 formed thereunder through the thermal treatment process.

[0151] Reference Fig.14 and Fig.15 , a first etching process (first etching) is performed to form a first photoresist PR1 on at least some areas of the oxide layer OXL formed by the heat treatment process and partially etch the oxide layer OXL. The first photoresist PR1 may perform a function of a mask for removing some areas of the oxide layer OXL. The first photoresist PR1 may be disposed on the first initial active layer 350' and may not be disposed on the second initial active layer 450'. Therefore, the oxide layer OXL disposed above the second initial active layer 450' may be removed by the first etching process (first etching), and only the oxide layer OXL disposed above the first initial active layer 350' may be retained ( Fig.15 370' in the figure).

[0152] Next, refer to Fig.16 and Fig.17, a conductive metal layer CML' is formed on the oxide layer 370' and the first insulating layer IL1, and the oxide layer 370' and the conductive metal layer CML' are partially etched to form the first oxide layer 370, the first gate electrode 310 and the second gate electrode 410. For example, an embodiment of the manufacturing process includes an action or sub-process of forming gate electrodes (S105) on the first oxide layer and the second oxide layer. The conductive metal layer CML' is formed on the entire surface of the first insulating layer IL1, and a first conductive layer may be formed in a subsequent process, wherein the conductive metal layer CML' covers the oxide layer 370'. For example, the conductive metal layer CML' may be patterned in a subsequent process to form the first gate electrode 310 and the second gate electrode 410.

[0153] like Fig.16 As shown in , a second etching process (second etching) is performed to form a second photoresist PR2 and a third photoresist PR3 on the conductive metal layer CML' and partially etch the conductive metal layer CML' and the oxide layer 370'. The second photoresist PR2 and the third photoresist PR3 may respectively perform the functions of a mask for forming the first gate electrode 310 and the second gate electrode 410. The second photoresist PR2 may be disposed over the first initial active layer 350', and the third photoresist PR3 may be disposed over the second initial active layer 450'. The conductive metal layer CML' and the oxide layer 370' in portions other than the second photoresist PR2 and the third photoresist PR3 may be etched and removed, as shown in FIG. Fig.17 As shown in , a first conductive layer including a first gate electrode 310 and a second gate electrode 410 and a first oxide layer 370 may be formed. Optionally, in some example embodiments, the conductive metal layer CML' and the oxide layer 370' may have an etching selectivity different from that of the first insulating layer IL1. The first insulating layer IL1 may be patterned in a subsequent process to form a first gate insulating layer 130.

[0154] In some embodiments, the width of the second photoresist PR2 may be substantially equal to the width of the first gate electrode 310, and the width of the third photoresist PR3 may be substantially equal to the width of the second gate electrode 410. In some embodiments, the width of the first photoresist PR1 may be greater than or less than the width of the second photoresist PR2. As shown in the drawings, when the width of the first photoresist PR1 is greater than the width of the second photoresist PR2, the width of the first oxide layer 370 formed along the second photoresist PR2 may be substantially equal to the width of the first gate electrode 310. The first gate electrode 310 is disposed only on the upper surface of the first oxide layer 370, and both side surfaces of the first oxide layer 370 are exposed (e.g., simultaneously) and may contact the first interlayer insulating layer 160 formed later. The width of the channel region 350c of the first active layer 350 formed in a subsequent process may be substantially equal to the width of the first gate electrode 310 and may also be substantially equal to the width of the first oxide layer 370.

[0155] On the other hand, when the width of the first photoresist PR1 is smaller than the width of the second photoresist PR2, the width of the first oxide layer 370 is substantially equal to the width of the first photoresist PR1, and the width of the first gate electrode 310 formed along the second photoresist PR2 may be greater than the width of the first oxide layer 370. In this case, the width of the first oxide layer 370 may be smaller than the width of the channel region 350c of the first active layer 350. In some embodiments, the first gate electrode 310 may be disposed on the upper surface and both side surfaces of the first oxide layer 370, and the first oxide layer 370 may not contact the first interlayer insulating layer 160. This will be described below with reference to other example embodiments.

[0156] Next, refer to Fig.17 and Fig.18 , a third etching process (third etching) of etching the first insulating layer IL1 along the second photoresist PR2 and the third photoresist PR3 is performed to form a first gate insulating layer 130, and some (set or predetermined) regions of each of the first preliminary active layer 350' and the second preliminary active layer 450' are doped to form a first active layer 350 and a second active layer 450 including first conductive regions 350a and 450a, second conductive regions 350b and 450b, and channel regions 350c and 450c. The first gate insulating layer 130 may be disposed between the first active layer 350 and the first oxide layer 370 and between the second active layer 450 and the second gate electrode 410.

[0157] Subsequently, the second photoresist PR2 and the third photoresist PR3 are removed.

[0158] Next, refer to Fig.19 , a second insulating layer IL2 is formed on the first conductive layer. The second insulating layer IL2 may be partially etched in a subsequent process to form a first interlayer insulating layer 160 ( Fig. 20 ).

[0159] Next, refer to Fig. 20 A plurality of contact holes CT1, CT2, CT4, and CT5 are formed in the second insulating layer IL2 to provide a first interlayer insulating layer 160. A first contact hole CT1, a second contact hole CT2, a fourth contact hole CT4, and a fifth contact hole CT5 may be formed in the first interlayer insulating layer 160.

[0160] Next, refer to Fig.21 , a second conductive layer is formed on the first interlayer insulating layer 160. The second conductive layer may include a first source electrode 330, a first drain electrode 340, a second source electrode 430, and a second drain electrode 440. The first source electrode 330 and the first drain electrode 340 may contact some regions of the first active layer 350 through the first contact hole CT1 and the second contact hole CT2, respectively, and the second source electrode 430 and the second drain electrode 440 may contact some regions of the second active layer 450 through the fourth contact hole CT4 and the fifth contact hole CT5, respectively. A description thereof has been provided above. For example, as Figures 17 to 21 As shown in , an embodiment of the manufacturing process includes an action or sub-process of forming an interlayer insulating film, a source electrode, and a drain electrode on a gate electrode ( S106 ).

[0161] Next, refer to Fig. 22 , forming a first protective film 170 disposed on the second conductive layer and a first planarization film 180 disposed on the first protective film 170, and then forming an electrode contact hole CNTD exposing the first source electrode 330 and the first electrode 191 on the first planarization film 180. For example, an embodiment of the manufacturing process includes an action or sub-process of forming a protective film, a planarization film, etc. on the drain electrode and the source electrode (S107).

[0162] Finally, a pixel defining film 195, an organic light emitting layer 192, a second electrode 193 and an encapsulation layer 196 are formed on the first electrode 191 to manufacture Figure 7 The display device 1 shown in FIG.

[0163] The display device 1 according to an example embodiment may be manufactured by the process described above. In the display device 1, the first switch transistor SCT may not include the first oxide layer 370 by including a process of forming the first oxide layer 370 only on the first active layer 350 of the driving transistor DRT. The process of forming the first oxide layer 370 may include a process of forming an oxide semiconductor layer OXL' and heat-treating the oxide semiconductor layer OXL' to form the oxide layer OXL. In the heat treatment process, oxygen (O) may be supplied to the first insulating layer IL1 disposed below the oxide layer OXL (for example, supplied to the first gate insulating layer 130), and may be injected into the first active layer 350 of the driving transistor DRT.

[0164] In some embodiments, in the process of forming the oxide layer OXL, it may not be necessary to perform a process of partially etching the oxide layer OXL after the heat treatment process.

[0165] Fig.23 is a cross-sectional view illustrating a portion of a manufacturing process of a display device according to another example embodiment.

[0166] Reference Fig.23 , the process of forming the oxide layer OXL may include removing the oxide semiconductor layer OXL' disposed on the second initial active layer 450' by partially etching the oxide semiconductor layer OXL', and performing a heat treatment on the oxide semiconductor layer OXL' remaining after the partial removal to form the oxide layer OXL. For example, the oxide layer OXL may be formed by partially etching the oxide semiconductor layer OXL' disposed on the entire surface of the first insulating layer IL1 and then performing a heat treatment process. In this case, in the heat treatment process, oxygen supplied from the oxide layer OXL may be supplied only to the first insulating layer IL1 disposed on the first initial active layer 350'. As a result, the content of oxygen injected into the second initial active layer 450' may be minimized or reduced, and the first switching transistor SCT including the second initial active layer 450' may have high mobility without releasing hydrogen.

[0167] Furthermore, in some cases, when the oxide semiconductor layer OXL′ is formed only over the first preliminary active layer 350′, the thermal treatment process may be performed in a state where the oxide semiconductor layer OXL′ is not disposed on the second preliminary active layer 450′. Fig.23 As shown in FIG. 1 , even when the heat treatment process is performed on the entire surface of the first insulating layer IL1 , since the oxide semiconductor layer OXL′ is disposed to overlap only the first preliminary active layer 350′, the oxide layer OXL may be formed only on the first preliminary active layer 350′. Figures 16 to 22 The process described is the same.

[0168] Hereinafter, various structures of the driving transistor DRT and the first switching transistor SCT will be described with reference to other drawings.

[0169] Fig.24 is a plan view illustrating a driving transistor DRT_1 according to another example embodiment. Fig.25 It is along Fig.24 The line I-I' and Figure 6 A cross-sectional view taken along line II-II'.

[0170] Reference Fig.24 and Fig.25 In the driving transistor DRT_1 according to the example embodiment, the width of the first oxide layer 370_1 may be smaller than the width of the first gate electrode 310_1. Both side surfaces of the first oxide layer 370_1 may be in contact with the first gate electrode 310_1 (eg, simultaneously) without being exposed. Figure 5 and Figure 7 The driving transistor DRT of FIG. 1 is different in that the first oxide layer 370_1 has a smaller width. Hereinafter, redundant descriptions will be omitted, and a description will be provided to focus on differences from the above description.

[0171] exist Fig.24 and Fig.25 In the driving transistor DRT_1, the width of the first oxide layer 370_1 may be smaller than the width of the first gate electrode 310_1. The upper surface and both side surfaces of the first oxide layer 370_1 may be in contact with the first gate electrode 310_1 (e.g., simultaneously), and the first gate electrode 310_1 may be arranged to cover the outer surface of the first oxide layer 370_1. Therefore, a portion of the lower surface of the first gate electrode 310_1 may also be in contact with the first gate insulating layer 130 like the second gate electrode 410.

[0172] In addition, according to example embodiments, the width of the first oxide layer 370_1 may be smaller than the width of the channel region 350c of the first active layer 350. The channel region 350c of the first active layer 350 may be formed to have substantially the same width as the width of the first gate electrode 310_1. When the first oxide layer 370_1 has a width smaller than the width of the first gate electrode 310_1, the width of the first oxide layer 370_1 may be smaller than the width of the channel region 350c of the first active layer 350.

[0173] When the first photoresist PR1 has a width smaller than that of the second photoresist PR2 during the manufacturing process of the display device 1, the first oxide layer 370_1 of such a shape may be formed. As described above, the width of the first gate electrode 310_1 may be substantially equal to the width of the second photoresist PR2, and the width of the first oxide layer 370_1 may vary according to the width of the first photoresist PR1. Referring again to Figures 14 to 18 , the width of the oxide layer OXL remaining on the first insulating layer IL1 due to the first photoresist PR1 is greater than the width of the second photoresist PR2.

[0174] Here, when the width of the first photoresist PR1 is smaller than the width of the second photoresist PR2, the width of the oxide layer OXL (similar to OXL') retained on the first insulating layer IL1 may be smaller than the width of the second photoresist PR2. In a subsequent process, the conductive metal layer CML' disposed on the oxide layer OXL may also contact (e.g., contact simultaneously) both side surfaces of the oxide layer OXL, and when the conductive metal layer CML' is etched along the second photoresist PR2, the portion in contact with both side surfaces of the oxide layer OXL remains. Because the width of the second photoresist PR2 is larger than the width of the oxide layer OXL, the region in which the second photoresist PR2 is disposed may include a region in which the oxide layer OXL is not disposed. Therefore, the first gate electrode 310_1 formed after the second etching process (second etching) is performed along the second photoresist PR2 may have a width greater than the width of the first oxide layer 370_1.

[0175] The first gate electrode 310_1 and the first oxide layer 370_1 may have different etching selectivities, so that when the first gate electrode 310_1 and the first oxide layer 370_1 are etched in the same process, the first oxide layer 370_1 may be etched more (e.g., etched to a greater extent). Therefore, the side surface of the first oxide layer 370_1 may be further recessed than the side surface of the first gate electrode 310_1. When the side surface of the first oxide layer 370_1 is recessed, the insulating material of the first interlayer insulating layer 160 formed in a subsequent process may not be deposited on the side surface of the first oxide layer 370_1, and cracks may be generated. This may be a factor that hinders the device characteristics and reliability of the drive transistor DRT.

[0176] According to example embodiments, the first gate electrode 310_1 may be formed to have a width greater than that of the first oxide layer 370_1. Therefore, cracks may be prevented or reduced from being formed in the first interlayer insulating layer 160, and further, device characteristics and reliability may be improved by ensuring structural stability of the driving transistor DRT_1. Since the first gate electrode 310_1 has a large width and is disposed on the first oxide layer 370_1, the first gate electrode 310_1 may be disposed to cover the upper surface and side surfaces of the first oxide layer 370_1. Figure 7 Unlike the example embodiments, the first oxide layer 370_1 may not contact the first interlayer insulating layer 160 .

[0177] In addition, the channel region 350c of the first active layer 350 formed in a subsequent process may have the same width as that of the first gate electrode 310_1, and at the same time, have a width greater than that of the first oxide layer 370_1. However, since the first oxide layer 370_1 may be formed to overlap at least the channel region 350c of the first active layer 350, oxygen (O) may be injected from the first oxide layer 370_1 into the first active layer 350, thereby ensuring a wide range of driving voltages.

[0178] Meanwhile, the display device 1 may further include a third conductive layer disposed between the first substrate 110 and the buffer layer 120 .

[0179] Fig.26 is a plan view illustrating a driving transistor according to still another example embodiment. Fig. 27 It is along Fig.26 The line I-I' and Figure 6 A cross-sectional view taken along line II-II'.

[0180] Reference Fig.26 and Fig. 27 , the display device 1 according to the example embodiment may further include a third conductive layer disposed between the first substrate 110 and the buffer layer 120. The third conductive layer may include a first light blocking layer 360_2 disposed to overlap with the first active layer 350 of the driving transistor DRT_2. The driving transistor DRT_2 includes a first gate electrode 310, a first source electrode 330_2, a first drain electrode 340, and a first light blocking layer 360_2, wherein the first source electrode 330_2 may be connected to the first light blocking layer 360_2. Fig.26 and Fig. 27 The driving transistor DRT_2 and Figure 5 and Figure 7 The driving transistor DRT of FIG. 1 is different in that the driving transistor DRT_2 further includes a first light blocking layer 360_2. Hereinafter, redundant descriptions will be omitted, and descriptions will be provided to focus on differences from the above.

[0181] The third conductive layer may be disposed between the first substrate 110 and the buffer layer 120. The third conductive layer includes a first light blocking layer 360_2 of the driving transistor DRT_2.

[0182] The first light blocking layer 360_2 may be disposed on the first substrate 110 to overlap with the first active layer 350 of the driving transistor DRT_2. The first light blocking layer 360_2 may block light from the outside from being incident on the first active layer 350 through the first substrate 110. The first light blocking layer 360_2 may prevent or reduce leakage current flowing in the first active layer 350 when light passing through the first substrate 110 is incident on the first active layer 350. The width of the first light blocking layer 360_2 measured along one direction (e.g., along the third direction DR3) may be greater than the width of the first active layer 350 measured along the one direction. However, the present disclosure is not limited thereto, and the width of the first light blocking layer 360_2 may be smaller than the width of the first active layer 350 but at least greater than the width of the channel region 350c of the first active layer 350. The first light blocking layer 360_2 may be formed of a single layer or multiple layers made of one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0183] A third contact hole CT3 exposing the first light blocking layer 360_2 through the first interlayer insulating layer 160 and the buffer layer 120 may be formed in the first interlayer insulating layer 160 and the buffer layer 120. The first source electrode 330_2 of the driving transistor DRT_2 may contact the first light blocking layer 360_2 exposed by the third contact hole CT3. As a result, the driving transistor DRT_2 may ensure a wider range of driving voltage.

[0184] Fig.28 and Fig.29 It is shown that Fig.26 A cross-sectional view of a portion of a manufacturing process of a driving transistor of a display device.

[0185] Reference Fig.28 Before forming the buffer layer 120 on the first substrate 110, a third conductive layer is formed on the first substrate 110. The third conductive layer includes a first light blocking layer 360_2. In example embodiments, the first light blocking layer 360_2 may be formed by patterning the third conductive layer formed on the first substrate 110 by a sputtering method, using an etching process using a photoresist pattern. However, the present disclosure is not limited thereto.

[0186] The buffer layer 120 formed in a subsequent process may be disposed on the first substrate 110 to cover the first light blocking layer 360_2 .

[0187] Next, refer to Fig.29 In the process of forming the first interlayer insulating layer 160, a third contact hole CT3 that passes through the second insulating layer IL2 and the buffer layer 120 to contact a portion of the first light blocking layer 360_2 may be formed in the second insulating layer IL2 and the buffer layer 120. The first interlayer insulating layer 160 may further include a third contact hole CT3, and the first source electrode 330_2 of the second conductive layer may contact the first light blocking layer 360_2 through the third contact hole CT3.

[0188] In some embodiments, the third conductive layer may further include a second light blocking layer overlapping the second active layer 450 of the first switching transistor SCT.

[0189] Fig.30 is a plan view showing a first switching transistor according to another example embodiment. Fig.31 It is along Fig.26 The line I-I' and Fig.30 A sectional view taken along line III-III'.

[0190] Reference Fig.30 and Fig.31 , the first switching transistor SCT_3 according to example embodiments further includes a second light blocking layer 460_3 , and the second gate electrode 410_3 may be connected to the second light blocking layer 460_3 . Fig.30 and Fig.31 The first switch transistor SCT_3 and Figure 7 The first switching transistor SCT is different in that the second gate electrode 410_3 is connected to the second light blocking layer 460_3. Hereinafter, redundant descriptions will be omitted, and descriptions will be provided to focus on the differences from the above. For example, Fig.31 The driving transistor DRT_3 including the first source electrode 330_3 and the first light blocking layer 360_3 in FIG. 3 may be substantially the same as the driving transistor DRT_2 including the first source electrode 330_2 and the first light blocking layer 360_2 .

[0191] Including Fig.30 The first switching transistor SCT_3 and Fig.31 In the display device 1 of the structure, the third conductive layer may further include a second light blocking layer 460_3. The first switch transistor SCT_3 may include a second gate electrode 410_3, a second active layer 450_3, a second source electrode 430_3, a second drain electrode 440_3, and a second light blocking layer 460_3. The second active layer 450_3 includes a first conductive region 450a_3, a second conductive region 450b_3, and a channel region 450c_3.

[0192] The second light blocking layer 460_3 is disposed on the first substrate 110. The second light blocking layer 460_3 may prevent, block or reduce light from the outside from passing through the first substrate 110 and being incident on the second active layer 450_3. The length of the second light blocking layer 460_3 in the third direction DR3 may be greater than the length of the second active layer 450_3 in the third direction DR3, and the length of the second light blocking layer 460_3 in the fourth direction DR4 may be greater than the length of the second active layer 450_3 in the fourth direction DR4. The second light blocking layer 460_3 may be formed as a single layer structure or a multilayer structure, wherein each layer may be selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and alloys thereof. The buffer layer 120 may be formed on the second light blocking layer 460_3.

[0193] The second gate electrode 410_3 may contact the second light blocking layer 460_3 through the sixth contact hole CT6. The sixth contact hole CT6 may be formed to expose the second light blocking layer 460_3 through the first gate insulating layer 130 and the buffer layer 120. In this case, the second gate electrode 410_3 and the second light blocking layer 460_3 disposed below the second active layer 450_3 have the same voltage. For example, the second gate electrode 410_3 may be used as an upper gate electrode, and the second light blocking layer 460_3 may be used as a lower gate electrode. Therefore, the first switching transistor SCT_3 used as a switching transistor may be driven by a dual gate method, so that when the first switching transistor SCT_3 is turned off, leakage current may be reduced or prevented from flowing in the channel region 450c_3 of the second active layer 450_3 of the first switching transistor SCT_3.

[0194] Meanwhile, according to some example embodiments, in some second switching transistors disposed in the non-display area NDA, the active layer may include polysilicon.

[0195] Fig.32 is a cross-sectional view illustrating a second switching transistor according to another example embodiment.

[0196] Reference Fig.32 , in the second switching transistor GPT_4 according to example embodiments, the third active layer 550_4 may include polysilicon. Hereinafter, redundant descriptions will be omitted, and descriptions will be provided to focus on differences from the above description.

[0197] Fig.32 The second switching transistor GPT_4 includes a third active layer 550_4, a third gate electrode 510_4, a third source electrode 530_4, and a third drain electrode 540_4.

[0198] The first semiconductor layer may include a third active layer 550_4 of the second switch transistor GPT_4. The third active layer 550_4 may include polycrystalline silicon and include a first heavily doped region 550a_4, a second heavily doped region 550b_4, a channel region 550c_4, a first lightly doped region 550d_4, and a second lightly doped region 550e_4. The channel region 550c_4 may be made of polycrystalline silicon not doped with impurities, the first heavily doped region 550a_4 and the second heavily doped region 550b_4 may be made of polycrystalline silicon doped with high-concentration impurities, and the first lightly doped region 550d_4 and the second lightly doped region 550e_4 may be made of polycrystalline silicon doped with low-concentration impurities. The third source electrode 530_4 and the third drain electrode 540_4 may contact the first heavily doped region 550a_4 and the second heavily doped region 550b_4, respectively.

[0199] The first gate insulating layer 130 is disposed on the third active layer 550_4. The description of the first gate insulating layer 130 is the same as that of the above reference Figure 7 Same as described.

[0200] The third gate electrode 510_4 is disposed on the first gate insulating layer 130. The third gate electrode 510_4 may overlap the third active layer 550_4, wherein the first gate insulating layer 130 is disposed between the third gate electrode 510_4 and the third active layer 550_4. For example, the third gate electrode 510_4 may overlap the channel region 550c_4 of the third active layer 550_4. The description of the third gate electrode 510_4 is substantially the same as that described above with reference to the first gate electrode 310.

[0201] The first interlayer insulating layer 160 is disposed on the third gate electrode 510_4. The first interlayer insulating layer 160 may be formed with a seventh contact hole CT7 and an eighth contact hole CT8, the seventh contact hole CT7 passing through the first interlayer insulating layer 160 to expose a portion of the upper surface of the third active layer 550_4, and the eighth contact hole CT8 passing through the first interlayer insulating layer 160 to expose another portion of the upper surface of the third active layer 550_4. The seventh contact hole CT7 may be formed to expose the first heavily doped region 550a_4 of the third active layer 550_4, and the eighth contact hole CT8 may be formed to expose the second heavily doped region 550b_4 of the third active layer 550_4.

[0202] The second conductive layer may further include a third source electrode 530_4 and a third drain electrode 540_4. The third source electrode 530_4 contacts the first heavily doped region 550a_4 formed at one side of the third active layer 550_4 through the seventh contact hole CT7. The third drain electrode 540_4 may contact the second heavily doped region 550b_4 formed on the other side of the third active layer 550_4 through the eighth contact hole CT8.

[0203] The first protection film 170 is disposed on the third source electrode 530_4 and the third drain electrode 540_4 . A first planarization film 180 configured to planarize a step caused by a thin film transistor such as the second switching transistor GPT_4 may be formed on the first protection film 170 .

[0204] When the third active layer 550_4 of the second switching transistor GPT_4 includes polysilicon, the third active layer 550_4 may have high mobility, so that the device characteristics of the second switching transistor GPT_4 may be improved. In addition, even when the channel region 550c_4 has a small width, the third active layer 550_4 may have excellent mobility, so that the area of ​​the non-display area NDA of the display device 1 may be minimized or reduced.

[0205] Each of the pull-up transistor and the pull-down transistor of the scan driver SDR and the plurality of transistors of the node controller may be formed to be connected to the Fig.32 In some embodiments, each of the first distribution transistor and the second distribution transistor of the data voltage distribution circuit DMUX may be formed as Fig.32 The second switching transistor GPT_4 shown in FIG. 1 is substantially identical to that shown in FIG.

[0206] In a display device according to an example embodiment, each pixel PX may include a driving transistor including multiple oxide semiconductors and a switching transistor including one oxide semiconductor. The driving transistor may include an active layer and an oxide layer capable of supplying oxygen to the active layer, and the switching transistor may not include an oxygen supply layer.

[0207] Therefore, the driving transistor can ensure a wide range of driving voltage for driving each pixel by the oxide semiconductor further including the oxygen supplying layer, and the switching transistor can have high electron mobility in the channel region.

[0208] The effects of the present disclosure are not limited to the exemplary embodiments set forth herein, and more various effects are included in the present description.

[0209] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the described embodiments without departing substantially from the principles of the present disclosure as set forth in the claims and their equivalents. Therefore, the disclosed embodiments disclosed are intended only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: pixels connected to scan lines and data lines crossing the scan lines, The pixel includes a light emitting element, a driving transistor and a first switching transistor, wherein the driving transistor is configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, and the first switching transistor is configured to apply the data voltage of the data line to the driving transistor according to a scanning signal applied to the scanning line. The driving transistor includes a first active layer and a first oxide layer, the first active layer includes an oxide semiconductor, the first oxide layer is located on the first active layer and includes an oxide semiconductor, and The first switching transistor includes a second active layer including an oxide semiconductor, wherein the first oxide layer is not disposed on the second active layer, and The hydrogen content of the first active layer is lower than the hydrogen content of the second active layer.

2. The display device according to claim 1, wherein: The oxide semiconductor of the first active layer and the oxide semiconductor of the second active layer each independently include at least one selected from indium, gallium, zinc, tin, and hafnium.

3. The display device according to claim 2, wherein: The oxide semiconductor of the first oxide layer includes at least one selected from indium, gallium, zinc, tin, and hafnium.

4. The display device according to claim 3, wherein: The first active layer has a higher oxygen content than the second active layer.

5. The display device according to any one of claims 1 to 4, wherein: The driving transistor further comprises: a first gate insulating layer, located on the first active layer, and a first gate electrode, located on the first gate insulating layer and overlapping the first active layer, and Wherein, the first oxide layer is located between the first gate electrode and the first gate insulating layer.

6. The display device according to claim 5, wherein: A width of the first oxide layer measured in one direction is equal to a width of the first gate electrode measured in the one direction.

7. The display device according to claim 1, wherein: The first active layer includes a first conductive region, a second conductive region, and a channel region between the first conductive region and the second conductive region, and The first oxide layer overlaps the channel region of the first active layer.

8. The display device according to claim 7, wherein: The driving transistor further includes: a first source electrode contacting the first conductive region through a first contact hole penetrating through the interlayer insulating layer on the first active layer, and The first drain electrode contacts the second conductive region through a second contact hole penetrating the interlayer insulating layer.

9. The display device according to claim 8, wherein: The driving transistor further includes a first light blocking layer located below the first active layer, and The first source electrode contacts the first light blocking layer.

10. The display device according to claim 5, wherein: The first gate insulating layer is located on the second active layer, and The first switching transistor further includes a second gate electrode located on the first gate insulating layer and overlapping the second active layer.

11. The display device according to claim 10, wherein: At least a portion of a lower surface of the first gate electrode is in contact with the first oxide layer, and A lower surface of the second gate electrode does not contact the first oxide layer.

12. A display device, comprising: A substrate, including a display area and a non-display area; a buffer layer, located on the substrate; a first semiconductor layer located on the buffer layer and comprising an oxide semiconductor, wherein the first semiconductor layer comprises a first active layer and a second active layer located in the display area; a gate insulating layer, located on the first semiconductor layer and covering the first active layer and the second active layer; a second semiconductor layer, located on the gate insulating layer and comprising an oxide semiconductor, wherein the second semiconductor layer comprises a first oxide layer located on the first active layer; A first conductive layer, located on the second semiconductor layer and comprising a gate electrode; an interlayer insulating layer, located on the first conductive layer and covering the gate electrode; and a second conductive layer, located on the interlayer insulating layer and comprising a source electrode and a drain electrode, wherein the first oxide layer is not located on the second active layer, and The hydrogen content of the first active layer is lower than the hydrogen content of the second active layer.

13. The display device according to claim 12, wherein: The oxide semiconductor of the first semiconductor layer and the oxide semiconductor of the second semiconductor layer each independently include at least one selected from indium, gallium, zinc, tin, and hafnium.

14. The display device according to claim 13, wherein: The first active layer has a higher oxygen content than the second active layer.

15. The display device according to any one of claims 12 to 14, wherein: The first conductive layer further includes: a first gate electrode located on the first active layer and including a lower surface in contact with the first oxide layer; and A second gate electrode is located on the second active layer and includes a lower surface contacting the gate insulating layer.

16. The display device according to claim 15, wherein: A width of the first gate electrode measured in one direction is at least equal to a width of the first oxide layer measured in the one direction.

17. The display device according to claim 15, wherein: The second conductive layer further includes: a first source electrode, contacting one end of the first active layer; a first drain electrode in contact with an opposite end of the first active layer; a second source electrode contacting one end of the second active layer; and The second drain electrode contacts the opposite end of the second active layer.

18. The display device according to claim 17, further comprising a third conductive layer, the third conductive layer being located between the substrate and the buffer layer and comprising a first light blocking layer stacked with the first active layer, in, The first source electrode contacts the first light blocking layer.

19. The display device according to claim 18, wherein: The third conductive layer further includes a second light blocking layer stacked with the second active layer, and The second gate electrode contacts the second light blocking layer.

20. A display device, comprising: pixels connected to scan lines and data lines crossing the scan lines, The pixel includes a light emitting element, a driving transistor and a first switching transistor, wherein the driving transistor is configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, and the first switching transistor is configured to apply the data voltage of the data line to the driving transistor according to a scanning signal applied to the scanning line. The driving transistor includes a first active layer and a first oxide layer, the first active layer includes an oxide semiconductor, the first oxide layer is located on the first active layer and includes an oxide semiconductor, The driving transistor further includes a first gate electrode located on the first oxide layer, and The first switching transistor includes a second active layer including an oxide semiconductor, wherein the first oxide layer is not disposed on the second active layer, and The width of the first oxide layer measured in one direction is smaller than the width of the first gate electrode measured in the one direction, and both side surfaces of the first oxide layer are in contact with the first gate electrode.

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